1 /** @file pcie_core.c
2 *
3 * Contains PCIe related functions that are shared between different driver models (e.g. firmware
4 * builds, DHD builds, BMAC builds), in order to avoid code duplication.
5 *
6 * Copyright (C) 2020, Broadcom.
7 *
8 * Unless you and Broadcom execute a separate written software license
9 * agreement governing use of this software, this software is licensed to you
10 * under the terms of the GNU General Public License version 2 (the "GPL"),
11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
12 * following added to such license:
13 *
14 * As a special exception, the copyright holders of this software give you
15 * permission to link this software with independent modules, and to copy and
16 * distribute the resulting executable under terms of your choice, provided that
17 * you also meet, for each linked independent module, the terms and conditions of
18 * the license of that module. An independent module is a module which is not
19 * derived from this software. The special exception does not apply to any
20 * modifications of the software.
21 *
22 *
23 * <<Broadcom-WL-IPTag/Dual:>>
24 */
25
26 #include <typedefs.h>
27 #include <bcmutils.h>
28 #include <bcmdefs.h>
29 #include <osl.h>
30 #include <siutils.h>
31 #include <hndsoc.h>
32 #include <sbchipc.h>
33 #include <pcicfg.h>
34 #if defined(DONGLEBUILD)
35 #include <pcieregsoffs.h>
36 #include <pcicfg.h>
37 #endif
38 #include "pcie_core.h"
39 #include <bcmdevs.h>
40
41 /* local prototypes */
42
43 /* local variables */
44
45 /* function definitions */
46
47 #ifdef BCMDRIVER /* this workaround can only be run on the host side since it resets the chip */
48 #if !defined(DONGLEBUILD) || defined(BCMSTANDALONE_TEST)
49
50 /* To avoid build error for dongle standalone test, define CAN_SLEEP if not defined */
51 #ifndef CAN_SLEEP
52 #define CAN_SLEEP() (FALSE)
53 #endif
54
55 #ifndef USEC_PER_MSEC
56 #define USEC_PER_MSEC 1000
57 #endif
58
59 /**
60 * WAR for CRWLPCIEGEN2-163, needed for all the chips at this point.
61 * The PCIe core contains a 'snoop bus', that allows the logic in the PCIe core to read and write
62 * to the PCIe configuration registers. When chip backplane reset hits, e.g. on driver unload, the
63 * pcie snoop out will reset to default values and may get out of sync with pcie config registers.
64 * This is causing failures because the LTR enable bit on the snoop bus gets out of sync. Also on
65 * the snoop bus are the device power state, MSI info, L1subenable which may potentially cause
66 * problems.
67 */
68 /* wd_mask/wd_val is only for chipc_corerev >= 65 */
pcie_watchdog_reset(osl_t * osh,si_t * sih,uint32 wd_mask,uint32 wd_val)69 void pcie_watchdog_reset(osl_t *osh, si_t *sih, uint32 wd_mask, uint32 wd_val)
70 {
71 uint32 val, i, lsc;
72 uint16 cfg_offset[] = {PCIECFGREG_STATUS_CMD, PCIECFGREG_PM_CSR,
73 PCIECFGREG_MSI_CAP, PCIECFGREG_MSI_ADDR_L,
74 PCIECFGREG_MSI_ADDR_H, PCIECFGREG_MSI_DATA,
75 PCIECFGREG_LINK_STATUS_CTRL2, PCIECFGREG_RBAR_CTRL,
76 PCIECFGREG_PML1_SUB_CTRL1, PCIECFGREG_REG_BAR2_CONFIG,
77 PCIECFGREG_REG_BAR3_CONFIG};
78 sbpcieregs_t *pcieregs = NULL;
79 uint32 origidx = si_coreidx(sih);
80
81 #if defined(BCMQT) || defined(BCMFPGA_HW)
82 /*
83 * JIRA : SWWLAN-283651, 4397A0 WAR : During insmod avoid existing
84 * PCIE WAR to avoid 'pcie_watchdog_reset'
85 */
86 if (BCM4397_CHIP(sih->chip)) {
87 return;
88 }
89
90 /* To avoid hang on FPGA, donot reset watchdog */
91 if (CCREV(sih->ccrev) < 65) {
92 si_setcoreidx(sih, origidx);
93 return;
94 }
95 #endif
96 #ifdef BCMFPGA_HW
97 if (CCREV(sih->ccrev) < 67) {
98 /* To avoid hang on FPGA, donot reset watchdog */
99 si_setcoreidx(sih, origidx);
100 return;
101 }
102 #endif
103
104 /* Switch to PCIE2 core */
105 pcieregs = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0);
106 BCM_REFERENCE(pcieregs);
107 ASSERT(pcieregs != NULL);
108
109 /* Disable/restore ASPM Control to protect the watchdog reset */
110 W_REG(osh, &pcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL);
111 lsc = R_REG(osh, &pcieregs->configdata);
112 val = lsc & (~PCIE_ASPM_ENAB);
113 W_REG(osh, &pcieregs->configdata, val);
114
115 if (CCREV(sih->ccrev) >= 65) {
116 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), wd_mask, wd_val);
117 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), WD_COUNTER_MASK, 4);
118 CAN_SLEEP() ? OSL_SLEEP(2) : OSL_DELAY(2 * USEC_PER_MSEC); /* 2 ms */
119 val = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, intstatus), 0, 0);
120 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, intstatus),
121 wd_mask, val & wd_mask);
122 } else {
123 si_corereg_writeonly(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, 4);
124 /* Read a config space to make sure the above write gets flushed on PCIe bus */
125 val = OSL_PCI_READ_CONFIG(osh, PCI_CFG_VID, sizeof(uint32));
126 CAN_SLEEP() ? OSL_SLEEP(100) : OSL_DELAY(100 * USEC_PER_MSEC); /* 100 ms */
127 }
128
129 W_REG(osh, &pcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL);
130 W_REG(osh, &pcieregs->configdata, lsc);
131
132 if (sih->buscorerev <= 13) {
133 /* Write configuration registers back to the shadow registers
134 * cause shadow registers are cleared out after watchdog reset.
135 */
136 for (i = 0; i < ARRAYSIZE(cfg_offset); i++) {
137 W_REG(osh, &pcieregs->configaddr, cfg_offset[i]);
138 val = R_REG(osh, &pcieregs->configdata);
139 W_REG(osh, &pcieregs->configdata, val);
140 }
141 }
142 si_setcoreidx(sih, origidx);
143 }
144
145 /* CRWLPCIEGEN2-117 pcie_pipe_Iddq should be controlled
146 * by the L12 state from MAC to save power by putting the
147 * SerDes analog in IDDQ mode
148 */
pcie_serdes_iddqdisable(osl_t * osh,si_t * sih,sbpcieregs_t * sbpcieregs)149 void pcie_serdes_iddqdisable(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs)
150 {
151 sbpcieregs_t *pcie = NULL;
152 uint crwlpciegen2_117_disable = 0;
153 uint32 origidx = si_coreidx(sih);
154
155 crwlpciegen2_117_disable = PCIE_PipeIddqDisable0 | PCIE_PipeIddqDisable1;
156 /* Switch to PCIE2 core */
157 pcie = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0);
158 BCM_REFERENCE(pcie);
159 ASSERT(pcie != NULL);
160
161 OR_REG(osh, &sbpcieregs->control,
162 crwlpciegen2_117_disable);
163
164 si_setcoreidx(sih, origidx);
165 }
166
167 #define PCIE_PMCR_REFUP_MASK 0x3f0001e0
168 #define PCIE_PMCR_REFEXT_MASK 0x400000
169 #define PCIE_PMCR_REFUP_100US 0x38000080
170 #define PCIE_PMCR_REFEXT_100US 0x400000
171
172 /* Set PCIE TRefUp time to 100us */
pcie_set_trefup_time_100us(si_t * sih)173 void pcie_set_trefup_time_100us(si_t *sih)
174 {
175 si_corereg(sih, sih->buscoreidx,
176 OFFSETOF(sbpcieregs_t, configaddr), ~0, PCI_PMCR_REFUP);
177 si_corereg(sih, sih->buscoreidx,
178 OFFSETOF(sbpcieregs_t, configdata), PCIE_PMCR_REFUP_MASK, PCIE_PMCR_REFUP_100US);
179
180 si_corereg(sih, sih->buscoreidx,
181 OFFSETOF(sbpcieregs_t, configaddr), ~0, PCI_PMCR_REFUP_EXT);
182 si_corereg(sih, sih->buscoreidx,
183 OFFSETOF(sbpcieregs_t, configdata), PCIE_PMCR_REFEXT_MASK, PCIE_PMCR_REFEXT_100US);
184 }
185
186 uint32
pcie_cto_to_thresh_default(uint corerev)187 pcie_cto_to_thresh_default(uint corerev)
188 {
189 return REV_GE_69(corerev) ?
190 PCIE_CTO_TO_THRESH_DEFAULT_REV69 : PCIE_CTO_TO_THRESH_DEFAULT;
191 }
192
193 uint32
pcie_corereg(osl_t * osh,volatile void * regs,uint32 offset,uint32 mask,uint32 val)194 pcie_corereg(osl_t *osh, volatile void *regs, uint32 offset, uint32 mask, uint32 val)
195 {
196 volatile uint32 *regsva =
197 (volatile uint32 *)((volatile char *)regs + PCI_16KB0_PCIREGS_OFFSET + offset);
198
199 if (mask || val) {
200 uint32 w = R_REG(osh, regsva);
201 w &= ~mask;
202 w |= val;
203 W_REG(osh, regsva, w);
204 }
205 return (R_REG(osh, regsva));
206 }
207 #endif /* !defined(DONGLEBUILD) || defined(BCMSTANDALONE_TEST) */
208
209 #if defined(DONGLEBUILD)
pcie_coherent_accenable(osl_t * osh,si_t * sih)210 void pcie_coherent_accenable(osl_t *osh, si_t *sih)
211 {
212 pcieregs_t *pcie = NULL;
213 uint32 val;
214 uint32 origidx = si_coreidx(sih);
215
216 if ((pcie = si_setcore(sih, PCIE2_CORE_ID, 0)) != NULL) {
217 /* PCIe BAR1 coherent access enabled */
218 W_REG(osh, PCIE_configindaddr_ALTBASE(pcie, 0), PCIECFGREG_SPROM_CTRL);
219 val = R_REG(osh, PCIE_configinddata_ALTBASE(pcie, 0));
220 val |= (SPROM_BAR1_COHERENT_ACC_EN | SPROM_BAR2_COHERENT_ACC_EN);
221 W_REG(osh, PCIE_configinddata_ALTBASE(pcie, 0), val);
222 }
223
224 si_setcoreidx(sih, origidx);
225 }
226 #endif /* DONGLEBUILD */
227 #endif /* BCMDRIVER */
228