1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for I2C adapter in Rockchip RK3xxx SoC
4 *
5 * Max Schwarz <max.schwarz@online.de>
6 * based on the patches by Rockchip Inc.
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/i2c.h>
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/errno.h>
15 #include <linux/err.h>
16 #include <linux/platform_device.h>
17 #include <linux/io.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/spinlock.h>
21 #include <linux/clk.h>
22 #include <linux/wait.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
25 #include <linux/math64.h>
26 #include <linux/reboot.h>
27 #include <linux/delay.h>
28
29 /* Register Map */
30 #define REG_CON 0x00 /* control register */
31 #define REG_CLKDIV 0x04 /* clock divisor register */
32 #define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */
33 #define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */
34 #define REG_MTXCNT 0x10 /* number of bytes to be transmitted */
35 #define REG_MRXCNT 0x14 /* number of bytes to be received */
36 #define REG_IEN 0x18 /* interrupt enable */
37 #define REG_IPD 0x1c /* interrupt pending */
38 #define REG_FCNT 0x20 /* finished count */
39
40 /* Data buffer offsets */
41 #define TXBUFFER_BASE 0x100
42 #define RXBUFFER_BASE 0x200
43
44 /* REG_CON bits */
45 #define REG_CON_EN BIT(0)
46 enum {
47 REG_CON_MOD_TX = 0, /* transmit data */
48 REG_CON_MOD_REGISTER_TX, /* select register and restart */
49 REG_CON_MOD_RX, /* receive data */
50 REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes
51 * register addr */
52 };
53 #define REG_CON_MOD(mod) ((mod) << 1)
54 #define REG_CON_MOD_MASK (BIT(1) | BIT(2))
55 #define REG_CON_START BIT(3)
56 #define REG_CON_STOP BIT(4)
57 #define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */
58 #define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */
59
60 #define REG_CON_TUNING_MASK GENMASK_ULL(15, 8)
61
62 #define REG_CON_SDA_CFG(cfg) ((cfg) << 8)
63 #define REG_CON_STA_CFG(cfg) ((cfg) << 12)
64 #define REG_CON_STO_CFG(cfg) ((cfg) << 14)
65
66 /* REG_MRXADDR bits */
67 #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */
68
69 /* REG_IEN/REG_IPD bits */
70 #define REG_INT_BTF BIT(0) /* a byte was transmitted */
71 #define REG_INT_BRF BIT(1) /* a byte was received */
72 #define REG_INT_MBTF BIT(2) /* master data transmit finished */
73 #define REG_INT_MBRF BIT(3) /* master data receive finished */
74 #define REG_INT_START BIT(4) /* START condition generated */
75 #define REG_INT_STOP BIT(5) /* STOP condition generated */
76 #define REG_INT_NAKRCV BIT(6) /* NACK received */
77 #define REG_INT_ALL 0xff
78
79 /* Disable i2c all irqs */
80 #define IEN_ALL_DISABLE 0
81
82 /* Constants */
83 #define WAIT_TIMEOUT 1000 /* ms */
84 #define DEFAULT_SCL_RATE (100 * 1000) /* Hz */
85
86 #define RK_I2C_MSG_LEN_MAX 32
87 #define RK_I2C_TX_TIMES_COUNT 8
88 #define RK_I2C_DWORD_TO_BYTE_COUNT 4
89 #define RK_I2C_BYTE_TO_BIT_COUNT 8
90 #define RK_I2C_ADDR_MASK 0x7f
91 #define RK_I2C_BYTE_VALUE_MASK 0xff
92 #define RK_I2C_BUS_FREQ_MIN 1000
93 #define RK_I2C_MIN_HIGH_NS_DIV_ROUND_PARA_ONE 875
94 #define RK_I2C_MIN_HIGH_NS_DIV_ROUND_PARA_TWO 2
95 #define RK_I2C_SCL_RATE_HZ_MUL 8
96 #define RK_I2C_SCL_RATE_HZ_VALUE 1000000
97 #define RK_I2C_MAX_DIV_VALUE 0xffff
98 #define RK_I2C_SCL_MIN_VALUE 2
99 #define RK_I2C_SDA_UPDATA_CFG_TIMES 3
100 #define RK_I2C_S_TO_NS 1000000000
101 #define RK_I2C_SCL_DIV_HIGH_SHIFT_MASK 16
102 #define RK_I2C_MSG_LEN_MIN 4
103 #define RK_I2C_MSG_NUM 2
104 #define RK_I2C_WAIT_POLL_UDELAY_VALUE_FIVE 5
105 #define RK_I2C_WAIT_POLL_UDELAY_VALUE_TEN 10
106 #define RK_I2C_PROBE_RETRY_TIMES 3
107 #define RK_I2C_RESTART_PRIORITY_VALUE 128
108 #define RK_I2C_BIT_MASK_FOUR 4
109 #define RK_I2C_BIT_MASK_TEN 10
110 #define RK_I2C_BIT_MASK_ELEVEN 11
111 #define RK_I2C_BIT_MASK_TWENTY 20
112 #define RK_I2C_BIT_MASK_TWENTY_SIX 26
113 #define RK_I2C_BIT_MASK_TWENTY_SEVEN 27
114 #define RK_I2C_ADAPTER_NUM 2
115
116 /**
117 * struct i2c_spec_values:
118 * @min_hold_start_ns: min hold time (repeated) START condition
119 * @min_low_ns: min LOW period of the SCL clock
120 * @min_high_ns: min HIGH period of the SCL cloc
121 * @min_setup_start_ns: min set-up time for a repeated START conditio
122 * @max_data_hold_ns: max data hold time
123 * @min_data_setup_ns: min data set-up time
124 * @min_setup_stop_ns: min set-up time for STOP condition
125 * @min_hold_buffer_ns: min bus free time between a STOP and
126 * START condition
127 */
128 struct i2c_spec_values {
129 unsigned long min_hold_start_ns;
130 unsigned long min_low_ns;
131 unsigned long min_high_ns;
132 unsigned long min_setup_start_ns;
133 unsigned long max_data_hold_ns;
134 unsigned long min_data_setup_ns;
135 unsigned long min_setup_stop_ns;
136 unsigned long min_hold_buffer_ns;
137 };
138
139 static const struct i2c_spec_values standard_mode_spec = {
140 .min_hold_start_ns = 4000,
141 .min_low_ns = 4700,
142 .min_high_ns = 4000,
143 .min_setup_start_ns = 4700,
144 .max_data_hold_ns = 3450,
145 .min_data_setup_ns = 250,
146 .min_setup_stop_ns = 4000,
147 .min_hold_buffer_ns = 4700,
148 };
149
150 static const struct i2c_spec_values fast_mode_spec = {
151 .min_hold_start_ns = 600,
152 .min_low_ns = 1300,
153 .min_high_ns = 600,
154 .min_setup_start_ns = 600,
155 .max_data_hold_ns = 900,
156 .min_data_setup_ns = 100,
157 .min_setup_stop_ns = 600,
158 .min_hold_buffer_ns = 1300,
159 };
160
161 static const struct i2c_spec_values fast_mode_plus_spec = {
162 .min_hold_start_ns = 260,
163 .min_low_ns = 500,
164 .min_high_ns = 260,
165 .min_setup_start_ns = 260,
166 .max_data_hold_ns = 400,
167 .min_data_setup_ns = 50,
168 .min_setup_stop_ns = 260,
169 .min_hold_buffer_ns = 500,
170 };
171
172 /**
173 * struct rk3x_i2c_calced_timings:
174 * @div_low: Divider output for low
175 * @div_high: Divider output for high
176 * @tuning: Used to adjust setup/hold data time,
177 * setup/hold start time and setup stop time for
178 * v1's calc_timings, the tuning should all be 0
179 * for old hardware anyone using v0's calc_timings.
180 */
181 struct rk3x_i2c_calced_timings {
182 unsigned long div_low;
183 unsigned long div_high;
184 unsigned int tuning;
185 };
186
187 enum rk3x_i2c_state { STATE_IDLE, STATE_READ, STATE_WRITE, STATE_STOP };
188
189 /**
190 * struct rk3x_i2c_soc_data:
191 * @grf_offset: offset inside the grf regmap for setting the i2c type
192 * @calc_timings: Callback function for i2c timing information calculated
193 */
194 struct rk3x_i2c_soc_data {
195 int grf_offset;
196 int (*calc_timings)(unsigned long, struct i2c_timings *, struct rk3x_i2c_calced_timings *);
197 };
198
199 /**
200 * struct rk3x_i2c - private data of the controller
201 * @adap: corresponding I2C adapter
202 * @dev: device for this controller
203 * @soc_data: related soc data struct
204 * @regs: virtual memory area
205 * @clk: function clk for rk3399 or function & Bus clks for others
206 * @pclk: Bus clk for rk3399
207 * @clk_rate_nb: i2c clk rate change notify
208 * @t: I2C known timing information
209 * @lock: spinlock for the i2c bus
210 * @wait: the waitqueue to wait for i2c transfer
211 * @busy: the condition for the event to wait for
212 * @msg: current i2c message
213 * @addr: addr of i2c slave device
214 * @mode: mode of i2c transfer
215 * @is_last_msg: flag determines whether it is the last msg in this transfer
216 * @state: state of i2c transfer
217 * @processed: byte length which has been send or received
218 * @error: error code for i2c transfer
219 * @i2c_restart_nb: make sure the i2c transfer to be finished
220 * @system_restarting: true if system is restarting
221 */
222 struct rk3x_i2c {
223 struct i2c_adapter adap;
224 struct device *dev;
225 const struct rk3x_i2c_soc_data *soc_data;
226
227 /* Hardware resources */
228 void __iomem *regs;
229 struct clk *clk;
230 struct clk *pclk;
231 struct notifier_block clk_rate_nb;
232
233 /* Settings */
234 struct i2c_timings t;
235
236 /* Synchronization & notification */
237 spinlock_t lock;
238 wait_queue_head_t wait;
239 bool busy;
240
241 /* Current message */
242 struct i2c_msg *msg;
243 u8 addr;
244 unsigned int mode;
245 bool is_last_msg;
246
247 /* I2C state machine */
248 enum rk3x_i2c_state state;
249 unsigned int processed;
250 int error;
251 unsigned int suspended : 1;
252
253 struct notifier_block i2c_restart_nb;
254 bool system_restarting;
255 };
256
257 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c);
258 static int rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c, bool sended);
259
rk3x_i2c_wake_up(struct rk3x_i2c * i2c)260 static inline void rk3x_i2c_wake_up(struct rk3x_i2c *i2c)
261 {
262 if (!i2c->system_restarting) {
263 wake_up(&i2c->wait);
264 }
265 }
266
i2c_writel(struct rk3x_i2c * i2c,u32 value,unsigned int offset)267 static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value, unsigned int offset)
268 {
269 writel(value, i2c->regs + offset);
270 }
271
i2c_readl(struct rk3x_i2c * i2c,unsigned int offset)272 static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset)
273 {
274 return readl(i2c->regs + offset);
275 }
276
277 /* Reset all interrupt pending bits */
rk3x_i2c_clean_ipd(struct rk3x_i2c * i2c)278 static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c)
279 {
280 i2c_writel(i2c, REG_INT_ALL, REG_IPD);
281 }
282
rk3x_i2c_disable_irq(struct rk3x_i2c * i2c)283 static inline void rk3x_i2c_disable_irq(struct rk3x_i2c *i2c)
284 {
285 i2c_writel(i2c, IEN_ALL_DISABLE, REG_IEN);
286 }
287
rk3x_i2c_disable(struct rk3x_i2c * i2c)288 static inline void rk3x_i2c_disable(struct rk3x_i2c *i2c)
289 {
290 u32 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
291
292 i2c_writel(i2c, val, REG_CON);
293 }
294
295 /**
296 * Generate a START condition, which triggers a REG_INT_START interrupt.
297 */
rk3x_i2c_start(struct rk3x_i2c * i2c)298 static void rk3x_i2c_start(struct rk3x_i2c *i2c)
299 {
300 u32 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
301 int length = 0;
302
303 /* enable appropriate interrupts */
304 if (i2c->mode == REG_CON_MOD_TX) {
305 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN);
306 i2c->state = STATE_WRITE;
307 length = rk3x_i2c_fill_transmit_buf(i2c, false);
308 } else {
309 /* in any other case, we are going to be reading. */
310 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN);
311 i2c->state = STATE_READ;
312 }
313
314 /* enable adapter with correct mode, send START condition */
315 val |= REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START;
316
317 /* if we want to react to NACK, set ACTACK bit */
318 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
319 val |= REG_CON_ACTACK;
320 }
321
322 i2c_writel(i2c, val, REG_CON);
323
324 /* enable transition */
325 if (i2c->mode == REG_CON_MOD_TX) {
326 i2c_writel(i2c, length, REG_MTXCNT);
327 } else {
328 rk3x_i2c_prepare_read(i2c);
329 }
330 }
331
332 /**
333 * Generate a STOP condition, which triggers a REG_INT_STOP interrupt.
334 *
335 * @error: Error code to return in rk3x_i2c_xfer
336 */
rk3x_i2c_stop(struct rk3x_i2c * i2c,int error)337 static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error)
338 {
339 unsigned int ctrl;
340
341 i2c->processed = 0;
342 i2c->msg = NULL;
343 i2c->error = error;
344
345 if (i2c->is_last_msg) {
346 /* Enable stop interrupt */
347 i2c_writel(i2c, REG_INT_STOP, REG_IEN);
348
349 i2c->state = STATE_STOP;
350
351 ctrl = i2c_readl(i2c, REG_CON);
352 ctrl |= REG_CON_STOP;
353 ctrl &= ~REG_CON_START;
354 i2c_writel(i2c, ctrl, REG_CON);
355 } else {
356 /* Signal rk3x_i2c_xfer to start the next message. */
357 i2c->busy = false;
358 i2c->state = STATE_IDLE;
359
360 /*
361 * The HW is actually not capable of REPEATED START. But we can
362 * get the intended effect by resetting its internal state
363 * and issuing an ordinary START.
364 */
365 ctrl = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
366 i2c_writel(i2c, ctrl, REG_CON);
367
368 /* signal that we are finished with the current msg */
369 rk3x_i2c_wake_up(i2c);
370 }
371 }
372
373 /**
374 * Setup a read according to i2c->msg
375 */
rk3x_i2c_prepare_read(struct rk3x_i2c * i2c)376 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c)
377 {
378 unsigned int len = i2c->msg->len - i2c->processed;
379 u32 con;
380
381 con = i2c_readl(i2c, REG_CON);
382
383 /*
384 * The hw can read up to 32 bytes at a time. If we need more than one
385 * chunk, send an ACK after the last byte of the current chunk.
386 */
387 if (len > RK_I2C_MSG_LEN_MAX) {
388 len = RK_I2C_MSG_LEN_MAX;
389 con &= ~REG_CON_LASTACK;
390 } else {
391 con |= REG_CON_LASTACK;
392 }
393
394 /* make sure we are in plain RX mode if we read a second chunk */
395 if (i2c->processed != 0) {
396 con &= ~REG_CON_MOD_MASK;
397 con |= REG_CON_MOD(REG_CON_MOD_RX);
398 if (con & REG_CON_START) {
399 con &= ~REG_CON_START;
400 }
401 }
402
403 i2c_writel(i2c, con, REG_CON);
404 i2c_writel(i2c, len, REG_MRXCNT);
405 }
406
407 /**
408 * Fill the transmit buffer with data from i2c->msg
409 */
rk3x_i2c_fill_transmit_buf(struct rk3x_i2c * i2c,bool sendend)410 static int rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c, bool sendend)
411 {
412 unsigned int i, j;
413 u32 cnt = 0;
414 u32 val;
415 u8 byte;
416
417 for (i = 0; i < RK_I2C_TX_TIMES_COUNT; ++i) {
418 val = 0;
419 for (j = 0; j < RK_I2C_DWORD_TO_BYTE_COUNT; ++j) {
420 if ((i2c->processed == i2c->msg->len) && (cnt != 0)) {
421 break;
422 }
423
424 if (i2c->processed == 0 && cnt == 0) {
425 byte = (i2c->addr & RK_I2C_ADDR_MASK) << 1;
426 } else {
427 byte = i2c->msg->buf[i2c->processed++];
428 }
429
430 val |= byte << (j * RK_I2C_BYTE_TO_BIT_COUNT);
431 cnt++;
432 }
433
434 i2c_writel(i2c, val, TXBUFFER_BASE + RK_I2C_DWORD_TO_BYTE_COUNT * i);
435
436 if (i2c->processed == i2c->msg->len) {
437 break;
438 }
439 }
440
441 if (sendend) {
442 i2c_writel(i2c, cnt, REG_MTXCNT);
443 }
444
445 return cnt;
446 }
447
448 /* IRQ handlers for individual states */
449
rk3x_i2c_handle_write(struct rk3x_i2c * i2c,unsigned int ipd)450 static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd)
451 {
452 if (!(ipd & REG_INT_MBTF)) {
453 rk3x_i2c_stop(i2c, -EIO);
454 dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd);
455 rk3x_i2c_clean_ipd(i2c);
456 return;
457 }
458
459 /* ack interrupt */
460 i2c_writel(i2c, REG_INT_MBTF, REG_IPD);
461
462 /* are we finished? */
463 if (i2c->processed == i2c->msg->len) {
464 rk3x_i2c_stop(i2c, i2c->error);
465 } else {
466 rk3x_i2c_fill_transmit_buf(i2c, true);
467 }
468 }
469
rk3x_i2c_handle_read(struct rk3x_i2c * i2c,unsigned int ipd)470 static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd)
471 {
472 unsigned int i;
473 unsigned int len = i2c->msg->len - i2c->processed;
474 u32 val;
475 u8 byte;
476
477 /* we only care for MBRF here. */
478 if (!(ipd & REG_INT_MBRF)) {
479 return;
480 }
481
482 /* ack interrupt */
483 i2c_writel(i2c, REG_INT_MBRF | REG_INT_START, REG_IPD);
484
485 /* Can only handle a maximum of 32 bytes at a time */
486 if (len > RK_I2C_MSG_LEN_MAX) {
487 len = RK_I2C_MSG_LEN_MAX;
488 }
489
490 /* read the data from receive buffer */
491 for (i = 0; i < len; ++i) {
492 if (i % RK_I2C_DWORD_TO_BYTE_COUNT == 0) {
493 val = i2c_readl(i2c, RXBUFFER_BASE + (i / RK_I2C_DWORD_TO_BYTE_COUNT) * RK_I2C_DWORD_TO_BYTE_COUNT);
494 }
495
496 byte = (val >> ((i % RK_I2C_DWORD_TO_BYTE_COUNT) * RK_I2C_BYTE_TO_BIT_COUNT)) & RK_I2C_BYTE_VALUE_MASK;
497 i2c->msg->buf[i2c->processed++] = byte;
498 }
499
500 /* are we finished? */
501 if (i2c->processed == i2c->msg->len) {
502 rk3x_i2c_stop(i2c, i2c->error);
503 } else {
504 rk3x_i2c_prepare_read(i2c);
505 }
506 }
507
rk3x_i2c_handle_stop(struct rk3x_i2c * i2c,unsigned int ipd)508 static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd)
509 {
510 unsigned int con;
511
512 if (!(ipd & REG_INT_STOP)) {
513 rk3x_i2c_stop(i2c, -EIO);
514 dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd);
515 rk3x_i2c_clean_ipd(i2c);
516 return;
517 }
518
519 /* ack interrupt */
520 i2c_writel(i2c, REG_INT_STOP, REG_IPD);
521
522 /* disable STOP bit */
523 con = i2c_readl(i2c, REG_CON);
524 con &= ~REG_CON_STOP;
525 i2c_writel(i2c, con, REG_CON);
526
527 i2c->busy = false;
528 i2c->state = STATE_IDLE;
529
530 /* signal rk3x_i2c_xfer that we are finished */
531 rk3x_i2c_wake_up(i2c);
532 }
533
rk3x_i2c_irq(int irqno,void * dev_id)534 static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id)
535 {
536 struct rk3x_i2c *i2c = dev_id;
537 unsigned int ipd;
538 spin_lock(&i2c->lock);
539 ipd = i2c_readl(i2c, REG_IPD);
540 if (i2c->state == STATE_IDLE) {
541 dev_warn_ratelimited(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd);
542 rk3x_i2c_clean_ipd(i2c);
543 goto out;
544 }
545 dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd);
546 /* Clean interrupt bits we don't care about */
547 ipd &= ~(REG_INT_BRF | REG_INT_BTF);
548 if (ipd & REG_INT_NAKRCV) {
549 /*
550 * We got a NACK in the last operation. Depending on whether
551 * IGNORE_NAK is set, we have to stop the operation and report
552 * an error.
553 */
554 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD);
555
556 ipd &= ~REG_INT_NAKRCV;
557
558 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
559 rk3x_i2c_stop(i2c, -ENXIO);
560 goto out;
561 }
562 }
563 /* is there anything left to handle? */
564 if ((ipd & REG_INT_ALL) == 0) {
565 goto out;
566 }
567 switch (i2c->state) {
568 case STATE_WRITE:
569 rk3x_i2c_handle_write(i2c, ipd);
570 break;
571 case STATE_READ:
572 rk3x_i2c_handle_read(i2c, ipd);
573 break;
574 case STATE_STOP:
575 rk3x_i2c_handle_stop(i2c, ipd);
576 break;
577 case STATE_IDLE:
578 break;
579 }
580
581 out:
582 spin_unlock(&i2c->lock);
583 return IRQ_HANDLED;
584 }
585
586 /**
587 * Get timing values of I2C specification
588 *
589 * @speed: Desired SCL frequency
590 *
591 * Returns: Matched i2c spec values.
592 */
rk3x_i2c_get_spec(unsigned int speed)593 static const struct i2c_spec_values *rk3x_i2c_get_spec(unsigned int speed)
594 {
595 if (speed <= I2C_MAX_STANDARD_MODE_FREQ) {
596 return &standard_mode_spec;
597 } else if (speed <= I2C_MAX_FAST_MODE_FREQ) {
598 return &fast_mode_spec;
599 } else {
600 return &fast_mode_plus_spec;
601 }
602 }
603
604 /**
605 * Calculate divider values for desired SCL frequency
606 *
607 * @clk_rate: I2C input clock rate
608 * @t: Known I2C timing information
609 * @t_calc: Caculated rk3x private timings that would be written into regs
610 *
611 * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
612 * a best-effort divider value is returned in divs. If the target rate is
613 * too high, we silently use the highest possible rate.
614 */
rk3x_i2c_v0_calc_timings(unsigned long clk_rate,struct i2c_timings * t,struct rk3x_i2c_calced_timings * t_calc)615 static int rk3x_i2c_v0_calc_timings(unsigned long clk_rate, struct i2c_timings *t,
616 struct rk3x_i2c_calced_timings *t_calc)
617 {
618 unsigned long min_low_ns, min_high_ns;
619 unsigned long max_low_ns, min_total_ns;
620
621 unsigned long clk_rate_khz, scl_rate_khz;
622
623 unsigned long min_low_div, min_high_div;
624 unsigned long max_low_div;
625
626 unsigned long min_div_for_hold, min_total_div;
627 unsigned long extra_div, extra_low_div, ideal_low_div;
628
629 unsigned long data_hold_buffer_ns = 50;
630 const struct i2c_spec_values *spec;
631 int ret = 0;
632
633 /* Only support standard-mode and fast-mode */
634 if (WARN_ON(t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ)) {
635 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
636 }
637
638 /* prevent scl_rate_khz from becoming 0 */
639 if (WARN_ON(t->bus_freq_hz < RK_I2C_BUS_FREQ_MIN)) {
640 t->bus_freq_hz = RK_I2C_BUS_FREQ_MIN;
641 }
642
643 /*
644 * min_low_ns: The minimum number of ns we need to hold low to
645 * meet I2C specification, should include fall time.
646 * min_high_ns: The minimum number of ns we need to hold high to
647 * meet I2C specification, should include rise time.
648 * max_low_ns: The maximum number of ns we can hold low to meet
649 * I2C specification.
650 *
651 * Note: max_low_ns should be (maximum data hold time * 2 - buffer)
652 * This is because the i2c host on Rockchip holds the data line
653 * for half the low time.
654 */
655 spec = rk3x_i2c_get_spec(t->bus_freq_hz);
656 min_high_ns = t->scl_rise_ns + spec->min_high_ns;
657
658 /*
659 * Timings for repeated start:
660 * - controller appears to drop SDA at .875x (7/8) programmed clk high.
661 * - controller appears to keep SCL high for 2x programmed clk high.
662 *
663 * We need to account for those rules in picking our "high" time so
664 * we meet tSU;STA and tHD;STA times.
665 */
666 min_high_ns = max(min_high_ns, DIV_ROUND_UP((t->scl_rise_ns + spec->min_setup_start_ns) * RK_I2C_BUS_FREQ_MIN,
667 RK_I2C_MIN_HIGH_NS_DIV_ROUND_PARA_ONE));
668 min_high_ns =
669 max(min_high_ns, DIV_ROUND_UP((t->scl_rise_ns + spec->min_setup_start_ns + t->sda_fall_ns + spec->min_high_ns),
670 RK_I2C_MIN_HIGH_NS_DIV_ROUND_PARA_TWO));
671
672 min_low_ns = t->scl_fall_ns + spec->min_low_ns;
673 max_low_ns = spec->max_data_hold_ns * RK_I2C_MIN_HIGH_NS_DIV_ROUND_PARA_TWO - data_hold_buffer_ns;
674 min_total_ns = min_low_ns + min_high_ns;
675
676 /* Adjust to avoid overflow */
677 clk_rate_khz = DIV_ROUND_UP(clk_rate, RK_I2C_BUS_FREQ_MIN);
678 scl_rate_khz = t->bus_freq_hz / RK_I2C_BUS_FREQ_MIN;
679
680 /*
681 * We need the total div to be >= this number
682 * so we don't clock too fast.
683 */
684 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * RK_I2C_SCL_RATE_HZ_MUL);
685
686 /* These are the min dividers needed for min hold times. */
687 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, RK_I2C_SCL_RATE_HZ_MUL * RK_I2C_SCL_RATE_HZ_VALUE);
688 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, RK_I2C_SCL_RATE_HZ_MUL * RK_I2C_SCL_RATE_HZ_VALUE);
689 min_div_for_hold = (min_low_div + min_high_div);
690
691 /*
692 * This is the maximum divider so we don't go over the maximum.
693 * We don't round up here (we round down) since this is a maximum.
694 */
695 max_low_div = clk_rate_khz * max_low_ns / (RK_I2C_SCL_RATE_HZ_MUL * RK_I2C_SCL_RATE_HZ_VALUE);
696
697 if (min_low_div > max_low_div) {
698 WARN_ONCE(true, "Conflicting, min_low_div %lu, max_low_div %lu\n", min_low_div, max_low_div);
699 max_low_div = min_low_div;
700 }
701
702 if (min_div_for_hold > min_total_div) {
703 /*
704 * Time needed to meet hold requirements is important.
705 * Just use that.
706 */
707 t_calc->div_low = min_low_div;
708 t_calc->div_high = min_high_div;
709 } else {
710 /*
711 * We've got to distribute some time among the low and high
712 * so we don't run too fast.
713 */
714 extra_div = min_total_div - min_div_for_hold;
715 /*
716 * We'll try to split things up perfectly evenly,
717 * biasing slightly towards having a higher div
718 * for low (spend more time low).
719 */
720 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, scl_rate_khz * RK_I2C_SCL_RATE_HZ_MUL * min_total_ns);
721 /* Don't allow it to go over the maximum */
722 if (ideal_low_div > max_low_div) {
723 ideal_low_div = max_low_div;
724 }
725 /*
726 * Handle when the ideal low div is going to take up
727 * more than we have.
728 */
729 if (ideal_low_div > min_low_div + extra_div) {
730 ideal_low_div = min_low_div + extra_div;
731 }
732 /* Give low the "ideal" and give high whatever extra is left */
733 extra_low_div = ideal_low_div - min_low_div;
734 t_calc->div_low = ideal_low_div;
735 t_calc->div_high = min_high_div + (extra_div - extra_low_div);
736 }
737
738 /*
739 * Adjust to the fact that the hardware has an implicit "+1".
740 * NOTE: Above calculations always produce div_low > 0 and div_high > 0.
741 */
742 t_calc->div_low--;
743 t_calc->div_high--;
744
745 /* Give the tuning value 0, that would not update con register */
746 t_calc->tuning = 0;
747 /* Maximum divider supported by hw is 0xffff */
748 if (t_calc->div_low > RK_I2C_MAX_DIV_VALUE) {
749 t_calc->div_low = RK_I2C_MAX_DIV_VALUE;
750 ret = -EINVAL;
751 }
752
753 if (t_calc->div_high > RK_I2C_MAX_DIV_VALUE) {
754 t_calc->div_high = RK_I2C_MAX_DIV_VALUE;
755 ret = -EINVAL;
756 }
757
758 return ret;
759 }
760
761 /**
762 * Calculate timing values for desired SCL frequency
763 *
764 * @clk_rate: I2C input clock rate
765 * @t: Known I2C timing information
766 * @t_calc: Caculated rk3x private timings that would be written into regs
767 *
768 * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
769 * a best-effort divider value is returned in divs. If the target rate is
770 * too high, we silently use the highest possible rate.
771 * The following formulas are v1's method to calculate timings.
772 *
773 * l = divl + 1;
774 * h = divh + 1;
775 * s = sda_update_config + 1;
776 * u = start_setup_config + 1;
777 * p = stop_setup_config + 1;
778 * T = Tclk_i2c;
779 *
780 * tHigh = 8 * h * T;
781 * tLow = 8 * l * T;
782 *
783 * tHD;sda = (l * s + 1) * T;
784 * tSU;sda = [(8 - s) * l + 1] * T;
785 * tI2C = 8 * (l + h) * T;
786 *
787 * tSU;sta = (8h * u + 1) * T;
788 * tHD;sta = [8h * (u + 1) - 1] * T;
789 * tSU;sto = (8h * p + 1) * T;
790 */
rk3x_i2c_v1_calc_timings(unsigned long clk_rate,struct i2c_timings * t,struct rk3x_i2c_calced_timings * t_calc)791 static int rk3x_i2c_v1_calc_timings(unsigned long clk_rate, struct i2c_timings *t,
792 struct rk3x_i2c_calced_timings *t_calc)
793 {
794 unsigned long min_low_ns, min_high_ns;
795 unsigned long min_setup_start_ns, min_setup_data_ns;
796 unsigned long min_setup_stop_ns, max_hold_data_ns;
797
798 unsigned long clk_rate_khz, scl_rate_khz;
799
800 unsigned long min_low_div, min_high_div;
801
802 unsigned long min_div_for_hold, min_total_div;
803 unsigned long extra_div, extra_low_div;
804 unsigned long sda_update_cfg, stp_sta_cfg, stp_sto_cfg;
805
806 const struct i2c_spec_values *spec;
807 int ret = 0;
808
809 /* Support standard-mode, fast-mode and fast-mode plus */
810 if (WARN_ON(t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)) {
811 t->bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ;
812 }
813
814 /* prevent scl_rate_khz from becoming 0 */
815 if (WARN_ON(t->bus_freq_hz < RK_I2C_BUS_FREQ_MIN)) {
816 t->bus_freq_hz = RK_I2C_BUS_FREQ_MIN;
817 }
818
819 /*
820 * min_low_ns: The minimum number of ns we need to hold low to
821 * meet I2C specification, should include fall time.
822 * min_high_ns: The minimum number of ns we need to hold high to
823 * meet I2C specification, should include rise time.
824 */
825 spec = rk3x_i2c_get_spec(t->bus_freq_hz);
826
827 /* calculate min-divh and min-divl */
828 clk_rate_khz = DIV_ROUND_UP(clk_rate, RK_I2C_BUS_FREQ_MIN);
829 scl_rate_khz = t->bus_freq_hz / RK_I2C_BUS_FREQ_MIN;
830 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * RK_I2C_SCL_RATE_HZ_MUL);
831
832 min_high_ns = t->scl_rise_ns + spec->min_high_ns;
833 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, RK_I2C_SCL_RATE_HZ_MUL * RK_I2C_SCL_RATE_HZ_VALUE);
834
835 min_low_ns = t->scl_fall_ns + spec->min_low_ns;
836 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, RK_I2C_SCL_RATE_HZ_MUL * RK_I2C_SCL_RATE_HZ_VALUE);
837
838 /*
839 * Final divh and divl must be greater than 0, otherwise the
840 * hardware would not output the i2c clk.
841 */
842 min_high_div = (min_high_div < 1) ? RK_I2C_SCL_MIN_VALUE : min_high_div;
843 min_low_div = (min_low_div < 1) ? RK_I2C_SCL_MIN_VALUE : min_low_div;
844
845 /* These are the min dividers needed for min hold times. */
846 min_div_for_hold = (min_low_div + min_high_div);
847
848 /*
849 * This is the maximum divider so we don't go over the maximum.
850 * We don't round up here (we round down) since this is a maximum.
851 */
852 if (min_div_for_hold >= min_total_div) {
853 /*
854 * Time needed to meet hold requirements is important.
855 * Just use that.
856 */
857 t_calc->div_low = min_low_div;
858 t_calc->div_high = min_high_div;
859 } else {
860 /*
861 * We've got to distribute some time among the low and high
862 * so we don't run too fast.
863 * We'll try to split things up by the scale of min_low_div and
864 * min_high_div, biasing slightly towards having a higher div
865 * for low (spend more time low).
866 */
867 extra_div = min_total_div - min_div_for_hold;
868 extra_low_div = DIV_ROUND_UP(min_low_div * extra_div, min_div_for_hold);
869
870 t_calc->div_low = min_low_div + extra_low_div;
871 t_calc->div_high = min_high_div + (extra_div - extra_low_div);
872 }
873
874 /*
875 * calculate sda data hold count by the rules, data_upd_st:3
876 * is a appropriate value to reduce calculated times.
877 */
878 for (sda_update_cfg = RK_I2C_SDA_UPDATA_CFG_TIMES; sda_update_cfg > 0; sda_update_cfg--) {
879 max_hold_data_ns =
880 DIV_ROUND_UP((sda_update_cfg * (t_calc->div_low) + 1) * RK_I2C_SCL_RATE_HZ_VALUE, clk_rate_khz);
881 min_setup_data_ns =
882 DIV_ROUND_UP(((RK_I2C_SCL_RATE_HZ_MUL - sda_update_cfg) * (t_calc->div_low) + 1) * RK_I2C_SCL_RATE_HZ_VALUE,
883 clk_rate_khz);
884 if ((max_hold_data_ns < spec->max_data_hold_ns) && (min_setup_data_ns > spec->min_data_setup_ns)) {
885 break;
886 }
887 }
888
889 /* calculate setup start config */
890 min_setup_start_ns = t->scl_rise_ns + spec->min_setup_start_ns;
891 stp_sta_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_start_ns - RK_I2C_SCL_RATE_HZ_VALUE,
892 RK_I2C_SCL_RATE_HZ_MUL * RK_I2C_SCL_RATE_HZ_VALUE * (t_calc->div_high));
893
894 /* calculate setup stop config */
895 min_setup_stop_ns = t->scl_rise_ns + spec->min_setup_stop_ns;
896 stp_sto_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_stop_ns - RK_I2C_SCL_RATE_HZ_VALUE,
897 RK_I2C_SCL_RATE_HZ_MUL * RK_I2C_SCL_RATE_HZ_VALUE * (t_calc->div_high));
898
899 t_calc->tuning =
900 REG_CON_SDA_CFG(--sda_update_cfg) | REG_CON_STA_CFG(--stp_sta_cfg) | REG_CON_STO_CFG(--stp_sto_cfg);
901
902 t_calc->div_low--;
903 t_calc->div_high--;
904
905 /* Maximum divider supported by hw is 0xffff */
906 if (t_calc->div_low > RK_I2C_MAX_DIV_VALUE) {
907 t_calc->div_low = RK_I2C_MAX_DIV_VALUE;
908 ret = -EINVAL;
909 }
910
911 if (t_calc->div_high > RK_I2C_MAX_DIV_VALUE) {
912 t_calc->div_high = RK_I2C_MAX_DIV_VALUE;
913 ret = -EINVAL;
914 }
915
916 return ret;
917 }
918
rk3x_i2c_adapt_div(struct rk3x_i2c * i2c,unsigned long clk_rate)919 static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
920 {
921 struct i2c_timings *t = &i2c->t;
922 struct rk3x_i2c_calced_timings calc;
923 u64 t_low_ns, t_high_ns;
924 unsigned long flags;
925 u32 val;
926 int ret;
927
928 ret = i2c->soc_data->calc_timings(clk_rate, t, &calc);
929 WARN_ONCE(ret != 0, "Could not reach SCL freq %u", t->bus_freq_hz);
930
931 clk_enable(i2c->pclk);
932
933 spin_lock_irqsave(&i2c->lock, flags);
934 val = i2c_readl(i2c, REG_CON);
935 val &= ~REG_CON_TUNING_MASK;
936 val |= calc.tuning;
937 i2c_writel(i2c, val, REG_CON);
938 i2c_writel(i2c, (calc.div_high << RK_I2C_SCL_DIV_HIGH_SHIFT_MASK) | (calc.div_low & RK_I2C_MAX_DIV_VALUE),
939 REG_CLKDIV);
940 spin_unlock_irqrestore(&i2c->lock, flags);
941
942 clk_disable(i2c->pclk);
943
944 t_low_ns = div_u64(((u64)calc.div_low + 1) * RK_I2C_SCL_RATE_HZ_MUL * RK_I2C_S_TO_NS, clk_rate);
945 t_high_ns = div_u64(((u64)calc.div_high + 1) * RK_I2C_SCL_RATE_HZ_MUL * RK_I2C_S_TO_NS, clk_rate);
946 }
947
948 /**
949 * rk3x_i2c_clk_notifier_cb - Clock rate change callback
950 * @nb: Pointer to notifier block
951 * @event: Notification reason
952 * @data: Pointer to notification data object
953 *
954 * The callback checks whether a valid bus frequency can be generated after the
955 * change. If so, the change is acknowledged, otherwise the change is aborted.
956 * New dividers are written to the HW in the pre- or post change notification
957 * depending on the scaling direction.
958 *
959 * Code adapted from i2c-cadence.c.
960 *
961 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
962 * to acknowledge the change, NOTIFY_DONE if the notification is
963 * considered irrelevant.
964 */
rk3x_i2c_clk_notifier_cb(struct notifier_block * nb,unsigned long event,void * data)965 static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long event, void *data)
966 {
967 struct clk_notifier_data *ndata = data;
968 struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb);
969 struct rk3x_i2c_calced_timings calc;
970
971 switch (event) {
972 case PRE_RATE_CHANGE:
973 /*
974 * Try the calculation (but don't store the result) ahead of
975 * time to see if we need to block the clock change. Timings
976 * shouldn't actually take effect until rk3x_i2c_adapt_div().
977 */
978 if (i2c->soc_data->calc_timings(ndata->new_rate, &i2c->t, &calc) != 0) {
979 return NOTIFY_STOP;
980 }
981
982 /* scale up */
983 if (ndata->new_rate > ndata->old_rate) {
984 rk3x_i2c_adapt_div(i2c, ndata->new_rate);
985 }
986
987 return NOTIFY_OK;
988 case POST_RATE_CHANGE:
989 /* scale down */
990 if (ndata->new_rate < ndata->old_rate) {
991 rk3x_i2c_adapt_div(i2c, ndata->new_rate);
992 }
993 return NOTIFY_OK;
994 case ABORT_RATE_CHANGE:
995 /* scale up */
996 if (ndata->new_rate > ndata->old_rate) {
997 rk3x_i2c_adapt_div(i2c, ndata->old_rate);
998 }
999 return NOTIFY_OK;
1000 default:
1001 return NOTIFY_DONE;
1002 }
1003 }
1004
1005 /**
1006 * Setup I2C registers for an I2C operation specified by msgs, num.
1007 *
1008 * Must be called with i2c->lock held.
1009 *
1010 * @msgs: I2C msgs to process
1011 * @num: Number of msgs
1012 *
1013 * returns: Number of I2C msgs processed or negative in case of error
1014 */
rk3x_i2c_setup(struct rk3x_i2c * i2c,struct i2c_msg * msgs,int num)1015 static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num)
1016 {
1017 u32 addr = (msgs[0].addr & RK_I2C_ADDR_MASK) << 1;
1018 int ret = 0;
1019
1020 /*
1021 * The I2C adapter can issue a small (len < 4) write packet before
1022 * reading. This speeds up SMBus-style register reads.
1023 * The MRXADDR/MRXRADDR hold the slave address and the slave register
1024 * address in this case.
1025 */
1026
1027 if (num >= RK_I2C_MSG_NUM && msgs[0].len < RK_I2C_MSG_LEN_MIN && !(msgs[0].flags & I2C_M_RD) &&
1028 (msgs[1].flags & I2C_M_RD)) {
1029 u32 reg_addr = 0;
1030 int i;
1031
1032 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n", addr >> 1);
1033
1034 /* Fill MRXRADDR with the register address(es) */
1035 for (i = 0; i < msgs[0].len; ++i) {
1036 reg_addr |= msgs[0].buf[i] << (i * RK_I2C_BYTE_TO_BIT_COUNT);
1037 reg_addr |= REG_MRXADDR_VALID(i);
1038 }
1039
1040 /* msgs[0] is handled by hw. */
1041 i2c->msg = &msgs[1];
1042
1043 i2c->mode = REG_CON_MOD_REGISTER_TX;
1044
1045 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR);
1046 i2c_writel(i2c, reg_addr, REG_MRXRADDR);
1047
1048 ret = 0x2;
1049 } else {
1050 /*
1051 * We'll have to do it the boring way and process the msgs
1052 * one-by-one.
1053 */
1054
1055 if (msgs[0].flags & I2C_M_RD) {
1056 addr |= 1; /* set read bit */
1057
1058 /*
1059 * We have to transmit the slave addr first. Use
1060 * MOD_REGISTER_TX for that purpose.
1061 */
1062 i2c->mode = REG_CON_MOD_REGISTER_TX;
1063 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR);
1064 i2c_writel(i2c, 0, REG_MRXRADDR);
1065 } else {
1066 i2c->mode = REG_CON_MOD_TX;
1067 }
1068
1069 i2c->msg = &msgs[0];
1070
1071 ret = 1;
1072 }
1073
1074 i2c->addr = msgs[0].addr;
1075 i2c->busy = true;
1076 i2c->processed = 0;
1077 i2c->error = 0;
1078
1079 rk3x_i2c_clean_ipd(i2c);
1080
1081 return ret;
1082 }
1083
rk3x_i2c_wait_xfer_poll(struct rk3x_i2c * i2c)1084 static int rk3x_i2c_wait_xfer_poll(struct rk3x_i2c *i2c)
1085 {
1086 ktime_t timeout = ktime_add_ms(ktime_get(), WAIT_TIMEOUT);
1087
1088 while (READ_ONCE(i2c->busy) && ktime_compare(ktime_get(), timeout) < 0) {
1089 udelay(RK_I2C_WAIT_POLL_UDELAY_VALUE_FIVE);
1090 rk3x_i2c_irq(0, i2c);
1091 }
1092
1093 return !i2c->busy;
1094 }
1095
rk3x_i2c_xfer_common(struct i2c_adapter * adap,struct i2c_msg * msgs,int num,bool polling)1096 static int rk3x_i2c_xfer_common(struct i2c_adapter *adap, struct i2c_msg *msgs, int num, bool polling)
1097 {
1098 struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data;
1099 unsigned long timeout, flags;
1100 u32 val;
1101 int ret = 0;
1102 int i;
1103 if (i2c->suspended) {
1104 return -EACCES;
1105 }
1106 spin_lock_irqsave(&i2c->lock, flags);
1107 clk_enable(i2c->clk);
1108 clk_enable(i2c->pclk);
1109 i2c->is_last_msg = false;
1110 /*
1111 * Process msgs. We can handle more than one message at once (see
1112 * rk3x_i2c_setup()).
1113 */
1114 for (i = 0; i < num; i += ret) {
1115 ret = rk3x_i2c_setup(i2c, msgs + i, num - i);
1116 if (ret < 0) {
1117 dev_err(i2c->dev, "rk3x_i2c_setup() failed\n");
1118 break;
1119 }
1120 if (i + ret >= num) {
1121 i2c->is_last_msg = true;
1122 }
1123 rk3x_i2c_start(i2c);
1124 spin_unlock_irqrestore(&i2c->lock, flags);
1125 if (!polling) {
1126 timeout = wait_event_timeout(i2c->wait, !i2c->busy, msecs_to_jiffies(WAIT_TIMEOUT));
1127 } else {
1128 timeout = rk3x_i2c_wait_xfer_poll(i2c);
1129 }
1130 spin_lock_irqsave(&i2c->lock, flags);
1131 if (timeout == 0) {
1132 dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n", i2c_readl(i2c, REG_IPD), i2c->state);
1133 /* Force a STOP condition without interrupt */
1134 rk3x_i2c_disable_irq(i2c);
1135 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
1136 val |= REG_CON_EN | REG_CON_STOP;
1137 i2c_writel(i2c, val, REG_CON);
1138 i2c->state = STATE_IDLE;
1139 ret = -ETIMEDOUT;
1140 break;
1141 }
1142 if (i2c->error) {
1143 ret = i2c->error;
1144 break;
1145 }
1146 }
1147
1148 rk3x_i2c_disable_irq(i2c);
1149 rk3x_i2c_disable(i2c);
1150
1151 clk_disable(i2c->pclk);
1152 clk_disable(i2c->clk);
1153
1154 spin_unlock_irqrestore(&i2c->lock, flags);
1155
1156 return ret < 0 ? ret : num;
1157 }
1158
rk3x_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)1159 static int rk3x_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
1160 {
1161 return rk3x_i2c_xfer_common(adap, msgs, num, false);
1162 }
1163
rk3x_i2c_xfer_polling(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)1164 static int rk3x_i2c_xfer_polling(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
1165 {
1166 return rk3x_i2c_xfer_common(adap, msgs, num, true);
1167 }
1168
rk3x_i2c_restart_notify(struct notifier_block * this,unsigned long mode,void * cmd)1169 static int rk3x_i2c_restart_notify(struct notifier_block *this, unsigned long mode, void *cmd)
1170 {
1171 struct rk3x_i2c *i2c = container_of(this, struct rk3x_i2c, i2c_restart_nb);
1172 int tmo = WAIT_TIMEOUT * USEC_PER_MSEC;
1173 u32 val;
1174
1175 if (i2c->state != STATE_IDLE) {
1176 i2c->system_restarting = true;
1177 /* complete the unfinished job */
1178 while (tmo-- && i2c->busy) {
1179 udelay(1);
1180 rk3x_i2c_irq(0, i2c);
1181 }
1182 }
1183
1184 if (tmo <= 0) {
1185 dev_err(i2c->dev, "restart timeout, ipd: 0x%02x, state: %d\n", i2c_readl(i2c, REG_IPD), i2c->state);
1186
1187 /* Force a STOP condition without interrupt */
1188 i2c_writel(i2c, 0, REG_IEN);
1189 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
1190 val |= REG_CON_EN | REG_CON_STOP;
1191 i2c_writel(i2c, val, REG_CON);
1192
1193 udelay(RK_I2C_WAIT_POLL_UDELAY_VALUE_TEN);
1194 i2c->state = STATE_IDLE;
1195 }
1196
1197 return NOTIFY_DONE;
1198 }
1199
rk3x_i2c_suspend_noirq(struct device * dev)1200 static __maybe_unused int rk3x_i2c_suspend_noirq(struct device *dev)
1201 {
1202 struct rk3x_i2c *i2c = dev_get_drvdata(dev);
1203
1204 /*
1205 * Below code is needed only to ensure that there are no
1206 * activities on I2C bus. if at this moment any driver
1207 * is trying to use I2C bus - this may cause i2c timeout.
1208 *
1209 * So forbid access to I2C device using i2c->suspended flag.
1210 */
1211 i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
1212 i2c->suspended = 1;
1213 i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
1214
1215 return 0;
1216 }
1217
rk3x_i2c_resume_noirq(struct device * dev)1218 static __maybe_unused int rk3x_i2c_resume_noirq(struct device *dev)
1219 {
1220 struct rk3x_i2c *i2c = dev_get_drvdata(dev);
1221
1222 rk3x_i2c_adapt_div(i2c, clk_get_rate(i2c->clk));
1223
1224 /* Allow access to I2C bus */
1225 i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
1226 i2c->suspended = 0;
1227 i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
1228
1229 return 0;
1230 }
1231
rk3x_i2c_func(struct i2c_adapter * adap)1232 static u32 rk3x_i2c_func(struct i2c_adapter *adap)
1233 {
1234 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
1235 }
1236
1237 static const struct i2c_algorithm rk3x_i2c_algorithm = {
1238 .master_xfer = rk3x_i2c_xfer,
1239 .master_xfer_atomic = rk3x_i2c_xfer_polling,
1240 .functionality = rk3x_i2c_func,
1241 };
1242
1243 static const struct rk3x_i2c_soc_data rv1108_soc_data = {
1244 .grf_offset = 0x408,
1245 .calc_timings = rk3x_i2c_v1_calc_timings,
1246 };
1247
1248 static const struct rk3x_i2c_soc_data rv1126_soc_data = {
1249 .grf_offset = 0x118,
1250 .calc_timings = rk3x_i2c_v1_calc_timings,
1251 };
1252
1253 static const struct rk3x_i2c_soc_data rk3066_soc_data = {
1254 .grf_offset = 0x154,
1255 .calc_timings = rk3x_i2c_v0_calc_timings,
1256 };
1257
1258 static const struct rk3x_i2c_soc_data rk3188_soc_data = {
1259 .grf_offset = 0x0a4,
1260 .calc_timings = rk3x_i2c_v0_calc_timings,
1261 };
1262
1263 static const struct rk3x_i2c_soc_data rk3228_soc_data = {
1264 .grf_offset = -1,
1265 .calc_timings = rk3x_i2c_v0_calc_timings,
1266 };
1267
1268 static const struct rk3x_i2c_soc_data rk3288_soc_data = {
1269 .grf_offset = -1,
1270 .calc_timings = rk3x_i2c_v0_calc_timings,
1271 };
1272
1273 static const struct rk3x_i2c_soc_data rk3399_soc_data = {
1274 .grf_offset = -1,
1275 .calc_timings = rk3x_i2c_v1_calc_timings,
1276 };
1277
1278 static const struct of_device_id rk3x_i2c_match[] = {
1279 {.compatible = "rockchip,rv1108-i2c", .data = &rv1108_soc_data},
1280 {.compatible = "rockchip,rv1126-i2c", .data = &rv1126_soc_data},
1281 {.compatible = "rockchip,rk3066-i2c", .data = &rk3066_soc_data},
1282 {.compatible = "rockchip,rk3188-i2c", .data = &rk3188_soc_data},
1283 {.compatible = "rockchip,rk3228-i2c", .data = &rk3228_soc_data},
1284 {.compatible = "rockchip,rk3288-i2c", .data = &rk3288_soc_data},
1285 {.compatible = "rockchip,rk3399-i2c", .data = &rk3399_soc_data},
1286 {},
1287 };
1288 MODULE_DEVICE_TABLE(of, rk3x_i2c_match);
1289
rk3x_i2c_probe(struct platform_device * pdev)1290 static int rk3x_i2c_probe(struct platform_device *pdev)
1291 {
1292 struct device_node *np = pdev->dev.of_node;
1293 const struct of_device_id *match;
1294 struct rk3x_i2c *i2c;
1295 int ret = 0;
1296 u32 value;
1297 int irq;
1298 unsigned long clk_rate;
1299
1300 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL);
1301 if (!i2c) {
1302 return -ENOMEM;
1303 }
1304
1305 match = of_match_node(rk3x_i2c_match, np);
1306 i2c->soc_data = match->data;
1307
1308 /* use common interface to get I2C timing properties */
1309 i2c_parse_fw_timings(&pdev->dev, &i2c->t, true);
1310
1311 strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
1312 i2c->adap.owner = THIS_MODULE;
1313 i2c->adap.algo = &rk3x_i2c_algorithm;
1314 i2c->adap.retries = RK_I2C_PROBE_RETRY_TIMES;
1315 i2c->adap.dev.of_node = np;
1316 i2c->adap.algo_data = i2c;
1317 i2c->adap.dev.parent = &pdev->dev;
1318
1319 i2c->dev = &pdev->dev;
1320
1321 spin_lock_init(&i2c->lock);
1322 init_waitqueue_head(&i2c->wait);
1323
1324 i2c->i2c_restart_nb.notifier_call = rk3x_i2c_restart_notify;
1325 i2c->i2c_restart_nb.priority = RK_I2C_RESTART_PRIORITY_VALUE;
1326 ret = register_pre_restart_handler(&i2c->i2c_restart_nb);
1327 if (ret) {
1328 dev_err(&pdev->dev, "failed to setup i2c restart handler.\n");
1329 return ret;
1330 }
1331
1332 i2c->regs = devm_platform_ioremap_resource(pdev, 0);
1333 if (IS_ERR(i2c->regs)) {
1334 return PTR_ERR(i2c->regs);
1335 }
1336
1337 /*
1338 * Switch to new interface if the SoC also offers the old one.
1339 * The control bit is located in the GRF register space.
1340 */
1341 if (i2c->soc_data->grf_offset >= 0) {
1342 struct regmap *grf;
1343
1344 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1345 if (!IS_ERR(grf)) {
1346 int bus_nr;
1347
1348 /* Try to set the I2C adapter number from dt */
1349 bus_nr = of_alias_get_id(np, "i2c");
1350 if (bus_nr < 0) {
1351 dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias");
1352 return -EINVAL;
1353 }
1354
1355 if (i2c->soc_data == &rv1108_soc_data && bus_nr == RK_I2C_ADAPTER_NUM) {
1356 /* rv1108 i2c2 set grf offset-0x408, bit-10 */
1357 value = BIT(RK_I2C_BIT_MASK_TWENTY_SIX) | BIT(RK_I2C_BIT_MASK_TEN);
1358 } else if (i2c->soc_data == &rv1126_soc_data && bus_nr == RK_I2C_ADAPTER_NUM) {
1359 /* rv1126 i2c2 set pmugrf offset-0x118, bit-4 */
1360 value = BIT(RK_I2C_BIT_MASK_TWENTY) | BIT(RK_I2C_BIT_MASK_FOUR);
1361 } else {
1362 /* rk3xxx 27+i: write mask, 11+i: value */
1363 value = BIT(RK_I2C_BIT_MASK_TWENTY_SEVEN + bus_nr) | BIT(RK_I2C_BIT_MASK_ELEVEN + bus_nr);
1364 }
1365
1366 ret = regmap_write(grf, i2c->soc_data->grf_offset, value);
1367 if (ret != 0) {
1368 dev_err(i2c->dev, "Could not write to GRF: %d\n", ret);
1369 return ret;
1370 }
1371 }
1372 }
1373
1374 /* IRQ setup */
1375 irq = platform_get_irq(pdev, 0);
1376 if (irq < 0) {
1377 return irq;
1378 }
1379
1380 ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq, 0, dev_name(&pdev->dev), i2c);
1381 if (ret < 0) {
1382 dev_err(&pdev->dev, "cannot request IRQ\n");
1383 return ret;
1384 }
1385
1386 platform_set_drvdata(pdev, i2c);
1387
1388 if (i2c->soc_data->calc_timings == rk3x_i2c_v0_calc_timings) {
1389 /* Only one clock to use for bus clock and peripheral clock */
1390 i2c->clk = devm_clk_get(&pdev->dev, NULL);
1391 i2c->pclk = i2c->clk;
1392 } else {
1393 i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1394 i2c->pclk = devm_clk_get(&pdev->dev, "pclk");
1395 }
1396
1397 if (IS_ERR(i2c->clk)) {
1398 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), "Can't get bus clk\n");
1399 }
1400
1401 if (IS_ERR(i2c->pclk)) {
1402 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->pclk), "Can't get periph clk\n");
1403 }
1404
1405 ret = clk_prepare(i2c->clk);
1406 if (ret < 0) {
1407 dev_err(&pdev->dev, "Can't prepare bus clk: %d\n", ret);
1408 return ret;
1409 }
1410 ret = clk_prepare(i2c->pclk);
1411 if (ret < 0) {
1412 dev_err(&pdev->dev, "Can't prepare periph clock: %d\n", ret);
1413 goto err_clk;
1414 }
1415
1416 i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb;
1417 ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb);
1418 if (ret != 0) {
1419 dev_err(&pdev->dev, "Unable to register clock notifier\n");
1420 goto err_pclk;
1421 }
1422
1423 clk_rate = clk_get_rate(i2c->clk);
1424 rk3x_i2c_adapt_div(i2c, clk_rate);
1425
1426 ret = i2c_add_adapter(&i2c->adap);
1427 if (ret < 0) {
1428 goto err_clk_notifier;
1429 }
1430
1431 return 0;
1432
1433 err_clk_notifier:
1434 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1435 err_pclk:
1436 clk_unprepare(i2c->pclk);
1437 err_clk:
1438 clk_unprepare(i2c->clk);
1439 return ret;
1440 }
1441
rk3x_i2c_remove(struct platform_device * pdev)1442 static int rk3x_i2c_remove(struct platform_device *pdev)
1443 {
1444 struct rk3x_i2c *i2c = platform_get_drvdata(pdev);
1445
1446 i2c_del_adapter(&i2c->adap);
1447
1448 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1449 unregister_pre_restart_handler(&i2c->i2c_restart_nb);
1450 clk_unprepare(i2c->pclk);
1451 clk_unprepare(i2c->clk);
1452
1453 return 0;
1454 }
1455
1456 static const struct dev_pm_ops rk3x_i2c_pm_ops = {
1457 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rk3x_i2c_suspend_noirq, rk3x_i2c_resume_noirq)};
1458
1459 static struct platform_driver rk3x_i2c_driver = {
1460 .probe = rk3x_i2c_probe,
1461 .remove = rk3x_i2c_remove,
1462 .driver =
1463 {
1464 .name = "rk3x-i2c",
1465 .of_match_table = rk3x_i2c_match,
1466 .pm = &rk3x_i2c_pm_ops,
1467 },
1468 };
1469
1470 #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
rk3x_i2c_driver_init(void)1471 static int __init rk3x_i2c_driver_init(void)
1472 {
1473 return platform_driver_register(&rk3x_i2c_driver);
1474 }
1475 subsys_initcall_sync(rk3x_i2c_driver_init);
1476
rk3x_i2c_driver_exit(void)1477 static void __exit rk3x_i2c_driver_exit(void)
1478 {
1479 platform_driver_unregister(&rk3x_i2c_driver);
1480 }
1481 module_exit(rk3x_i2c_driver_exit);
1482 #else
1483 module_platform_driver(rk3x_i2c_driver);
1484 #endif
1485
1486 MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver");
1487 MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>");
1488 MODULE_LICENSE("GPL v2");
1489