1 /* 2 * Copyright (c) 2021-2022 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_WDG_H 10 #define HPM_WDG_H 11 12 typedef struct { 13 __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ 14 __RW uint32_t CTRL; /* 0x10: Control Register */ 15 __W uint32_t RESTART; /* 0x14: Restart Register */ 16 __W uint32_t WREN; /* 0x18: Write Protection Register */ 17 __W uint32_t ST; /* 0x1C: Status Register */ 18 } WDG_Type; 19 20 21 /* Bitfield definition for register: CTRL */ 22 /* 23 * RSTTIME (RW) 24 * 25 * The time interval of the reset stage: 26 * 0: Clock period x 2^7 27 * 1: Clock period x 2^8 28 * 2: Clock period x 2^9 29 * 3: Clock period x 2^10 30 * 4: Clock period x 2^11 31 * 5: Clock period x 2^12 32 * 6: Clock period x 2^13 33 * 7: Clock period x 2^14 34 */ 35 #define WDG_CTRL_RSTTIME_MASK (0x700U) 36 #define WDG_CTRL_RSTTIME_SHIFT (8U) 37 #define WDG_CTRL_RSTTIME_SET(x) (((uint32_t)(x) << WDG_CTRL_RSTTIME_SHIFT) & WDG_CTRL_RSTTIME_MASK) 38 #define WDG_CTRL_RSTTIME_GET(x) (((uint32_t)(x) & WDG_CTRL_RSTTIME_MASK) >> WDG_CTRL_RSTTIME_SHIFT) 39 40 /* 41 * INTTIME (RW) 42 * 43 * The timer interval of the interrupt stage: 44 * 0: Clock period x 2^6 45 * 1: Clock period x 2^8 46 * 2: Clock period x 2^10 47 * 3: Clock period x 2^11 48 * 4: Clock period x 2^12 49 * 5: Clock period x 2^13 50 * 6: Clock period x 2^14 51 * 7: Clock period x 2^15 52 * 8: Clock period x 2^17 53 * 9: Clock period x 2^19 54 * 10: Clock period x 2^21 55 * 11: Clock period x 2^23 56 * 12: Clock period x 2^25 57 * 13: Clock period x 2^27 58 * 14: Clock period x 2^29 59 * 15: Clock period x 2^31 60 */ 61 #define WDG_CTRL_INTTIME_MASK (0xF0U) 62 #define WDG_CTRL_INTTIME_SHIFT (4U) 63 #define WDG_CTRL_INTTIME_SET(x) (((uint32_t)(x) << WDG_CTRL_INTTIME_SHIFT) & WDG_CTRL_INTTIME_MASK) 64 #define WDG_CTRL_INTTIME_GET(x) (((uint32_t)(x) & WDG_CTRL_INTTIME_MASK) >> WDG_CTRL_INTTIME_SHIFT) 65 66 /* 67 * RSTEN (RW) 68 * 69 * Enable or disable the watchdog reset 70 * 0: Disable 71 * 1: Enable 72 */ 73 #define WDG_CTRL_RSTEN_MASK (0x8U) 74 #define WDG_CTRL_RSTEN_SHIFT (3U) 75 #define WDG_CTRL_RSTEN_SET(x) (((uint32_t)(x) << WDG_CTRL_RSTEN_SHIFT) & WDG_CTRL_RSTEN_MASK) 76 #define WDG_CTRL_RSTEN_GET(x) (((uint32_t)(x) & WDG_CTRL_RSTEN_MASK) >> WDG_CTRL_RSTEN_SHIFT) 77 78 /* 79 * INTEN (RW) 80 * 81 * Enable or disable the watchdog interrupt 82 * 0: Disable 83 * 1: Enable 84 */ 85 #define WDG_CTRL_INTEN_MASK (0x4U) 86 #define WDG_CTRL_INTEN_SHIFT (2U) 87 #define WDG_CTRL_INTEN_SET(x) (((uint32_t)(x) << WDG_CTRL_INTEN_SHIFT) & WDG_CTRL_INTEN_MASK) 88 #define WDG_CTRL_INTEN_GET(x) (((uint32_t)(x) & WDG_CTRL_INTEN_MASK) >> WDG_CTRL_INTEN_SHIFT) 89 90 /* 91 * CLKSEL (RW) 92 * 93 * Clock source of timer: 94 * 0: EXTCLK 95 * 1: PCLK 96 */ 97 #define WDG_CTRL_CLKSEL_MASK (0x2U) 98 #define WDG_CTRL_CLKSEL_SHIFT (1U) 99 #define WDG_CTRL_CLKSEL_SET(x) (((uint32_t)(x) << WDG_CTRL_CLKSEL_SHIFT) & WDG_CTRL_CLKSEL_MASK) 100 #define WDG_CTRL_CLKSEL_GET(x) (((uint32_t)(x) & WDG_CTRL_CLKSEL_MASK) >> WDG_CTRL_CLKSEL_SHIFT) 101 102 /* 103 * EN (RW) 104 * 105 * Enable or disable the watchdog timer 106 * 0: Disable 107 * 1: Enable 108 */ 109 #define WDG_CTRL_EN_MASK (0x1U) 110 #define WDG_CTRL_EN_SHIFT (0U) 111 #define WDG_CTRL_EN_SET(x) (((uint32_t)(x) << WDG_CTRL_EN_SHIFT) & WDG_CTRL_EN_MASK) 112 #define WDG_CTRL_EN_GET(x) (((uint32_t)(x) & WDG_CTRL_EN_MASK) >> WDG_CTRL_EN_SHIFT) 113 114 /* Bitfield definition for register: RESTART */ 115 /* 116 * RESTART (WO) 117 * 118 * Write the magic number 119 * ATCWDT200_RESTART_NUM to restart the 120 * watchdog timer. 121 */ 122 #define WDG_RESTART_RESTART_MASK (0xFFFFU) 123 #define WDG_RESTART_RESTART_SHIFT (0U) 124 #define WDG_RESTART_RESTART_SET(x) (((uint32_t)(x) << WDG_RESTART_RESTART_SHIFT) & WDG_RESTART_RESTART_MASK) 125 #define WDG_RESTART_RESTART_GET(x) (((uint32_t)(x) & WDG_RESTART_RESTART_MASK) >> WDG_RESTART_RESTART_SHIFT) 126 127 /* Bitfield definition for register: WREN */ 128 /* 129 * WEN (WO) 130 * 131 * Write the magic code to disable the write 132 * protection of the Control Register and the 133 * Restart Register. 134 */ 135 #define WDG_WREN_WEN_MASK (0xFFFFU) 136 #define WDG_WREN_WEN_SHIFT (0U) 137 #define WDG_WREN_WEN_SET(x) (((uint32_t)(x) << WDG_WREN_WEN_SHIFT) & WDG_WREN_WEN_MASK) 138 #define WDG_WREN_WEN_GET(x) (((uint32_t)(x) & WDG_WREN_WEN_MASK) >> WDG_WREN_WEN_SHIFT) 139 140 /* Bitfield definition for register: ST */ 141 /* 142 * INTEXPIRED (W1C) 143 * 144 * The status of the watchdog interrupt timer 145 * 0: timer is not expired yet 146 * 1: timer is expired 147 */ 148 #define WDG_ST_INTEXPIRED_MASK (0x1U) 149 #define WDG_ST_INTEXPIRED_SHIFT (0U) 150 #define WDG_ST_INTEXPIRED_SET(x) (((uint32_t)(x) << WDG_ST_INTEXPIRED_SHIFT) & WDG_ST_INTEXPIRED_MASK) 151 #define WDG_ST_INTEXPIRED_GET(x) (((uint32_t)(x) & WDG_ST_INTEXPIRED_MASK) >> WDG_ST_INTEXPIRED_SHIFT) 152 153 154 155 156 #endif /* HPM_WDG_H */