1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 #ifndef __ODM_TYPES_H__ 26 #define __ODM_TYPES_H__ 27 28 /*Define Different SW team support*/ 29 #define ODM_AP 0x01 /*BIT(0)*/ 30 #define ODM_CE 0x04 /*BIT(2)*/ 31 #define ODM_WIN 0x08 /*BIT(3)*/ 32 #define ODM_ADSL 0x10 33 /*BIT(4)*/ /*already combine with ODM_AP, and is nouse now*/ 34 #define ODM_IOT 0x20 /*BIT(5)*/ 35 36 /*For FW API*/ 37 #define __iram_odm_func__ 38 #define __odm_func__ 39 #define __odm_func_aon__ 40 41 /*Deifne HW endian support*/ 42 #define ODM_ENDIAN_BIG 0 43 #define ODM_ENDIAN_LITTLE 1 44 45 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 46 #define GET_PDM_ODM(__padapter) ((struct dm_struct*)(&(GET_HAL_DATA(__padapter))->DM_OutSrc)) 47 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) 48 #define GET_PDM_ODM(__padapter) ((struct dm_struct *)(&(GET_HAL_DATA(__padapter))->odmpriv)) 49 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) 50 #define GET_PDM_ODM(__padapter) ((struct dm_struct*)(&__padapter->pshare->_dmODM)) 51 #endif 52 53 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) 54 #if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) 55 /* enable PCI & USB HCI at the same time */ 56 #define RT_PCI_USB_INTERFACE 1 57 #define RT_PCI_INTERFACE RT_PCI_USB_INTERFACE 58 #define RT_USB_INTERFACE RT_PCI_USB_INTERFACE 59 #define RT_SDIO_INTERFACE 3 60 #else 61 #define RT_PCI_INTERFACE 1 62 #define RT_USB_INTERFACE 2 63 #define RT_SDIO_INTERFACE 3 64 #endif 65 #endif 66 67 enum hal_status { 68 HAL_STATUS_SUCCESS, 69 HAL_STATUS_FAILURE, 70 #if 0 71 RT_STATUS_PENDING, 72 RT_STATUS_RESOURCE, 73 RT_STATUS_INVALID_CONTEXT, 74 RT_STATUS_INVALID_PARAMETER, 75 RT_STATUS_NOT_SUPPORT, 76 RT_STATUS_OS_API_FAILED, 77 #endif 78 }; 79 80 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) 81 82 #define VISTA_USB_RX_REVISE 0 83 84 /* 85 * Declare for ODM spin lock definition temporarily fro compile pass. 86 */ 87 enum rt_spinlock_type { 88 RT_TX_SPINLOCK = 1, 89 RT_RX_SPINLOCK = 2, 90 RT_RM_SPINLOCK = 3, 91 RT_CAM_SPINLOCK = 4, 92 RT_SCAN_SPINLOCK = 5, 93 RT_LOG_SPINLOCK = 7, 94 RT_BW_SPINLOCK = 8, 95 RT_CHNLOP_SPINLOCK = 9, 96 RT_RF_OPERATE_SPINLOCK = 10, 97 RT_INITIAL_SPINLOCK = 11, 98 RT_RF_STATE_SPINLOCK = 12, 99 /* For RF state. Added by Bruce, 2007-10-30. */ 100 #if VISTA_USB_RX_REVISE 101 RT_USBRX_CONTEXT_SPINLOCK = 13, 102 RT_USBRX_POSTPROC_SPINLOCK = 14, 103 /* protect data of adapter->IndicateW/ IndicateR */ 104 #endif 105 /* Shall we define Ndis 6.2 SpinLock Here ? */ 106 RT_PORT_SPINLOCK = 16, 107 RT_VNIC_SPINLOCK = 17, 108 RT_HVL_SPINLOCK = 18, 109 RT_H2C_SPINLOCK = 20, 110 /* For H2C cmd. Added by tynli. 2009.11.09. */ 111 112 rt_bt_data_spinlock = 25, 113 114 RT_WAPI_OPTION_SPINLOCK = 26, 115 RT_WAPI_RX_SPINLOCK = 27, 116 117 /* add for 92D CCK control issue */ 118 RT_CCK_PAGEA_SPINLOCK = 28, 119 RT_BUFFER_SPINLOCK = 29, 120 RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30, 121 RT_GEN_TEMP_BUF_SPINLOCK = 31, 122 RT_AWB_SPINLOCK = 32, 123 RT_FW_PS_SPINLOCK = 33, 124 RT_HW_TIMER_SPIN_LOCK = 34, 125 RT_MPT_WI_SPINLOCK = 35, 126 RT_P2P_SPIN_LOCK = 36, /* Protect P2P context */ 127 RT_DBG_SPIN_LOCK = 37, 128 RT_IQK_SPINLOCK = 38, 129 RT_PENDED_OID_SPINLOCK = 39, 130 RT_CHNLLIST_SPINLOCK = 40, 131 RT_INDIC_SPINLOCK = 41, /* protect indication */ 132 RT_RFD_SPINLOCK = 42, 133 RT_SYNC_IO_CNT_SPINLOCK = 43, 134 RT_LAST_SPINLOCK, 135 }; 136 137 #endif 138 139 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 140 #define sta_info _RT_WLAN_STA 141 #define __func__ __FUNCTION__ 142 #define PHYDM_TESTCHIP_SUPPORT TESTCHIP_SUPPORT 143 #define MASKH3BYTES 0xffffff00 144 #define SUCCESS 0 145 #define FAIL (-1) 146 147 #define u8 u1Byte 148 #define s8 s1Byte 149 150 #define u16 u2Byte 151 #define s16 s2Byte 152 153 #define u32 u4Byte 154 #define s32 s4Byte 155 156 #define u64 u8Byte 157 #define s64 s8Byte 158 159 #define phydm_timer_list _RT_TIMER 160 161 // for power limit table 162 enum odm_pw_lmt_regulation_type { 163 PW_LMT_REGU_FCC = 0, 164 PW_LMT_REGU_ETSI = 1, 165 PW_LMT_REGU_MKK = 2, 166 PW_LMT_REGU_WW13 = 3, 167 PW_LMT_REGU_IC = 4, 168 PW_LMT_REGU_KCC = 5, 169 PW_LMT_REGU_ACMA = 6, 170 PW_LMT_REGU_CHILE = 7, 171 PW_LMT_REGU_UKRAINE = 8, 172 PW_LMT_REGU_MEXICO = 9, 173 PW_LMT_REGU_CN = 10 174 }; 175 176 enum odm_pw_lmt_band_type { 177 PW_LMT_BAND_2_4G = 0, 178 PW_LMT_BAND_5G = 1 179 }; 180 181 enum odm_pw_lmt_bandwidth_type { 182 PW_LMT_BW_20M = 0, 183 PW_LMT_BW_40M = 1, 184 PW_LMT_BW_80M = 2, 185 PW_LMT_BW_160M = 3 186 }; 187 188 enum odm_pw_lmt_ratesection_type { 189 PW_LMT_RS_CCK = 0, 190 PW_LMT_RS_OFDM = 1, 191 PW_LMT_RS_HT = 2, 192 PW_LMT_RS_VHT = 3 193 }; 194 195 enum odm_pw_lmt_rfpath_type { 196 PW_LMT_PH_1T = 0, 197 PW_LMT_PH_2T = 1, 198 PW_LMT_PH_3T = 2, 199 PW_LMT_PH_4T = 3 200 }; 201 202 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) 203 #include "../typedef.h" 204 205 #ifdef CONFIG_PCI_HCI 206 #if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) 207 #define DEV_BUS_TYPE RT_PCI_USB_INTERFACE 208 #else 209 #define DEV_BUS_TYPE RT_PCI_INTERFACE 210 #endif 211 #endif 212 213 #if (defined(TESTCHIP_SUPPORT)) 214 #define PHYDM_TESTCHIP_SUPPORT 1 215 #else 216 #define PHYDM_TESTCHIP_SUPPORT 0 217 #endif 218 219 #define sta_info stat_info 220 #define boolean bool 221 222 #define phydm_timer_list timer_list 223 #if defined(__ECOS) 224 #define s64 s8Byte 225 #endif 226 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) 227 228 #include <asm/byteorder.h> 229 230 #define DEV_BUS_TYPE RT_PCI_INTERFACE 231 232 #if defined(__LITTLE_ENDIAN) 233 #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE 234 #elif defined(__BIG_ENDIAN) 235 #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG 236 #else 237 #error 238 #endif 239 240 /* define useless flag to avoid compile warning */ 241 #define USE_WORKITEM 0 242 #define FOR_BRAZIL_PRETEST 0 243 #define FPGA_TWO_MAC_VERIFICATION 0 244 #define RTL8881A_SUPPORT 0 245 #define PHYDM_TESTCHIP_SUPPORT 0 246 247 248 #define RATE_ADAPTIVE_SUPPORT 0 249 #define POWER_TRAINING_ACTIVE 0 250 251 #define sta_info rtl_sta_info 252 #define boolean bool 253 254 #define phydm_timer_list timer_list 255 256 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) 257 #include <drv_types.h> 258 259 #ifdef CONFIG_USB_HCI 260 #define DEV_BUS_TYPE RT_USB_INTERFACE 261 #elif defined(CONFIG_PCI_HCI) 262 #define DEV_BUS_TYPE RT_PCI_INTERFACE 263 #elif defined(CONFIG_SDIO_HCI) 264 #define DEV_BUS_TYPE RT_SDIO_INTERFACE 265 #elif defined(CONFIG_GSPI_HCI) 266 #define DEV_BUS_TYPE RT_SDIO_INTERFACE 267 #endif 268 269 270 #if defined(CONFIG_LITTLE_ENDIAN) 271 #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE 272 #elif defined(CONFIG_BIG_ENDIAN) 273 #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG 274 #endif 275 276 #define boolean bool 277 278 #define SET_TX_DESC_ANTSEL_A_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 8, 24, 1, __value) 279 #define SET_TX_DESC_ANTSEL_B_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 8, 25, 1, __value) 280 #define SET_TX_DESC_ANTSEL_C_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 28, 29, 1, __value) 281 282 /* define useless flag to avoid compile warning */ 283 #define USE_WORKITEM 0 284 #define FOR_BRAZIL_PRETEST 0 285 #define FPGA_TWO_MAC_VERIFICATION 0 286 #define RTL8881A_SUPPORT 0 287 288 #if (defined(TESTCHIP_SUPPORT)) 289 #define PHYDM_TESTCHIP_SUPPORT 1 290 #else 291 #define PHYDM_TESTCHIP_SUPPORT 0 292 #endif 293 294 #define phydm_timer_list rtw_timer_list 295 296 // for power limit table 297 enum odm_pw_lmt_regulation_type { 298 PW_LMT_REGU_FCC = 0, 299 PW_LMT_REGU_ETSI = 1, 300 PW_LMT_REGU_MKK = 2, 301 PW_LMT_REGU_WW13 = 3, 302 PW_LMT_REGU_IC = 4, 303 PW_LMT_REGU_KCC = 5, 304 PW_LMT_REGU_ACMA = 6, 305 PW_LMT_REGU_CHILE = 7, 306 PW_LMT_REGU_UKRAINE = 8, 307 PW_LMT_REGU_MEXICO = 9, 308 PW_LMT_REGU_CN = 10 309 }; 310 311 enum odm_pw_lmt_band_type { 312 PW_LMT_BAND_2_4G = 0, 313 PW_LMT_BAND_5G = 1 314 }; 315 316 enum odm_pw_lmt_bandwidth_type { 317 PW_LMT_BW_20M = 0, 318 PW_LMT_BW_40M = 1, 319 PW_LMT_BW_80M = 2, 320 PW_LMT_BW_160M = 3 321 }; 322 323 enum odm_pw_lmt_ratesection_type { 324 PW_LMT_RS_CCK = 0, 325 PW_LMT_RS_OFDM = 1, 326 PW_LMT_RS_HT = 2, 327 PW_LMT_RS_VHT = 3 328 }; 329 330 enum odm_pw_lmt_rfpath_type { 331 PW_LMT_PH_1T = 0, 332 PW_LMT_PH_2T = 1, 333 PW_LMT_PH_3T = 2, 334 PW_LMT_PH_4T = 3 335 }; 336 337 #elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) 338 #define boolean bool 339 #define true _TRUE 340 #define false _FALSE 341 342 // for power limit table 343 enum odm_pw_lmt_regulation_type { 344 PW_LMT_REGU_NULL = 0, 345 PW_LMT_REGU_FCC = 1, 346 PW_LMT_REGU_ETSI = 2, 347 PW_LMT_REGU_MKK = 3, 348 PW_LMT_REGU_WW13 = 4, 349 PW_LMT_REGU_IC = 5, 350 PW_LMT_REGU_KCC = 6, 351 PW_LMT_REGU_ACMA = 7, 352 PW_LMT_REGU_CHILE = 8, 353 PW_LMT_REGU_UKRAINE = 9, 354 PW_LMT_REGU_MEXICO = 10, 355 PW_LMT_REGU_CN = 11, 356 PW_LMT_REGU_MAX_NUM = 12 357 }; 358 359 enum odm_pw_lmt_band_type { 360 PW_LMT_BAND_NULL = 0, 361 PW_LMT_BAND_2_4G = 1, 362 PW_LMT_BAND_5G = 2 363 }; 364 365 enum odm_pw_lmt_bandwidth_type { 366 PW_LMT_BW_NULL = 0, 367 PW_LMT_BW_20M = 1, 368 PW_LMT_BW_40M = 2, 369 PW_LMT_BW_80M = 3 370 }; 371 372 enum odm_pw_lmt_ratesection_type { 373 PW_LMT_RS_NULL = 0, 374 PW_LMT_RS_CCK = 1, 375 PW_LMT_RS_OFDM = 2, 376 PW_LMT_RS_HT = 3, 377 PW_LMT_RS_VHT = 4 378 }; 379 380 enum odm_pw_lmt_rfpath_type { 381 PW_LMT_PH_NULL = 0, 382 PW_LMT_PH_1T = 1, 383 PW_LMT_PH_2T = 2, 384 PW_LMT_PH_3T = 3, 385 PW_LMT_PH_4T = 4 386 }; 387 388 #define phydm_timer_list timer_list 389 390 #endif 391 392 #define READ_NEXT_PAIR(v1, v2, i) do { if (i + 2 >= array_len) break; i += 2; v1 = array[i]; v2 = array[i + 1]; } while (0) 393 #define COND_ELSE 2 394 #define COND_ENDIF 3 395 396 #define MASKBYTE0 0xff 397 #define MASKBYTE1 0xff00 398 #define MASKBYTE2 0xff0000 399 #define MASKBYTE3 0xff000000 400 #define MASKHWORD 0xffff0000 401 #define MASKLWORD 0x0000ffff 402 #define MASKDWORD 0xffffffff 403 404 #define MASK7BITS 0x7f 405 #define MASK12BITS 0xfff 406 #define MASKH4BITS 0xf0000000 407 #define MASK20BITS 0xfffff 408 #define MASK24BITS 0xffffff 409 #define MASKOFDM_D 0xffc00000 410 #define MASKCCK 0x3f3f3f3f 411 412 #define RFREGOFFSETMASK 0xfffff 413 #define RFREG_MASK 0xfffff 414 415 #define MASKH3BYTES 0xffffff00 416 #define MASKL3BYTES 0x00ffffff 417 #define MASKBYTE2HIGHNIBBLE 0x00f00000 418 #define MASKBYTE3LOWNIBBLE 0x0f000000 419 #define MASKL3BYTES 0x00ffffff 420 421 #endif /* __ODM_TYPES_H__ */ 422