1 /*
2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #ifndef FREEDRENO_CONTEXT_H_
28 #define FREEDRENO_CONTEXT_H_
29
30 #include "pipe/p_context.h"
31 #include "util/libsync.h"
32 #include "util/list.h"
33 #include "util/slab.h"
34 #include "util/u_blitter.h"
35 #include "util/u_string.h"
36 #include "util/u_threaded_context.h"
37 #include "util/perf/u_trace.h"
38
39 #include "freedreno_autotune.h"
40 #include "freedreno_gmem.h"
41 #include "freedreno_perfetto.h"
42 #include "freedreno_screen.h"
43 #include "freedreno_util.h"
44
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48
49 #define BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE)
50
51 struct fd_vertex_stateobj;
52 struct fd_batch;
53
54 struct fd_texture_stateobj {
55 struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
56 unsigned num_textures;
57 unsigned valid_textures;
58 struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
59 unsigned num_samplers;
60 unsigned valid_samplers;
61 };
62
63 struct fd_program_stateobj {
64 void *vs, *hs, *ds, *gs, *fs;
65 };
66
67 struct fd_constbuf_stateobj {
68 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
69 uint32_t enabled_mask;
70 };
71
72 struct fd_shaderbuf_stateobj {
73 struct pipe_shader_buffer sb[PIPE_MAX_SHADER_BUFFERS];
74 uint32_t enabled_mask;
75 uint32_t writable_mask;
76 };
77
78 struct fd_shaderimg_stateobj {
79 struct pipe_image_view si[PIPE_MAX_SHADER_IMAGES];
80 uint32_t enabled_mask;
81 };
82
83 struct fd_vertexbuf_stateobj {
84 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
85 unsigned count;
86 uint32_t enabled_mask;
87 };
88
89 struct fd_vertex_stateobj {
90 struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
91 unsigned num_elements;
92 };
93
94 struct fd_stream_output_target {
95 struct pipe_stream_output_target base;
96 struct pipe_resource *offset_buf;
97 /* stride of the last stream out recorded to this target, for
98 * glDrawTransformFeedback(). */
99 uint32_t stride;
100 };
101
102 struct fd_streamout_stateobj {
103 struct pipe_stream_output_target *targets[PIPE_MAX_SO_BUFFERS];
104 /* Bitmask of stream that should be reset. */
105 unsigned reset;
106
107 unsigned num_targets;
108 /* Track offset from vtxcnt for streamout data. This counter
109 * is just incremented by # of vertices on each draw until
110 * reset or new streamout buffer bound.
111 *
112 * When we eventually have GS, the CPU won't actually know the
113 * number of vertices per draw, so I think we'll have to do
114 * something more clever.
115 */
116 unsigned offsets[PIPE_MAX_SO_BUFFERS];
117
118 /* Pre-a6xx, the maximum number of vertices that could be recorded to this
119 * set of targets with the current vertex shader. a6xx and newer, hardware
120 * queries are used.
121 */
122 unsigned max_tf_vtx;
123
124 /* Pre-a6xx, the number of verts written to the buffers since the last
125 * Begin. Used for overflow checking for SW queries.
126 */
127 unsigned verts_written;
128 };
129
130 #define MAX_GLOBAL_BUFFERS 16
131 struct fd_global_bindings_stateobj {
132 struct pipe_resource *buf[MAX_GLOBAL_BUFFERS];
133 uint32_t enabled_mask;
134 };
135
136 /* group together the vertex and vertexbuf state.. for ease of passing
137 * around, and because various internal operations (gmem<->mem, etc)
138 * need their own vertex state:
139 */
140 struct fd_vertex_state {
141 struct fd_vertex_stateobj *vtx;
142 struct fd_vertexbuf_stateobj vertexbuf;
143 };
144
145 /* global 3d pipeline dirty state: */
146 enum fd_dirty_3d_state {
147 FD_DIRTY_BLEND = BIT(0),
148 FD_DIRTY_RASTERIZER = BIT(1),
149 FD_DIRTY_ZSA = BIT(2),
150 FD_DIRTY_BLEND_COLOR = BIT(3),
151 FD_DIRTY_STENCIL_REF = BIT(4),
152 FD_DIRTY_SAMPLE_MASK = BIT(5),
153 FD_DIRTY_FRAMEBUFFER = BIT(6),
154 FD_DIRTY_STIPPLE = BIT(7),
155 FD_DIRTY_VIEWPORT = BIT(8),
156 FD_DIRTY_VTXSTATE = BIT(9),
157 FD_DIRTY_VTXBUF = BIT(10),
158 FD_DIRTY_MIN_SAMPLES = BIT(11),
159 FD_DIRTY_SCISSOR = BIT(12),
160 FD_DIRTY_STREAMOUT = BIT(13),
161 FD_DIRTY_UCP = BIT(14),
162 FD_DIRTY_PROG = BIT(15),
163 FD_DIRTY_CONST = BIT(16),
164 FD_DIRTY_TEX = BIT(17),
165 FD_DIRTY_IMAGE = BIT(18),
166 FD_DIRTY_SSBO = BIT(19),
167
168 /* only used by a2xx.. possibly can be removed.. */
169 FD_DIRTY_TEXSTATE = BIT(20),
170
171 /* fine grained state changes, for cases where state is not orthogonal
172 * from hw perspective:
173 */
174 FD_DIRTY_RASTERIZER_DISCARD = BIT(24),
175 FD_DIRTY_RASTERIZER_CLIP_PLANE_ENABLE = BIT(25),
176 FD_DIRTY_BLEND_DUAL = BIT(26),
177 #define NUM_DIRTY_BITS 27
178
179 /* additional flag for state requires updated resource tracking: */
180 FD_DIRTY_RESOURCE = BIT(31),
181 };
182
183 /* per shader-stage dirty state: */
184 enum fd_dirty_shader_state {
185 FD_DIRTY_SHADER_PROG = BIT(0),
186 FD_DIRTY_SHADER_CONST = BIT(1),
187 FD_DIRTY_SHADER_TEX = BIT(2),
188 FD_DIRTY_SHADER_SSBO = BIT(3),
189 FD_DIRTY_SHADER_IMAGE = BIT(4),
190 #define NUM_DIRTY_SHADER_BITS 5
191 };
192
193 #define MAX_HW_SAMPLE_PROVIDERS 7
194 struct fd_hw_sample_provider;
195 struct fd_hw_sample;
196
197 struct ir3_shader_key;
198
199 struct fd_context {
200 struct pipe_context base;
201
202 unsigned flags; /* PIPE_CONTEXT_x */
203
204 struct threaded_context *tc;
205
206 struct list_head node; /* node in screen->context_list */
207
208 /* We currently need to serialize emitting GMEM batches, because of
209 * VSC state access in the context.
210 *
211 * In practice this lock should not be contended, since pipe_context
212 * use should be single threaded. But it is needed to protect the
213 * case, with batch reordering where a ctxB batch triggers flushing
214 * a ctxA batch
215 */
216 simple_mtx_t gmem_lock;
217
218 struct fd_device *dev;
219 struct fd_screen *screen;
220 struct fd_pipe *pipe;
221
222 struct blitter_context *blitter dt;
223 void *clear_rs_state[2] dt;
224
225 /* slab for pipe_transfer allocations: */
226 struct slab_child_pool transfer_pool dt;
227 struct slab_child_pool transfer_pool_unsync; /* for threaded_context */
228
229 struct fd_autotune autotune dt;
230
231 /**
232 * query related state:
233 */
234 /*@{*/
235 /* slabs for fd_hw_sample and fd_hw_sample_period allocations: */
236 struct slab_mempool sample_pool dt;
237 struct slab_mempool sample_period_pool dt;
238
239 /* sample-providers for hw queries: */
240 const struct fd_hw_sample_provider
241 *hw_sample_providers[MAX_HW_SAMPLE_PROVIDERS];
242
243 /* list of active queries: */
244 struct list_head hw_active_queries dt;
245
246 /* sample-providers for accumulating hw queries: */
247 const struct fd_acc_sample_provider
248 *acc_sample_providers[MAX_HW_SAMPLE_PROVIDERS];
249
250 /* list of active accumulating queries: */
251 struct list_head acc_active_queries dt;
252 /*@}*/
253
254 uint8_t patch_vertices;
255
256 /* Whether we need to recheck the active_queries list next
257 * fd_batch_update_queries().
258 */
259 bool update_active_queries dt;
260
261 /* Current state of pctx->set_active_query_state() (i.e. "should drawing
262 * be counted against non-perfcounter queries")
263 */
264 bool active_queries dt;
265
266 /* shaders used by clear, and gmem->mem blits: */
267 struct fd_program_stateobj solid_prog; // TODO move to screen?
268 struct fd_program_stateobj solid_layered_prog;
269
270 /* shaders used by mem->gmem blits: */
271 struct fd_program_stateobj
272 blit_prog[MAX_RENDER_TARGETS]; // TODO move to screen?
273 struct fd_program_stateobj blit_z, blit_zs;
274
275 /* Stats/counters:
276 */
277 struct {
278 uint64_t prims_emitted;
279 uint64_t prims_generated;
280 uint64_t draw_calls;
281 uint64_t batch_total, batch_sysmem, batch_gmem, batch_nondraw,
282 batch_restore;
283 uint64_t staging_uploads, shadow_uploads;
284 uint64_t vs_regs, hs_regs, ds_regs, gs_regs, fs_regs;
285 } stats dt;
286
287 /* Counter for number of users who need sw counters (so we can
288 * skip collecting them when not needed)
289 */
290 unsigned stats_users;
291
292 /* Current batch.. the rule here is that you can deref ctx->batch
293 * in codepaths from pipe_context entrypoints. But not in code-
294 * paths from fd_batch_flush() (basically, the stuff that gets
295 * called from GMEM code), since in those code-paths the batch
296 * you care about is not necessarily the same as ctx->batch.
297 */
298 struct fd_batch *batch dt;
299
300 /* NULL if there has been rendering since last flush. Otherwise
301 * keeps a reference to the last fence so we can re-use it rather
302 * than having to flush no-op batch.
303 */
304 struct pipe_fence_handle *last_fence dt;
305
306 /* Fence fd we are told to wait on via ->fence_server_sync() (or -1
307 * if none). The in-fence is transferred over to the batch on the
308 * next draw/blit/grid.
309 *
310 * The reason for this extra complexity is that apps will typically
311 * do eglWaitSyncKHR()/etc at the beginning of the frame, before the
312 * first draw. But mesa/st doesn't flush down framebuffer state
313 * change until we hit a draw, so at ->fence_server_sync() time, we
314 * don't yet have the correct batch. If we created a batch at that
315 * point, it would be the wrong one, and we'd have to flush it pre-
316 * maturely, causing us to stall early in the frame where we could
317 * be building up cmdstream.
318 */
319 int in_fence_fd dt;
320
321 /* track last known reset status globally and per-context to
322 * determine if more resets occurred since then. If global reset
323 * count increases, it means some other context crashed. If
324 * per-context reset count increases, it means we crashed the
325 * gpu.
326 *
327 * Only accessed by front-end thread, never accessed by TC driver
328 * thread.
329 */
330 uint32_t context_reset_count;
331 uint32_t global_reset_count;
332
333 /* Context sequence #, used for batch-cache key: */
334 uint16_t seqno;
335
336 /* Cost per draw, used in conjunction with samples-passed history to
337 * estimate whether GMEM or bypass is the better option.
338 */
339 uint8_t draw_cost;
340
341 /* Are we in process of shadowing a resource? Used to detect recursion
342 * in transfer_map, and skip unneeded synchronization.
343 */
344 bool in_shadow : 1 dt;
345
346 /* For catching recursion problems with blit fallback: */
347 bool in_blit : 1 dt;
348
349 /* points to either scissor or disabled_scissor depending on rast state: */
350 struct pipe_scissor_state *current_scissor dt;
351
352 struct pipe_scissor_state scissor dt;
353
354 /* we don't have a disable/enable bit for scissor, so instead we keep
355 * a disabled-scissor state which matches the entire bound framebuffer
356 * and use that when scissor is not enabled.
357 */
358 struct pipe_scissor_state disabled_scissor dt;
359
360 /* Per vsc pipe bo's (a2xx-a5xx): */
361 struct fd_bo *vsc_pipe_bo[32] dt;
362
363 /* Maps generic gallium oriented fd_dirty_3d_state bits to generation
364 * specific bitmask of state "groups".
365 */
366 uint32_t gen_dirty_map[NUM_DIRTY_BITS];
367 uint32_t gen_dirty_shader_map[PIPE_SHADER_TYPES][NUM_DIRTY_SHADER_BITS];
368
369 /* Bitmask of all possible gen_dirty bits: */
370 uint32_t gen_all_dirty;
371
372 /* Generation specific bitmask of dirty state groups: */
373 uint32_t gen_dirty;
374
375 /* which state objects need to be re-emit'd: */
376 enum fd_dirty_3d_state dirty dt;
377
378 /* per shader-stage dirty status: */
379 enum fd_dirty_shader_state dirty_shader[PIPE_SHADER_TYPES] dt;
380
381 void *compute dt;
382 struct pipe_blend_state *blend dt;
383 struct pipe_rasterizer_state *rasterizer dt;
384 struct pipe_depth_stencil_alpha_state *zsa dt;
385
386 struct fd_texture_stateobj tex[PIPE_SHADER_TYPES] dt;
387
388 struct fd_program_stateobj prog dt;
389 uint32_t bound_shader_stages dt;
390
391 struct fd_vertex_state vtx dt;
392
393 struct pipe_blend_color blend_color dt;
394 struct pipe_stencil_ref stencil_ref dt;
395 unsigned sample_mask dt;
396 unsigned min_samples dt;
397 /* local context fb state, for when ctx->batch is null: */
398 struct pipe_framebuffer_state framebuffer dt;
399 struct pipe_poly_stipple stipple dt;
400 struct pipe_viewport_state viewport dt;
401 struct pipe_scissor_state viewport_scissor dt;
402 struct fd_constbuf_stateobj constbuf[PIPE_SHADER_TYPES] dt;
403 struct fd_shaderbuf_stateobj shaderbuf[PIPE_SHADER_TYPES] dt;
404 struct fd_shaderimg_stateobj shaderimg[PIPE_SHADER_TYPES] dt;
405 struct fd_streamout_stateobj streamout dt;
406 struct fd_global_bindings_stateobj global_bindings dt;
407 struct pipe_clip_state ucp dt;
408
409 struct pipe_query *cond_query dt;
410 bool cond_cond dt; /* inverted rendering condition */
411 uint cond_mode dt;
412
413 /* Private memory is a memory space where each fiber gets its own piece of
414 * memory, in addition to registers. It is backed by a buffer which needs
415 * to be large enough to hold the contents of every possible wavefront in
416 * every core of the GPU. Because it allocates space via the internal
417 * wavefront ID which is shared between all currently executing shaders,
418 * the same buffer can be reused by all shaders, as long as all shaders
419 * sharing the same buffer use the exact same configuration. There are two
420 * inputs to the configuration, the amount of per-fiber space and whether
421 * to use the newer per-wave or older per-fiber layout. We only ever
422 * increase the size, and shaders with a smaller size requirement simply
423 * use the larger existing buffer, so that we only need to keep track of
424 * one buffer and its size, but we still need to keep track of per-fiber
425 * and per-wave buffers separately so that we never use the same buffer
426 * for different layouts. pvtmem[0] is for per-fiber, and pvtmem[1] is for
427 * per-wave.
428 */
429 struct {
430 struct fd_bo *bo;
431 uint32_t per_fiber_size;
432 } pvtmem[2] dt;
433
434 /* maps per-shader-stage state plus variant key to hw
435 * program stateobj:
436 */
437 struct ir3_cache *shader_cache;
438
439 struct util_debug_callback debug;
440
441 struct u_trace_context trace_context dt;
442
443 #ifdef HAVE_PERFETTO
444 struct fd_perfetto_state perfetto;
445 #endif
446
447 /*
448 * Counter to generate submit-ids
449 */
450 uint32_t submit_count;
451
452 /* Called on rebind_resource() for any per-gen cleanup required: */
453 void (*rebind_resource)(struct fd_context *ctx, struct fd_resource *rsc) dt;
454
455 /* GMEM/tile handling fxns: */
456 void (*emit_tile_init)(struct fd_batch *batch) dt;
457 void (*emit_tile_prep)(struct fd_batch *batch,
458 const struct fd_tile *tile) dt;
459 void (*emit_tile_mem2gmem)(struct fd_batch *batch,
460 const struct fd_tile *tile) dt;
461 void (*emit_tile_renderprep)(struct fd_batch *batch,
462 const struct fd_tile *tile) dt;
463 void (*emit_tile)(struct fd_batch *batch, const struct fd_tile *tile) dt;
464 void (*emit_tile_gmem2mem)(struct fd_batch *batch,
465 const struct fd_tile *tile) dt;
466 void (*emit_tile_fini)(struct fd_batch *batch) dt; /* optional */
467
468 /* optional, for GMEM bypass: */
469 void (*emit_sysmem_prep)(struct fd_batch *batch) dt;
470 void (*emit_sysmem_fini)(struct fd_batch *batch) dt;
471
472 /* draw: */
473 bool (*draw_vbo)(struct fd_context *ctx, const struct pipe_draw_info *info,
474 unsigned drawid_offset,
475 const struct pipe_draw_indirect_info *indirect,
476 const struct pipe_draw_start_count_bias *draw,
477 unsigned index_offset) dt;
478 bool (*clear)(struct fd_context *ctx, unsigned buffers,
479 const union pipe_color_union *color, double depth,
480 unsigned stencil) dt;
481
482 /* compute: */
483 void (*launch_grid)(struct fd_context *ctx,
484 const struct pipe_grid_info *info) dt;
485
486 /* query: */
487 struct fd_query *(*create_query)(struct fd_context *ctx, unsigned query_type,
488 unsigned index);
489 void (*query_prepare)(struct fd_batch *batch, uint32_t num_tiles) dt;
490 void (*query_prepare_tile)(struct fd_batch *batch, uint32_t n,
491 struct fd_ringbuffer *ring) dt;
492 void (*query_update_batch)(struct fd_batch *batch, bool disable_all) dt;
493
494 /* blitter: */
495 bool (*blit)(struct fd_context *ctx, const struct pipe_blit_info *info) dt;
496 void (*clear_ubwc)(struct fd_batch *batch, struct fd_resource *rsc) dt;
497
498 /* uncompress resource, if necessary, to use as the specified format: */
499 void (*validate_format)(struct fd_context *ctx, struct fd_resource *rsc,
500 enum pipe_format format) dt;
501
502 /* handling for barriers: */
503 void (*framebuffer_barrier)(struct fd_context *ctx) dt;
504
505 /* logger: */
506 void (*record_timestamp)(struct fd_ringbuffer *ring, struct fd_bo *bo,
507 unsigned offset);
508 uint64_t (*ts_to_ns)(uint64_t ts);
509
510 /*
511 * Common pre-cooked VBO state (used for a3xx and later):
512 */
513
514 /* for clear/gmem->mem vertices, and mem->gmem */
515 struct pipe_resource *solid_vbuf;
516
517 /* for mem->gmem tex coords: */
518 struct pipe_resource *blit_texcoord_vbuf;
519
520 /* vertex state for solid_vbuf:
521 * - solid_vbuf / 12 / R32G32B32_FLOAT
522 */
523 struct fd_vertex_state solid_vbuf_state;
524
525 /* vertex state for blit_prog:
526 * - blit_texcoord_vbuf / 8 / R32G32_FLOAT
527 * - solid_vbuf / 12 / R32G32B32_FLOAT
528 */
529 struct fd_vertex_state blit_vbuf_state;
530
531 /*
532 * Info about state of previous draw, for state that comes from
533 * pipe_draw_info (ie. not part of a CSO). This allows us to
534 * skip some register emit when the state doesn't change from
535 * draw-to-draw
536 */
537 struct {
538 bool dirty; /* last draw state unknown */
539 bool primitive_restart;
540 uint32_t index_start;
541 uint32_t instance_start;
542 uint32_t restart_index;
543 uint32_t streamout_mask;
544
545 /* some state changes require a different shader variant. Keep
546 * track of this so we know when we need to re-emit shader state
547 * due to variant change. See ir3_fixup_shader_state()
548 *
549 * (used for a3xx+, NULL otherwise)
550 */
551 struct ir3_shader_key *key;
552
553 } last dt;
554 };
555
556 static inline struct fd_context *
fd_context(struct pipe_context * pctx)557 fd_context(struct pipe_context *pctx)
558 {
559 return (struct fd_context *)pctx;
560 }
561
562 static inline struct fd_stream_output_target *
fd_stream_output_target(struct pipe_stream_output_target * target)563 fd_stream_output_target(struct pipe_stream_output_target *target)
564 {
565 return (struct fd_stream_output_target *)target;
566 }
567
568 /**
569 * Does the dirty state require resource tracking, ie. in general
570 * does it reference some resource. There are some special cases:
571 *
572 * - FD_DIRTY_CONST can reference a resource, but cb0 is handled
573 * specially as if it is not a user-buffer, we expect it to be
574 * coming from const_uploader, so we can make some assumptions
575 * that future transfer_map will be UNSYNCRONIZED
576 * - FD_DIRTY_ZSA controls how the framebuffer is accessed
577 * - FD_DIRTY_BLEND needs to update GMEM reason
578 *
579 * TODO if we can make assumptions that framebuffer state is bound
580 * first, before blend/zsa/etc state we can move some of the ZSA/
581 * BLEND state handling from draw time to bind time. I think this
582 * is true of mesa/st, perhaps we can just document it to be a
583 * frontend requirement?
584 */
585 static inline bool
fd_context_dirty_resource(enum fd_dirty_3d_state dirty)586 fd_context_dirty_resource(enum fd_dirty_3d_state dirty)
587 {
588 return dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_ZSA | FD_DIRTY_BLEND |
589 FD_DIRTY_SSBO | FD_DIRTY_IMAGE | FD_DIRTY_VTXBUF |
590 FD_DIRTY_TEX | FD_DIRTY_STREAMOUT);
591 }
592
593 /* Mark specified non-shader-stage related state as dirty: */
594 static inline void
fd_context_dirty(struct fd_context * ctx,enum fd_dirty_3d_state dirty)595 fd_context_dirty(struct fd_context *ctx, enum fd_dirty_3d_state dirty) assert_dt
596 {
597 assert(util_is_power_of_two_nonzero(dirty));
598 assert(ffs(dirty) <= ARRAY_SIZE(ctx->gen_dirty_map));
599
600 ctx->gen_dirty |= ctx->gen_dirty_map[ffs(dirty) - 1];
601
602 if (fd_context_dirty_resource(dirty))
603 or_mask(dirty, FD_DIRTY_RESOURCE);
604
605 or_mask(ctx->dirty, dirty);
606 }
607
608 static inline void
fd_context_dirty_shader(struct fd_context * ctx,enum pipe_shader_type shader,enum fd_dirty_shader_state dirty)609 fd_context_dirty_shader(struct fd_context *ctx, enum pipe_shader_type shader,
610 enum fd_dirty_shader_state dirty) assert_dt
611 {
612 const enum fd_dirty_3d_state map[] = {
613 FD_DIRTY_PROG, FD_DIRTY_CONST, FD_DIRTY_TEX,
614 FD_DIRTY_SSBO, FD_DIRTY_IMAGE,
615 };
616
617 /* Need to update the table above if these shift: */
618 STATIC_ASSERT(FD_DIRTY_SHADER_PROG == BIT(0));
619 STATIC_ASSERT(FD_DIRTY_SHADER_CONST == BIT(1));
620 STATIC_ASSERT(FD_DIRTY_SHADER_TEX == BIT(2));
621 STATIC_ASSERT(FD_DIRTY_SHADER_SSBO == BIT(3));
622 STATIC_ASSERT(FD_DIRTY_SHADER_IMAGE == BIT(4));
623
624 assert(util_is_power_of_two_nonzero(dirty));
625 assert(ffs(dirty) <= ARRAY_SIZE(map));
626
627 ctx->gen_dirty |= ctx->gen_dirty_shader_map[shader][ffs(dirty) - 1];
628
629 or_mask(ctx->dirty_shader[shader], dirty);
630 fd_context_dirty(ctx, map[ffs(dirty) - 1]);
631 }
632
633 /* mark all state dirty: */
634 static inline void
fd_context_all_dirty(struct fd_context * ctx)635 fd_context_all_dirty(struct fd_context *ctx) assert_dt
636 {
637 ctx->last.dirty = true;
638 ctx->dirty = (enum fd_dirty_3d_state) ~0;
639
640 /* NOTE: don't use ~0 for gen_dirty, because the gen specific
641 * emit code will loop over all the bits:
642 */
643 ctx->gen_dirty = ctx->gen_all_dirty;
644
645 for (unsigned i = 0; i < PIPE_SHADER_TYPES; i++)
646 ctx->dirty_shader[i] = (enum fd_dirty_shader_state) ~0;
647 }
648
649 static inline void
fd_context_all_clean(struct fd_context * ctx)650 fd_context_all_clean(struct fd_context *ctx) assert_dt
651 {
652 ctx->last.dirty = false;
653 ctx->dirty = (enum fd_dirty_3d_state)0;
654 ctx->gen_dirty = 0;
655 for (unsigned i = 0; i < PIPE_SHADER_TYPES; i++) {
656 /* don't mark compute state as clean, since it is not emitted
657 * during normal draw call. The places that call _all_dirty(),
658 * it is safe to mark compute state dirty as well, but the
659 * inverse is not true.
660 */
661 if (i == PIPE_SHADER_COMPUTE)
662 continue;
663 ctx->dirty_shader[i] = (enum fd_dirty_shader_state)0;
664 }
665 }
666
667 /**
668 * Add mapping between global dirty bit and generation specific dirty
669 * bit.
670 */
671 static inline void
fd_context_add_map(struct fd_context * ctx,enum fd_dirty_3d_state dirty,uint32_t gen_dirty)672 fd_context_add_map(struct fd_context *ctx, enum fd_dirty_3d_state dirty,
673 uint32_t gen_dirty)
674 {
675 u_foreach_bit (b, dirty) {
676 ctx->gen_dirty_map[b] |= gen_dirty;
677 }
678 ctx->gen_all_dirty |= gen_dirty;
679 }
680
681 /**
682 * Add mapping between shader stage specific dirty bit and generation
683 * specific dirty bit
684 */
685 static inline void
fd_context_add_shader_map(struct fd_context * ctx,enum pipe_shader_type shader,enum fd_dirty_shader_state dirty,uint32_t gen_dirty)686 fd_context_add_shader_map(struct fd_context *ctx, enum pipe_shader_type shader,
687 enum fd_dirty_shader_state dirty, uint32_t gen_dirty)
688 {
689 u_foreach_bit (b, dirty) {
690 ctx->gen_dirty_shader_map[shader][b] |= gen_dirty;
691 }
692 ctx->gen_all_dirty |= gen_dirty;
693 }
694
695 static inline struct pipe_scissor_state *
fd_context_get_scissor(struct fd_context * ctx)696 fd_context_get_scissor(struct fd_context *ctx) assert_dt
697 {
698 return ctx->current_scissor;
699 }
700
701 void fd_context_switch_from(struct fd_context *ctx) assert_dt;
702 void fd_context_switch_to(struct fd_context *ctx,
703 struct fd_batch *batch) assert_dt;
704 struct fd_batch *fd_context_batch(struct fd_context *ctx) assert_dt;
705 struct fd_batch *fd_context_batch_locked(struct fd_context *ctx) assert_dt;
706
707 void fd_context_setup_common_vbos(struct fd_context *ctx);
708 void fd_context_cleanup_common_vbos(struct fd_context *ctx);
709 void fd_emit_string(struct fd_ringbuffer *ring, const char *string, int len);
710 void fd_emit_string5(struct fd_ringbuffer *ring, const char *string, int len);
711
712 struct pipe_context *fd_context_init(struct fd_context *ctx,
713 struct pipe_screen *pscreen,
714 void *priv, unsigned flags);
715 struct pipe_context *fd_context_init_tc(struct pipe_context *pctx,
716 unsigned flags);
717
718 void fd_context_destroy(struct pipe_context *pctx) assert_dt;
719
720 #ifdef __cplusplus
721 }
722 #endif
723
724 #endif /* FREEDRENO_CONTEXT_H_ */
725