1 // Copyright (C) 2022 Beken Corporation
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #pragma once
16
17 #include <soc/soc.h>
18 #include "hal_port.h"
19 #include "aon_rtc_hw.h"
20 #include <driver/hal/hal_aon_rtc_types.h>
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 #define AON_RTC_LL_REG_BASE(_aon_rtc_unit_id) (SOC_AON_RTC_REG_BASE + (AON_RTC_SOC_REG_ADDRESS_OFFSET * _aon_rtc_unit_id))
27
aon_rtc_ll_enable(aon_rtc_hw_t * hw)28 static inline void aon_rtc_ll_enable(aon_rtc_hw_t *hw)
29 {
30 hw->ctrl.en = 1;
31 }
32
aon_rtc_ll_disable(aon_rtc_hw_t * hw)33 static inline void aon_rtc_ll_disable(aon_rtc_hw_t *hw)
34 {
35 hw->ctrl.en = 0;
36 }
37
aon_rtc_ll_is_enable(aon_rtc_hw_t * hw)38 static inline bool aon_rtc_ll_is_enable(aon_rtc_hw_t *hw)
39 {
40 return hw->ctrl.en;
41 }
42
aon_rtc_ll_stop_counter(aon_rtc_hw_t * hw)43 static inline void aon_rtc_ll_stop_counter(aon_rtc_hw_t *hw)
44 {
45 hw->ctrl.cnt_stop = 1;
46 }
47
aon_rtc_ll_start_counter(aon_rtc_hw_t * hw)48 static inline void aon_rtc_ll_start_counter(aon_rtc_hw_t *hw)
49 {
50 hw->ctrl.cnt_stop = 0;
51 }
52
aon_rtc_ll_is_counter_stop(aon_rtc_hw_t * hw)53 static inline bool aon_rtc_ll_is_counter_stop(aon_rtc_hw_t *hw)
54 {
55 return hw->ctrl.cnt_stop;
56 }
57
aon_rtc_ll_reset_counter(aon_rtc_hw_t * hw)58 static inline void aon_rtc_ll_reset_counter(aon_rtc_hw_t *hw)
59 {
60 hw->ctrl.cnt_reset = 1;
61 }
62
aon_rtc_ll_clear_reset_counter(aon_rtc_hw_t * hw)63 static inline void aon_rtc_ll_clear_reset_counter(aon_rtc_hw_t *hw)
64 {
65 hw->ctrl.cnt_reset = 0;
66 }
67
aon_rtc_ll_is_counter_reset(aon_rtc_hw_t * hw)68 static inline bool aon_rtc_ll_is_counter_reset(aon_rtc_hw_t *hw)
69 {
70 return hw->ctrl.cnt_reset;
71 }
72
aon_rtc_ll_clear_ctrl(aon_rtc_hw_t * hw)73 static inline void aon_rtc_ll_clear_ctrl(aon_rtc_hw_t *hw)
74 {
75 hw->ctrl.ctrl_v = 0;
76 }
77
aon_rtc_ll_set_tick_val(aon_rtc_hw_t * hw,uint32_t val)78 static inline void aon_rtc_ll_set_tick_val(aon_rtc_hw_t *hw, uint32_t val)
79 {
80 hw->tick_val = val;
81 }
82
aon_rtc_ll_get_tick_val(aon_rtc_hw_t * hw)83 static inline uint32_t aon_rtc_ll_get_tick_val(aon_rtc_hw_t *hw)
84 {
85 return hw->tick_val;
86 }
87
aon_rtc_ll_enable_tick_int(aon_rtc_hw_t * hw)88 static inline void aon_rtc_ll_enable_tick_int(aon_rtc_hw_t *hw)
89 {
90 hw->ctrl.tick_int_en = 1;
91 }
92
aon_rtc_ll_disable_tick_int(aon_rtc_hw_t * hw)93 static inline void aon_rtc_ll_disable_tick_int(aon_rtc_hw_t *hw)
94 {
95 hw->ctrl.tick_int_en = 0;
96 }
97
aon_rtc_ll_is_tick_int_enable(aon_rtc_hw_t * hw)98 static inline bool aon_rtc_ll_is_tick_int_enable(aon_rtc_hw_t *hw)
99 {
100 return hw->ctrl.tick_int_en;
101 }
102
aon_rtc_ll_get_tick_int_status(aon_rtc_hw_t * hw)103 static inline bool aon_rtc_ll_get_tick_int_status(aon_rtc_hw_t *hw)
104 {
105 return hw->ctrl.tick_int_sts;
106 }
107
108 //write 1 to clear interrupt
aon_rtc_ll_clear_tick_int_status(aon_rtc_hw_t * hw)109 static inline void aon_rtc_ll_clear_tick_int_status(aon_rtc_hw_t *hw)
110 {
111 hw->ctrl.tick_int_sts = 1;
112 }
113
aon_rtc_ll_set_upper_val(aon_rtc_hw_t * hw,uint32_t up_val)114 static inline void aon_rtc_ll_set_upper_val(aon_rtc_hw_t *hw, uint32_t up_val)
115 {
116 hw->upper_val = up_val;
117 }
118
aon_rtc_ll_get_upper_val(aon_rtc_hw_t * hw)119 static inline uint32_t aon_rtc_ll_get_upper_val(aon_rtc_hw_t *hw)
120 {
121 return hw->upper_val;
122 }
123
aon_rtc_ll_enable_upper_int(aon_rtc_hw_t * hw)124 static inline void aon_rtc_ll_enable_upper_int(aon_rtc_hw_t *hw)
125 {
126 hw->ctrl.up_int_en = 1;
127 }
128
aon_rtc_ll_disable_upper_int(aon_rtc_hw_t * hw)129 static inline void aon_rtc_ll_disable_upper_int(aon_rtc_hw_t *hw)
130 {
131 hw->ctrl.up_int_en = 0;
132 }
133
aon_rtc_ll_is_upper_int_enable(aon_rtc_hw_t * hw)134 static inline bool aon_rtc_ll_is_upper_int_enable(aon_rtc_hw_t *hw)
135 {
136 return hw->ctrl.up_int_en;
137 }
138
aon_rtc_ll_get_upper_int_status(aon_rtc_hw_t * hw)139 static inline bool aon_rtc_ll_get_upper_int_status(aon_rtc_hw_t *hw)
140 {
141 return hw->ctrl.up_int_sts;
142 }
143
144 //write 1 to clear interrupt
aon_rtc_ll_clear_upper_int_status(aon_rtc_hw_t * hw)145 static inline void aon_rtc_ll_clear_upper_int_status(aon_rtc_hw_t *hw)
146 {
147 hw->ctrl.up_int_sts = 1;
148 }
149
aon_rtc_ll_get_counter_val(aon_rtc_hw_t * hw)150 static inline uint32_t aon_rtc_ll_get_counter_val(aon_rtc_hw_t *hw)
151 {
152 return hw->counter_val;
153 }
154
aon_rtc_ll_get_upper_val_lpo(aon_rtc_hw_t * hw)155 static inline uint32_t aon_rtc_ll_get_upper_val_lpo(aon_rtc_hw_t *hw)
156 {
157 return hw->up_val_lpo;
158 }
159
aon_rtc_ll_get_tick_val_lpo(aon_rtc_hw_t * hw)160 static inline uint32_t aon_rtc_ll_get_tick_val_lpo(aon_rtc_hw_t *hw)
161 {
162 return hw->tick_val_lpo;
163 }
aon_rtc_ll_tick_init()164 static inline uint32_t aon_rtc_ll_tick_init()
165 {
166 uint32_t reg00 = 0X40;
167 uint32_t reg01 = 0xffffffff;
168 uint32_t reg02 = 0x0;
169
170 REG_WRITE(SOC_AON_RTC_REG_BASE+0x0*4, reg00);
171 REG_WRITE(SOC_AON_RTC_REG_BASE+0x1*4, reg01);
172 REG_WRITE(SOC_AON_RTC_REG_BASE+0x2*4, reg02);
173 return BK_OK;
174 }
aon_rtc_ll_get_current_tick()175 static inline uint32_t aon_rtc_ll_get_current_tick()
176 {
177 uint32_t val= 0;
178 val = REG_READ(SOC_AON_RTC_REG_BASE+0x3*4);
179
180 while(val != REG_READ(SOC_AON_RTC_REG_BASE+0x3*4))
181 {
182 val = REG_READ(SOC_AON_RTC_REG_BASE+0x3*4);
183 }
184 return val;
185 }
186 #define BIT_AON_RTC_RTC_TICK_INT_EN (0x8U)
aon_rtc_ll_open_rtc_wakeup(uint32_t period)187 static inline uint32_t aon_rtc_ll_open_rtc_wakeup(uint32_t period)
188 {
189 uint32_t wakeup_period= 0;
190 uint32_t rtc_int= 0;
191
192 wakeup_period = aon_rtc_ll_get_current_tick() + period;
193 REG_WRITE(SOC_AON_RTC_REG_BASE+0x2*4, wakeup_period);
194
195 rtc_int = REG_READ(SOC_AON_RTC_REG_BASE+0x0*4);
196 rtc_int |= BIT_AON_RTC_RTC_TICK_INT_EN;
197
198 REG_WRITE(SOC_AON_RTC_REG_BASE+0x0*4, rtc_int);
199 return BK_OK;
200 }
201 #ifdef __cplusplus
202 }
203 #endif
204
205
206