1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
23 u32 queues, bool drop);
24
ath9k_parse_mpdudensity(u8 mpdudensity)25 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
26 {
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58 }
59
ath9k_has_pending_frames(struct ath_softc * sc,struct ath_txq * txq,bool sw_pending)60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
61 bool sw_pending)
62 {
63 bool pending = false;
64
65 spin_lock_bh(&txq->axq_lock);
66
67 if (txq->axq_depth) {
68 pending = true;
69 goto out;
70 }
71
72 if (!sw_pending)
73 goto out;
74
75 if (txq->mac80211_qnum >= 0) {
76 struct ath_acq *acq;
77
78 acq = &sc->cur_chan->acq[txq->mac80211_qnum];
79 if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old))
80 pending = true;
81 }
82 out:
83 spin_unlock_bh(&txq->axq_lock);
84 return pending;
85 }
86
ath9k_setpower(struct ath_softc * sc,enum ath9k_power_mode mode)87 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
88 {
89 unsigned long flags;
90 bool ret;
91
92 spin_lock_irqsave(&sc->sc_pm_lock, flags);
93 ret = ath9k_hw_setpower(sc->sc_ah, mode);
94 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
95
96 return ret;
97 }
98
ath_ps_full_sleep(struct timer_list * t)99 void ath_ps_full_sleep(struct timer_list *t)
100 {
101 struct ath_softc *sc = from_timer(sc, t, sleep_timer);
102 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
103 unsigned long flags;
104 bool reset;
105
106 spin_lock_irqsave(&common->cc_lock, flags);
107 ath_hw_cycle_counters_update(common);
108 spin_unlock_irqrestore(&common->cc_lock, flags);
109
110 ath9k_hw_setrxabort(sc->sc_ah, 1);
111 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
112
113 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
114 }
115
ath9k_ps_wakeup(struct ath_softc * sc)116 void ath9k_ps_wakeup(struct ath_softc *sc)
117 {
118 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
119 unsigned long flags;
120 enum ath9k_power_mode power_mode;
121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (++sc->ps_usecount != 1)
124 goto unlock;
125
126 del_timer_sync(&sc->sleep_timer);
127 power_mode = sc->sc_ah->power_mode;
128 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
129
130 /*
131 * While the hardware is asleep, the cycle counters contain no
132 * useful data. Better clear them now so that they don't mess up
133 * survey data results.
134 */
135 if (power_mode != ATH9K_PM_AWAKE) {
136 spin_lock(&common->cc_lock);
137 ath_hw_cycle_counters_update(common);
138 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
139 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
140 spin_unlock(&common->cc_lock);
141 }
142
143 unlock:
144 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
145 }
146
ath9k_ps_restore(struct ath_softc * sc)147 void ath9k_ps_restore(struct ath_softc *sc)
148 {
149 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
150 enum ath9k_power_mode mode;
151 unsigned long flags;
152
153 spin_lock_irqsave(&sc->sc_pm_lock, flags);
154 if (--sc->ps_usecount != 0)
155 goto unlock;
156
157 if (sc->ps_idle) {
158 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
159 goto unlock;
160 }
161
162 if (sc->ps_enabled &&
163 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
164 PS_WAIT_FOR_CAB |
165 PS_WAIT_FOR_PSPOLL_DATA |
166 PS_WAIT_FOR_TX_ACK |
167 PS_WAIT_FOR_ANI))) {
168 mode = ATH9K_PM_NETWORK_SLEEP;
169 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
170 ath9k_btcoex_stop_gen_timer(sc);
171 } else {
172 goto unlock;
173 }
174
175 spin_lock(&common->cc_lock);
176 ath_hw_cycle_counters_update(common);
177 spin_unlock(&common->cc_lock);
178
179 ath9k_hw_setpower(sc->sc_ah, mode);
180
181 unlock:
182 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
183 }
184
__ath_cancel_work(struct ath_softc * sc)185 static void __ath_cancel_work(struct ath_softc *sc)
186 {
187 cancel_work_sync(&sc->paprd_work);
188 cancel_delayed_work_sync(&sc->hw_check_work);
189 cancel_delayed_work_sync(&sc->hw_pll_work);
190
191 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
192 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
193 cancel_work_sync(&sc->mci_work);
194 #endif
195 }
196
ath_cancel_work(struct ath_softc * sc)197 void ath_cancel_work(struct ath_softc *sc)
198 {
199 __ath_cancel_work(sc);
200 cancel_work_sync(&sc->hw_reset_work);
201 }
202
ath_restart_work(struct ath_softc * sc)203 void ath_restart_work(struct ath_softc *sc)
204 {
205 ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work,
206 ATH_HW_CHECK_POLL_INT);
207
208 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
209 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
210 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
211
212 ath_start_ani(sc);
213 }
214
ath_prepare_reset(struct ath_softc * sc)215 static bool ath_prepare_reset(struct ath_softc *sc)
216 {
217 struct ath_hw *ah = sc->sc_ah;
218 bool ret = true;
219
220 ieee80211_stop_queues(sc->hw);
221 ath_stop_ani(sc);
222 ath9k_hw_disable_interrupts(ah);
223
224 if (AR_SREV_9300_20_OR_LATER(ah)) {
225 ret &= ath_stoprecv(sc);
226 ret &= ath_drain_all_txq(sc);
227 } else {
228 ret &= ath_drain_all_txq(sc);
229 ret &= ath_stoprecv(sc);
230 }
231
232 return ret;
233 }
234
ath_complete_reset(struct ath_softc * sc,bool start)235 static bool ath_complete_reset(struct ath_softc *sc, bool start)
236 {
237 struct ath_hw *ah = sc->sc_ah;
238 struct ath_common *common = ath9k_hw_common(ah);
239 unsigned long flags;
240
241 ath9k_calculate_summary_state(sc, sc->cur_chan);
242 ath_startrecv(sc);
243 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
244 sc->cur_chan->txpower,
245 &sc->cur_chan->cur_txpower);
246 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
247
248 if (!sc->cur_chan->offchannel && start) {
249 /* restore per chanctx TSF timer */
250 if (sc->cur_chan->tsf_val) {
251 u32 offset;
252
253 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
254 NULL);
255 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
256 }
257
258
259 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
260 goto work;
261
262 if (ah->opmode == NL80211_IFTYPE_STATION &&
263 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
264 spin_lock_irqsave(&sc->sc_pm_lock, flags);
265 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
266 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
267 } else {
268 ath9k_set_beacon(sc);
269 }
270 work:
271 ath_restart_work(sc);
272 ath_txq_schedule_all(sc);
273 }
274
275 sc->gtt_cnt = 0;
276
277 ath9k_hw_set_interrupts(ah);
278 ath9k_hw_enable_interrupts(ah);
279 ieee80211_wake_queues(sc->hw);
280 ath9k_p2p_ps_timer(sc);
281
282 return true;
283 }
284
ath_reset_internal(struct ath_softc * sc,struct ath9k_channel * hchan)285 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
286 {
287 struct ath_hw *ah = sc->sc_ah;
288 struct ath_common *common = ath9k_hw_common(ah);
289 struct ath9k_hw_cal_data *caldata = NULL;
290 bool fastcc = true;
291 int r;
292
293 __ath_cancel_work(sc);
294
295 disable_irq(sc->irq);
296 tasklet_disable(&sc->intr_tq);
297 tasklet_disable(&sc->bcon_tasklet);
298 spin_lock_bh(&sc->sc_pcu_lock);
299
300 if (!sc->cur_chan->offchannel) {
301 fastcc = false;
302 caldata = &sc->cur_chan->caldata;
303 }
304
305 if (!hchan) {
306 fastcc = false;
307 hchan = ah->curchan;
308 }
309
310 if (!hchan) {
311 fastcc = false;
312 hchan = ath9k_cmn_get_channel(sc->hw, ah, &sc->cur_chan->chandef);
313 }
314
315 if (!ath_prepare_reset(sc))
316 fastcc = false;
317
318 if (ath9k_is_chanctx_enabled())
319 fastcc = false;
320
321 spin_lock_bh(&sc->chan_lock);
322 sc->cur_chandef = sc->cur_chan->chandef;
323 spin_unlock_bh(&sc->chan_lock);
324
325 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
326 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
327
328 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
329 if (r) {
330 ath_err(common,
331 "Unable to reset channel, reset status %d\n", r);
332
333 ath9k_hw_enable_interrupts(ah);
334 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
335
336 goto out;
337 }
338
339 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
340 sc->cur_chan->offchannel)
341 ath9k_mci_set_txpower(sc, true, false);
342
343 if (!ath_complete_reset(sc, true))
344 r = -EIO;
345
346 out:
347 enable_irq(sc->irq);
348 spin_unlock_bh(&sc->sc_pcu_lock);
349 tasklet_enable(&sc->bcon_tasklet);
350 tasklet_enable(&sc->intr_tq);
351
352 return r;
353 }
354
ath_node_attach(struct ath_softc * sc,struct ieee80211_sta * sta,struct ieee80211_vif * vif)355 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
356 struct ieee80211_vif *vif)
357 {
358 struct ath_node *an;
359 an = (struct ath_node *)sta->drv_priv;
360
361 an->sc = sc;
362 an->sta = sta;
363 an->vif = vif;
364 memset(&an->key_idx, 0, sizeof(an->key_idx));
365
366 ath_tx_node_init(sc, an);
367
368 ath_dynack_node_init(sc->sc_ah, an);
369 }
370
ath_node_detach(struct ath_softc * sc,struct ieee80211_sta * sta)371 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
372 {
373 struct ath_node *an = (struct ath_node *)sta->drv_priv;
374 ath_tx_node_cleanup(sc, an);
375
376 ath_dynack_node_deinit(sc->sc_ah, an);
377 }
378
ath9k_tasklet(struct tasklet_struct * t)379 void ath9k_tasklet(struct tasklet_struct *t)
380 {
381 struct ath_softc *sc = from_tasklet(sc, t, intr_tq);
382 struct ath_hw *ah = sc->sc_ah;
383 struct ath_common *common = ath9k_hw_common(ah);
384 enum ath_reset_type type;
385 unsigned long flags;
386 u32 status;
387 u32 rxmask;
388
389 spin_lock_irqsave(&sc->intr_lock, flags);
390 status = sc->intrstatus;
391 sc->intrstatus = 0;
392 spin_unlock_irqrestore(&sc->intr_lock, flags);
393
394 ath9k_ps_wakeup(sc);
395 spin_lock(&sc->sc_pcu_lock);
396
397 if (status & ATH9K_INT_FATAL) {
398 type = RESET_TYPE_FATAL_INT;
399 ath9k_queue_reset(sc, type);
400 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
401 goto out;
402 }
403
404 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
405 (status & ATH9K_INT_BB_WATCHDOG)) {
406 spin_lock_irqsave(&common->cc_lock, flags);
407 ath_hw_cycle_counters_update(common);
408 ar9003_hw_bb_watchdog_dbg_info(ah);
409 spin_unlock_irqrestore(&common->cc_lock, flags);
410
411 if (ar9003_hw_bb_watchdog_check(ah)) {
412 type = RESET_TYPE_BB_WATCHDOG;
413 ath9k_queue_reset(sc, type);
414
415 ath_dbg(common, RESET,
416 "BB_WATCHDOG: Skipping interrupts\n");
417 goto out;
418 }
419 }
420
421 if (status & ATH9K_INT_GTT) {
422 sc->gtt_cnt++;
423
424 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
425 type = RESET_TYPE_TX_GTT;
426 ath9k_queue_reset(sc, type);
427 ath_dbg(common, RESET,
428 "GTT: Skipping interrupts\n");
429 goto out;
430 }
431 }
432
433 spin_lock_irqsave(&sc->sc_pm_lock, flags);
434 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
435 /*
436 * TSF sync does not look correct; remain awake to sync with
437 * the next Beacon.
438 */
439 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
440 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
441 }
442 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
443
444 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
445 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
446 ATH9K_INT_RXORN);
447 else
448 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
449
450 if (status & rxmask) {
451 /* Check for high priority Rx first */
452 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
453 (status & ATH9K_INT_RXHP))
454 ath_rx_tasklet(sc, 0, true);
455
456 ath_rx_tasklet(sc, 0, false);
457 }
458
459 if (status & ATH9K_INT_TX) {
460 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
461 /*
462 * For EDMA chips, TX completion is enabled for the
463 * beacon queue, so if a beacon has been transmitted
464 * successfully after a GTT interrupt, the GTT counter
465 * gets reset to zero here.
466 */
467 sc->gtt_cnt = 0;
468
469 ath_tx_edma_tasklet(sc);
470 } else {
471 ath_tx_tasklet(sc);
472 }
473
474 wake_up(&sc->tx_wait);
475 }
476
477 if (status & ATH9K_INT_GENTIMER)
478 ath_gen_timer_isr(sc->sc_ah);
479
480 ath9k_btcoex_handle_interrupt(sc, status);
481
482 /* re-enable hardware interrupt */
483 ath9k_hw_resume_interrupts(ah);
484 out:
485 spin_unlock(&sc->sc_pcu_lock);
486 ath9k_ps_restore(sc);
487 }
488
ath_isr(int irq,void * dev)489 irqreturn_t ath_isr(int irq, void *dev)
490 {
491 #define SCHED_INTR ( \
492 ATH9K_INT_FATAL | \
493 ATH9K_INT_BB_WATCHDOG | \
494 ATH9K_INT_RXORN | \
495 ATH9K_INT_RXEOL | \
496 ATH9K_INT_RX | \
497 ATH9K_INT_RXLP | \
498 ATH9K_INT_RXHP | \
499 ATH9K_INT_TX | \
500 ATH9K_INT_BMISS | \
501 ATH9K_INT_CST | \
502 ATH9K_INT_GTT | \
503 ATH9K_INT_TSFOOR | \
504 ATH9K_INT_GENTIMER | \
505 ATH9K_INT_MCI)
506
507 struct ath_softc *sc = dev;
508 struct ath_hw *ah = sc->sc_ah;
509 struct ath_common *common = ath9k_hw_common(ah);
510 enum ath9k_int status;
511 u32 sync_cause = 0;
512 bool sched = false;
513
514 /*
515 * The hardware is not ready/present, don't
516 * touch anything. Note this can happen early
517 * on if the IRQ is shared.
518 */
519 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
520 return IRQ_NONE;
521
522 /* shared irq, not for us */
523 if (!ath9k_hw_intrpend(ah))
524 return IRQ_NONE;
525
526 /*
527 * Figure out the reason(s) for the interrupt. Note
528 * that the hal returns a pseudo-ISR that may include
529 * bits we haven't explicitly enabled so we mask the
530 * value to insure we only process bits we requested.
531 */
532 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
533 ath9k_debug_sync_cause(sc, sync_cause);
534 status &= ah->imask; /* discard unasked-for bits */
535
536 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {
537 ath9k_hw_kill_interrupts(sc->sc_ah);
538 return IRQ_HANDLED;
539 }
540
541 /*
542 * If there are no status bits set, then this interrupt was not
543 * for me (should have been caught above).
544 */
545 if (!status)
546 return IRQ_NONE;
547
548 /* Cache the status */
549 spin_lock(&sc->intr_lock);
550 sc->intrstatus |= status;
551 spin_unlock(&sc->intr_lock);
552
553 if (status & SCHED_INTR)
554 sched = true;
555
556 /*
557 * If a FATAL interrupt is received, we have to reset the chip
558 * immediately.
559 */
560 if (status & ATH9K_INT_FATAL)
561 goto chip_reset;
562
563 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
564 (status & ATH9K_INT_BB_WATCHDOG))
565 goto chip_reset;
566
567 if (status & ATH9K_INT_SWBA)
568 tasklet_schedule(&sc->bcon_tasklet);
569
570 if (status & ATH9K_INT_TXURN)
571 ath9k_hw_updatetxtriglevel(ah, true);
572
573 if (status & ATH9K_INT_RXEOL) {
574 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
575 ath9k_hw_set_interrupts(ah);
576 }
577
578 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
579 if (status & ATH9K_INT_TIM_TIMER) {
580 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
581 goto chip_reset;
582 /* Clear RxAbort bit so that we can
583 * receive frames */
584 ath9k_setpower(sc, ATH9K_PM_AWAKE);
585 spin_lock(&sc->sc_pm_lock);
586 ath9k_hw_setrxabort(sc->sc_ah, 0);
587 sc->ps_flags |= PS_WAIT_FOR_BEACON;
588 spin_unlock(&sc->sc_pm_lock);
589 }
590
591 chip_reset:
592
593 ath_debug_stat_interrupt(sc, status);
594
595 if (sched) {
596 /* turn off every interrupt */
597 ath9k_hw_kill_interrupts(ah);
598 tasklet_schedule(&sc->intr_tq);
599 }
600
601 return IRQ_HANDLED;
602
603 #undef SCHED_INTR
604 }
605
606 /*
607 * This function is called when a HW reset cannot be deferred
608 * and has to be immediate.
609 */
ath_reset(struct ath_softc * sc,struct ath9k_channel * hchan)610 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
611 {
612 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
613 int r;
614
615 ath9k_hw_kill_interrupts(sc->sc_ah);
616 set_bit(ATH_OP_HW_RESET, &common->op_flags);
617
618 ath9k_ps_wakeup(sc);
619 r = ath_reset_internal(sc, hchan);
620 ath9k_ps_restore(sc);
621
622 return r;
623 }
624
625 /*
626 * When a HW reset can be deferred, it is added to the
627 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
628 * queueing.
629 */
ath9k_queue_reset(struct ath_softc * sc,enum ath_reset_type type)630 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
631 {
632 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
633 #ifdef CONFIG_ATH9K_DEBUGFS
634 RESET_STAT_INC(sc, type);
635 #endif
636 ath9k_hw_kill_interrupts(sc->sc_ah);
637 set_bit(ATH_OP_HW_RESET, &common->op_flags);
638 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
639 }
640
ath_reset_work(struct work_struct * work)641 void ath_reset_work(struct work_struct *work)
642 {
643 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
644
645 ath9k_ps_wakeup(sc);
646 ath_reset_internal(sc, NULL);
647 ath9k_ps_restore(sc);
648 }
649
650 /**********************/
651 /* mac80211 callbacks */
652 /**********************/
653
ath9k_start(struct ieee80211_hw * hw)654 static int ath9k_start(struct ieee80211_hw *hw)
655 {
656 struct ath_softc *sc = hw->priv;
657 struct ath_hw *ah = sc->sc_ah;
658 struct ath_common *common = ath9k_hw_common(ah);
659 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
660 struct ath_chanctx *ctx = sc->cur_chan;
661 struct ath9k_channel *init_channel;
662 int r;
663
664 ath_dbg(common, CONFIG,
665 "Starting driver with initial channel: %d MHz\n",
666 curchan->center_freq);
667
668 ath9k_ps_wakeup(sc);
669 mutex_lock(&sc->mutex);
670
671 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
672 sc->cur_chandef = hw->conf.chandef;
673
674 /* Reset SERDES registers */
675 ath9k_hw_configpcipowersave(ah, false);
676
677 /*
678 * The basic interface to setting the hardware in a good
679 * state is ``reset''. On return the hardware is known to
680 * be powered up and with interrupts disabled. This must
681 * be followed by initialization of the appropriate bits
682 * and then setup of the interrupt mask.
683 */
684 spin_lock_bh(&sc->sc_pcu_lock);
685
686 atomic_set(&ah->intr_ref_cnt, -1);
687
688 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
689 if (r) {
690 ath_err(common,
691 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
692 r, curchan->center_freq);
693 ah->reset_power_on = false;
694 }
695
696 /* Setup our intr mask. */
697 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
698 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
699 ATH9K_INT_GLOBAL;
700
701 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
702 ah->imask |= ATH9K_INT_RXHP |
703 ATH9K_INT_RXLP;
704 else
705 ah->imask |= ATH9K_INT_RX;
706
707 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
708 ah->imask |= ATH9K_INT_BB_WATCHDOG;
709
710 /*
711 * Enable GTT interrupts only for AR9003/AR9004 chips
712 * for now.
713 */
714 if (AR_SREV_9300_20_OR_LATER(ah))
715 ah->imask |= ATH9K_INT_GTT;
716
717 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
718 ah->imask |= ATH9K_INT_CST;
719
720 ath_mci_enable(sc);
721
722 clear_bit(ATH_OP_INVALID, &common->op_flags);
723 sc->sc_ah->is_monitoring = false;
724
725 if (!ath_complete_reset(sc, false))
726 ah->reset_power_on = false;
727
728 if (ah->led_pin >= 0) {
729 ath9k_hw_set_gpio(ah, ah->led_pin,
730 (ah->config.led_active_high) ? 1 : 0);
731 ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL,
732 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
733 }
734
735 /*
736 * Reset key cache to sane defaults (all entries cleared) instead of
737 * semi-random values after suspend/resume.
738 */
739 ath9k_cmn_init_crypto(sc->sc_ah);
740
741 ath9k_hw_reset_tsf(ah);
742
743 spin_unlock_bh(&sc->sc_pcu_lock);
744
745 ath9k_rng_start(sc);
746
747 mutex_unlock(&sc->mutex);
748
749 ath9k_ps_restore(sc);
750
751 return 0;
752 }
753
ath9k_tx(struct ieee80211_hw * hw,struct ieee80211_tx_control * control,struct sk_buff * skb)754 static void ath9k_tx(struct ieee80211_hw *hw,
755 struct ieee80211_tx_control *control,
756 struct sk_buff *skb)
757 {
758 struct ath_softc *sc = hw->priv;
759 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
760 struct ath_tx_control txctl;
761 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
762 unsigned long flags;
763
764 if (sc->ps_enabled) {
765 /*
766 * mac80211 does not set PM field for normal data frames, so we
767 * need to update that based on the current PS mode.
768 */
769 if (ieee80211_is_data(hdr->frame_control) &&
770 !ieee80211_is_nullfunc(hdr->frame_control) &&
771 !ieee80211_has_pm(hdr->frame_control)) {
772 ath_dbg(common, PS,
773 "Add PM=1 for a TX frame while in PS mode\n");
774 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
775 }
776 }
777
778 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
779 /*
780 * We are using PS-Poll and mac80211 can request TX while in
781 * power save mode. Need to wake up hardware for the TX to be
782 * completed and if needed, also for RX of buffered frames.
783 */
784 ath9k_ps_wakeup(sc);
785 spin_lock_irqsave(&sc->sc_pm_lock, flags);
786 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
787 ath9k_hw_setrxabort(sc->sc_ah, 0);
788 if (ieee80211_is_pspoll(hdr->frame_control)) {
789 ath_dbg(common, PS,
790 "Sending PS-Poll to pick a buffered frame\n");
791 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
792 } else {
793 ath_dbg(common, PS, "Wake up to complete TX\n");
794 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
795 }
796 /*
797 * The actual restore operation will happen only after
798 * the ps_flags bit is cleared. We are just dropping
799 * the ps_usecount here.
800 */
801 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
802 ath9k_ps_restore(sc);
803 }
804
805 /*
806 * Cannot tx while the hardware is in full sleep, it first needs a full
807 * chip reset to recover from that
808 */
809 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
810 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
811 goto exit;
812 }
813
814 memset(&txctl, 0, sizeof(struct ath_tx_control));
815 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
816 txctl.sta = control->sta;
817
818 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
819
820 if (ath_tx_start(hw, skb, &txctl) != 0) {
821 ath_dbg(common, XMIT, "TX failed\n");
822 TX_STAT_INC(sc, txctl.txq->axq_qnum, txfailed);
823 goto exit;
824 }
825
826 return;
827 exit:
828 ieee80211_free_txskb(hw, skb);
829 }
830
ath9k_txq_list_has_key(struct list_head * txq_list,u32 keyix)831 static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix)
832 {
833 struct ath_buf *bf;
834 struct ieee80211_tx_info *txinfo;
835 struct ath_frame_info *fi;
836
837 list_for_each_entry(bf, txq_list, list) {
838 if (bf->bf_state.stale || !bf->bf_mpdu)
839 continue;
840
841 txinfo = IEEE80211_SKB_CB(bf->bf_mpdu);
842 fi = (struct ath_frame_info *)&txinfo->status.status_driver_data[0];
843 if (fi->keyix == keyix)
844 return true;
845 }
846
847 return false;
848 }
849
ath9k_txq_has_key(struct ath_softc * sc,u32 keyix)850 static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix)
851 {
852 struct ath_hw *ah = sc->sc_ah;
853 int i;
854 struct ath_txq *txq;
855 bool key_in_use = false;
856
857 for (i = 0; !key_in_use && i < ATH9K_NUM_TX_QUEUES; i++) {
858 if (!ATH_TXQ_SETUP(sc, i))
859 continue;
860 txq = &sc->tx.txq[i];
861 if (!txq->axq_depth)
862 continue;
863 if (!ath9k_hw_numtxpending(ah, txq->axq_qnum))
864 continue;
865
866 ath_txq_lock(sc, txq);
867 key_in_use = ath9k_txq_list_has_key(&txq->axq_q, keyix);
868 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
869 int idx = txq->txq_tailidx;
870
871 while (!key_in_use &&
872 !list_empty(&txq->txq_fifo[idx])) {
873 key_in_use = ath9k_txq_list_has_key(
874 &txq->txq_fifo[idx], keyix);
875 INCR(idx, ATH_TXFIFO_DEPTH);
876 }
877 }
878 ath_txq_unlock(sc, txq);
879 }
880
881 return key_in_use;
882 }
883
ath9k_pending_key_del(struct ath_softc * sc,u8 keyix)884 static void ath9k_pending_key_del(struct ath_softc *sc, u8 keyix)
885 {
886 struct ath_hw *ah = sc->sc_ah;
887 struct ath_common *common = ath9k_hw_common(ah);
888
889 if (!test_bit(keyix, ah->pending_del_keymap) ||
890 ath9k_txq_has_key(sc, keyix))
891 return;
892
893 /* No more TXQ frames point to this key cache entry, so delete it. */
894 clear_bit(keyix, ah->pending_del_keymap);
895 ath_key_delete(common, keyix);
896 }
897
ath9k_stop(struct ieee80211_hw * hw)898 static void ath9k_stop(struct ieee80211_hw *hw)
899 {
900 struct ath_softc *sc = hw->priv;
901 struct ath_hw *ah = sc->sc_ah;
902 struct ath_common *common = ath9k_hw_common(ah);
903 bool prev_idle;
904 int i;
905
906 ath9k_deinit_channel_context(sc);
907
908 mutex_lock(&sc->mutex);
909
910 ath9k_rng_stop(sc);
911
912 ath_cancel_work(sc);
913
914 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
915 ath_dbg(common, ANY, "Device not present\n");
916 mutex_unlock(&sc->mutex);
917 return;
918 }
919
920 /* Ensure HW is awake when we try to shut it down. */
921 ath9k_ps_wakeup(sc);
922
923 spin_lock_bh(&sc->sc_pcu_lock);
924
925 /* prevent tasklets to enable interrupts once we disable them */
926 ah->imask &= ~ATH9K_INT_GLOBAL;
927
928 /* make sure h/w will not generate any interrupt
929 * before setting the invalid flag. */
930 ath9k_hw_disable_interrupts(ah);
931
932 spin_unlock_bh(&sc->sc_pcu_lock);
933
934 /* we can now sync irq and kill any running tasklets, since we already
935 * disabled interrupts and not holding a spin lock */
936 synchronize_irq(sc->irq);
937 tasklet_kill(&sc->intr_tq);
938 tasklet_kill(&sc->bcon_tasklet);
939
940 prev_idle = sc->ps_idle;
941 sc->ps_idle = true;
942
943 spin_lock_bh(&sc->sc_pcu_lock);
944
945 if (ah->led_pin >= 0) {
946 ath9k_hw_set_gpio(ah, ah->led_pin,
947 (ah->config.led_active_high) ? 0 : 1);
948 ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL);
949 }
950
951 ath_prepare_reset(sc);
952
953 if (sc->rx.frag) {
954 dev_kfree_skb_any(sc->rx.frag);
955 sc->rx.frag = NULL;
956 }
957
958 if (!ah->curchan)
959 ah->curchan = ath9k_cmn_get_channel(hw, ah,
960 &sc->cur_chan->chandef);
961
962 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
963
964 set_bit(ATH_OP_INVALID, &common->op_flags);
965
966 ath9k_hw_phy_disable(ah);
967
968 ath9k_hw_configpcipowersave(ah, true);
969
970 spin_unlock_bh(&sc->sc_pcu_lock);
971
972 for (i = 0; i < ATH_KEYMAX; i++)
973 ath9k_pending_key_del(sc, i);
974
975 /* Clear key cache entries explicitly to get rid of any potentially
976 * remaining keys.
977 */
978 ath9k_cmn_init_crypto(sc->sc_ah);
979
980 ath9k_ps_restore(sc);
981
982 sc->ps_idle = prev_idle;
983
984 mutex_unlock(&sc->mutex);
985
986 ath_dbg(common, CONFIG, "Driver halt\n");
987 }
988
ath9k_uses_beacons(int type)989 static bool ath9k_uses_beacons(int type)
990 {
991 switch (type) {
992 case NL80211_IFTYPE_AP:
993 case NL80211_IFTYPE_ADHOC:
994 case NL80211_IFTYPE_MESH_POINT:
995 return true;
996 default:
997 return false;
998 }
999 }
1000
ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data * iter_data,struct ieee80211_vif * vif)1001 static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data,
1002 struct ieee80211_vif *vif)
1003 {
1004 /* Use the first (configured) interface, but prefering AP interfaces. */
1005 if (!iter_data->primary_beacon_vif) {
1006 iter_data->primary_beacon_vif = vif;
1007 } else {
1008 if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP &&
1009 vif->type == NL80211_IFTYPE_AP)
1010 iter_data->primary_beacon_vif = vif;
1011 }
1012
1013 iter_data->beacons = true;
1014 iter_data->nbcnvifs += 1;
1015 }
1016
ath9k_vif_iter(struct ath9k_vif_iter_data * iter_data,u8 * mac,struct ieee80211_vif * vif)1017 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
1018 u8 *mac, struct ieee80211_vif *vif)
1019 {
1020 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1021 int i;
1022
1023 if (iter_data->has_hw_macaddr) {
1024 for (i = 0; i < ETH_ALEN; i++)
1025 iter_data->mask[i] &=
1026 ~(iter_data->hw_macaddr[i] ^ mac[i]);
1027 } else {
1028 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
1029 iter_data->has_hw_macaddr = true;
1030 }
1031
1032 if (!vif->bss_conf.use_short_slot)
1033 iter_data->slottime = 20;
1034
1035 switch (vif->type) {
1036 case NL80211_IFTYPE_AP:
1037 iter_data->naps++;
1038 if (vif->bss_conf.enable_beacon)
1039 ath9k_vif_iter_set_beacon(iter_data, vif);
1040 break;
1041 case NL80211_IFTYPE_STATION:
1042 iter_data->nstations++;
1043 if (avp->assoc && !iter_data->primary_sta)
1044 iter_data->primary_sta = vif;
1045 break;
1046 case NL80211_IFTYPE_OCB:
1047 iter_data->nocbs++;
1048 break;
1049 case NL80211_IFTYPE_ADHOC:
1050 iter_data->nadhocs++;
1051 if (vif->bss_conf.enable_beacon)
1052 ath9k_vif_iter_set_beacon(iter_data, vif);
1053 break;
1054 case NL80211_IFTYPE_MESH_POINT:
1055 iter_data->nmeshes++;
1056 if (vif->bss_conf.enable_beacon)
1057 ath9k_vif_iter_set_beacon(iter_data, vif);
1058 break;
1059 case NL80211_IFTYPE_WDS:
1060 iter_data->nwds++;
1061 break;
1062 default:
1063 break;
1064 }
1065 }
1066
ath9k_update_bssid_mask(struct ath_softc * sc,struct ath_chanctx * ctx,struct ath9k_vif_iter_data * iter_data)1067 static void ath9k_update_bssid_mask(struct ath_softc *sc,
1068 struct ath_chanctx *ctx,
1069 struct ath9k_vif_iter_data *iter_data)
1070 {
1071 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1072 struct ath_vif *avp;
1073 int i;
1074
1075 if (!ath9k_is_chanctx_enabled())
1076 return;
1077
1078 list_for_each_entry(avp, &ctx->vifs, list) {
1079 if (ctx->nvifs_assigned != 1)
1080 continue;
1081
1082 if (!iter_data->has_hw_macaddr)
1083 continue;
1084
1085 ether_addr_copy(common->curbssid, avp->bssid);
1086
1087 /* perm_addr will be used as the p2p device address. */
1088 for (i = 0; i < ETH_ALEN; i++)
1089 iter_data->mask[i] &=
1090 ~(iter_data->hw_macaddr[i] ^
1091 sc->hw->wiphy->perm_addr[i]);
1092 }
1093 }
1094
1095 /* Called with sc->mutex held. */
ath9k_calculate_iter_data(struct ath_softc * sc,struct ath_chanctx * ctx,struct ath9k_vif_iter_data * iter_data)1096 void ath9k_calculate_iter_data(struct ath_softc *sc,
1097 struct ath_chanctx *ctx,
1098 struct ath9k_vif_iter_data *iter_data)
1099 {
1100 struct ath_vif *avp;
1101
1102 /*
1103 * The hardware will use primary station addr together with the
1104 * BSSID mask when matching addresses.
1105 */
1106 memset(iter_data, 0, sizeof(*iter_data));
1107 eth_broadcast_addr(iter_data->mask);
1108 iter_data->slottime = 9;
1109
1110 list_for_each_entry(avp, &ctx->vifs, list)
1111 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1112
1113 ath9k_update_bssid_mask(sc, ctx, iter_data);
1114 }
1115
ath9k_set_assoc_state(struct ath_softc * sc,struct ieee80211_vif * vif,bool changed)1116 static void ath9k_set_assoc_state(struct ath_softc *sc,
1117 struct ieee80211_vif *vif, bool changed)
1118 {
1119 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1120 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1121 unsigned long flags;
1122
1123 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1124
1125 ether_addr_copy(common->curbssid, avp->bssid);
1126 common->curaid = avp->aid;
1127 ath9k_hw_write_associd(sc->sc_ah);
1128
1129 if (changed) {
1130 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1131 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1132
1133 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1134 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1135 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1136 }
1137
1138 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1139 ath9k_mci_update_wlan_channels(sc, false);
1140
1141 ath_dbg(common, CONFIG,
1142 "Primary Station interface: %pM, BSSID: %pM\n",
1143 vif->addr, common->curbssid);
1144 }
1145
1146 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
ath9k_set_offchannel_state(struct ath_softc * sc)1147 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1148 {
1149 struct ath_hw *ah = sc->sc_ah;
1150 struct ath_common *common = ath9k_hw_common(ah);
1151 struct ieee80211_vif *vif = NULL;
1152
1153 ath9k_ps_wakeup(sc);
1154
1155 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1156 vif = sc->offchannel.scan_vif;
1157 else
1158 vif = sc->offchannel.roc_vif;
1159
1160 if (WARN_ON(!vif))
1161 goto exit;
1162
1163 eth_zero_addr(common->curbssid);
1164 eth_broadcast_addr(common->bssidmask);
1165 memcpy(common->macaddr, vif->addr, ETH_ALEN);
1166 common->curaid = 0;
1167 ah->opmode = vif->type;
1168 ah->imask &= ~ATH9K_INT_SWBA;
1169 ah->imask &= ~ATH9K_INT_TSFOOR;
1170 ah->slottime = 9;
1171
1172 ath_hw_setbssidmask(common);
1173 ath9k_hw_setopmode(ah);
1174 ath9k_hw_write_associd(sc->sc_ah);
1175 ath9k_hw_set_interrupts(ah);
1176 ath9k_hw_init_global_settings(ah);
1177
1178 exit:
1179 ath9k_ps_restore(sc);
1180 }
1181 #endif
1182
1183 /* Called with sc->mutex held. */
ath9k_calculate_summary_state(struct ath_softc * sc,struct ath_chanctx * ctx)1184 void ath9k_calculate_summary_state(struct ath_softc *sc,
1185 struct ath_chanctx *ctx)
1186 {
1187 struct ath_hw *ah = sc->sc_ah;
1188 struct ath_common *common = ath9k_hw_common(ah);
1189 struct ath9k_vif_iter_data iter_data;
1190
1191 ath_chanctx_check_active(sc, ctx);
1192
1193 if (ctx != sc->cur_chan)
1194 return;
1195
1196 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1197 if (ctx == &sc->offchannel.chan)
1198 return ath9k_set_offchannel_state(sc);
1199 #endif
1200
1201 ath9k_ps_wakeup(sc);
1202 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1203
1204 if (iter_data.has_hw_macaddr)
1205 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1206
1207 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1208 ath_hw_setbssidmask(common);
1209
1210 if (iter_data.naps > 0) {
1211 ath9k_hw_set_tsfadjust(ah, true);
1212 ah->opmode = NL80211_IFTYPE_AP;
1213 } else {
1214 ath9k_hw_set_tsfadjust(ah, false);
1215 if (iter_data.beacons)
1216 ath9k_beacon_ensure_primary_slot(sc);
1217
1218 if (iter_data.nmeshes)
1219 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1220 else if (iter_data.nocbs)
1221 ah->opmode = NL80211_IFTYPE_OCB;
1222 else if (iter_data.nwds)
1223 ah->opmode = NL80211_IFTYPE_AP;
1224 else if (iter_data.nadhocs)
1225 ah->opmode = NL80211_IFTYPE_ADHOC;
1226 else
1227 ah->opmode = NL80211_IFTYPE_STATION;
1228 }
1229
1230 ath9k_hw_setopmode(ah);
1231
1232 ctx->switch_after_beacon = false;
1233 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1234 ah->imask |= ATH9K_INT_TSFOOR;
1235 else {
1236 ah->imask &= ~ATH9K_INT_TSFOOR;
1237 if (iter_data.naps == 1 && iter_data.beacons)
1238 ctx->switch_after_beacon = true;
1239 }
1240
1241 if (ah->opmode == NL80211_IFTYPE_STATION) {
1242 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1243
1244 if (iter_data.primary_sta) {
1245 iter_data.primary_beacon_vif = iter_data.primary_sta;
1246 iter_data.beacons = true;
1247 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1248 changed);
1249 ctx->primary_sta = iter_data.primary_sta;
1250 } else {
1251 ctx->primary_sta = NULL;
1252 eth_zero_addr(common->curbssid);
1253 common->curaid = 0;
1254 ath9k_hw_write_associd(sc->sc_ah);
1255 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1256 ath9k_mci_update_wlan_channels(sc, true);
1257 }
1258 }
1259 sc->nbcnvifs = iter_data.nbcnvifs;
1260 ath9k_beacon_config(sc, iter_data.primary_beacon_vif,
1261 iter_data.beacons);
1262 ath9k_hw_set_interrupts(ah);
1263
1264 if (ah->slottime != iter_data.slottime) {
1265 ah->slottime = iter_data.slottime;
1266 ath9k_hw_init_global_settings(ah);
1267 }
1268
1269 if (iter_data.primary_sta)
1270 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1271 else
1272 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1273
1274 ath_dbg(common, CONFIG,
1275 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1276 common->macaddr, common->curbssid, common->bssidmask);
1277
1278 ath9k_ps_restore(sc);
1279 }
1280
ath9k_tpc_vif_iter(void * data,u8 * mac,struct ieee80211_vif * vif)1281 static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1282 {
1283 int *power = data;
1284
1285 if (vif->bss_conf.txpower == INT_MIN)
1286 return;
1287
1288 if (*power < vif->bss_conf.txpower)
1289 *power = vif->bss_conf.txpower;
1290 }
1291
1292 /* Called with sc->mutex held. */
ath9k_set_txpower(struct ath_softc * sc,struct ieee80211_vif * vif)1293 void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1294 {
1295 int power;
1296 struct ath_hw *ah = sc->sc_ah;
1297 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1298
1299 ath9k_ps_wakeup(sc);
1300 if (ah->tpc_enabled) {
1301 power = (vif) ? vif->bss_conf.txpower : -1;
1302 ieee80211_iterate_active_interfaces_atomic(
1303 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1304 ath9k_tpc_vif_iter, &power);
1305 if (power == -1)
1306 power = sc->hw->conf.power_level;
1307 } else {
1308 power = sc->hw->conf.power_level;
1309 }
1310 sc->cur_chan->txpower = 2 * power;
1311 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1312 sc->cur_chan->cur_txpower = reg->max_power_level;
1313 ath9k_ps_restore(sc);
1314 }
1315
ath9k_assign_hw_queues(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1316 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1317 struct ieee80211_vif *vif)
1318 {
1319 int i;
1320
1321 if (!ath9k_is_chanctx_enabled())
1322 return;
1323
1324 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1325 vif->hw_queue[i] = i;
1326
1327 if (vif->type == NL80211_IFTYPE_AP ||
1328 vif->type == NL80211_IFTYPE_MESH_POINT)
1329 vif->cab_queue = hw->queues - 2;
1330 else
1331 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1332 }
1333
ath9k_add_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1334 static int ath9k_add_interface(struct ieee80211_hw *hw,
1335 struct ieee80211_vif *vif)
1336 {
1337 struct ath_softc *sc = hw->priv;
1338 struct ath_hw *ah = sc->sc_ah;
1339 struct ath_common *common = ath9k_hw_common(ah);
1340 struct ath_vif *avp = (void *)vif->drv_priv;
1341 struct ath_node *an = &avp->mcast_node;
1342
1343 mutex_lock(&sc->mutex);
1344 if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1345 if (sc->cur_chan->nvifs >= 1) {
1346 mutex_unlock(&sc->mutex);
1347 return -EOPNOTSUPP;
1348 }
1349 sc->tx99_vif = vif;
1350 }
1351
1352 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1353 sc->cur_chan->nvifs++;
1354
1355 if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
1356 vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
1357
1358 if (ath9k_uses_beacons(vif->type))
1359 ath9k_beacon_assign_slot(sc, vif);
1360
1361 avp->vif = vif;
1362 if (!ath9k_is_chanctx_enabled()) {
1363 avp->chanctx = sc->cur_chan;
1364 list_add_tail(&avp->list, &avp->chanctx->vifs);
1365 }
1366
1367 ath9k_calculate_summary_state(sc, avp->chanctx);
1368
1369 ath9k_assign_hw_queues(hw, vif);
1370
1371 ath9k_set_txpower(sc, vif);
1372
1373 an->sc = sc;
1374 an->sta = NULL;
1375 an->vif = vif;
1376 an->no_ps_filter = true;
1377 ath_tx_node_init(sc, an);
1378
1379 mutex_unlock(&sc->mutex);
1380 return 0;
1381 }
1382
ath9k_change_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif,enum nl80211_iftype new_type,bool p2p)1383 static int ath9k_change_interface(struct ieee80211_hw *hw,
1384 struct ieee80211_vif *vif,
1385 enum nl80211_iftype new_type,
1386 bool p2p)
1387 {
1388 struct ath_softc *sc = hw->priv;
1389 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1390 struct ath_vif *avp = (void *)vif->drv_priv;
1391
1392 mutex_lock(&sc->mutex);
1393
1394 if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1395 mutex_unlock(&sc->mutex);
1396 return -EOPNOTSUPP;
1397 }
1398
1399 ath_dbg(common, CONFIG, "Change Interface\n");
1400
1401 if (ath9k_uses_beacons(vif->type))
1402 ath9k_beacon_remove_slot(sc, vif);
1403
1404 vif->type = new_type;
1405 vif->p2p = p2p;
1406
1407 if (ath9k_uses_beacons(vif->type))
1408 ath9k_beacon_assign_slot(sc, vif);
1409
1410 ath9k_assign_hw_queues(hw, vif);
1411 ath9k_calculate_summary_state(sc, avp->chanctx);
1412
1413 ath9k_set_txpower(sc, vif);
1414
1415 mutex_unlock(&sc->mutex);
1416 return 0;
1417 }
1418
ath9k_remove_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1419 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1420 struct ieee80211_vif *vif)
1421 {
1422 struct ath_softc *sc = hw->priv;
1423 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1424 struct ath_vif *avp = (void *)vif->drv_priv;
1425
1426 ath_dbg(common, CONFIG, "Detach Interface\n");
1427
1428 mutex_lock(&sc->mutex);
1429
1430 ath9k_p2p_remove_vif(sc, vif);
1431
1432 sc->cur_chan->nvifs--;
1433 sc->tx99_vif = NULL;
1434 if (!ath9k_is_chanctx_enabled())
1435 list_del(&avp->list);
1436
1437 if (ath9k_uses_beacons(vif->type))
1438 ath9k_beacon_remove_slot(sc, vif);
1439
1440 ath_tx_node_cleanup(sc, &avp->mcast_node);
1441
1442 ath9k_calculate_summary_state(sc, avp->chanctx);
1443
1444 ath9k_set_txpower(sc, NULL);
1445
1446 mutex_unlock(&sc->mutex);
1447 }
1448
ath9k_enable_ps(struct ath_softc * sc)1449 static void ath9k_enable_ps(struct ath_softc *sc)
1450 {
1451 struct ath_hw *ah = sc->sc_ah;
1452 struct ath_common *common = ath9k_hw_common(ah);
1453
1454 if (IS_ENABLED(CONFIG_ATH9K_TX99))
1455 return;
1456
1457 sc->ps_enabled = true;
1458 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1459 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1460 ah->imask |= ATH9K_INT_TIM_TIMER;
1461 ath9k_hw_set_interrupts(ah);
1462 }
1463 ath9k_hw_setrxabort(ah, 1);
1464 }
1465 ath_dbg(common, PS, "PowerSave enabled\n");
1466 }
1467
ath9k_disable_ps(struct ath_softc * sc)1468 static void ath9k_disable_ps(struct ath_softc *sc)
1469 {
1470 struct ath_hw *ah = sc->sc_ah;
1471 struct ath_common *common = ath9k_hw_common(ah);
1472
1473 if (IS_ENABLED(CONFIG_ATH9K_TX99))
1474 return;
1475
1476 sc->ps_enabled = false;
1477 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1478 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1479 ath9k_hw_setrxabort(ah, 0);
1480 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1481 PS_WAIT_FOR_CAB |
1482 PS_WAIT_FOR_PSPOLL_DATA |
1483 PS_WAIT_FOR_TX_ACK);
1484 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1485 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1486 ath9k_hw_set_interrupts(ah);
1487 }
1488 }
1489 ath_dbg(common, PS, "PowerSave disabled\n");
1490 }
1491
ath9k_config(struct ieee80211_hw * hw,u32 changed)1492 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1493 {
1494 struct ath_softc *sc = hw->priv;
1495 struct ath_hw *ah = sc->sc_ah;
1496 struct ath_common *common = ath9k_hw_common(ah);
1497 struct ieee80211_conf *conf = &hw->conf;
1498 struct ath_chanctx *ctx = sc->cur_chan;
1499
1500 ath9k_ps_wakeup(sc);
1501 mutex_lock(&sc->mutex);
1502
1503 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1504 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1505 if (sc->ps_idle) {
1506 ath_cancel_work(sc);
1507 ath9k_stop_btcoex(sc);
1508 } else {
1509 ath9k_start_btcoex(sc);
1510 /*
1511 * The chip needs a reset to properly wake up from
1512 * full sleep
1513 */
1514 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1515 }
1516 }
1517
1518 /*
1519 * We just prepare to enable PS. We have to wait until our AP has
1520 * ACK'd our null data frame to disable RX otherwise we'll ignore
1521 * those ACKs and end up retransmitting the same null data frames.
1522 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1523 */
1524 if (changed & IEEE80211_CONF_CHANGE_PS) {
1525 unsigned long flags;
1526 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1527 if (conf->flags & IEEE80211_CONF_PS)
1528 ath9k_enable_ps(sc);
1529 else
1530 ath9k_disable_ps(sc);
1531 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1532 }
1533
1534 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1535 if (conf->flags & IEEE80211_CONF_MONITOR) {
1536 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1537 sc->sc_ah->is_monitoring = true;
1538 } else {
1539 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1540 sc->sc_ah->is_monitoring = false;
1541 }
1542 }
1543
1544 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1545 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1546 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1547 }
1548
1549 if (changed & IEEE80211_CONF_CHANGE_POWER)
1550 ath9k_set_txpower(sc, NULL);
1551
1552 mutex_unlock(&sc->mutex);
1553 ath9k_ps_restore(sc);
1554
1555 return 0;
1556 }
1557
1558 #define SUPPORTED_FILTERS \
1559 (FIF_ALLMULTI | \
1560 FIF_CONTROL | \
1561 FIF_PSPOLL | \
1562 FIF_OTHER_BSS | \
1563 FIF_BCN_PRBRESP_PROMISC | \
1564 FIF_PROBE_REQ | \
1565 FIF_MCAST_ACTION | \
1566 FIF_FCSFAIL)
1567
1568 /* FIXME: sc->sc_full_reset ? */
ath9k_configure_filter(struct ieee80211_hw * hw,unsigned int changed_flags,unsigned int * total_flags,u64 multicast)1569 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1570 unsigned int changed_flags,
1571 unsigned int *total_flags,
1572 u64 multicast)
1573 {
1574 struct ath_softc *sc = hw->priv;
1575 struct ath_chanctx *ctx;
1576 u32 rfilt;
1577
1578 changed_flags &= SUPPORTED_FILTERS;
1579 *total_flags &= SUPPORTED_FILTERS;
1580
1581 spin_lock_bh(&sc->chan_lock);
1582 ath_for_each_chanctx(sc, ctx)
1583 ctx->rxfilter = *total_flags;
1584 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1585 sc->offchannel.chan.rxfilter = *total_flags;
1586 #endif
1587 spin_unlock_bh(&sc->chan_lock);
1588
1589 ath9k_ps_wakeup(sc);
1590 rfilt = ath_calcrxfilter(sc);
1591 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1592 ath9k_ps_restore(sc);
1593
1594 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1595 rfilt);
1596 }
1597
ath9k_sta_add(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1598 static int ath9k_sta_add(struct ieee80211_hw *hw,
1599 struct ieee80211_vif *vif,
1600 struct ieee80211_sta *sta)
1601 {
1602 struct ath_softc *sc = hw->priv;
1603 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1604 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1605 struct ieee80211_key_conf ps_key = { };
1606 int key;
1607
1608 ath_node_attach(sc, sta, vif);
1609
1610 if (vif->type != NL80211_IFTYPE_AP &&
1611 vif->type != NL80211_IFTYPE_AP_VLAN)
1612 return 0;
1613
1614 key = ath_key_config(common, vif, sta, &ps_key);
1615 if (key > 0) {
1616 an->ps_key = key;
1617 an->key_idx[0] = key;
1618 }
1619
1620 return 0;
1621 }
1622
ath9k_del_ps_key(struct ath_softc * sc,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1623 static void ath9k_del_ps_key(struct ath_softc *sc,
1624 struct ieee80211_vif *vif,
1625 struct ieee80211_sta *sta)
1626 {
1627 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1628 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1629
1630 if (!an->ps_key)
1631 return;
1632
1633 ath_key_delete(common, an->ps_key);
1634 an->ps_key = 0;
1635 an->key_idx[0] = 0;
1636 }
1637
ath9k_sta_remove(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1638 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1639 struct ieee80211_vif *vif,
1640 struct ieee80211_sta *sta)
1641 {
1642 struct ath_softc *sc = hw->priv;
1643
1644 ath9k_del_ps_key(sc, vif, sta);
1645 ath_node_detach(sc, sta);
1646
1647 return 0;
1648 }
1649
ath9k_sta_state(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta,enum ieee80211_sta_state old_state,enum ieee80211_sta_state new_state)1650 static int ath9k_sta_state(struct ieee80211_hw *hw,
1651 struct ieee80211_vif *vif,
1652 struct ieee80211_sta *sta,
1653 enum ieee80211_sta_state old_state,
1654 enum ieee80211_sta_state new_state)
1655 {
1656 struct ath_softc *sc = hw->priv;
1657 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1658 int ret = 0;
1659
1660 if (old_state == IEEE80211_STA_NOTEXIST &&
1661 new_state == IEEE80211_STA_NONE) {
1662 ret = ath9k_sta_add(hw, vif, sta);
1663 ath_dbg(common, CONFIG,
1664 "Add station: %pM\n", sta->addr);
1665 } else if (old_state == IEEE80211_STA_NONE &&
1666 new_state == IEEE80211_STA_NOTEXIST) {
1667 ret = ath9k_sta_remove(hw, vif, sta);
1668 ath_dbg(common, CONFIG,
1669 "Remove station: %pM\n", sta->addr);
1670 }
1671
1672 if (ath9k_is_chanctx_enabled()) {
1673 if (vif->type == NL80211_IFTYPE_STATION) {
1674 if (old_state == IEEE80211_STA_ASSOC &&
1675 new_state == IEEE80211_STA_AUTHORIZED)
1676 ath_chanctx_event(sc, vif,
1677 ATH_CHANCTX_EVENT_AUTHORIZED);
1678 }
1679 }
1680
1681 return ret;
1682 }
1683
ath9k_sta_set_tx_filter(struct ath_hw * ah,struct ath_node * an,bool set)1684 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1685 struct ath_node *an,
1686 bool set)
1687 {
1688 int i;
1689
1690 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1691 if (!an->key_idx[i])
1692 continue;
1693 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1694 }
1695 }
1696
ath9k_sta_notify(struct ieee80211_hw * hw,struct ieee80211_vif * vif,enum sta_notify_cmd cmd,struct ieee80211_sta * sta)1697 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1698 struct ieee80211_vif *vif,
1699 enum sta_notify_cmd cmd,
1700 struct ieee80211_sta *sta)
1701 {
1702 struct ath_softc *sc = hw->priv;
1703 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1704
1705 switch (cmd) {
1706 case STA_NOTIFY_SLEEP:
1707 an->sleeping = true;
1708 ath_tx_aggr_sleep(sta, sc, an);
1709 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1710 break;
1711 case STA_NOTIFY_AWAKE:
1712 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1713 an->sleeping = false;
1714 ath_tx_aggr_wakeup(sc, an);
1715 break;
1716 }
1717 }
1718
ath9k_conf_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u16 queue,const struct ieee80211_tx_queue_params * params)1719 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1720 struct ieee80211_vif *vif, u16 queue,
1721 const struct ieee80211_tx_queue_params *params)
1722 {
1723 struct ath_softc *sc = hw->priv;
1724 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1725 struct ath_txq *txq;
1726 struct ath9k_tx_queue_info qi;
1727 int ret = 0;
1728
1729 if (queue >= IEEE80211_NUM_ACS)
1730 return 0;
1731
1732 txq = sc->tx.txq_map[queue];
1733
1734 ath9k_ps_wakeup(sc);
1735 mutex_lock(&sc->mutex);
1736
1737 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1738
1739 qi.tqi_aifs = params->aifs;
1740 qi.tqi_cwmin = params->cw_min;
1741 qi.tqi_cwmax = params->cw_max;
1742 qi.tqi_burstTime = params->txop * 32;
1743
1744 ath_dbg(common, CONFIG,
1745 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1746 queue, txq->axq_qnum, params->aifs, params->cw_min,
1747 params->cw_max, params->txop);
1748
1749 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1750 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1751 if (ret)
1752 ath_err(common, "TXQ Update failed\n");
1753
1754 mutex_unlock(&sc->mutex);
1755 ath9k_ps_restore(sc);
1756
1757 return ret;
1758 }
1759
ath9k_set_key(struct ieee80211_hw * hw,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key)1760 static int ath9k_set_key(struct ieee80211_hw *hw,
1761 enum set_key_cmd cmd,
1762 struct ieee80211_vif *vif,
1763 struct ieee80211_sta *sta,
1764 struct ieee80211_key_conf *key)
1765 {
1766 struct ath_softc *sc = hw->priv;
1767 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1768 struct ath_node *an = NULL;
1769 int ret = 0, i;
1770
1771 if (ath9k_modparam_nohwcrypt)
1772 return -ENOSPC;
1773
1774 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1775 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1776 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1777 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1778 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1779 /*
1780 * For now, disable hw crypto for the RSN IBSS group keys. This
1781 * could be optimized in the future to use a modified key cache
1782 * design to support per-STA RX GTK, but until that gets
1783 * implemented, use of software crypto for group addressed
1784 * frames is a acceptable to allow RSN IBSS to be used.
1785 */
1786 return -EOPNOTSUPP;
1787 }
1788
1789 /* There may be MPDUs queued for the outgoing PTK key. Flush queues to
1790 * make sure these are not send unencrypted or with a wrong (new) key
1791 */
1792 if (cmd == DISABLE_KEY && key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
1793 ieee80211_stop_queues(hw);
1794 ath9k_flush(hw, vif, 0, true);
1795 ieee80211_wake_queues(hw);
1796 }
1797
1798 mutex_lock(&sc->mutex);
1799 ath9k_ps_wakeup(sc);
1800 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1801 if (sta)
1802 an = (struct ath_node *)sta->drv_priv;
1803
1804 /* Delete pending key cache entries if no more frames are pointing to
1805 * them in TXQs.
1806 */
1807 for (i = 0; i < ATH_KEYMAX; i++)
1808 ath9k_pending_key_del(sc, i);
1809
1810 switch (cmd) {
1811 case SET_KEY:
1812 if (sta)
1813 ath9k_del_ps_key(sc, vif, sta);
1814
1815 key->hw_key_idx = 0;
1816 ret = ath_key_config(common, vif, sta, key);
1817 if (ret >= 0) {
1818 key->hw_key_idx = ret;
1819 /* push IV and Michael MIC generation to stack */
1820 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1821 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1822 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1823 if (sc->sc_ah->sw_mgmt_crypto_tx &&
1824 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1825 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1826 ret = 0;
1827 }
1828 if (an && key->hw_key_idx) {
1829 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1830 if (an->key_idx[i])
1831 continue;
1832 an->key_idx[i] = key->hw_key_idx;
1833 break;
1834 }
1835 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1836 }
1837 break;
1838 case DISABLE_KEY:
1839 if (ath9k_txq_has_key(sc, key->hw_key_idx)) {
1840 /* Delay key cache entry deletion until there are no
1841 * remaining TXQ frames pointing to this entry.
1842 */
1843 set_bit(key->hw_key_idx, sc->sc_ah->pending_del_keymap);
1844 ath_hw_keysetmac(common, key->hw_key_idx, NULL);
1845 } else {
1846 ath_key_delete(common, key->hw_key_idx);
1847 }
1848 if (an) {
1849 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1850 if (an->key_idx[i] != key->hw_key_idx)
1851 continue;
1852 an->key_idx[i] = 0;
1853 break;
1854 }
1855 }
1856 key->hw_key_idx = 0;
1857 break;
1858 default:
1859 ret = -EINVAL;
1860 }
1861
1862 ath9k_ps_restore(sc);
1863 mutex_unlock(&sc->mutex);
1864
1865 return ret;
1866 }
1867
ath9k_bss_info_changed(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf,u32 changed)1868 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1869 struct ieee80211_vif *vif,
1870 struct ieee80211_bss_conf *bss_conf,
1871 u32 changed)
1872 {
1873 #define CHECK_ANI \
1874 (BSS_CHANGED_ASSOC | \
1875 BSS_CHANGED_IBSS | \
1876 BSS_CHANGED_BEACON_ENABLED)
1877
1878 struct ath_softc *sc = hw->priv;
1879 struct ath_hw *ah = sc->sc_ah;
1880 struct ath_common *common = ath9k_hw_common(ah);
1881 struct ath_vif *avp = (void *)vif->drv_priv;
1882 int slottime;
1883
1884 ath9k_ps_wakeup(sc);
1885 mutex_lock(&sc->mutex);
1886
1887 if (changed & BSS_CHANGED_ASSOC) {
1888 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1889 bss_conf->bssid, bss_conf->assoc);
1890
1891 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1892 avp->aid = bss_conf->aid;
1893 avp->assoc = bss_conf->assoc;
1894
1895 ath9k_calculate_summary_state(sc, avp->chanctx);
1896 }
1897
1898 if ((changed & BSS_CHANGED_IBSS) ||
1899 (changed & BSS_CHANGED_OCB)) {
1900 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1901 common->curaid = bss_conf->aid;
1902 ath9k_hw_write_associd(sc->sc_ah);
1903 }
1904
1905 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1906 (changed & BSS_CHANGED_BEACON_INT) ||
1907 (changed & BSS_CHANGED_BEACON_INFO)) {
1908 ath9k_calculate_summary_state(sc, avp->chanctx);
1909 }
1910
1911 if ((avp->chanctx == sc->cur_chan) &&
1912 (changed & BSS_CHANGED_ERP_SLOT)) {
1913 if (bss_conf->use_short_slot)
1914 slottime = 9;
1915 else
1916 slottime = 20;
1917
1918 if (vif->type == NL80211_IFTYPE_AP) {
1919 /*
1920 * Defer update, so that connected stations can adjust
1921 * their settings at the same time.
1922 * See beacon.c for more details
1923 */
1924 sc->beacon.slottime = slottime;
1925 sc->beacon.updateslot = UPDATE;
1926 } else {
1927 ah->slottime = slottime;
1928 ath9k_hw_init_global_settings(ah);
1929 }
1930 }
1931
1932 if (changed & BSS_CHANGED_P2P_PS)
1933 ath9k_p2p_bss_info_changed(sc, vif);
1934
1935 if (changed & CHECK_ANI)
1936 ath_check_ani(sc);
1937
1938 if (changed & BSS_CHANGED_TXPOWER) {
1939 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1940 vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1941 ath9k_set_txpower(sc, vif);
1942 }
1943
1944 mutex_unlock(&sc->mutex);
1945 ath9k_ps_restore(sc);
1946
1947 #undef CHECK_ANI
1948 }
1949
ath9k_get_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1950 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1951 {
1952 struct ath_softc *sc = hw->priv;
1953 struct ath_vif *avp = (void *)vif->drv_priv;
1954 u64 tsf;
1955
1956 mutex_lock(&sc->mutex);
1957 ath9k_ps_wakeup(sc);
1958 /* Get current TSF either from HW or kernel time. */
1959 if (sc->cur_chan == avp->chanctx) {
1960 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1961 } else {
1962 tsf = sc->cur_chan->tsf_val +
1963 ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL);
1964 }
1965 tsf += le64_to_cpu(avp->tsf_adjust);
1966 ath9k_ps_restore(sc);
1967 mutex_unlock(&sc->mutex);
1968
1969 return tsf;
1970 }
1971
ath9k_set_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u64 tsf)1972 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1973 struct ieee80211_vif *vif,
1974 u64 tsf)
1975 {
1976 struct ath_softc *sc = hw->priv;
1977 struct ath_vif *avp = (void *)vif->drv_priv;
1978
1979 mutex_lock(&sc->mutex);
1980 ath9k_ps_wakeup(sc);
1981 tsf -= le64_to_cpu(avp->tsf_adjust);
1982 ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1983 if (sc->cur_chan == avp->chanctx)
1984 ath9k_hw_settsf64(sc->sc_ah, tsf);
1985 avp->chanctx->tsf_val = tsf;
1986 ath9k_ps_restore(sc);
1987 mutex_unlock(&sc->mutex);
1988 }
1989
ath9k_reset_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1990 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1991 {
1992 struct ath_softc *sc = hw->priv;
1993 struct ath_vif *avp = (void *)vif->drv_priv;
1994
1995 mutex_lock(&sc->mutex);
1996
1997 ath9k_ps_wakeup(sc);
1998 ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1999 if (sc->cur_chan == avp->chanctx)
2000 ath9k_hw_reset_tsf(sc->sc_ah);
2001 avp->chanctx->tsf_val = 0;
2002 ath9k_ps_restore(sc);
2003
2004 mutex_unlock(&sc->mutex);
2005 }
2006
ath9k_ampdu_action(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_ampdu_params * params)2007 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2008 struct ieee80211_vif *vif,
2009 struct ieee80211_ampdu_params *params)
2010 {
2011 struct ath_softc *sc = hw->priv;
2012 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2013 bool flush = false;
2014 int ret = 0;
2015 struct ieee80211_sta *sta = params->sta;
2016 struct ath_node *an = (struct ath_node *)sta->drv_priv;
2017 enum ieee80211_ampdu_mlme_action action = params->action;
2018 u16 tid = params->tid;
2019 u16 *ssn = ¶ms->ssn;
2020 struct ath_atx_tid *atid;
2021
2022 mutex_lock(&sc->mutex);
2023
2024 switch (action) {
2025 case IEEE80211_AMPDU_RX_START:
2026 break;
2027 case IEEE80211_AMPDU_RX_STOP:
2028 break;
2029 case IEEE80211_AMPDU_TX_START:
2030 if (ath9k_is_chanctx_enabled()) {
2031 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2032 ret = -EBUSY;
2033 break;
2034 }
2035 }
2036 ath9k_ps_wakeup(sc);
2037 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2038 if (!ret)
2039 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
2040 ath9k_ps_restore(sc);
2041 break;
2042 case IEEE80211_AMPDU_TX_STOP_FLUSH:
2043 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
2044 flush = true;
2045 fallthrough;
2046 case IEEE80211_AMPDU_TX_STOP_CONT:
2047 ath9k_ps_wakeup(sc);
2048 ath_tx_aggr_stop(sc, sta, tid);
2049 if (!flush)
2050 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2051 ath9k_ps_restore(sc);
2052 break;
2053 case IEEE80211_AMPDU_TX_OPERATIONAL:
2054 atid = ath_node_to_tid(an, tid);
2055 atid->baw_size = IEEE80211_MIN_AMPDU_BUF <<
2056 sta->ht_cap.ampdu_factor;
2057 break;
2058 default:
2059 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
2060 }
2061
2062 mutex_unlock(&sc->mutex);
2063
2064 return ret;
2065 }
2066
ath9k_get_survey(struct ieee80211_hw * hw,int idx,struct survey_info * survey)2067 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2068 struct survey_info *survey)
2069 {
2070 struct ath_softc *sc = hw->priv;
2071 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2072 struct ieee80211_supported_band *sband;
2073 struct ieee80211_channel *chan;
2074 unsigned long flags;
2075 int pos;
2076
2077 if (IS_ENABLED(CONFIG_ATH9K_TX99))
2078 return -EOPNOTSUPP;
2079
2080 spin_lock_irqsave(&common->cc_lock, flags);
2081 if (idx == 0)
2082 ath_update_survey_stats(sc);
2083
2084 sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
2085 if (sband && idx >= sband->n_channels) {
2086 idx -= sband->n_channels;
2087 sband = NULL;
2088 }
2089
2090 if (!sband)
2091 sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
2092
2093 if (!sband || idx >= sband->n_channels) {
2094 spin_unlock_irqrestore(&common->cc_lock, flags);
2095 return -ENOENT;
2096 }
2097
2098 chan = &sband->channels[idx];
2099 pos = chan->hw_value;
2100 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2101 survey->channel = chan;
2102 spin_unlock_irqrestore(&common->cc_lock, flags);
2103
2104 return 0;
2105 }
2106
ath9k_enable_dynack(struct ath_softc * sc)2107 static void ath9k_enable_dynack(struct ath_softc *sc)
2108 {
2109 #ifdef CONFIG_ATH9K_DYNACK
2110 u32 rfilt;
2111 struct ath_hw *ah = sc->sc_ah;
2112
2113 ath_dynack_reset(ah);
2114
2115 ah->dynack.enabled = true;
2116 rfilt = ath_calcrxfilter(sc);
2117 ath9k_hw_setrxfilter(ah, rfilt);
2118 #endif
2119 }
2120
ath9k_set_coverage_class(struct ieee80211_hw * hw,s16 coverage_class)2121 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
2122 s16 coverage_class)
2123 {
2124 struct ath_softc *sc = hw->priv;
2125 struct ath_hw *ah = sc->sc_ah;
2126
2127 if (IS_ENABLED(CONFIG_ATH9K_TX99))
2128 return;
2129
2130 mutex_lock(&sc->mutex);
2131
2132 if (coverage_class >= 0) {
2133 ah->coverage_class = coverage_class;
2134 if (ah->dynack.enabled) {
2135 u32 rfilt;
2136
2137 ah->dynack.enabled = false;
2138 rfilt = ath_calcrxfilter(sc);
2139 ath9k_hw_setrxfilter(ah, rfilt);
2140 }
2141 ath9k_ps_wakeup(sc);
2142 ath9k_hw_init_global_settings(ah);
2143 ath9k_ps_restore(sc);
2144 } else if (!ah->dynack.enabled) {
2145 ath9k_enable_dynack(sc);
2146 }
2147
2148 mutex_unlock(&sc->mutex);
2149 }
2150
ath9k_has_tx_pending(struct ath_softc * sc,bool sw_pending)2151 static bool ath9k_has_tx_pending(struct ath_softc *sc,
2152 bool sw_pending)
2153 {
2154 int i, npend = 0;
2155
2156 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2157 if (!ATH_TXQ_SETUP(sc, i))
2158 continue;
2159
2160 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2161 sw_pending);
2162 if (npend)
2163 break;
2164 }
2165
2166 return !!npend;
2167 }
2168
ath9k_flush(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u32 queues,bool drop)2169 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2170 u32 queues, bool drop)
2171 {
2172 struct ath_softc *sc = hw->priv;
2173 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2174
2175 if (ath9k_is_chanctx_enabled()) {
2176 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2177 goto flush;
2178
2179 /*
2180 * If MCC is active, extend the flush timeout
2181 * and wait for the HW/SW queues to become
2182 * empty. This needs to be done outside the
2183 * sc->mutex lock to allow the channel scheduler
2184 * to switch channel contexts.
2185 *
2186 * The vif queues have been stopped in mac80211,
2187 * so there won't be any incoming frames.
2188 */
2189 __ath9k_flush(hw, queues, drop, true, true);
2190 return;
2191 }
2192 flush:
2193 mutex_lock(&sc->mutex);
2194 __ath9k_flush(hw, queues, drop, true, false);
2195 mutex_unlock(&sc->mutex);
2196 }
2197
__ath9k_flush(struct ieee80211_hw * hw,u32 queues,bool drop,bool sw_pending,bool timeout_override)2198 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
2199 bool sw_pending, bool timeout_override)
2200 {
2201 struct ath_softc *sc = hw->priv;
2202 struct ath_hw *ah = sc->sc_ah;
2203 struct ath_common *common = ath9k_hw_common(ah);
2204 int timeout;
2205 bool drain_txq;
2206
2207 cancel_delayed_work_sync(&sc->hw_check_work);
2208
2209 if (ah->ah_flags & AH_UNPLUGGED) {
2210 ath_dbg(common, ANY, "Device has been unplugged!\n");
2211 return;
2212 }
2213
2214 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2215 ath_dbg(common, ANY, "Device not present\n");
2216 return;
2217 }
2218
2219 spin_lock_bh(&sc->chan_lock);
2220 if (timeout_override)
2221 timeout = HZ / 5;
2222 else
2223 timeout = sc->cur_chan->flush_timeout;
2224 spin_unlock_bh(&sc->chan_lock);
2225
2226 ath_dbg(common, CHAN_CTX,
2227 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2228
2229 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2230 timeout) > 0)
2231 drop = false;
2232
2233 if (drop) {
2234 ath9k_ps_wakeup(sc);
2235 spin_lock_bh(&sc->sc_pcu_lock);
2236 drain_txq = ath_drain_all_txq(sc);
2237 spin_unlock_bh(&sc->sc_pcu_lock);
2238
2239 if (!drain_txq)
2240 ath_reset(sc, NULL);
2241
2242 ath9k_ps_restore(sc);
2243 }
2244
2245 ieee80211_queue_delayed_work(hw, &sc->hw_check_work,
2246 ATH_HW_CHECK_POLL_INT);
2247 }
2248
ath9k_tx_frames_pending(struct ieee80211_hw * hw)2249 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2250 {
2251 struct ath_softc *sc = hw->priv;
2252
2253 return ath9k_has_tx_pending(sc, true);
2254 }
2255
ath9k_tx_last_beacon(struct ieee80211_hw * hw)2256 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2257 {
2258 struct ath_softc *sc = hw->priv;
2259 struct ath_hw *ah = sc->sc_ah;
2260 struct ieee80211_vif *vif;
2261 struct ath_vif *avp;
2262 struct ath_buf *bf;
2263 struct ath_tx_status ts;
2264 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2265 int status;
2266
2267 vif = sc->beacon.bslot[0];
2268 if (!vif)
2269 return 0;
2270
2271 if (!vif->bss_conf.enable_beacon)
2272 return 0;
2273
2274 avp = (void *)vif->drv_priv;
2275
2276 if (!sc->beacon.tx_processed && !edma) {
2277 tasklet_disable(&sc->bcon_tasklet);
2278
2279 bf = avp->av_bcbuf;
2280 if (!bf || !bf->bf_mpdu)
2281 goto skip;
2282
2283 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2284 if (status == -EINPROGRESS)
2285 goto skip;
2286
2287 sc->beacon.tx_processed = true;
2288 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2289
2290 skip:
2291 tasklet_enable(&sc->bcon_tasklet);
2292 }
2293
2294 return sc->beacon.tx_last;
2295 }
2296
ath9k_get_stats(struct ieee80211_hw * hw,struct ieee80211_low_level_stats * stats)2297 static int ath9k_get_stats(struct ieee80211_hw *hw,
2298 struct ieee80211_low_level_stats *stats)
2299 {
2300 struct ath_softc *sc = hw->priv;
2301 struct ath_hw *ah = sc->sc_ah;
2302 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2303
2304 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2305 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2306 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2307 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2308 return 0;
2309 }
2310
fill_chainmask(u32 cap,u32 new)2311 static u32 fill_chainmask(u32 cap, u32 new)
2312 {
2313 u32 filled = 0;
2314 int i;
2315
2316 for (i = 0; cap && new; i++, cap >>= 1) {
2317 if (!(cap & BIT(0)))
2318 continue;
2319
2320 if (new & BIT(0))
2321 filled |= BIT(i);
2322
2323 new >>= 1;
2324 }
2325
2326 return filled;
2327 }
2328
validate_antenna_mask(struct ath_hw * ah,u32 val)2329 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2330 {
2331 if (AR_SREV_9300_20_OR_LATER(ah))
2332 return true;
2333
2334 switch (val & 0x7) {
2335 case 0x1:
2336 case 0x3:
2337 case 0x7:
2338 return true;
2339 case 0x2:
2340 return (ah->caps.rx_chainmask == 1);
2341 default:
2342 return false;
2343 }
2344 }
2345
ath9k_set_antenna(struct ieee80211_hw * hw,u32 tx_ant,u32 rx_ant)2346 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2347 {
2348 struct ath_softc *sc = hw->priv;
2349 struct ath_hw *ah = sc->sc_ah;
2350
2351 if (ah->caps.rx_chainmask != 1)
2352 rx_ant |= tx_ant;
2353
2354 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2355 return -EINVAL;
2356
2357 sc->ant_rx = rx_ant;
2358 sc->ant_tx = tx_ant;
2359
2360 if (ah->caps.rx_chainmask == 1)
2361 return 0;
2362
2363 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2364 if (AR_SREV_9100(ah))
2365 ah->rxchainmask = 0x7;
2366 else
2367 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2368
2369 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2370 ath9k_cmn_reload_chainmask(ah);
2371
2372 return 0;
2373 }
2374
ath9k_get_antenna(struct ieee80211_hw * hw,u32 * tx_ant,u32 * rx_ant)2375 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2376 {
2377 struct ath_softc *sc = hw->priv;
2378
2379 *tx_ant = sc->ant_tx;
2380 *rx_ant = sc->ant_rx;
2381 return 0;
2382 }
2383
ath9k_sw_scan_start(struct ieee80211_hw * hw,struct ieee80211_vif * vif,const u8 * mac_addr)2384 static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2385 struct ieee80211_vif *vif,
2386 const u8 *mac_addr)
2387 {
2388 struct ath_softc *sc = hw->priv;
2389 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2390 set_bit(ATH_OP_SCANNING, &common->op_flags);
2391 }
2392
ath9k_sw_scan_complete(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2393 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2394 struct ieee80211_vif *vif)
2395 {
2396 struct ath_softc *sc = hw->priv;
2397 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2398 clear_bit(ATH_OP_SCANNING, &common->op_flags);
2399 }
2400
2401 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2402
ath9k_cancel_pending_offchannel(struct ath_softc * sc)2403 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2404 {
2405 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2406
2407 if (sc->offchannel.roc_vif) {
2408 ath_dbg(common, CHAN_CTX,
2409 "%s: Aborting RoC\n", __func__);
2410
2411 del_timer_sync(&sc->offchannel.timer);
2412 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2413 ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
2414 }
2415
2416 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2417 ath_dbg(common, CHAN_CTX,
2418 "%s: Aborting HW scan\n", __func__);
2419
2420 del_timer_sync(&sc->offchannel.timer);
2421 ath_scan_complete(sc, true);
2422 }
2423 }
2424
ath9k_hw_scan(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_scan_request * hw_req)2425 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2426 struct ieee80211_scan_request *hw_req)
2427 {
2428 struct cfg80211_scan_request *req = &hw_req->req;
2429 struct ath_softc *sc = hw->priv;
2430 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2431 int ret = 0;
2432
2433 mutex_lock(&sc->mutex);
2434
2435 if (WARN_ON(sc->offchannel.scan_req)) {
2436 ret = -EBUSY;
2437 goto out;
2438 }
2439
2440 ath9k_ps_wakeup(sc);
2441 set_bit(ATH_OP_SCANNING, &common->op_flags);
2442 sc->offchannel.scan_vif = vif;
2443 sc->offchannel.scan_req = req;
2444 sc->offchannel.scan_idx = 0;
2445
2446 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2447 vif->addr);
2448
2449 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2450 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2451 ath_offchannel_next(sc);
2452 }
2453
2454 out:
2455 mutex_unlock(&sc->mutex);
2456
2457 return ret;
2458 }
2459
ath9k_cancel_hw_scan(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2460 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2461 struct ieee80211_vif *vif)
2462 {
2463 struct ath_softc *sc = hw->priv;
2464 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2465
2466 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2467
2468 mutex_lock(&sc->mutex);
2469 del_timer_sync(&sc->offchannel.timer);
2470 ath_scan_complete(sc, true);
2471 mutex_unlock(&sc->mutex);
2472 }
2473
ath9k_remain_on_channel(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_channel * chan,int duration,enum ieee80211_roc_type type)2474 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2475 struct ieee80211_vif *vif,
2476 struct ieee80211_channel *chan, int duration,
2477 enum ieee80211_roc_type type)
2478 {
2479 struct ath_softc *sc = hw->priv;
2480 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2481 int ret = 0;
2482
2483 mutex_lock(&sc->mutex);
2484
2485 if (WARN_ON(sc->offchannel.roc_vif)) {
2486 ret = -EBUSY;
2487 goto out;
2488 }
2489
2490 ath9k_ps_wakeup(sc);
2491 sc->offchannel.roc_vif = vif;
2492 sc->offchannel.roc_chan = chan;
2493 sc->offchannel.roc_duration = duration;
2494
2495 ath_dbg(common, CHAN_CTX,
2496 "RoC request on vif: %pM, type: %d duration: %d\n",
2497 vif->addr, type, duration);
2498
2499 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2500 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2501 ath_offchannel_next(sc);
2502 }
2503
2504 out:
2505 mutex_unlock(&sc->mutex);
2506
2507 return ret;
2508 }
2509
ath9k_cancel_remain_on_channel(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2510 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw,
2511 struct ieee80211_vif *vif)
2512 {
2513 struct ath_softc *sc = hw->priv;
2514 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2515
2516 mutex_lock(&sc->mutex);
2517
2518 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2519 del_timer_sync(&sc->offchannel.timer);
2520
2521 if (sc->offchannel.roc_vif) {
2522 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2523 ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
2524 }
2525
2526 mutex_unlock(&sc->mutex);
2527
2528 return 0;
2529 }
2530
ath9k_add_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf)2531 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2532 struct ieee80211_chanctx_conf *conf)
2533 {
2534 struct ath_softc *sc = hw->priv;
2535 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2536 struct ath_chanctx *ctx, **ptr;
2537 int pos;
2538
2539 mutex_lock(&sc->mutex);
2540
2541 ath_for_each_chanctx(sc, ctx) {
2542 if (ctx->assigned)
2543 continue;
2544
2545 ptr = (void *) conf->drv_priv;
2546 *ptr = ctx;
2547 ctx->assigned = true;
2548 pos = ctx - &sc->chanctx[0];
2549 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2550
2551 ath_dbg(common, CHAN_CTX,
2552 "Add channel context: %d MHz\n",
2553 conf->def.chan->center_freq);
2554
2555 ath_chanctx_set_channel(sc, ctx, &conf->def);
2556
2557 mutex_unlock(&sc->mutex);
2558 return 0;
2559 }
2560
2561 mutex_unlock(&sc->mutex);
2562 return -ENOSPC;
2563 }
2564
2565
ath9k_remove_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf)2566 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2567 struct ieee80211_chanctx_conf *conf)
2568 {
2569 struct ath_softc *sc = hw->priv;
2570 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2571 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2572
2573 mutex_lock(&sc->mutex);
2574
2575 ath_dbg(common, CHAN_CTX,
2576 "Remove channel context: %d MHz\n",
2577 conf->def.chan->center_freq);
2578
2579 ctx->assigned = false;
2580 ctx->hw_queue_base = 0;
2581 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2582
2583 mutex_unlock(&sc->mutex);
2584 }
2585
ath9k_change_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf,u32 changed)2586 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2587 struct ieee80211_chanctx_conf *conf,
2588 u32 changed)
2589 {
2590 struct ath_softc *sc = hw->priv;
2591 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2592 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2593
2594 mutex_lock(&sc->mutex);
2595 ath_dbg(common, CHAN_CTX,
2596 "Change channel context: %d MHz\n",
2597 conf->def.chan->center_freq);
2598 ath_chanctx_set_channel(sc, ctx, &conf->def);
2599 mutex_unlock(&sc->mutex);
2600 }
2601
ath9k_assign_vif_chanctx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_chanctx_conf * conf)2602 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2603 struct ieee80211_vif *vif,
2604 struct ieee80211_chanctx_conf *conf)
2605 {
2606 struct ath_softc *sc = hw->priv;
2607 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2608 struct ath_vif *avp = (void *)vif->drv_priv;
2609 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2610 int i;
2611
2612 ath9k_cancel_pending_offchannel(sc);
2613
2614 mutex_lock(&sc->mutex);
2615
2616 ath_dbg(common, CHAN_CTX,
2617 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2618 vif->addr, vif->type, vif->p2p,
2619 conf->def.chan->center_freq);
2620
2621 avp->chanctx = ctx;
2622 ctx->nvifs_assigned++;
2623 list_add_tail(&avp->list, &ctx->vifs);
2624 ath9k_calculate_summary_state(sc, ctx);
2625 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2626 vif->hw_queue[i] = ctx->hw_queue_base + i;
2627
2628 mutex_unlock(&sc->mutex);
2629
2630 return 0;
2631 }
2632
ath9k_unassign_vif_chanctx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_chanctx_conf * conf)2633 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2634 struct ieee80211_vif *vif,
2635 struct ieee80211_chanctx_conf *conf)
2636 {
2637 struct ath_softc *sc = hw->priv;
2638 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2639 struct ath_vif *avp = (void *)vif->drv_priv;
2640 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2641 int ac;
2642
2643 ath9k_cancel_pending_offchannel(sc);
2644
2645 mutex_lock(&sc->mutex);
2646
2647 ath_dbg(common, CHAN_CTX,
2648 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2649 vif->addr, vif->type, vif->p2p,
2650 conf->def.chan->center_freq);
2651
2652 avp->chanctx = NULL;
2653 ctx->nvifs_assigned--;
2654 list_del(&avp->list);
2655 ath9k_calculate_summary_state(sc, ctx);
2656 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2657 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2658
2659 mutex_unlock(&sc->mutex);
2660 }
2661
ath9k_mgd_prepare_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u16 duration)2662 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2663 struct ieee80211_vif *vif,
2664 u16 duration)
2665 {
2666 struct ath_softc *sc = hw->priv;
2667 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2668 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2669 struct ath_beacon_config *cur_conf;
2670 struct ath_chanctx *go_ctx;
2671 unsigned long timeout;
2672 bool changed = false;
2673 u32 beacon_int;
2674
2675 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2676 return;
2677
2678 if (!avp->chanctx)
2679 return;
2680
2681 mutex_lock(&sc->mutex);
2682
2683 spin_lock_bh(&sc->chan_lock);
2684 if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2685 changed = true;
2686 spin_unlock_bh(&sc->chan_lock);
2687
2688 if (!changed)
2689 goto out;
2690
2691 ath9k_cancel_pending_offchannel(sc);
2692
2693 go_ctx = ath_is_go_chanctx_present(sc);
2694
2695 if (go_ctx) {
2696 /*
2697 * Wait till the GO interface gets a chance
2698 * to send out an NoA.
2699 */
2700 spin_lock_bh(&sc->chan_lock);
2701 sc->sched.mgd_prepare_tx = true;
2702 cur_conf = &go_ctx->beacon;
2703 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2704 spin_unlock_bh(&sc->chan_lock);
2705
2706 timeout = usecs_to_jiffies(beacon_int * 2);
2707 init_completion(&sc->go_beacon);
2708
2709 mutex_unlock(&sc->mutex);
2710
2711 if (wait_for_completion_timeout(&sc->go_beacon,
2712 timeout) == 0) {
2713 ath_dbg(common, CHAN_CTX,
2714 "Failed to send new NoA\n");
2715
2716 spin_lock_bh(&sc->chan_lock);
2717 sc->sched.mgd_prepare_tx = false;
2718 spin_unlock_bh(&sc->chan_lock);
2719 }
2720
2721 mutex_lock(&sc->mutex);
2722 }
2723
2724 ath_dbg(common, CHAN_CTX,
2725 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2726 __func__, vif->addr);
2727
2728 spin_lock_bh(&sc->chan_lock);
2729 sc->next_chan = avp->chanctx;
2730 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2731 spin_unlock_bh(&sc->chan_lock);
2732
2733 ath_chanctx_set_next(sc, true);
2734 out:
2735 mutex_unlock(&sc->mutex);
2736 }
2737
ath9k_fill_chanctx_ops(void)2738 void ath9k_fill_chanctx_ops(void)
2739 {
2740 if (!ath9k_is_chanctx_enabled())
2741 return;
2742
2743 ath9k_ops.hw_scan = ath9k_hw_scan;
2744 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2745 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
2746 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2747 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2748 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2749 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2750 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2751 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
2752 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
2753 }
2754
2755 #endif
2756
ath9k_get_txpower(struct ieee80211_hw * hw,struct ieee80211_vif * vif,int * dbm)2757 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2758 int *dbm)
2759 {
2760 struct ath_softc *sc = hw->priv;
2761 struct ath_vif *avp = (void *)vif->drv_priv;
2762
2763 mutex_lock(&sc->mutex);
2764 if (avp->chanctx)
2765 *dbm = avp->chanctx->cur_txpower;
2766 else
2767 *dbm = sc->cur_chan->cur_txpower;
2768 mutex_unlock(&sc->mutex);
2769
2770 *dbm /= 2;
2771
2772 return 0;
2773 }
2774
2775 struct ieee80211_ops ath9k_ops = {
2776 .tx = ath9k_tx,
2777 .start = ath9k_start,
2778 .stop = ath9k_stop,
2779 .add_interface = ath9k_add_interface,
2780 .change_interface = ath9k_change_interface,
2781 .remove_interface = ath9k_remove_interface,
2782 .config = ath9k_config,
2783 .configure_filter = ath9k_configure_filter,
2784 .sta_state = ath9k_sta_state,
2785 .sta_notify = ath9k_sta_notify,
2786 .conf_tx = ath9k_conf_tx,
2787 .bss_info_changed = ath9k_bss_info_changed,
2788 .set_key = ath9k_set_key,
2789 .get_tsf = ath9k_get_tsf,
2790 .set_tsf = ath9k_set_tsf,
2791 .reset_tsf = ath9k_reset_tsf,
2792 .ampdu_action = ath9k_ampdu_action,
2793 .get_survey = ath9k_get_survey,
2794 .rfkill_poll = ath9k_rfkill_poll_state,
2795 .set_coverage_class = ath9k_set_coverage_class,
2796 .flush = ath9k_flush,
2797 .tx_frames_pending = ath9k_tx_frames_pending,
2798 .tx_last_beacon = ath9k_tx_last_beacon,
2799 .release_buffered_frames = ath9k_release_buffered_frames,
2800 .get_stats = ath9k_get_stats,
2801 .set_antenna = ath9k_set_antenna,
2802 .get_antenna = ath9k_get_antenna,
2803
2804 #ifdef CONFIG_ATH9K_WOW
2805 .suspend = ath9k_suspend,
2806 .resume = ath9k_resume,
2807 .set_wakeup = ath9k_set_wakeup,
2808 #endif
2809
2810 #ifdef CONFIG_ATH9K_DEBUGFS
2811 .get_et_sset_count = ath9k_get_et_sset_count,
2812 .get_et_stats = ath9k_get_et_stats,
2813 .get_et_strings = ath9k_get_et_strings,
2814 #endif
2815
2816 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2817 .sta_add_debugfs = ath9k_sta_add_debugfs,
2818 #endif
2819 .sw_scan_start = ath9k_sw_scan_start,
2820 .sw_scan_complete = ath9k_sw_scan_complete,
2821 .get_txpower = ath9k_get_txpower,
2822 .wake_tx_queue = ath9k_wake_tx_queue,
2823 };
2824