1 /* 2 * Copyright 2011 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __NV50_IR_DRIVER_H__ 24 #define __NV50_IR_DRIVER_H__ 25 26 #include "util/macros.h" 27 #include "util/blob.h" 28 29 #define NV50_CODEGEN_MAX_VARYINGS 80 30 struct nir_shader_compiler_options; 31 32 /* 33 * This struct constitutes linkage information in TGSI terminology. 34 * 35 * It is created by the code generator and handed to the pipe driver 36 * for input/output slot assignment. 37 */ 38 struct nv50_ir_varying 39 { 40 uint8_t slot[4]; /* native slots for xyzw (addresses in 32-bit words) */ 41 42 unsigned mask : 4; /* vec4 mask */ 43 unsigned linear : 1; /* linearly interpolated if true (and not flat) */ 44 unsigned flat : 1; 45 unsigned sc : 1; /* special colour interpolation mode (SHADE_MODEL) */ 46 unsigned centroid : 1; 47 unsigned patch : 1; /* patch constant value */ 48 unsigned regular : 1; /* driver-specific meaning (e.g. input in sreg) */ 49 unsigned input : 1; /* indicates direction of system values */ 50 unsigned oread : 1; /* true if output is read from parallel TCP */ 51 52 uint8_t id; /* TGSI register index */ 53 uint8_t sn; /* TGSI semantic name */ 54 uint8_t si; /* TGSI semantic index */ 55 }; 56 57 #ifndef NDEBUG 58 # define NV50_IR_DEBUG_BASIC (1 << 0) 59 # define NV50_IR_DEBUG_VERBOSE (2 << 0) 60 # define NV50_IR_DEBUG_REG_ALLOC (1 << 2) 61 #else 62 # define NV50_IR_DEBUG_BASIC 0 63 # define NV50_IR_DEBUG_VERBOSE 0 64 # define NV50_IR_DEBUG_REG_ALLOC 0 65 #endif 66 67 struct nv50_ir_prog_symbol 68 { 69 uint32_t label; 70 uint32_t offset; 71 }; 72 73 #define NVISA_G80_CHIPSET 0x50 74 #define NVISA_GF100_CHIPSET 0xc0 75 #define NVISA_GK104_CHIPSET 0xe0 76 #define NVISA_GK20A_CHIPSET 0xea 77 #define NVISA_GM107_CHIPSET 0x110 78 #define NVISA_GM200_CHIPSET 0x120 79 #define NVISA_GV100_CHIPSET 0x140 80 81 struct nv50_ir_prog_info_out; 82 83 /* used for the input data and assignSlot interface */ 84 struct nv50_ir_prog_info 85 { 86 uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */ 87 88 uint8_t type; /* PIPE_SHADER */ 89 90 uint8_t optLevel; /* optimization level (0 to 3) */ 91 uint8_t dbgFlags; 92 bool omitLineNum; /* only used for printing the prog when dbgFlags is set */ 93 94 struct { 95 uint32_t smemSize; /* required shared memory per block */ 96 uint8_t sourceRep; /* PIPE_SHADER_IR_* */ 97 const void *source; 98 } bin; 99 100 union { 101 struct { 102 uint32_t inputOffset; /* base address for user args */ 103 uint32_t gridInfoBase; /* base address for NTID,NCTAID */ 104 uint16_t numThreads[3]; /* max number of threads */ 105 } cp; 106 } prop; 107 108 struct { 109 int8_t genUserClip; /* request user clip planes for ClipVertex */ 110 uint8_t auxCBSlot; /* driver constant buffer slot */ 111 uint16_t ucpBase; /* base address for UCPs */ 112 uint16_t drawInfoBase; /* base address for draw parameters */ 113 uint16_t alphaRefBase; /* base address for alpha test values */ 114 int8_t viewportId; /* output index of ViewportIndex */ 115 bool mul_zero_wins; /* program wants for x*0 = 0 */ 116 bool nv50styleSurfaces; /* generate gX[] access for raw buffers */ 117 uint16_t texBindBase; /* base address for tex handles (nve4) */ 118 uint16_t fbtexBindBase; /* base address for fbtex handle (nve4) */ 119 uint16_t suInfoBase; /* base address for surface info (nve4) */ 120 uint16_t bindlessBase; /* base address for bindless image info (nve4) */ 121 uint16_t bufInfoBase; /* base address for buffer info */ 122 uint16_t sampleInfoBase; /* base address for sample positions */ 123 uint8_t msInfoCBSlot; /* cX[] used for multisample info */ 124 uint16_t msInfoBase; /* base address for multisample info */ 125 uint16_t uboInfoBase; /* base address for compute UBOs (gk104+) */ 126 127 uint16_t membarOffset; /* base address for membar reads (nv50) */ 128 uint8_t gmemMembar; /* gX[] on which to perform membar reads (nv50) */ 129 } io; 130 131 /* driver callback to assign input/output locations */ 132 int (*assignSlots)(struct nv50_ir_prog_info_out *); 133 }; 134 135 /* the produced binary with metadata */ 136 struct nv50_ir_prog_info_out 137 { 138 uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */ 139 140 uint8_t type; /* PIPE_SHADER */ 141 142 struct { 143 int16_t maxGPR; /* may be -1 if none used */ 144 uint32_t tlsSpace; /* required local memory per thread */ 145 uint32_t smemSize; /* required shared memory per block */ 146 uint32_t *code; 147 uint32_t codeSize; 148 uint32_t instructions; 149 void *relocData; 150 void *fixupData; 151 } bin; 152 153 struct nv50_ir_varying sv[NV50_CODEGEN_MAX_VARYINGS]; 154 struct nv50_ir_varying in[NV50_CODEGEN_MAX_VARYINGS]; 155 struct nv50_ir_varying out[NV50_CODEGEN_MAX_VARYINGS]; 156 uint8_t numInputs; 157 uint8_t numOutputs; 158 uint8_t numPatchConstants; /* also included in numInputs/numOutputs */ 159 uint8_t numSysVals; 160 uint32_t loops; 161 162 union { 163 struct { 164 bool usesDrawParameters; 165 } vp; 166 struct { 167 uint8_t outputPatchSize; 168 uint8_t partitioning; /* PIPE_TESS_PART */ 169 int8_t winding; /* +1 (clockwise) / -1 (counter-clockwise) */ 170 uint8_t domain; /* PIPE_PRIM_{QUADS,TRIANGLES,LINES} */ 171 uint8_t outputPrim; /* PIPE_PRIM_{TRIANGLES,LINES,POINTS} */ 172 } tp; 173 struct { 174 uint8_t outputPrim; 175 unsigned instanceCount; 176 unsigned maxVertices; 177 } gp; 178 struct { 179 unsigned numColourResults; 180 bool writesDepth : 1; 181 bool earlyFragTests : 1; 182 bool postDepthCoverage : 1; 183 bool usesDiscard : 1; 184 bool usesSampleMaskIn : 1; 185 bool readsFramebuffer : 1; 186 bool readsSampleLocations : 1; 187 bool separateFragData : 1; 188 } fp; 189 struct { 190 struct { 191 unsigned valid : 1; 192 unsigned image : 1; 193 unsigned slot : 6; 194 } gmem[16]; /* nv50 only */ 195 } cp; 196 } prop; 197 198 struct { 199 uint8_t clipDistances; /* number of clip distance outputs */ 200 uint8_t cullDistances; /* number of cull distance outputs */ 201 int8_t genUserClip; /* request user clip planes for ClipVertex */ 202 uint8_t instanceId; /* system value index of InstanceID */ 203 uint8_t vertexId; /* system value index of VertexID */ 204 uint8_t edgeFlagIn; 205 uint8_t edgeFlagOut; 206 uint8_t fragDepth; /* output index of FragDepth */ 207 uint8_t sampleMask; /* output index of SampleMask */ 208 uint8_t globalAccess; /* 1 for read, 2 for wr, 3 for rw */ 209 bool fp64; /* program uses fp64 math */ 210 bool layer_viewport_relative; 211 } io; 212 213 uint8_t numBarriers; 214 215 void *driverPriv; 216 }; 217 218 #ifdef __cplusplus 219 extern "C" { 220 #endif 221 222 const struct nir_shader_compiler_options * 223 nv50_ir_nir_shader_compiler_options(int chipset, uint8_t shader_type); 224 225 extern int nv50_ir_generate_code(struct nv50_ir_prog_info *, 226 struct nv50_ir_prog_info_out *); 227 228 extern void nv50_ir_relocate_code(void *relocData, uint32_t *code, 229 uint32_t codePos, 230 uint32_t libPos, 231 uint32_t dataPos); 232 233 extern void 234 nv50_ir_apply_fixups(void *fixupData, uint32_t *code, 235 bool force_per_sample, bool flatshade, 236 uint8_t alphatest, bool msaa); 237 238 /* obtain code that will be shared among programs */ 239 extern void nv50_ir_get_target_library(uint32_t chipset, 240 const uint32_t **code, uint32_t *size); 241 242 243 #ifdef __cplusplus 244 namespace nv50_ir 245 { 246 struct FixupEntry; 247 struct FixupData; 248 249 void 250 gk110_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code, 251 const nv50_ir::FixupData& data); 252 void 253 gm107_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code, 254 const nv50_ir::FixupData& data); 255 void 256 nv50_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code, 257 const nv50_ir::FixupData& data); 258 void 259 nvc0_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code, 260 const nv50_ir::FixupData& data); 261 void 262 gv100_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code, 263 const nv50_ir::FixupData& data); 264 void 265 gk110_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code, 266 const nv50_ir::FixupData& data); 267 void 268 gm107_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code, 269 const nv50_ir::FixupData& data); 270 void 271 nvc0_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code, 272 const nv50_ir::FixupData& data); 273 void 274 gv100_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code, 275 const nv50_ir::FixupData& data); 276 } 277 #endif 278 279 extern void 280 nv50_ir_prog_info_out_print(struct nv50_ir_prog_info_out *); 281 282 /* Serialize a nv50_ir_prog_info structure and save it into blob */ 283 extern bool 284 nv50_ir_prog_info_serialize(struct blob *, struct nv50_ir_prog_info *); 285 286 /* Serialize a nv50_ir_prog_info_out structure and save it into blob */ 287 extern bool MUST_CHECK 288 nv50_ir_prog_info_out_serialize(struct blob *, struct nv50_ir_prog_info_out *); 289 290 /* Deserialize from data and save into a nv50_ir_prog_info_out structure 291 * using a pointer. Size is a total size of the serialized data. 292 * Offset points to where info_out in data is located. */ 293 extern bool MUST_CHECK 294 nv50_ir_prog_info_out_deserialize(void *data, size_t size, size_t offset, 295 struct nv50_ir_prog_info_out *); 296 297 #ifdef __cplusplus 298 } 299 #endif 300 301 #endif // __NV50_IR_DRIVER_H__ 302