1 /*
2 * Copyright (c) 2022 HPMicro
3 * SPDX-License-Identifier: BSD-3-Clause
4 *
5 */
6
7 #include "board.h"
8 #include "hpm_uart_drv.h"
9 #include "hpm_gptmr_drv.h"
10 #include "hpm_lcdc_drv.h"
11 #include "hpm_i2c_drv.h"
12 #include "hpm_gpio_drv.h"
13 #include "hpm_dram_drv.h"
14 #include "pinmux.h"
15 #include "hpm_pmp_drv.h"
16 #include "assert.h"
17 #include "hpm_clock_drv.h"
18 #include "hpm_sysctl_drv.h"
19 #include "hpm_sdxc_drv.h"
20 #include "hpm_pwm_drv.h"
21 #include "hpm_trgm_drv.h"
22 #include "hpm_pllctlv2_drv.h"
23 #include "hpm_pcfg_drv.h"
24
25 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
26 #include "hpm_debug_console.h"
27 #endif
28
29 static board_timer_cb timer_cb;
30
31 /**
32 * @brief FLASH configuration option definitions:
33 * option[0]:
34 * [31:16] 0xfcf9 - FLASH configuration option tag
35 * [15:4] 0 - Reserved
36 * [3:0] option words (exclude option[0])
37 * option[1]:
38 * [31:28] Flash probe type
39 * 0 - SFDP SDR / 1 - SFDP DDR
40 * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
41 * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
42 * 6 - OctaBus DDR (SPI -> OPI DDR)
43 * 8 - Xccela DDR (SPI -> OPI DDR)
44 * 10 - EcoXiP DDR (SPI -> OPI DDR)
45 * [27:24] Command Pads after Power-on Reset
46 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
47 * [23:20] Command Pads after Configuring FLASH
48 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
49 * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
50 * 0 - Not needed
51 * 1 - QE bit is at bit 6 in Status Register 1
52 * 2 - QE bit is at bit1 in Status Register 2
53 * 3 - QE bit is at bit7 in Status Register 2
54 * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
55 * [15:8] Dummy cycles
56 * 0 - Auto-probed / detected / default value
57 * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
58 * [7:4] Misc.
59 * 0 - Not used
60 * 1 - SPI mode
61 * 2 - Internal loopback
62 * 3 - External DQS
63 * [3:0] Frequency option
64 * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
65 *
66 * option[2] (Effective only if the bit[3:0] in option[0] > 1)
67 * [31:20] Reserved
68 * [19:16] IO voltage
69 * 0 - 3V / 1 - 1.8V
70 * [15:12] Pin group
71 * 0 - 1st group / 1 - 2nd group
72 * [11:8] Connection selection
73 * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
74 * [7:0] Drive Strength
75 * 0 - Default value
76 * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
77 * JESD216)
78 * [31:16] reserved
79 * [15:12] Sector Erase Command Option, not required here
80 * [11:8] Sector Size Option, not required here
81 * [7:0] Flash Size Option
82 * 0 - 4MB / 1 - 8MB / 2 - 16MB
83 */
84 #if defined(FLASH_XIP) && FLASH_XIP
85 __attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0};
86 #endif
87
88 #if defined(FLASH_UF2) && FLASH_UF2
89 ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
90 #endif
91
board_init_console(void)92 void board_init_console(void)
93 {
94 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
95 #if console_type_uart == BOARD_CONSOLE_TYPE
96 console_config_t cfg;
97
98 /* Configure the UART clock to 24MHz */
99 clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U);
100
101 cfg.type = BOARD_CONSOLE_TYPE;
102 cfg.base = (uint32_t) BOARD_CONSOLE_BASE;
103 cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME);
104 cfg.baudrate = BOARD_CONSOLE_BAUDRATE;
105
106 init_uart_pins((UART_Type *) cfg.base);
107
108 if (status_success != console_init(&cfg)) {
109 /* failed to initialize debug console */
110 while (1) {
111 }
112 }
113 #else
114 while (1) {
115 }
116 #endif
117 #endif
118 }
119
board_print_clock_freq(void)120 void board_print_clock_freq(void)
121 {
122 printf("==============================\n");
123 printf(" %s clock summary\n", BOARD_NAME);
124 printf("==============================\n");
125 printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0));
126 printf("axi:\t\t %luHz\n", clock_get_frequency(clock_axi));
127 printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb));
128 printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0));
129 printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0));
130 printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1));
131 printf("dram:\t\t %luHz\n", clock_get_frequency(clock_dram));
132 printf("==============================\n");
133 }
134
board_init_uart(UART_Type * ptr)135 void board_init_uart(UART_Type *ptr)
136 {
137 init_uart_pins(ptr);
138 }
139
board_init_ahb(void)140 void board_init_ahb(void)
141 {
142 clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2);/*200m hz*/
143 }
144
board_print_banner(void)145 void board_print_banner(void)
146 {
147 const uint8_t banner[] = {"\n\
148 ----------------------------------------------------------------------\n\
149 $$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\
150 $$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\
151 $$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\
152 $$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\
153 $$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\
154 $$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\
155 $$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\
156 \\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\
157 ----------------------------------------------------------------------\n"};
158 printf("%s", banner);
159 }
160
board_ungate_mchtmr_at_lp_mode(void)161 void board_ungate_mchtmr_at_lp_mode(void)
162 {
163 /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */
164 sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock);
165 }
166
board_init(void)167 void board_init(void)
168 {
169 pcfg_dcdc_set_voltage(HPM_PCFG, 1100);
170 board_init_clock();
171 board_init_console();
172 board_init_pmp();
173 board_init_ahb();
174 #if BOARD_SHOW_CLOCK
175 board_print_clock_freq();
176 #endif
177 #if BOARD_SHOW_BANNER
178 board_print_banner();
179 #endif
180 }
181
board_init_sdram_pins(void)182 void board_init_sdram_pins(void)
183 {
184 init_sdram_pins();
185 }
186
board_init_dram_clock(void)187 uint32_t board_init_dram_clock(void)
188 {
189 clock_add_to_group(clock_dram, 0);
190 /* Configure the SDRAM to 133MHz */
191 clock_set_source_divider(clock_dram, clk_src_pll0_clk1, 2U);
192
193 return clock_get_frequency(clock_dram);
194 }
195
board_delay_us(uint32_t us)196 void board_delay_us(uint32_t us)
197 {
198 clock_cpu_delay_us(us);
199 }
200
board_delay_ms(uint32_t ms)201 void board_delay_ms(uint32_t ms)
202 {
203 clock_cpu_delay_ms(ms);
204 }
205
board_timer_isr(void)206 void board_timer_isr(void)
207 {
208 if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
209 gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH));
210 timer_cb();
211 }
212 }
213 SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr);
214
board_timer_create(uint32_t ms,board_timer_cb cb)215 void board_timer_create(uint32_t ms, board_timer_cb cb)
216 {
217 uint32_t gptmr_freq;
218 gptmr_channel_config_t config;
219
220 timer_cb = cb;
221 gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config);
222
223 clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0);
224 gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME);
225
226 config.reload = gptmr_freq / 1000 * ms;
227 gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false);
228 gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH));
229 intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1);
230
231 gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
232 }
233
board_i2c_bus_clear(I2C_Type * ptr)234 void board_i2c_bus_clear(I2C_Type *ptr)
235 {
236 init_i2c_pins_as_gpio(ptr);
237 }
238
board_init_i2c(I2C_Type * ptr)239 void board_init_i2c(I2C_Type *ptr)
240 {
241 }
242
board_init_spi_clock(SPI_Type * ptr)243 uint32_t board_init_spi_clock(SPI_Type *ptr)
244 {
245 if (ptr == HPM_SPI3) {
246 /* SPI3 clock configure */
247 clock_add_to_group(clock_spi3, 0);
248 clock_set_source_divider(clock_spi3, clk_src_osc24m, 1U);
249
250 return clock_get_frequency(clock_spi3);
251 }
252 return 0;
253 }
254
board_init_gpio_pins(void)255 void board_init_gpio_pins(void)
256 {
257 init_gpio_pins();
258 }
259
board_init_spi_pins(SPI_Type * ptr)260 void board_init_spi_pins(SPI_Type *ptr)
261 {
262 init_spi_pins(ptr);
263 }
264
board_init_spi_pins_with_gpio_as_cs(SPI_Type * ptr)265 void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
266 {
267 init_spi_pins_with_gpio_as_cs(ptr);
268 gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN),
269 GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
270 }
271
board_write_spi_cs(uint32_t pin,uint8_t state)272 void board_write_spi_cs(uint32_t pin, uint8_t state)
273 {
274 gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state);
275 }
276
board_init_led_pins(void)277 void board_init_led_pins(void)
278 {
279 init_led_pins();
280 gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
281 }
282
board_led_toggle(void)283 void board_led_toggle(void)
284 {
285 gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
286 }
287
board_led_write(uint8_t state)288 void board_led_write(uint8_t state)
289 {
290 gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
291 }
292
board_init_usb_pins(void)293 void board_init_usb_pins(void)
294 {
295 /* set pull-up for USBx ID pin */
296 init_usb_pins();
297
298 /* configure USBx ID pin as input function */
299 gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN);
300 }
301
board_get_usb_id_status(void)302 uint8_t board_get_usb_id_status(void)
303 {
304 return gpio_read_pin(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN);
305 }
306
board_usb_vbus_ctrl(uint8_t usb_index,uint8_t level)307 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
308 {
309 }
310
board_init_pmp(void)311 void board_init_pmp(void)
312 {
313 extern uint32_t __noncacheable_start__[];
314 extern uint32_t __noncacheable_end__[];
315
316 uint32_t start_addr = (uint32_t) __noncacheable_start__;
317 uint32_t end_addr = (uint32_t) __noncacheable_end__;
318 uint32_t length = end_addr - start_addr;
319
320 if (length == 0) {
321 return;
322 }
323
324 /* Ensure the address and the length are power of 2 aligned */
325 assert((length & (length - 1U)) == 0U);
326 assert((start_addr & (length - 1U)) == 0U);
327
328 pmp_entry_t pmp_entry[3] = {0};
329 pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(0x0000000, 0x80000000);
330 pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
331
332
333 pmp_entry[1].pmp_addr = PMP_NAPOT_ADDR(0x80000000, 0x80000000);
334 pmp_entry[1].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
335
336 pmp_entry[2].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
337 pmp_entry[2].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
338 pmp_entry[2].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
339 pmp_entry[2].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
340 pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry));
341 }
342
board_init_clock(void)343 void board_init_clock(void)
344 {
345 uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
346 if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
347 /* Configure the External OSC ramp-up time: ~9ms */
348 pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U);
349
350 /* Select clock setting preset1 */
351 sysctl_clock_set_preset(HPM_SYSCTL, 2);
352 }
353 /* Add most Clocks to group 0 */
354 clock_add_to_group(clock_cpu0, 0);
355 clock_add_to_group(clock_ahbp, 0);
356 clock_add_to_group(clock_axic, 0);
357 clock_add_to_group(clock_axis, 0);
358
359 clock_add_to_group(clock_mchtmr0, 0);
360 clock_add_to_group(clock_dram, 0);
361 clock_add_to_group(clock_xpi0, 0);
362 clock_add_to_group(clock_xpi1, 0);
363 clock_add_to_group(clock_gptmr0, 0);
364 clock_add_to_group(clock_gptmr1, 0);
365 clock_add_to_group(clock_gptmr2, 0);
366 clock_add_to_group(clock_gptmr3, 0);
367 clock_add_to_group(clock_uart0, 0);
368 clock_add_to_group(clock_uart1, 0);
369 clock_add_to_group(clock_uart2, 0);
370 clock_add_to_group(clock_uart3, 0);
371 clock_add_to_group(clock_i2c0, 0);
372 clock_add_to_group(clock_i2c1, 0);
373 clock_add_to_group(clock_i2c2, 0);
374 clock_add_to_group(clock_i2c3, 0);
375 clock_add_to_group(clock_spi0, 0);
376 clock_add_to_group(clock_spi1, 0);
377 clock_add_to_group(clock_spi2, 0);
378 clock_add_to_group(clock_spi3, 0);
379 clock_add_to_group(clock_can0, 0);
380 clock_add_to_group(clock_can1, 0);
381 clock_add_to_group(clock_sdxc0, 0);
382 clock_add_to_group(clock_ptpc, 0);
383 clock_add_to_group(clock_ref0, 0);
384 clock_add_to_group(clock_ref1, 0);
385 clock_add_to_group(clock_watchdog0, 0);
386 clock_add_to_group(clock_eth0, 0);
387 clock_add_to_group(clock_sdp, 0);
388 clock_add_to_group(clock_xdma, 0);
389 clock_add_to_group(clock_ram0, 0);
390 clock_add_to_group(clock_usb0, 0);
391 clock_add_to_group(clock_kman, 0);
392 clock_add_to_group(clock_gpio, 0);
393 clock_add_to_group(clock_mbx0, 0);
394 clock_add_to_group(clock_hdma, 0);
395 clock_add_to_group(clock_rng, 0);
396 clock_add_to_group(clock_mot0, 0);
397 clock_add_to_group(clock_mot1, 0);
398 clock_add_to_group(clock_acmp, 0);
399 clock_add_to_group(clock_dao, 0);
400 clock_add_to_group(clock_msyn, 0);
401 clock_add_to_group(clock_lmm0, 0);
402 clock_add_to_group(clock_pdm, 0);
403
404 clock_add_to_group(clock_adc0, 0);
405 clock_add_to_group(clock_adc1, 0);
406 clock_add_to_group(clock_adc2, 0);
407
408 clock_add_to_group(clock_dac0, 0);
409
410 clock_add_to_group(clock_i2s0, 0);
411 clock_add_to_group(clock_i2s1, 0);
412
413 clock_add_to_group(clock_ffa0, 0);
414 clock_add_to_group(clock_tsns, 0);
415
416 /* Connect Group0 to CPU0 */
417 clock_connect_group_to_cpu(0, 0);
418 /* Configure CPU0 to 480MHz */
419 clock_set_source_divider(clock_cpu0, clk_src_pll1_clk0, 1);
420
421 clock_update_core_clock();
422 }
423
board_init_adc12_clock(ADC16_Type * ptr)424 uint32_t board_init_adc12_clock(ADC16_Type *ptr)
425 {
426 uint32_t freq = 0;
427 switch ((uint32_t) ptr) {
428 case HPM_ADC0_BASE:
429 /* Configure the ADC clock to 200MHz */
430 clock_set_adc_source(clock_adc0, clk_adc_src_ana);
431 clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
432 freq = clock_get_frequency(clock_adc0);
433 break;
434 case HPM_ADC1_BASE:
435 /* Configure the ADC clock to 200MHz */
436 clock_set_adc_source(clock_adc1, clk_adc_src_ana);
437 clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
438 freq = clock_get_frequency(clock_adc1);
439 break;
440 case HPM_ADC2_BASE:
441 /* Configure the ADC clock to 200MHz */
442 clock_set_adc_source(clock_adc2, clk_adc_src_ana);
443 clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
444 freq = clock_get_frequency(clock_adc2);
445 break;
446 default:
447 /* Invalid ADC instance */
448 break;
449 }
450
451 return freq;
452 }
453
board_init_dao_clock(void)454 uint32_t board_init_dao_clock(void)
455 {
456 return clock_get_frequency(clock_dao);
457 }
458
board_init_pdm_clock(void)459 uint32_t board_init_pdm_clock(void)
460 {
461 return clock_get_frequency(clock_pdm);
462 }
463
board_set_audio_pll_clock(uint32_t freq)464 hpm_stat_t board_set_audio_pll_clock(uint32_t freq)
465 {
466 return pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 2, freq); /* pll2clk */
467 }
468
board_init_i2s_clock(I2S_Type * ptr)469 uint32_t board_init_i2s_clock(I2S_Type *ptr)
470 {
471 return 0;
472 }
473
board_init_adc16_clock(ADC16_Type * ptr)474 uint32_t board_init_adc16_clock(ADC16_Type *ptr)
475 {
476 return 0;
477 }
478
board_init_dac_clock(DAC_Type * ptr,bool clk_src_ahb)479 uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb)
480 {
481 uint32_t freq = 0;
482
483 if (ptr == HPM_DAC) {
484 if (clk_src_ahb == true) {
485 /* Configure the DAC clock to 160MHz */
486 clock_set_dac_source(clock_dac0, clk_dac_src_ahb);
487 } else {
488 /* Configure the DAC clock to 166MHz */
489 clock_set_dac_source(clock_dac0, clk_dac_src_ana);
490 clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2);
491 }
492
493 freq = clock_get_frequency(clock_dac0);
494 }
495
496 return freq;
497 }
498
board_init_can(CAN_Type * ptr)499 void board_init_can(CAN_Type *ptr)
500 {
501 init_can_pins(ptr);
502 }
503
board_init_can_clock(CAN_Type * ptr)504 uint32_t board_init_can_clock(CAN_Type *ptr)
505 {
506 uint32_t freq = 0;
507 if (ptr == HPM_CAN0) {
508 /* Set the CAN0 peripheral clock to 80MHz */
509 clock_set_source_divider(clock_can0, clk_src_pll0_clk0, 5);
510 freq = clock_get_frequency(clock_can0);
511 } else if (ptr == HPM_CAN1) {
512 /* Set the CAN1 peripheral clock to 80MHz */
513 clock_set_source_divider(clock_can1, clk_src_pll0_clk0, 5);
514 freq = clock_get_frequency(clock_can1);
515 } else {
516 /* Invalid CAN instance */
517 }
518 return freq;
519 }
520
521 #ifdef INIT_EXT_RAM_FOR_DATA
522 /*
523 * this function will be called during startup to initialize external memory for data use
524 */
_init_ext_ram(void)525 void _init_ext_ram(void)
526 {
527 uint32_t dram_clk_in_hz;
528 board_init_sdram_pins();
529 dram_clk_in_hz = board_init_dram_clock();
530
531 dram_config_t config = {0};
532 dram_sdram_config_t sdram_config = {0};
533
534 dram_default_config(HPM_DRAM, &config);
535 config.dqs = DRAM_DQS_INTERNAL;
536 dram_init(HPM_DRAM, &config);
537
538 sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4;
539 sdram_config.prescaler = 0x3;
540 sdram_config.burst_len_in_byte = 8;
541 sdram_config.auto_refresh_count_in_one_burst = 1;
542 sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS;
543 sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3;
544
545 sdram_config.precharge_to_act_in_ns = 18; /* Trp */
546 sdram_config.act_to_rw_in_ns = 18; /* Trcd */
547 sdram_config.refresh_recover_in_ns = 70; /* Trfc/Trc */
548 sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */
549 sdram_config.cke_off_in_ns = 42; /* Trcd */
550 sdram_config.act_to_precharge_in_ns = 42; /* Tras */
551
552 sdram_config.self_refresh_recover_in_ns = 66; /* Txsr */
553 sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */
554 sdram_config.act_to_act_in_ns = 12; /* Trrd */
555 sdram_config.idle_timeout_in_ns = 6;
556 sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED;
557
558 sdram_config.cs = BOARD_SDRAM_CS;
559 sdram_config.base_address = BOARD_SDRAM_ADDRESS;
560 sdram_config.size_in_byte = BOARD_SDRAM_SIZE;
561 sdram_config.port_size = BOARD_SDRAM_PORT_SIZE;
562 sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT;
563 sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS;
564 sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE;
565 sdram_config.delay_cell_value = 29;
566
567 dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config);
568 }
569 #endif
570
board_init_sd_pins(SDXC_Type * ptr)571 void board_init_sd_pins(SDXC_Type *ptr)
572 {
573 init_sdxc_pins(ptr, false);
574 }
575
board_sd_configure_clock(SDXC_Type * ptr,uint32_t freq)576 uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq)
577 {
578 uint32_t actual_freq = 0;
579 do {
580 if (ptr != HPM_SDXC0) {
581 break;
582 }
583 clock_name_t sdxc_clk = clock_sdxc0;
584 sdxc_enable_sd_clock(ptr, false);
585 /* Configure the SDXC Frequency to 200MHz */
586 clock_set_source_divider(sdxc_clk, clk_src_pll0_clk0, 2);
587 sdxc_enable_freq_selection(ptr);
588
589 /* Configure the clock below 400KHz for the identification state */
590 if (freq <= 400000UL) {
591 sdxc_set_clock_divider(ptr, 600);
592 }
593 /* configure the clock to 24MHz for the SDR12/Default speed */
594 else if (freq <= 25000000UL) {
595 sdxc_set_clock_divider(ptr, 8);
596 }
597 /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */
598 else if (freq <= 50000000UL) {
599 sdxc_set_clock_divider(ptr, 4);
600 }
601 /* Configure the clock to 100MHz for the SDR50 */
602 else if (freq <= 100000000UL) {
603 sdxc_set_clock_divider(ptr, 2);
604 }
605 /* Configure the clock to 166MHz for SDR104/HS200/HS400 */
606 else if (freq <= 208000000UL) {
607 sdxc_set_clock_divider(ptr, 1);
608 }
609 /* For other unsupported clock ranges, configure the clock to 24MHz */
610 else {
611 sdxc_set_clock_divider(ptr, 8);
612 }
613 sdxc_enable_sd_clock(ptr, true);
614 actual_freq = clock_get_frequency(sdxc_clk) / sdxc_get_clock_divider(ptr);
615 } while (false);
616
617 return actual_freq;
618 }
619
board_sd_switch_pins_to_1v8(SDXC_Type * ptr)620 void board_sd_switch_pins_to_1v8(SDXC_Type *ptr)
621 {
622 /* This feature is not supported */
623 }
624
board_sd_detect_card(SDXC_Type * ptr)625 bool board_sd_detect_card(SDXC_Type *ptr)
626 {
627 return sdxc_is_card_inserted(ptr);
628 }
629
board_init_enet_ptp_clock(ENET_Type * ptr)630 hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr)
631 {
632 /* set clock source */
633 if (ptr == HPM_ENET0) {
634 /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for ent0 ptp clock */
635 clock_set_source_divider(clock_ptp0, clk_src_pll0_clk0, 4); /* 100MHz */
636 } else {
637 return status_invalid_argument;
638 }
639
640 return status_success;
641 }
642
board_init_enet_rmii_reference_clock(ENET_Type * ptr,bool internal)643 hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal)
644 {
645 if (internal == false) {
646 return status_success;
647 }
648
649 /* Configure Enet clock to output reference clock */
650 if (ptr == HPM_ENET0) {
651 /* make sure pll0_clk2 output clock at 250MHz then set 50MHz for enet0 */
652 clock_set_source_divider(clock_eth0, clk_src_pll0_clk2, 5);
653 } else {
654 return status_invalid_argument;
655 }
656 return status_success;
657 }
658
board_init_adc16_pins(void)659 void board_init_adc16_pins(void)
660 {
661 init_adc_pins();
662 }
663
board_init_enet_pins(ENET_Type * ptr)664 hpm_stat_t board_init_enet_pins(ENET_Type *ptr)
665 {
666 init_enet_pins(ptr);
667
668 return status_success;
669 }
670
board_reset_enet_phy(ENET_Type * ptr)671 hpm_stat_t board_reset_enet_phy(ENET_Type *ptr)
672 {
673 return status_success;
674 }
675
board_init_dac_pins(DAC_Type * ptr)676 void board_init_dac_pins(DAC_Type *ptr)
677 {
678 init_dac_pins(ptr);
679 }
680
board_init_uart_clock(UART_Type * ptr)681 uint32_t board_init_uart_clock(UART_Type *ptr)
682 {
683 uint32_t freq = 0U;
684 if (ptr == HPM_UART0) {
685 clock_set_source_divider(clock_uart0, clk_src_osc24m, 1);
686 freq = clock_get_frequency(clock_uart0);
687 } else if (ptr == HPM_UART1) {
688 clock_set_source_divider(clock_uart1, clk_src_osc24m, 1);
689 freq = clock_get_frequency(clock_uart1);
690 } else if (ptr == HPM_UART2) {
691 clock_set_source_divider(clock_uart2, clk_src_osc24m, 1);
692 freq = clock_get_frequency(clock_uart2);
693 } else {
694 /* Not supported */
695 }
696 return freq;
697 }
698