1 // Copyright 2019 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #include <stdint.h>
15 #include "sdkconfig.h"
16 #include "esp_attr.h"
17 #include "esp_log.h"
18 #include "esp_image_format.h"
19 #include "flash_qio_mode.h"
20
21 #include "bootloader_init.h"
22 #include "bootloader_clock.h"
23 #include "bootloader_common.h"
24 #include "bootloader_flash_config.h"
25 #include "bootloader_mem.h"
26 #include "bootloader_console.h"
27 #include "bootloader_flash_priv.h"
28
29 #include "soc/cpu.h"
30 #include "soc/dport_reg.h"
31 #include "soc/efuse_reg.h"
32 #include "soc/gpio_periph.h"
33 #include "soc/gpio_sig_map.h"
34 #include "soc/io_mux_reg.h"
35 #include "soc/rtc.h"
36 #include "soc/spi_periph.h"
37 #include "hal/gpio_hal.h"
38
39 #include "esp32/rom/cache.h"
40 #include "esp_rom_gpio.h"
41 #include "esp_rom_efuse.h"
42 #include "esp_rom_sys.h"
43 #include "esp32/rom/spi_flash.h"
44 #include "esp32/rom/rtc.h"
45
46 static const char *TAG = "boot.esp32";
47
48 #define FLASH_CLK_IO SPI_CLK_GPIO_NUM
49 #define FLASH_CS_IO SPI_CS0_GPIO_NUM
50 #define FLASH_SPIQ_IO SPI_Q_GPIO_NUM
51 #define FLASH_SPID_IO SPI_D_GPIO_NUM
52 #define FLASH_SPIWP_IO SPI_WP_GPIO_NUM
53 #define FLASH_SPIHD_IO SPI_HD_GPIO_NUM
54
bootloader_configure_spi_pins(int drv)55 void bootloader_configure_spi_pins(int drv)
56 {
57 uint32_t pkg_ver = bootloader_common_get_chip_ver_pkg();
58
59 if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
60 pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
61 pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 ||
62 pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
63 // For ESP32D2WD or ESP32-PICO series,the SPI pins are already configured
64 // flash clock signal should come from IO MUX.
65 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
66 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
67 } else {
68 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
69 if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
70 esp_rom_gpio_connect_out_signal(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
71 esp_rom_gpio_connect_out_signal(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
72 esp_rom_gpio_connect_in_signal(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
73 esp_rom_gpio_connect_out_signal(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
74 esp_rom_gpio_connect_in_signal(FLASH_SPID_IO, SPID_IN_IDX, 0);
75 esp_rom_gpio_connect_out_signal(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
76 esp_rom_gpio_connect_in_signal(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
77 esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
78 esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
79 //select pin function gpio
80 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
81 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
82 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
83 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
84 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
85 // flash clock signal should come from IO MUX.
86 // set drive ability for clock
87 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
88 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
89
90 #if CONFIG_SPIRAM_TYPE_ESPPSRAM32 || CONFIG_SPIRAM_TYPE_ESPPSRAM64
91 uint32_t flash_id = g_rom_flashchip.device_id;
92 if (flash_id == FLASH_ID_GD25LQ32C) {
93 // Set drive ability for 1.8v flash in 80Mhz.
94 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA0_U, FUN_DRV, 3, FUN_DRV_S);
95 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA1_U, FUN_DRV, 3, FUN_DRV_S);
96 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA2_U, FUN_DRV, 3, FUN_DRV_S);
97 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA3_U, FUN_DRV, 3, FUN_DRV_S);
98 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CMD_U, FUN_DRV, 3, FUN_DRV_S);
99 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3, FUN_DRV_S);
100 }
101 #endif
102 }
103 }
104 }
105
bootloader_reset_mmu(void)106 static void bootloader_reset_mmu(void)
107 {
108 /* completely reset MMU in case serial bootloader was running */
109 Cache_Read_Disable(0);
110 #if !CONFIG_FREERTOS_UNICORE
111 Cache_Read_Disable(1);
112 #endif
113 Cache_Flush(0);
114 #if !CONFIG_FREERTOS_UNICORE
115 Cache_Flush(1);
116 #endif
117 mmu_init(0);
118 #if !CONFIG_FREERTOS_UNICORE
119 /* The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are
120 necessary to work around a hardware bug. */
121 DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
122 mmu_init(1);
123 DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
124 #endif
125
126 /* normal ROM boot exits with DROM0 cache unmasked,
127 but serial bootloader exits with it masked. */
128 DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
129 #if !CONFIG_FREERTOS_UNICORE
130 DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
131 #endif
132 }
133
bootloader_check_rated_cpu_clock(void)134 static esp_err_t bootloader_check_rated_cpu_clock(void)
135 {
136 int rated_freq = bootloader_clock_get_rated_freq_mhz();
137 if (rated_freq < CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) {
138 ESP_LOGE(TAG, "Chip CPU frequency rated for %dMHz, configured for %dMHz. Modify CPU frequency in menuconfig",
139 rated_freq, CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ);
140 return ESP_FAIL;
141 }
142 return ESP_OK;
143 }
144
update_flash_config(const esp_image_header_t * bootloader_hdr)145 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
146 {
147 uint32_t size;
148 switch (bootloader_hdr->spi_size) {
149 case ESP_IMAGE_FLASH_SIZE_1MB:
150 size = 1;
151 break;
152 case ESP_IMAGE_FLASH_SIZE_2MB:
153 size = 2;
154 break;
155 case ESP_IMAGE_FLASH_SIZE_4MB:
156 size = 4;
157 break;
158 case ESP_IMAGE_FLASH_SIZE_8MB:
159 size = 8;
160 break;
161 case ESP_IMAGE_FLASH_SIZE_16MB:
162 size = 16;
163 break;
164 default:
165 size = 2;
166 }
167 Cache_Read_Disable(0);
168 // Set flash chip size
169 esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
170 // TODO: set mode
171 // TODO: set frequency
172 Cache_Flush(0);
173 Cache_Read_Enable(0);
174 }
175
print_flash_info(const esp_image_header_t * bootloader_hdr)176 static void print_flash_info(const esp_image_header_t *bootloader_hdr)
177 {
178 ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
179 ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
180 ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
181 ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
182 ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
183
184 const char *str;
185 switch (bootloader_hdr->spi_speed) {
186 case ESP_IMAGE_SPI_SPEED_40M:
187 str = "40MHz";
188 break;
189 case ESP_IMAGE_SPI_SPEED_26M:
190 str = "26.7MHz";
191 break;
192 case ESP_IMAGE_SPI_SPEED_20M:
193 str = "20MHz";
194 break;
195 case ESP_IMAGE_SPI_SPEED_80M:
196 str = "80MHz";
197 break;
198 default:
199 str = "20MHz";
200 break;
201 }
202 ESP_LOGI(TAG, "SPI Speed : %s", str);
203
204 /* SPI mode could have been set to QIO during boot already,
205 so test the SPI registers not the flash header */
206 uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0));
207 if (spi_ctrl & SPI_FREAD_QIO) {
208 str = "QIO";
209 } else if (spi_ctrl & SPI_FREAD_QUAD) {
210 str = "QOUT";
211 } else if (spi_ctrl & SPI_FREAD_DIO) {
212 str = "DIO";
213 } else if (spi_ctrl & SPI_FREAD_DUAL) {
214 str = "DOUT";
215 } else if (spi_ctrl & SPI_FASTRD_MODE) {
216 str = "FAST READ";
217 } else {
218 str = "SLOW READ";
219 }
220 ESP_LOGI(TAG, "SPI Mode : %s", str);
221
222 switch (bootloader_hdr->spi_size) {
223 case ESP_IMAGE_FLASH_SIZE_1MB:
224 str = "1MB";
225 break;
226 case ESP_IMAGE_FLASH_SIZE_2MB:
227 str = "2MB";
228 break;
229 case ESP_IMAGE_FLASH_SIZE_4MB:
230 str = "4MB";
231 break;
232 case ESP_IMAGE_FLASH_SIZE_8MB:
233 str = "8MB";
234 break;
235 case ESP_IMAGE_FLASH_SIZE_16MB:
236 str = "16MB";
237 break;
238 default:
239 str = "2MB";
240 break;
241 }
242 ESP_LOGI(TAG, "SPI Flash Size : %s", str);
243 }
244
bootloader_init_flash_configure(void)245 static void IRAM_ATTR bootloader_init_flash_configure(void)
246 {
247 bootloader_flash_gpio_config(&bootloader_image_hdr);
248 bootloader_flash_dummy_config(&bootloader_image_hdr);
249 bootloader_flash_cs_timing_config();
250 }
251
bootloader_init_spi_flash(void)252 static esp_err_t bootloader_init_spi_flash(void)
253 {
254 bootloader_init_flash_configure();
255 #ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
256 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
257 if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
258 ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
259 return ESP_FAIL;
260 }
261 #endif
262
263 esp_rom_spiflash_unlock();
264
265 #if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
266 bootloader_enable_qio_mode();
267 #endif
268
269 print_flash_info(&bootloader_image_hdr);
270 update_flash_config(&bootloader_image_hdr);
271 //ensure the flash is write-protected
272 bootloader_enable_wp();
273 return ESP_OK;
274 }
275
wdt_reset_cpu0_info_enable(void)276 static void wdt_reset_cpu0_info_enable(void)
277 {
278 //We do not reset core1 info here because it didn't work before cpu1 was up. So we put it into call_start_cpu1.
279 DPORT_REG_SET_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_PDEBUG_ENABLE | DPORT_PRO_CPU_RECORD_ENABLE);
280 DPORT_REG_CLR_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_RECORD_ENABLE);
281 }
282
wdt_reset_info_dump(int cpu)283 static void wdt_reset_info_dump(int cpu)
284 {
285 uint32_t inst = 0, pid = 0, stat = 0, data = 0, pc = 0,
286 lsstat = 0, lsaddr = 0, lsdata = 0, dstat = 0;
287 const char *cpu_name = cpu ? "APP" : "PRO";
288
289 if (cpu == 0) {
290 stat = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_STATUS_REG);
291 pid = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PID_REG);
292 inst = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGINST_REG);
293 dstat = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG);
294 data = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG);
295 pc = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGPC_REG);
296 lsstat = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG);
297 lsaddr = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG);
298 lsdata = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG);
299 } else {
300 #if !CONFIG_FREERTOS_UNICORE
301 stat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_STATUS_REG);
302 pid = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PID_REG);
303 inst = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGINST_REG);
304 dstat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG);
305 data = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGDATA_REG);
306 pc = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGPC_REG);
307 lsstat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG);
308 lsaddr = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG);
309 lsdata = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG);
310 #endif
311 }
312
313 if (DPORT_RECORD_PDEBUGINST_SZ(inst) == 0 &&
314 DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(dstat) == DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI) {
315 ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%x (waiti mode)", cpu_name, pc);
316 } else {
317 ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%x", cpu_name, pc);
318 }
319 ESP_LOGD(TAG, "WDT reset info: %s CPU STATUS 0x%08x", cpu_name, stat);
320 ESP_LOGD(TAG, "WDT reset info: %s CPU PID 0x%08x", cpu_name, pid);
321 ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGINST 0x%08x", cpu_name, inst);
322 ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGSTATUS 0x%08x", cpu_name, dstat);
323 ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGDATA 0x%08x", cpu_name, data);
324 ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGPC 0x%08x", cpu_name, pc);
325 ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0STAT 0x%08x", cpu_name, lsstat);
326 ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0ADDR 0x%08x", cpu_name, lsaddr);
327 ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08x", cpu_name, lsdata);
328 }
329
bootloader_check_wdt_reset(void)330 static void bootloader_check_wdt_reset(void)
331 {
332 int wdt_rst = 0;
333 RESET_REASON rst_reas[2];
334
335 rst_reas[0] = rtc_get_reset_reason(0);
336 rst_reas[1] = rtc_get_reset_reason(1);
337 if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
338 rst_reas[0] == TGWDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
339 ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
340 wdt_rst = 1;
341 }
342 if (rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET || rst_reas[1] == TG1WDT_SYS_RESET ||
343 rst_reas[1] == TGWDT_CPU_RESET || rst_reas[1] == RTCWDT_CPU_RESET) {
344 ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
345 wdt_rst = 1;
346 }
347 if (wdt_rst) {
348 // if reset by WDT dump info from trace port
349 wdt_reset_info_dump(0);
350 #if !CONFIG_FREERTOS_UNICORE
351 wdt_reset_info_dump(1);
352 #endif
353 }
354 wdt_reset_cpu0_info_enable();
355 }
356
bootloader_init(void)357 esp_err_t bootloader_init(void)
358 {
359 esp_err_t ret = ESP_OK;
360
361 bootloader_init_mem();
362
363 // check that static RAM is after the stack
364 #ifndef NDEBUG
365 {
366 assert(&_bss_start <= &_bss_end);
367 assert(&_data_start <= &_data_end);
368 int *sp = get_sp();
369 assert(sp < &_bss_start);
370 assert(sp < &_data_start);
371 }
372 #endif
373 // clear bss section
374 bootloader_clear_bss_section();
375 // bootst up vddsdio
376 bootloader_common_vddsdio_configure();
377 // reset MMU
378 bootloader_reset_mmu();
379 // check rated CPU clock
380 if ((ret = bootloader_check_rated_cpu_clock()) != ESP_OK) {
381 goto err;
382 }
383 // config clock
384 bootloader_clock_configure();
385 // initialize uart console, from now on, we can use esp_log
386 bootloader_console_init();
387 /* print 2nd bootloader banner */
388 bootloader_print_banner();
389 // update flash ID
390 bootloader_flash_update_id();
391 // read bootloader header
392 if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
393 goto err;
394 }
395 // read chip revision and check if it's compatible to bootloader
396 if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
397 goto err;
398 }
399 // initialize spi flash
400 if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
401 goto err;
402 }
403 // check whether a WDT reset happend
404 bootloader_check_wdt_reset();
405 // config WDT
406 bootloader_config_wdt();
407 // enable RNG early entropy source
408 bootloader_enable_random();
409 err:
410 return ret;
411 }
412