1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef __TWAI_STRUCT_H__ 16 #define __TWAI_STRUCT_H__ 17 18 #pragma once 19 20 #include <stdint.h> 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif /* __cplusplus */ 25 /* ---------------------------- Register Layout ------------------------------ */ 26 27 /* The TWAI peripheral's registers are 8bits, however the ESP32 can only access 28 * peripheral registers every 32bits. Therefore each TWAI register is mapped to 29 * the least significant byte of every 32bits. 30 */ 31 32 typedef volatile struct twai_dev_s { 33 //Configuration and Control Registers 34 union { 35 struct { 36 uint32_t rm: 1; /* MOD.0 Reset Mode */ 37 uint32_t lom: 1; /* MOD.1 Listen Only Mode */ 38 uint32_t stm: 1; /* MOD.2 Self Test Mode */ 39 uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */ 40 uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */ 41 }; 42 uint32_t val; 43 } mode_reg; /* Address 0 */ 44 union { 45 struct { 46 uint32_t tr: 1; /* CMR.0 Transmission Request */ 47 uint32_t at: 1; /* CMR.1 Abort Transmission */ 48 uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */ 49 uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */ 50 uint32_t srr: 1; /* CMR.4 Self Reception Request */ 51 uint32_t reserved27: 27; /* Internal Reserved */ 52 }; 53 uint32_t val; 54 } command_reg; /* Address 1 */ 55 union { 56 struct { 57 uint32_t rbs: 1; /* SR.0 Receive Buffer Status */ 58 uint32_t dos: 1; /* SR.1 Data Overrun Status */ 59 uint32_t tbs: 1; /* SR.2 Transmit Buffer Status */ 60 uint32_t tcs: 1; /* SR.3 Transmission Complete Status */ 61 uint32_t rs: 1; /* SR.4 Receive Status */ 62 uint32_t ts: 1; /* SR.5 Transmit Status */ 63 uint32_t es: 1; /* SR.6 Error Status */ 64 uint32_t bs: 1; /* SR.7 Bus Status */ 65 uint32_t reserved24: 24; /* Internal Reserved */ 66 }; 67 uint32_t val; 68 } status_reg; /* Address 2 */ 69 union { 70 struct { 71 uint32_t ri: 1; /* IR.0 Receive Interrupt */ 72 uint32_t ti: 1; /* IR.1 Transmit Interrupt */ 73 uint32_t ei: 1; /* IR.2 Error Interrupt */ 74 uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */ 75 uint32_t epi: 1; /* IR.5 Error Passive Interrupt */ 76 uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */ 77 uint32_t bei: 1; /* IR.7 Bus Error Interrupt */ 78 uint32_t reserved24: 24; /* Internal Reserved */ 79 }; 80 uint32_t val; 81 } interrupt_reg; /* Address 3 */ 82 union { 83 struct { 84 uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */ 85 uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */ 86 uint32_t eie: 1; /* IER.2 Error Interrupt Enable */ 87 uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */ 88 uint32_t brp_div: 1; /* THIS IS NOT AN INTERRUPT. brp_div will prescale BRP by 2. Only available on ESP32 Revision 2 or later. Reserved otherwise */ 89 uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */ 90 uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */ 91 uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */ 92 uint32_t reserved24: 24; /* Internal Reserved */ 93 }; 94 uint32_t val; 95 } interrupt_enable_reg; /* Address 4 */ 96 uint32_t reserved_05; /* Address 5 */ 97 union { 98 struct { 99 uint32_t brp: 6; /* BTR0[5:0] Baud Rate Prescaler */ 100 uint32_t sjw: 2; /* BTR0[7:6] Synchronization Jump Width*/ 101 uint32_t reserved24: 24; /* Internal Reserved */ 102 }; 103 uint32_t val; 104 } bus_timing_0_reg; /* Address 6 */ 105 union { 106 struct { 107 uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */ 108 uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */ 109 uint32_t sam: 1; /* BTR1.7 Sampling*/ 110 uint32_t reserved24: 24; /* Internal Reserved */ 111 }; 112 uint32_t val; 113 } bus_timing_1_reg; /* Address 7 */ 114 uint32_t reserved_08; /* Address 8 (Output control not supported) */ 115 uint32_t reserved_09; /* Address 9 (Test Register not supported) */ 116 uint32_t reserved_10; /* Address 10 */ 117 118 //Capture and Counter Registers 119 union { 120 struct { 121 uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */ 122 uint32_t reserved27: 27; /* Internal Reserved */ 123 }; 124 uint32_t val; 125 } arbitration_lost_captue_reg; /* Address 11 */ 126 union { 127 struct { 128 uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */ 129 uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */ 130 uint32_t errc: 2; /* ECC[7:6] Error Code */ 131 uint32_t reserved24: 24; /* Internal Reserved */ 132 }; 133 uint32_t val; 134 } error_code_capture_reg; /* Address 12 */ 135 union { 136 struct { 137 uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */ 138 uint32_t reserved24: 24; /* Internal Reserved */ 139 }; 140 uint32_t val; 141 } error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */ 142 union { 143 struct { 144 uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */ 145 uint32_t reserved24: 24; /* Internal Reserved */ 146 }; 147 uint32_t val; 148 } rx_error_counter_reg; /* Address 12 */ 149 union { 150 struct { 151 uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */ 152 uint32_t reserved24: 24; /* Internal Reserved */ 153 }; 154 uint32_t val; 155 } tx_error_counter_reg; /* Address 15 */ 156 157 //Shared Registers (TX Buff/RX Buff/Acc Filter) 158 union { 159 struct { 160 union { 161 struct { 162 uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */ 163 uint32_t reserved24: 24; /* Internal Reserved */ 164 }; 165 uint32_t val; 166 } acr[4]; 167 union { 168 struct { 169 uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */ 170 uint32_t reserved24: 24; /* Internal Reserved */ 171 }; 172 uint32_t val; 173 } amr[4]; 174 uint32_t reserved32[5]; 175 } acceptance_filter; 176 union { 177 struct { 178 uint32_t byte: 8; 179 uint32_t reserved24: 24; 180 }; 181 uint32_t val; 182 } tx_rx_buffer[13]; 183 }; /* Address 16-28 TX/RX Buffer and Acc Filter*/; 184 185 //Misc Registers 186 union { 187 struct { 188 uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */ 189 uint32_t reserved25: 25; /* Internal Reserved */ 190 }; 191 uint32_t val; 192 } rx_message_counter_reg; /* Address 29 */ 193 uint32_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */ 194 union { 195 struct { 196 uint32_t cd: 3; /* CDR[2:0] CLKOUT frequency selector based of fOSC */ 197 uint32_t co: 1; /* CDR.3 CLKOUT enable/disable */ 198 uint32_t reserved3: 3; /* Internal Reserved. RXINTEN and CBP not supported */ 199 uint32_t cm: 1; /* CDR.7 Register Layout. Basic:0 Extended:1 */ 200 uint32_t reserved24: 24; /* Internal Reserved */ 201 }; 202 uint32_t val; 203 } clock_divider_reg; /* Address 31 */ 204 } twai_dev_t; 205 206 _Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes"); 207 208 extern twai_dev_t TWAI; 209 210 211 #ifdef __cplusplus 212 } 213 #endif /* __cplusplus */ 214 #endif /* __TWAI_STRUCT_H__ */ 215