1 /* 2 * linux-5.4/drivers/media/platform/sunxi-vin/vin-video/dma_reg.h 3 * 4 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd. 5 * 6 * Authors: Zhao Wei <zhaowei@allwinnertech.com> 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef __CSIC__DMA__REG__H__ 20 #define __CSIC__DMA__REG__H__ 21 22 #include <linux/types.h> 23 #include <media/sunxi_camera_v2.h> 24 25 /*register value*/ 26 27 /* 28 * output data format 29 */ 30 enum output_fmt { 31 /* only when input is raw */ 32 FIELD_RAW_8 = 0, 33 FIELD_RAW_10 = 1, 34 FIELD_RAW_12 = 2, 35 FIELD_RGB565 = 4, 36 FIELD_RGB888 = 5, 37 FIELD_PRGB888 = 6, 38 FRAME_RAW_8 = 8, 39 FRAME_RAW_10 = 9, 40 FRAME_RAW_12 = 10, 41 FRAME_RGB565 = 12, 42 FRAME_RGB888 = 13, 43 FRAME_PRGB888 = 14, 44 45 /* only when input is yuv422/yuv420 */ 46 FIELD_PLANAR_YUV422 = 0, /* yuv422 */ 47 LBC_MODE_OUTPUT = 0, /* yuv420 */ 48 FIELD_PLANAR_YUV420 = 1, 49 FRAME_PLANAR_YUV420 = 2, 50 FRAME_PLANAR_YUV422 = 3, 51 FIELD_UV_CB_YUV422 = 4, 52 FIELD_UV_CB_YUV420 = 5, 53 FRAME_UV_CB_YUV420 = 6, 54 FRAME_UV_CB_YUV422 = 7, 55 FIELD_VU_CB_YUV422 = 8, 56 FIELD_VU_CB_YUV420 = 9, 57 FRAME_VU_CB_YUV420 = 10, 58 FRAME_VU_CB_YUV422 = 11, 59 FIELD_CB_YUV400 = 13, 60 FRAME_CB_YUV400 = 15, 61 }; 62 63 /* 64 * input field selection, only when input is ccir656 65 */ 66 enum field_sel { 67 FIELD_1, /* odd field */ 68 FIELD_2, /* even field */ 69 FIELD_EITHER, /* either field */ 70 }; 71 72 /* 73 * fps down sample 74 */ 75 enum fps_ds { 76 FPS_NO_DS, /* no down sample */ 77 FPS_2_DS, /* only receives the first frame every 2 frames */ 78 FPS_3_DS, /* only receives the first frame every 3 frames */ 79 FPS_4_DS, /* only receives the first frame every 4 frames */ 80 FPS_5_DS, /* only receives the first frame every 5 frames */ 81 FPS_6_DS, /* only receives the first frame every 6 frames */ 82 FPS_7_DS, /* only receives the first frame every 7 frames */ 83 FPS_8_DS, /* only receives the first frame every 8 frames */ 84 FPS_9_DS, /* only receives the first frame every 9 frames */ 85 FPS_10_DS, /* only receives the first frame every 10 frames */ 86 FPS_11_DS, /* only receives the first frame every 11 frames */ 87 FPS_12_DS, /* only receives the first frame every 12 frames */ 88 FPS_13_DS, /* only receives the first frame every 13 frames */ 89 FPS_14_DS, /* only receives the first frame every 14 frames */ 90 FPS_15_DS, /* only receives the first frame every 15 frames */ 91 FPS_16_DS, /* only receives the first frame every 16 frames */ 92 }; 93 94 /* 95 * Minimum size of SDRAM block write 96 */ 97 enum min_sdr_wr_size { 98 SDR_256B, /* if hflip is enable, always select 256 bytes */ 99 SDR_512B, 100 SDR_1K, 101 SDR_2K, 102 }; 103 104 /* 105 * dma fifo buffer select 106 */ 107 enum fifo_buf_sel { 108 FIFO0_BUF_A = 0, 109 FIFO1_BUF_A, 110 FIFO2_BUF_A, 111 }; 112 113 /* 114 * dma interrupt select 115 */ 116 enum dma_int_sel { 117 DMA_INT_CAPTURE_DONE = 0X1, 118 DMA_INT_FRAME_DONE = 0X2, 119 DMA_INT_BUF_0_OVERFLOW = 0X4, 120 DMA_INT_BUF_1_OVERFLOW = 0X8, 121 DMA_INT_BUF_2_OVERFLOW = 0X10, 122 DMA_INT_LINE_CNT = 0X20, 123 DMA_INT_HBLANK_OVERFLOW = 0X40, 124 DMA_INT_VSYNC_TRIG = 0X80, 125 DMA_INT_FBC_OVHD_WRDDR_FULL = 0X100, 126 DMA_INT_FBC_DATA_WRDDR_FULL = 0X200, 127 DMA_INT_BUF_ADDR_FIFO = 0x2000, 128 DMA_INT_STORED_FRM_CNT = 0x4000, 129 DMA_INT_FRM_LOST = 0x8000, 130 DMA_INT_LBC_HB = 0x10000, 131 DMA_INT_ALL = 0X1E3FF, 132 }; 133 134 /*register data struct*/ 135 136 struct csic_dma_flip { 137 unsigned int hflip_en; 138 unsigned int vflip_en; 139 }; 140 141 struct csic_dma_cfg { 142 enum output_fmt fmt; 143 struct csic_dma_flip flip; 144 enum field_sel field; 145 enum fps_ds ds; 146 enum min_sdr_wr_size block; 147 }; 148 149 struct dma_output_size { 150 unsigned int hor_len; 151 unsigned int hor_start; 152 unsigned int ver_len; 153 unsigned int ver_start; 154 }; 155 156 struct dma_buf_len { 157 unsigned int buf_len_y; 158 unsigned int buf_len_c; 159 }; 160 161 struct dma_flip_size { 162 unsigned int ver_len; 163 unsigned int hor_len; 164 }; 165 166 struct dma_capture_status { 167 bool field_sta; 168 bool vcap_sta; 169 bool scap_sta; 170 }; 171 172 struct dma_int_status { 173 bool capture_done; 174 bool frame_done; 175 bool buf_0_overflow; 176 bool buf_1_overflow; 177 bool buf_2_overflow; 178 bool line_cnt_flag; 179 bool hblank_overflow; 180 bool vsync_trig; 181 bool fbc_ovhd_wrddr_full; 182 bool fbc_data_wrddr_full; 183 bool buf_addr_fifo; 184 bool stored_frm_cnt; 185 bool frm_lost; 186 bool lbc_hb; 187 }; 188 189 struct dma_fifo_threshold { 190 unsigned int fifo_nearly_full_th; 191 unsigned int fifo_thrs; 192 }; 193 194 struct dma_pclk_statistic { 195 unsigned int pclk_cnt_line_max; 196 unsigned int pclk_cnt_line_min; 197 }; 198 199 struct dma_lbc_cmp { 200 unsigned char is_lossy; 201 unsigned char bit_depth; 202 unsigned char glb_enable; 203 unsigned char dts_enable; 204 unsigned char ots_enable; 205 unsigned char msq_enable; 206 unsigned int cmp_ratio_even; 207 unsigned int cmp_ratio_odd; 208 unsigned int mb_mi_bits[2]; 209 unsigned char rc_adv[4]; 210 unsigned char lmtqp_en; 211 unsigned char lmtqp_min; 212 unsigned char updata_adv_en; 213 unsigned char updata_adv_ratio; 214 unsigned int line_tar_bits[2]; 215 }; 216 217 struct dma_bufa_threshold { 218 unsigned char bufa_fifo_threshold; 219 unsigned char stored_frm_threshold; 220 unsigned char bufa_fifo_total; 221 }; 222 223 int csic_dma_set_base_addr(unsigned int sel, unsigned long addr); 224 int csic_dma_get_frame_cnt(unsigned int sel); 225 void csic_dma_top_enable(unsigned int sel); 226 void csic_dma_top_disable(unsigned int sel); 227 void csic_dma_enable(unsigned int sel); 228 void csic_dma_disable(unsigned int sel); 229 void csic_fbc_enable(unsigned int sel); 230 void csic_fbc_disable(unsigned int sel); 231 void csic_lbc_enable(unsigned int sel); 232 void csic_lbc_disable(unsigned int sel); 233 void csic_frame_cnt_enable(unsigned int sel); 234 void csic_frame_cnt_disable(unsigned int sel); 235 void csic_buf_addr_fifo_en(unsigned int sel, unsigned int en); 236 void csic_dma_clk_cnt_en(unsigned int sel, unsigned int en); 237 void csic_dma_clk_cnt_sample(unsigned int sel, unsigned int en); 238 void csic_dma_output_fmt_cfg(unsigned int sel, enum output_fmt fmt); 239 void csic_dma_buf_length_software_enable(unsigned int sel, unsigned int en); 240 void csi_dam_flip_software_enable(unsigned int sel, unsigned int en); 241 void csic_dma_flip_en(unsigned int sel, struct csic_dma_flip *flip); 242 void csic_dma_config(unsigned int sel, struct csic_dma_cfg *cfg); 243 void csic_dma_10bit_cut2_8bit_enable(unsigned int sel); 244 void csic_dma_10bit_cut2_8bit_disable(unsigned int sel); 245 void csic_set_threshold_for_bufa_mode(unsigned int sel, struct dma_bufa_threshold *threshold); 246 void csic_dma_output_size_cfg(unsigned int sel, struct dma_output_size *size); 247 void csic_dma_buffer_address(unsigned int sel, unsigned int buf, 248 unsigned long addr); 249 void csic_dma_buffer_length(unsigned int sel, struct dma_buf_len *buf_len); 250 void csic_dma_flip_size(unsigned int sel, struct dma_flip_size *flip_size); 251 void csic_dma_line_cnt(unsigned int sel, int line); 252 void csic_dma_frm_cnt(unsigned int sel, struct csi_sync_ctrl *sync); 253 void csic_dma_cap_status(unsigned int sel, struct dma_capture_status *status); 254 void csic_dma_int_enable(unsigned int sel, enum dma_int_sel interrupt); 255 void csic_dma_int_disable(unsigned int sel, enum dma_int_sel interrupt); 256 void csic_dma_int_get_status(unsigned int sel, struct dma_int_status *status); 257 void csic_dma_int_clear_status(unsigned int sel, enum dma_int_sel interrupt); 258 void csic_lbc_cmp_ratio(unsigned int sel, struct dma_lbc_cmp *lbc_cmp); 259 260 /*for debug*/ 261 void csic_dma_line_count(unsigned int sel, unsigned int line_cnt); 262 void csic_dma_frame_clk_cnt(unsigned int sel, unsigned int clk_cnt); 263 void csic_dma_acc_itnl_cnt(unsigned int sel, unsigned int acc_clk_cnt, 264 unsigned int itnl_clk_cnt); 265 void csic_dma_fifo_statistic(unsigned int sel, unsigned int fifo_frm_max); 266 void csic_dma_fifo_threshold(unsigned int sel, struct dma_fifo_threshold *threshold); 267 void csic_dma_pclk_statistic(unsigned int sel, struct dma_pclk_statistic *pclk_stat); 268 269 #endif /* __CSIC__DMA__REG__H__ */ 270