1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #include <stdint.h> 18 #include <stdbool.h> 19 20 #include "esp_err.h" 21 22 #include "soc/soc_caps.h" 23 #include "hal/cpu_types.h" 24 #include "hal/cpu_ll.h" 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 /** 31 * Return the ID of the core currently executing this code. 32 * 33 * @return core id [0..SOC_CPU_CORES_NUM - 1] 34 */ 35 #define cpu_hal_get_core_id() cpu_ll_get_core_id() 36 37 /** 38 * Get the current value of the stack pointer. 39 * 40 * @return the current stack pointer 41 */ 42 #define cpu_hal_get_sp() cpu_ll_get_sp() 43 44 /** 45 * Get the current value of the internal counter that increments 46 * every processor-clock cycle. 47 * 48 * @return cycle count; returns 0 if not supported 49 */ 50 #define cpu_hal_get_cycle_count() cpu_ll_get_cycle_count() 51 52 /** 53 * Set the given value into the internal counter that increments 54 * every processor-clock cycle. 55 */ 56 #define cpu_hal_set_cycle_count(val) cpu_ll_set_cycle_count(val) 57 58 /** 59 * Check if some form of debugger is attached to CPU. 60 * 61 * @return true debugger is attached 62 * @return false no debugger is attached/ no support for debuggers 63 */ 64 #define cpu_hal_is_debugger_attached() cpu_ll_is_debugger_attached() 65 66 /** 67 * Init HW loop status. 68 */ 69 #define cpu_hal_init_hwloop() cpu_ll_init_hwloop() 70 71 /** 72 * Trigger a call to debugger. 73 */ 74 #define cpu_hal_break() cpu_ll_break() 75 76 /** 77 * Wait for interrupt. 78 */ 79 #define cpu_hal_waiti() cpu_ll_waiti() 80 81 #if SOC_CPU_BREAKPOINTS_NUM > 0 82 83 /** 84 * Set and enable breakpoint at an instruction address. 85 * 86 * @note Overwrites previously set breakpoint with same breakpoint ID. 87 * 88 * @param id breakpoint to set [0..SOC_CPU_BREAKPOINTS_NUM - 1] 89 * @param addr address to set a breakpoint on 90 */ 91 void cpu_hal_set_breakpoint(int id, const void* addr); 92 93 /** 94 * Clear and disable breakpoint. 95 * 96 * @param id breakpoint to clear [0..SOC_CPU_BREAKPOINTS_NUM - 1] 97 */ 98 void cpu_hal_clear_breakpoint(int id); 99 100 #endif // SOC_CPU_BREAKPOINTS_NUM > 0 101 102 #if SOC_CPU_WATCHPOINTS_NUM > 0 103 104 /** 105 * Set and enable a watchpoint, specifying the memory range and trigger operation. 106 * 107 * @param id watchpoint to set [0..SOC_CPU_WATCHPOINTS_NUM - 1] 108 * @param addr starting address 109 * @param size number of bytes from starting address to watch 110 * @param trigger operation on specified memory range that triggers the watchpoint (read, write, read/write) 111 */ 112 void cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_trigger_t trigger); 113 114 /** 115 * Clear and disable watchpoint. 116 * 117 * @param id watchpoint to clear [0..SOC_CPU_WATCHPOINTS_NUM - 1] 118 */ 119 void cpu_hal_clear_watchpoint(int id); 120 121 #endif // SOC_CPU_WATCHPOINTS_NUM > 0 122 123 /** 124 * Set exception vector table base address. 125 * 126 * @param base address to move the exception vector table to 127 */ 128 void cpu_hal_set_vecbase(const void* base); 129 130 #ifdef __cplusplus 131 } 132 #endif 133