1 /* 2 * Copyright (c) 2022 Winner Microelectronics Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 /** 17 * @file wm_hostspi.h 18 * 19 * @brief host spi Driver Module 20 * 21 * @author dave 22 * 23 * Copyright (c) 2015 Winner Microelectronics Co., Ltd. 24 */ 25 #ifndef WM_HOST_SPI_H 26 #define WM_HOST_SPI_H 27 28 #include "wm_type_def.h" 29 #include "list.h" 30 #include "wm_osal.h" 31 #include "wm_ram_config.h" 32 33 #define SPI_USE_DMA 34 35 #define SPI_DMA_CMD_MAX_SIZE (0x20) 36 #define SPI_DMA_BUF_MAX_SIZE (8160) 37 #define SPI_DMA_MAX_TRANS_SIZE (4092) 38 39 /** 40 * error code. 41 */ 42 #define TLS_SPI_STATUS_OK (0) 43 #define TLS_SPI_STATUS_EINVAL (-1) 44 #define TLS_SPI_STATUS_ENOMEM (-2) 45 #define TLS_SPI_STATUS_EBUSY (-3) 46 #define TLS_SPI_STATUS_ESHUTDOWN (-4) 47 #define TLS_SPI_STATUS_EPERM (-5) 48 #define TLS_SPI_STATUS_ECLKNOSUPPORT (-6) 49 #define TLS_SPI_STATUS_EMODENOSUPPORT (-7) 50 51 #define SPI_MASTER_FIFO_SIZE (32) 52 53 /** 54 * the SPI master controller's configuration data. 55 */ 56 /** configuration data. */ 57 #define SPI_CPHA (0x01) /** clock phase. */ 58 #define SPI_CPOL (0x02) /** clock polarity. */ 59 #define TLS_SPI_MODE_0 (0|0) /** motorola mode. */ 60 #define TLS_SPI_MODE_1 (0|SPI_CPHA) 61 #define TLS_SPI_MODE_2 (SPI_CPOL|0) 62 #define TLS_SPI_MODE_3 (SPI_CPOL|SPI_CPHA) 63 #define TLS_SPI_CS_LOW 0x00 /** chipselect active low. */ 64 #define TLS_SPI_CS_HIGH 0x01 /** chipselect active high. */ 65 #define TLS_SPI_FCLK_MIN (1000) /** minimum work clock rate(Hz). */ 66 #define TLS_SPI_FCLK_MAX (APB_CLK/2) /** maximum work clock rate(Hz). */ 67 68 /** default configuration data. */ 69 #define SPI_DEFAULT_SPEED (2000000) /** default clock rate is 2MHz. */ 70 #define SPI_DEFAULT_MODE (TLS_SPI_MODE_0) /** default mode MODE_0. */ 71 #define SPI_CS_ACTIVE_MODE (TLS_SPI_CS_LOW) /** default chipselect mode is active low. */ 72 #define SPI_CS_INACTIVE_MODE (TLS_SPI_CS_HIGH) 73 74 /** SPI transaction message status. */ 75 #define SPI_MESSAGE_STATUS_IDLE (0) 76 #define SPI_MESSAGE_STATUS_INPROGRESS (1) 77 #define SPI_MESSAGE_STATUS_DONE (2) 78 79 /**slave type*/ 80 #define SPI_SLAVE_FLASH 0 /**flash */ 81 #define SPI_SLAVE_CARD 1 /** SD card */ 82 #define SPI_SLAVE_CONTROL_PIN 0 83 /**transfer type*/ 84 #define SPI_BYTE_TRANSFER 0 /**byte transfer*/ 85 #define SPI_WORD_TRANSFER 1 /**word transfer*/ 86 #define SPI_USE_DMA_TRANSFER 2 /** DMA transfer */ 87 88 /** 89 * a read/write buffer pair 90 * 91 * SPI transfers always write the same number of bytes as they read. 92 * If the transmit buffer is null, zeroes will be shifted out while 93 * filling rx_buf. If the receive buffer is null, the data shifted in 94 * will be discarded. 95 */ 96 struct tls_spi_transfer { 97 struct dl_list transfer_list; /**< transfers are sequenced through 98 tls_spi_message.transfers. */ 99 100 const void *tx_buf; /**< data to be written, or NULL. */ 101 void *rx_buf; /**< data to be read, or NULL. */ 102 u32 len; /**< size of rx and tx buffers (in bytes). */ 103 u32 delay_usecs; /**< microseconds to delay after this transfer. */ 104 }; 105 106 /** 107 * one multi-segment SPI transaction 108 * 109 * A struct tls_spi_message is used to execute an atomic sequence of data 110 * transfers, each represented by a struct tls_spi_transfer. The sequence 111 * is "atomic" in the sense that no other spi_message may use that SPI bus 112 * until that sequence completes. 113 */ 114 struct tls_spi_message { 115 struct dl_list queue; /**< transaction messages are sequenced through 116 tls_spi_port.wait_queue. */ 117 118 struct dl_list transfers; /**< list of transfer segments in this transaction. */ 119 void (*complete) (void *); /**< called to report transaction completions. */ 120 void *context; /**< the argument to complete() when it's called. */ 121 u32 status; /**< transaction message status. */ 122 }; 123 124 /** 125 * driver structure to SPI master controller 126 * 127 * This data structure presents the SPI master controller's configuration 128 * data. The device attached to this SPI master controller share the same 129 * transfer mode, chipselect mode and clock rate. And this structure maintains 130 * a queue of tls_spi_message transactions and uses this tls_spi_message transaction 131 * to access to the SPI device. For each such message it queues, it calls the message's 132 * completion function when the transaction completes. 133 */ 134 struct tls_spi_port { 135 u32 speed_hz; /**< clock rate to be used. */ 136 u8 cs_active; /**< chipselect mode, maybe active low or active 137 high. */ 138 u8 mode; /**< SPI transfer mode: mode_0(CPHA=0, CHOL=0), 139 mode_1(CPHA=0, CHOL=1), mode_2(CPHA=1, 140 CHOL=0), mode_3(CPHA=1, CHOL=1). */ 141 u8 reconfig; 142 143 struct dl_list wait_queue; /**< wait list of transaction messages. */ 144 tls_os_queue_t *lock; 145 146 tls_os_queue_t *msg_queue; /**< notify the schedule thread that there's 147 transaction message queued. */ 148 struct tls_spi_message *current_message; /**< current transaction message 149 in-progressing. */ 150 u32 current_remaining_transfer; /**< remaining transfer segments count in 151 current transaction message. */ 152 153 struct tls_spi_transfer *current_transfer; /**< current transfer segment 154 in-progressing. */ 155 u32 current_remaining_bytes; /**< remaining data length in current 156 transfer segment. */ 157 158 u8 transtype; /**< transfer type */ 159 }; 160 161 /** 162 * @defgroup Driver_APIs Driver APIs 163 * @brief Driver APIs 164 */ 165 166 /** 167 * @addtogroup Driver_APIs 168 * @{ 169 */ 170 171 /** 172 * @defgroup MASTERSPI_Driver_APIs MASTER SPI Driver APIs 173 * @brief MASTERSPI driver APIs 174 */ 175 176 /** 177 * @addtogroup MASTERSPI_Driver_APIs 178 * @{ 179 */ 180 181 /** 182 * @brief This function is used to initialize the SPI master driver. 183 * 184 * @param[in] None 185 * 186 * @retval TLS_SPI_STATUS_OK if initialize success 187 * @retval TLS_SPI_STATUS_EBUSY if SPI is already initialized 188 * @retval TLS_SPI_STATUS_ENOMEM if malloc SPI memory fail 189 * 190 * @note None 191 */ 192 int tls_spi_init(void); 193 194 /** 195 * @brief This function is used to setup the spi controller. 196 * 197 * @param[in] mode is CPOL and CPHA type defined in TLS_SPI_MODE_0 to TLS_SPI_MODE_3 198 * @param[in] cs_active is cs mode, defined as TLS_SPI_CS_LOW or TLS_SPI_CS_HIGH 199 * @param[in] fclk is spi clock,the unit is HZ. 200 * 201 * @retval TLS_SPI_STATUS_OK if setup success 202 * @retval TLS_SPI_STATUS_EMODENOSUPPORT if mode is not support 203 * @retval TLS_SPI_STATUS_EINVAL if cs_active is not support 204 * @retval TLS_SPI_STATUS_ECLKNOSUPPORT if fclk is not support 205 * 206 * @note None 207 */ 208 int tls_spi_setup(u8 mode, u8 cs_active, u32 fclk); 209 210 /** 211 * @brief This function is used to synchronous write data by SPI. 212 * 213 * @param[in] buf data to be sent. 214 * @param[in] len data length. 215 * 216 * @retval TLS_SPI_STATUS_OK if write success. 217 * @retval TLS_SPI_STATUS_EINVAL if argument is invalid. 218 * @retval TLS_SPI_STATUS_ENOMEM if there is no enough memory. 219 * @retval TLS_SPI_STATUS_ESHUTDOWN if SPI driver does not installed. 220 * 221 * @note None 222 */ 223 int tls_spi_write(const u8 *buf, u32 len); 224 225 /** 226 * @brief This function is used to synchronously read data from SPI. 227 * 228 * @param[in] buf is the buffer for saving SPI data. 229 * @param[in] len is the data length. 230 * 231 * @retval TLS_SPI_STATUS_OK if write success. 232 * @retval TLS_SPI_STATUS_EINVAL if argument is invalid. 233 * @retval TLS_SPI_STATUS_ENOMEM if there is no enough memory. 234 * @retval TLS_SPI_STATUS_ESHUTDOWN if SPI driver does not installed. 235 * 236 * @note None 237 */ 238 int tls_spi_read(u8 *buf, u32 len); 239 240 /** 241 * @brief This function is used to synchronously write command and then read data from SPI. 242 * 243 * @param[in] txbuf is the write data buffer. 244 * @param[in] n_tx is the write data length. 245 * @param[in] rxbuf is the read data buffer. 246 * @param[in] n_rx is the read data length. 247 * 248 * @retval TLS_SPI_STATUS_OK if write success. 249 * @retval TLS_SPI_STATUS_EINVAL if argument is invalid. 250 * @retval TLS_SPI_STATUS_ENOMEM if there is no enough memory. 251 * @retval TLS_SPI_STATUS_ESHUTDOWN if SPI driver has not been installed. 252 * 253 * @note None 254 */ 255 int tls_spi_read_with_cmd(const u8 *txbuf, u32 n_tx, u8 *rxbuf, u32 n_rx); 256 257 /** 258 * @brief This function is used to synchronous write 32bit command then write data from SPI. 259 * 260 * @param[in] cmd is the command data. 261 * @param[in] n_cmd is the command len,can not bigger than four 262 * @param[in] txbuf is the write data buffer. 263 * @param[in] n_tx is the write data length. 264 * 265 * @retval TLS_SPI_STATUS_OK if write success. 266 * @retval TLS_SPI_STATUS_EINVAL if argument is invalid. 267 * @retval TLS_SPI_STATUS_ENOMEM if there is no enough memory. 268 * @retval TLS_SPI_STATUS_ESHUTDOWN if SPI driver does not installed. 269 * 270 * @note None 271 */ 272 int tls_spi_write_with_cmd(const u8 *cmd, u32 n_cmd, const u8 *txbuf, u32 n_tx); 273 274 /** 275 * @brief This function is used to set SPI transfer mode. 276 * 277 * @param[in] type is the transfer type. 278 * SPI_BYTE_TRANSFER ->byte transfer; 279 * SPI_WORD_TRANSFER ->word transfer; 280 * SPI_USE_DMA_TRANSFER ->DMA transfer; 281 282 * 283 * @return None 284 * 285 * @note None 286 */ 287 void tls_spi_trans_type(u8 type); 288 289 /** 290 * @} 291 */ 292 293 /** 294 * @} 295 */ 296 297 #endif /* WM_HOST_SPI_H */ 298