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1 /*
2  * Copyright (c) 2006 Luc Verhaegen (quirks list)
3  * Copyright (c) 2007-2008 Intel Corporation
4  *   Jesse Barnes <jesse.barnes@intel.com>
5  * Copyright 2010 Red Hat, Inc.
6  *
7  * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8  * FB layer.
9  *   Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10  *
11  * Permission is hereby granted, free of charge, to any person obtaining a
12  * copy of this software and associated documentation files (the "Software"),
13  * to deal in the Software without restriction, including without limitation
14  * the rights to use, copy, modify, merge, publish, distribute, sub license,
15  * and/or sell copies of the Software, and to permit persons to whom the
16  * Software is furnished to do so, subject to the following conditions:
17  *
18  * The above copyright notice and this permission notice (including the
19  * next paragraph) shall be included in all copies or substantial portions
20  * of the Software.
21  *
22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28  * DEALINGS IN THE SOFTWARE.
29  */
30 
31 #include <linux/hdmi.h>
32 #include <linux/i2c.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/vga_switcheroo.h>
37 
38 #include <drm/drm_displayid.h>
39 #include <drm/drm_drv.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_encoder.h>
42 #include <drm/drm_print.h>
43 #include <drm/drm_scdc_helper.h>
44 
45 #include "drm_crtc_internal.h"
46 
47 #define version_greater(edid, maj, min)                                                                                \
48     (((edid)->version > (maj)) || ((edid)->version == (maj) && (edid)->revision > (min)))
49 
50 #define EDID_EST_TIMINGS 0x10
51 #define EDID_STD_TIMINGS 0x8
52 #define EDID_DETAILED_TIMINGS 0x4
53 
54 /*
55  * EDID blocks out in the wild have a variety of bugs, try to collect
56  * them here (note that userspace may work around broken monitors first,
57  * but fixes should make their way here so that the kernel "just works"
58  * on as many displays as possible).
59  */
60 
61 /* First detailed mode wrong, use largest 60Hz mode */
62 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
63 /* Reported 135MHz pixel clock is too high, needs adjustment */
64 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
65 /* Prefer the largest mode at 75 Hz */
66 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
67 /* Detail timing is in cm not mm */
68 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
69 /* Detailed timing descriptors have bogus size values, so just take the
70  * maximum size and use that.
71  */
72 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
73 /* use +hsync +vsync for detailed mode */
74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
75 /* Force reduced-blanking timings for detailed modes */
76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
77 /* Force 8bpc */
78 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
79 /* Force 12bpc */
80 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
81 /* Force 6bpc */
82 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
83 /* Force 10bpc */
84 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
85 /* Non desktop display (i.e. HMD) */
86 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
87 
88 struct detailed_mode_closure {
89     struct drm_connector *connector;
90     struct edid *edid;
91     bool preferred;
92     u32 quirks;
93     int modes;
94 };
95 
96 #define LEVEL_DMT 0
97 #define LEVEL_GTF 1
98 #define LEVEL_GTF2 2
99 #define LEVEL_CVT 3
100 
101 static const struct edid_quirk {
102     char vendor[4];
103     int product_id;
104     u32 quirks;
105 } edid_quirk_list[] = {
106     /* Acer AL1706 */
107     {"ACR", 44358, EDID_QUIRK_PREFER_LARGE_60},
108     /* Acer F51 */
109     {"API", 0x7602, EDID_QUIRK_PREFER_LARGE_60},
110 
111     /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
112     {"AEO", 0, EDID_QUIRK_FORCE_6BPC},
113 
114     /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
115     {"BOE", 0x78b, EDID_QUIRK_FORCE_6BPC},
116 
117     /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
118     {"CPT", 0x17df, EDID_QUIRK_FORCE_6BPC},
119 
120     /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
121     {"SDC", 0x3652, EDID_QUIRK_FORCE_6BPC},
122 
123     /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
124     {"BOE", 0x0771, EDID_QUIRK_FORCE_6BPC},
125 
126     /* Belinea 10 15 55 */
127     {"MAX", 1516, EDID_QUIRK_PREFER_LARGE_60},
128     {"MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60},
129 
130     /* Envision Peripherals, Inc. EN-7100e */
131     {"EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH},
132     /* Envision EN2028 */
133     {"EPI", 8232, EDID_QUIRK_PREFER_LARGE_60},
134 
135     /* Funai Electronics PM36B */
136     {"FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | EDID_QUIRK_DETAILED_IN_CM},
137 
138     /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
139     {"LGD", 764, EDID_QUIRK_FORCE_10BPC},
140 
141     /* LG Philips LCD LP154W01-A5 */
142     {"LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE},
143     {"LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE},
144 
145     /* Samsung SyncMaster 205BW.  Note: irony */
146     {"SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP},
147     /* Samsung SyncMaster 22[5-6]BW */
148     {"SAM", 596, EDID_QUIRK_PREFER_LARGE_60},
149     {"SAM", 638, EDID_QUIRK_PREFER_LARGE_60},
150 
151     /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
152     {"SNY", 0x2541, EDID_QUIRK_FORCE_12BPC},
153 
154     /* ViewSonic VA2026w */
155     {"VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING},
156 
157     /* Medion MD 30217 PG */
158     {"MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75},
159 
160     /* Lenovo G50 */
161     {"SDC", 18514, EDID_QUIRK_FORCE_6BPC},
162 
163     /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
164     {"SEC", 0xd033, EDID_QUIRK_FORCE_8BPC},
165 
166     /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1 */
167     {"ETR", 13896, EDID_QUIRK_FORCE_8BPC},
168 
169     /* Valve Index Headset */
170     {"VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP},
171     {"VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP},
172     {"VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP},
173     {"VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP},
174     {"VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP},
175     {"VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP},
176     {"VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP},
177     {"VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP},
178     {"VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP},
179     {"VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP},
180     {"VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP},
181     {"VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP},
182     {"VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP},
183     {"VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP},
184     {"VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP},
185     {"VLV", 0x91be, EDID_QUIRK_NON_DESKTOP},
186     {"VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP},
187 
188     /* HTC Vive and Vive Pro VR Headsets */
189     {"HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP},
190     {"HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP},
191 
192     /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
193     {"OVR", 0x0001, EDID_QUIRK_NON_DESKTOP},
194     {"OVR", 0x0003, EDID_QUIRK_NON_DESKTOP},
195     {"OVR", 0x0004, EDID_QUIRK_NON_DESKTOP},
196     {"OVR", 0x0012, EDID_QUIRK_NON_DESKTOP},
197 
198     /* Windows Mixed Reality Headsets */
199     {"ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP},
200     {"HPN", 0x3515, EDID_QUIRK_NON_DESKTOP},
201     {"LEN", 0x0408, EDID_QUIRK_NON_DESKTOP},
202     {"LEN", 0xb800, EDID_QUIRK_NON_DESKTOP},
203     {"FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP},
204     {"DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP},
205     {"SEC", 0x144a, EDID_QUIRK_NON_DESKTOP},
206     {"AUS", 0xc102, EDID_QUIRK_NON_DESKTOP},
207 
208     /* Sony PlayStation VR Headset */
209     {"SNY", 0x0704, EDID_QUIRK_NON_DESKTOP},
210 
211     /* Sensics VR Headsets */
212     {"SEN", 0x1019, EDID_QUIRK_NON_DESKTOP},
213 
214     /* OSVR HDK and HDK2 VR Headsets */
215     {"SVR", 0x1019, EDID_QUIRK_NON_DESKTOP},
216 };
217 
218 /*
219  * Autogenerated from the DMT spec.
220  * This table is copied from xfree86/modes/xf86EdidModes.c.
221  */
222 static const struct drm_display_mode drm_dmt_modes[] = {
223     /* 0x01 - 640x350@85Hz */
224     {DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 736, 832, 0, 350, 382, 385, 445, 0,
225               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
226     /* 0x02 - 640x400@85Hz */
227     {DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 736, 832, 0, 400, 401, 404, 445, 0,
228               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
229     /* 0x03 - 720x400@85Hz */
230     {DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 828, 936, 0, 400, 401, 404, 446, 0,
231               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
232     /* 0x04 - 640x480@60Hz */
233     {DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 752, 800, 0, 480, 490, 492, 525, 0,
234               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
235     /* 0x05 - 640x480@72Hz */
236     {DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 704, 832, 0, 480, 489, 492, 520, 0,
237               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
238     /* 0x06 - 640x480@75Hz */
239     {DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 720, 840, 0, 480, 481, 484, 500, 0,
240               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
241     /* 0x07 - 640x480@85Hz */
242     {DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 752, 832, 0, 480, 481, 484, 509, 0,
243               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
244     /* 0x08 - 800x600@56Hz */
245     {DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 896, 1024, 0, 600, 601, 603, 625, 0,
246               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
247     /* 0x09 - 800x600@60Hz */
248     {DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 968, 1056, 0, 600, 601, 605, 628, 0,
249               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
250     /* 0x0a - 800x600@72Hz */
251     {DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 976, 1040, 0, 600, 637, 643, 666, 0,
252               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
253     /* 0x0b - 800x600@75Hz */
254     {DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 896, 1056, 0, 600, 601, 604, 625, 0,
255               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
256     /* 0x0c - 800x600@85Hz */
257     {DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 896, 1048, 0, 600, 601, 604, 631, 0,
258               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
259     /* 0x0d - 800x600@120Hz RB */
260     {DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 880, 960, 0, 600, 603, 607, 636, 0,
261               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
262     /* 0x0e - 848x480@60Hz */
263     {DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 976, 1088, 0, 480, 486, 494, 517, 0,
264               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
265     /* 0x0f - 1024x768@43Hz, interlace */
266     {DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1208, 1264, 0, 768, 768, 776, 817, 0,
267               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE)},
268     /* 0x10 - 1024x768@60Hz */
269     {DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1184, 1344, 0, 768, 771, 777, 806, 0,
270               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
271     /* 0x11 - 1024x768@70Hz */
272     {DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1184, 1328, 0, 768, 771, 777, 806, 0,
273               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
274     /* 0x12 - 1024x768@75Hz */
275     {DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1136, 1312, 0, 768, 769, 772, 800, 0,
276               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
277     /* 0x13 - 1024x768@85Hz */
278     {DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 1168, 1376, 0, 768, 769, 772, 808, 0,
279               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
280     /* 0x14 - 1024x768@120Hz RB */
281     {DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 1104, 1184, 0, 768, 771, 775, 813, 0,
282               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
283     /* 0x15 - 1152x864@75Hz */
284     {DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1344, 1600, 0, 864, 865, 868, 900, 0,
285               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
286     /* 0x55 - 1280x720@60Hz */
287     {DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1430, 1650, 0, 720, 725, 730, 750, 0,
288               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
289     /* 0x16 - 1280x768@60Hz RB */
290     {DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 1360, 1440, 0, 768, 771, 778, 790, 0,
291               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
292     /* 0x17 - 1280x768@60Hz */
293     {DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 1472, 1664, 0, 768, 771, 778, 798, 0,
294               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
295     /* 0x18 - 1280x768@75Hz */
296     {DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 1488, 1696, 0, 768, 771, 778, 805, 0,
297               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
298     /* 0x19 - 1280x768@85Hz */
299     {DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 1496, 1712, 0, 768, 771, 778, 809, 0,
300               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
301     /* 0x1a - 1280x768@120Hz RB */
302     {DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 1360, 1440, 0, 768, 771, 778, 813, 0,
303               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
304     /* 0x1b - 1280x800@60Hz RB */
305     {DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 1360, 1440, 0, 800, 803, 809, 823, 0,
306               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
307     /* 0x1c - 1280x800@60Hz */
308     {DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 1480, 1680, 0, 800, 803, 809, 831, 0,
309               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
310     /* 0x1d - 1280x800@75Hz */
311     {DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 1488, 1696, 0, 800, 803, 809, 838, 0,
312               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
313     /* 0x1e - 1280x800@85Hz */
314     {DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 1496, 1712, 0, 800, 803, 809, 843, 0,
315               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
316     /* 0x1f - 1280x800@120Hz RB */
317     {DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 1360, 1440, 0, 800, 803, 809, 847, 0,
318               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
319     /* 0x20 - 1280x960@60Hz */
320     {DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 1488, 1800, 0, 960, 961, 964, 1000, 0,
321               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
322     /* 0x21 - 1280x960@85Hz */
323     {DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 1504, 1728, 0, 960, 961, 964, 1011, 0,
324               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
325     /* 0x22 - 1280x960@120Hz RB */
326     {DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 1360, 1440, 0, 960, 963, 967, 1017, 0,
327               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
328     /* 0x23 - 1280x1024@60Hz */
329     {DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
330               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
331     /* 0x24 - 1280x1024@75Hz */
332     {DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
333               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
334     /* 0x25 - 1280x1024@85Hz */
335     {DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
336               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
337     /* 0x26 - 1280x1024@120Hz RB */
338     {DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
339               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
340     /* 0x27 - 1360x768@60Hz */
341     {DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 1536, 1792, 0, 768, 771, 777, 795, 0,
342               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
343     /* 0x28 - 1360x768@120Hz RB */
344     {DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 1440, 1520, 0, 768, 771, 776, 813, 0,
345               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
346     /* 0x51 - 1366x768@60Hz */
347     {DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 1579, 1792, 0, 768, 771, 774, 798, 0,
348               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
349     /* 0x56 - 1366x768@60Hz */
350     {DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 1436, 1500, 0, 768, 769, 772, 800, 0,
351               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
352     /* 0x29 - 1400x1050@60Hz RB */
353     {DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
354               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
355     /* 0x2a - 1400x1050@60Hz */
356     {DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
357               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
358     /* 0x2b - 1400x1050@75Hz */
359     {DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
360               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
361     /* 0x2c - 1400x1050@85Hz */
362     {DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
363               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
364     /* 0x2d - 1400x1050@120Hz RB */
365     {DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
366               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
367     /* 0x2e - 1440x900@60Hz RB */
368     {DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 1520, 1600, 0, 900, 903, 909, 926, 0,
369               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
370     /* 0x2f - 1440x900@60Hz */
371     {DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 1672, 1904, 0, 900, 903, 909, 934, 0,
372               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
373     /* 0x30 - 1440x900@75Hz */
374     {DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 1688, 1936, 0, 900, 903, 909, 942, 0,
375               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
376     /* 0x31 - 1440x900@85Hz */
377     {DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 1696, 1952, 0, 900, 903, 909, 948, 0,
378               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
379     /* 0x32 - 1440x900@120Hz RB */
380     {DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 1520, 1600, 0, 900, 903, 909, 953, 0,
381               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
382     /* 0x53 - 1600x900@60Hz */
383     {DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 1704, 1800, 0, 900, 901, 904, 1000, 0,
384               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
385     /* 0x33 - 1600x1200@60Hz */
386     {DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
387               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
388     /* 0x34 - 1600x1200@65Hz */
389     {DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
390               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
391     /* 0x35 - 1600x1200@70Hz */
392     {DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
393               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
394     /* 0x36 - 1600x1200@75Hz */
395     {DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
396               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
397     /* 0x37 - 1600x1200@85Hz */
398     {DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
399               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
400     /* 0x38 - 1600x1200@120Hz RB */
401     {DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
402               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
403     /* 0x39 - 1680x1050@60Hz RB */
404     {DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
405               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
406     /* 0x3a - 1680x1050@60Hz */
407     {DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
408               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
409     /* 0x3b - 1680x1050@75Hz */
410     {DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
411               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
412     /* 0x3c - 1680x1050@85Hz */
413     {DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
414               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
415     /* 0x3d - 1680x1050@120Hz RB */
416     {DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
417               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
418     /* 0x3e - 1792x1344@60Hz */
419     {DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
420               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
421     /* 0x3f - 1792x1344@75Hz */
422     {DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
423               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
424     /* 0x40 - 1792x1344@120Hz RB */
425     {DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
426               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
427     /* 0x41 - 1856x1392@60Hz */
428     {DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
429               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
430     /* 0x42 - 1856x1392@75Hz */
431     {DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
432               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
433     /* 0x43 - 1856x1392@120Hz RB */
434     {DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
435               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
436     /* 0x52 - 1920x1080@60Hz */
437     {DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
438               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
439     /* 0x44 - 1920x1200@60Hz RB */
440     {DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
441               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
442     /* 0x45 - 1920x1200@60Hz */
443     {DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
444               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
445     /* 0x46 - 1920x1200@75Hz */
446     {DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
447               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
448     /* 0x47 - 1920x1200@85Hz */
449     {DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
450               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
451     /* 0x48 - 1920x1200@120Hz RB */
452     {DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
453               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
454     /* 0x49 - 1920x1440@60Hz */
455     {DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
456               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
457     /* 0x4a - 1920x1440@75Hz */
458     {DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
459               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
460     /* 0x4b - 1920x1440@120Hz RB */
461     {DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
462               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
463     /* 0x54 - 2048x1152@60Hz */
464     {DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
465               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
466     /* 0x4c - 2560x1600@60Hz RB */
467     {DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
468               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
469     /* 0x4d - 2560x1600@60Hz */
470     {DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
471               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
472     /* 0x4e - 2560x1600@75Hz */
473     {DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
474               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
475     /* 0x4f - 2560x1600@85Hz */
476     {DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
477               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)},
478     /* 0x50 - 2560x1600@120Hz RB */
479     {DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
480               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
481     /* 0x57 - 4096x2160@60Hz RB */
482     {DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
483               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
484     /* 0x58 - 4096x2160@59.94Hz RB */
485     {DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
486               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC)},
487 };
488 
489 /*
490  * These more or less come from the DMT spec.  The 720x400 modes are
491  * inferred from historical 80x25 practice.  The 640x480@67 and 832x624@75
492  * modes are old-school Mac modes.  The EDID spec says the 1152x864@75 mode
493  * should be 1152x870, again for the Mac, but instead we use the x864 DMT
494  * mode.
495  *
496  * The DMT modes have been fact-checked; the rest are mild guesses.
497  */
498 static const struct drm_display_mode edid_est_modes[] = {
499     {DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 968, 1056, 0, 600, 601, 605, 628, 0,
500               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, /* 800x600@60Hz */
501     {DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 896, 1024, 0, 600, 601, 603, 625, 0,
502               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, /* 800x600@56Hz */
503     {DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 720, 840, 0, 480, 481, 484, 500, 0,
504               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)}, /* 640x480@75Hz */
505     {DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 704, 832, 0, 480, 489, 492, 520, 0,
506               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)}, /* 640x480@72Hz */
507     {DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 768, 864, 0, 480, 483, 486, 525, 0,
508               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)}, /* 640x480@67Hz */
509     {DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 752, 800, 0, 480, 490, 492, 525, 0,
510               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)}, /* 640x480@60Hz */
511     {DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 846, 900, 0, 400, 421, 423, 449, 0,
512               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)}, /* 720x400@88Hz */
513     {DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 846, 900, 0, 400, 412, 414, 449, 0,
514               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)}, /* 720x400@70Hz */
515     {DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
516               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, /* 1280x1024@75Hz */
517     {DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1136, 1312, 0, 768, 769, 772, 800, 0,
518               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, /* 1024x768@75Hz */
519     {DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1184, 1328, 0, 768, 771, 777, 806, 0,
520               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)}, /* 1024x768@70Hz */
521     {DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1184, 1344, 0, 768, 771, 777, 806, 0,
522               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)}, /* 1024x768@60Hz */
523     {DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1208, 1264, 0, 768, 768, 776, 817, 0,
524               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE)}, /* 1024x768@43Hz */
525     {DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 928, 1152, 0, 624, 625, 628, 667, 0,
526               DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)}, /* 832x624@75Hz */
527     {DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 896, 1056, 0, 600, 601, 604, 625, 0,
528               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, /* 800x600@75Hz */
529     {DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 976, 1040, 0, 600, 637, 643, 666, 0,
530               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, /* 800x600@72Hz */
531     {DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1344, 1600, 0, 864, 865, 868, 900, 0,
532               DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, /* 1152x864@75Hz */
533 };
534 
535 struct minimode {
536     short w;
537     short h;
538     short r;
539     short rb;
540 };
541 
542 static const struct minimode est3_modes[] = {
543     /* byte 6 */
544     {640, 350, 85, 0},
545     {640, 400, 85, 0},
546     {720, 400, 85, 0},
547     {640, 480, 85, 0},
548     {848, 480, 60, 0},
549     {800, 600, 85, 0},
550     {1024, 768, 85, 0},
551     {1152, 864, 75, 0},
552     /* byte 7 */
553     {1280, 768, 60, 1},
554     {1280, 768, 60, 0},
555     {1280, 768, 75, 0},
556     {1280, 768, 85, 0},
557     {1280, 960, 60, 0},
558     {1280, 960, 85, 0},
559     {1280, 1024, 60, 0},
560     {1280, 1024, 85, 0},
561     /* byte 8 */
562     {1360, 768, 60, 0},
563     {1440, 900, 60, 1},
564     {1440, 900, 60, 0},
565     {1440, 900, 75, 0},
566     {1440, 900, 85, 0},
567     {1400, 1050, 60, 1},
568     {1400, 1050, 60, 0},
569     {1400, 1050, 75, 0},
570     /* byte 9 */
571     {1400, 1050, 85, 0},
572     {1680, 1050, 60, 1},
573     {1680, 1050, 60, 0},
574     {1680, 1050, 75, 0},
575     {1680, 1050, 85, 0},
576     {1600, 1200, 60, 0},
577     {1600, 1200, 65, 0},
578     {1600, 1200, 70, 0},
579     /* byte 10 */
580     {1600, 1200, 75, 0},
581     {1600, 1200, 85, 0},
582     {1792, 1344, 60, 0},
583     {1792, 1344, 75, 0},
584     {1856, 1392, 60, 0},
585     {1856, 1392, 75, 0},
586     {1920, 1200, 60, 1},
587     {1920, 1200, 60, 0},
588     /* byte 11 */
589     {1920, 1200, 75, 0},
590     {1920, 1200, 85, 0},
591     {1920, 1440, 60, 0},
592     {1920, 1440, 75, 0},
593 };
594 
595 static const struct minimode extra_modes[] = {
596     {1024, 576, 60, 0},  {1366, 768, 60, 0},  {1600, 900, 60, 0},  {1680, 945, 60, 0},
597     {1920, 1080, 60, 0}, {2048, 1152, 60, 0}, {2048, 1536, 60, 0},
598 };
599 
600 /*
601  * From CEA/CTA-861 spec.
602  *
603  * Do not access directly, instead always use cea_mode_for_vic().
604  */
605 static const struct drm_display_mode edid_cea_modes_1[] = {
606     /* 1 - 640x480@60Hz 4:3 */
607     {
608         DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 752, 800, 0, 480, 490, 492, 525, 0,
609                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
610         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
611     },
612     /* 2 - 720x480@60Hz 4:3 */
613     {
614         DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 798, 858, 0, 480, 489, 495, 525, 0,
615                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
616         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
617     },
618     /* 3 - 720x480@60Hz 16:9 */
619     {
620         DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 798, 858, 0, 480, 489, 495, 525, 0,
621                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
622         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
623     },
624     /* 4 - 1280x720@60Hz 16:9 */
625     {
626         DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1430, 1650, 0, 720, 725, 730, 750, 0,
627                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
628         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
629     },
630     /* 5 - 1920x1080i@60Hz 16:9 */
631     {
632         DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
633                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE),
634         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
635     },
636     /* 6 - 720(1440)x480i@60Hz 4:3 */
637     {
638         DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 801, 858, 0, 480, 488, 494, 525, 0,
639                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
640         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
641     },
642     /* 7 - 720(1440)x480i@60Hz 16:9 */
643     {
644         DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 801, 858, 0, 480, 488, 494, 525, 0,
645                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
646         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
647     },
648     /* 8 - 720(1440)x240@60Hz 4:3 */
649     {
650         DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 801, 858, 0, 240, 244, 247, 262, 0,
651                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_DBLCLK),
652         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
653     },
654     /* 9 - 720(1440)x240@60Hz 16:9 */
655     {
656         DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 801, 858, 0, 240, 244, 247, 262, 0,
657                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_DBLCLK),
658         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
659     },
660     /* 10 - 2880x480i@60Hz 4:3 */
661     {
662         DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 3204, 3432, 0, 480, 488, 494, 525, 0,
663                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE),
664         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
665     },
666     /* 11 - 2880x480i@60Hz 16:9 */
667     {
668         DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 3204, 3432, 0, 480, 488, 494, 525, 0,
669                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE),
670         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
671     },
672     /* 12 - 2880x240@60Hz 4:3 */
673     {
674         DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 3204, 3432, 0, 240, 244, 247, 262, 0,
675                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
676         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
677     },
678     /* 13 - 2880x240@60Hz 16:9 */
679     {
680         DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 3204, 3432, 0, 240, 244, 247, 262, 0,
681                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
682         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
683     },
684     /* 14 - 1440x480@60Hz 4:3 */
685     {
686         DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 1596, 1716, 0, 480, 489, 495, 525, 0,
687                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
688         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
689     },
690     /* 15 - 1440x480@60Hz 16:9 */
691     {
692         DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 1596, 1716, 0, 480, 489, 495, 525, 0,
693                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
694         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
695     },
696     /* 16 - 1920x1080@60Hz 16:9 */
697     {
698         DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
699                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
700         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
701     },
702     /* 17 - 720x576@50Hz 4:3 */
703     {
704         DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 796, 864, 0, 576, 581, 586, 625, 0,
705                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
706         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
707     },
708     /* 18 - 720x576@50Hz 16:9 */
709     {
710         DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 796, 864, 0, 576, 581, 586, 625, 0,
711                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
712         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
713     },
714     /* 19 - 1280x720@50Hz 16:9 */
715     {
716         DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1760, 1980, 0, 720, 725, 730, 750, 0,
717                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
718         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
719     },
720     /* 20 - 1920x1080i@50Hz 16:9 */
721     {
722         DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
723                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE),
724         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
725     },
726     /* 21 - 720(1440)x576i@50Hz 4:3 */
727     {
728         DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 795, 864, 0, 576, 580, 586, 625, 0,
729                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
730         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
731     },
732     /* 22 - 720(1440)x576i@50Hz 16:9 */
733     {
734         DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 795, 864, 0, 576, 580, 586, 625, 0,
735                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
736         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
737     },
738     /* 23 - 720(1440)x288@50Hz 4:3 */
739     {
740         DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 795, 864, 0, 288, 290, 293, 312, 0,
741                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_DBLCLK),
742         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
743     },
744     /* 24 - 720(1440)x288@50Hz 16:9 */
745     {
746         DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 795, 864, 0, 288, 290, 293, 312, 0,
747                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_DBLCLK),
748         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
749     },
750     /* 25 - 2880x576i@50Hz 4:3 */
751     {
752         DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 3180, 3456, 0, 576, 580, 586, 625, 0,
753                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE),
754         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
755     },
756     /* 26 - 2880x576i@50Hz 16:9 */
757     {
758         DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 3180, 3456, 0, 576, 580, 586, 625, 0,
759                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE),
760         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
761     },
762     /* 27 - 2880x288@50Hz 4:3 */
763     {
764         DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 3180, 3456, 0, 288, 290, 293, 312, 0,
765                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
766         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
767     },
768     /* 28 - 2880x288@50Hz 16:9 */
769     {
770         DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 3180, 3456, 0, 288, 290, 293, 312, 0,
771                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
772         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
773     },
774     /* 29 - 1440x576@50Hz 4:3 */
775     {
776         DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 1592, 1728, 0, 576, 581, 586, 625, 0,
777                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
778         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
779     },
780     /* 30 - 1440x576@50Hz 16:9 */
781     {
782         DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 1592, 1728, 0, 576, 581, 586, 625, 0,
783                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
784         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
785     },
786     /* 31 - 1920x1080@50Hz 16:9 */
787     {
788         DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
789                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
790         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
791     },
792     /* 32 - 1920x1080@24Hz 16:9 */
793     {
794         DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
795                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
796         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
797     },
798     /* 33 - 1920x1080@25Hz 16:9 */
799     {
800         DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
801                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
802         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
803     },
804     /* 34 - 1920x1080@30Hz 16:9 */
805     {
806         DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
807                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
808         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
809     },
810     /* 35 - 2880x480@60Hz 4:3 */
811     {
812         DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 3192, 3432, 0, 480, 489, 495, 525, 0,
813                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
814         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
815     },
816     /* 36 - 2880x480@60Hz 16:9 */
817     {
818         DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 3192, 3432, 0, 480, 489, 495, 525, 0,
819                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
820         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
821     },
822     /* 37 - 2880x576@50Hz 4:3 */
823     {
824         DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 3184, 3456, 0, 576, 581, 586, 625, 0,
825                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
826         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
827     },
828     /* 38 - 2880x576@50Hz 16:9 */
829     {
830         DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 3184, 3456, 0, 576, 581, 586, 625, 0,
831                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
832         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
833     },
834     /* 39 - 1920x1080i@50Hz 16:9 */
835     {
836         DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
837                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE),
838         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
839     },
840     /* 40 - 1920x1080i@100Hz 16:9 */
841     {
842         DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
843                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE),
844         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
845     },
846     /* 41 - 1280x720@100Hz 16:9 */
847     {
848         DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1760, 1980, 0, 720, 725, 730, 750, 0,
849                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
850         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
851     },
852     /* 42 - 720x576@100Hz 4:3 */
853     {
854         DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 796, 864, 0, 576, 581, 586, 625, 0,
855                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
856         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
857     },
858     /* 43 - 720x576@100Hz 16:9 */
859     {
860         DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 796, 864, 0, 576, 581, 586, 625, 0,
861                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
862         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
863     },
864     /* 44 - 720(1440)x576i@100Hz 4:3 */
865     {
866         DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 795, 864, 0, 576, 580, 586, 625, 0,
867                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
868         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
869     },
870     /* 45 - 720(1440)x576i@100Hz 16:9 */
871     {
872         DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 795, 864, 0, 576, 580, 586, 625, 0,
873                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
874         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
875     },
876     /* 46 - 1920x1080i@120Hz 16:9 */
877     {
878         DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
879                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE),
880         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
881     },
882     /* 47 - 1280x720@120Hz 16:9 */
883     {
884         DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1430, 1650, 0, 720, 725, 730, 750, 0,
885                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
886         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
887     },
888     /* 48 - 720x480@120Hz 4:3 */
889     {
890         DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 798, 858, 0, 480, 489, 495, 525, 0,
891                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
892         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
893     },
894     /* 49 - 720x480@120Hz 16:9 */
895     {
896         DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 798, 858, 0, 480, 489, 495, 525, 0,
897                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
898         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
899     },
900     /* 50 - 720(1440)x480i@120Hz 4:3 */
901     {
902         DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 801, 858, 0, 480, 488, 494, 525, 0,
903                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
904         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
905     },
906     /* 51 - 720(1440)x480i@120Hz 16:9 */
907     {
908         DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 801, 858, 0, 480, 488, 494, 525, 0,
909                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
910         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
911     },
912     /* 52 - 720x576@200Hz 4:3 */
913     {
914         DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 796, 864, 0, 576, 581, 586, 625, 0,
915                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
916         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
917     },
918     /* 53 - 720x576@200Hz 16:9 */
919     {
920         DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 796, 864, 0, 576, 581, 586, 625, 0,
921                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
922         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
923     },
924     /* 54 - 720(1440)x576i@200Hz 4:3 */
925     {
926         DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 795, 864, 0, 576, 580, 586, 625, 0,
927                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
928         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
929     },
930     /* 55 - 720(1440)x576i@200Hz 16:9 */
931     {
932         DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 795, 864, 0, 576, 580, 586, 625, 0,
933                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
934         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
935     },
936     /* 56 - 720x480@240Hz 4:3 */
937     {
938         DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 798, 858, 0, 480, 489, 495, 525, 0,
939                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
940         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
941     },
942     /* 57 - 720x480@240Hz 16:9 */
943     {
944         DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 798, 858, 0, 480, 489, 495, 525, 0,
945                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
946         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
947     },
948     /* 58 - 720(1440)x480i@240Hz 4:3 */
949     {
950         DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 801, 858, 0, 480, 488, 494, 525, 0,
951                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
952         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
953     },
954     /* 59 - 720(1440)x480i@240Hz 16:9 */
955     {
956         DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 801, 858, 0, 480, 488, 494, 525, 0,
957                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
958         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
959     },
960     /* 60 - 1280x720@24Hz 16:9 */
961     {
962         DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 3080, 3300, 0, 720, 725, 730, 750, 0,
963                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
964         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
965     },
966     /* 61 - 1280x720@25Hz 16:9 */
967     {
968         DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 3740, 3960, 0, 720, 725, 730, 750, 0,
969                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
970         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
971     },
972     /* 62 - 1280x720@30Hz 16:9 */
973     {
974         DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 3080, 3300, 0, 720, 725, 730, 750, 0,
975                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
976         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
977     },
978     /* 63 - 1920x1080@120Hz 16:9 */
979     {
980         DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
981                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
982         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
983     },
984     /* 64 - 1920x1080@100Hz 16:9 */
985     {
986         DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
987                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
988         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
989     },
990     /* 65 - 1280x720@24Hz 64:27 */
991     {
992         DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 3080, 3300, 0, 720, 725, 730, 750, 0,
993                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
994         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
995     },
996     /* 66 - 1280x720@25Hz 64:27 */
997     {
998         DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 3740, 3960, 0, 720, 725, 730, 750, 0,
999                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1000         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1001     },
1002     /* 67 - 1280x720@30Hz 64:27 */
1003     {
1004         DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 3080, 3300, 0, 720, 725, 730, 750, 0,
1005                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1006         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1007     },
1008     /* 68 - 1280x720@50Hz 64:27 */
1009     {
1010         DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1760, 1980, 0, 720, 725, 730, 750, 0,
1011                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1012         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1013     },
1014     /* 69 - 1280x720@60Hz 64:27 */
1015     {
1016         DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1430, 1650, 0, 720, 725, 730, 750, 0,
1017                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1018         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1019     },
1020     /* 70 - 1280x720@100Hz 64:27 */
1021     {
1022         DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1760, 1980, 0, 720, 725, 730, 750, 0,
1023                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1024         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1025     },
1026     /* 71 - 1280x720@120Hz 64:27 */
1027     {
1028         DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1430, 1650, 0, 720, 725, 730, 750, 0,
1029                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1030         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1031     },
1032     /* 72 - 1920x1080@24Hz 64:27 */
1033     {
1034         DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1035                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1036         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1037     },
1038     /* 73 - 1920x1080@25Hz 64:27 */
1039     {
1040         DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1041                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1042         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1043     },
1044     /* 74 - 1920x1080@30Hz 64:27 */
1045     {
1046         DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1047                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1048         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1049     },
1050     /* 75 - 1920x1080@50Hz 64:27 */
1051     {
1052         DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1053                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1054         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1055     },
1056     /* 76 - 1920x1080@60Hz 64:27 */
1057     {
1058         DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1059                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1060         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1061     },
1062     /* 77 - 1920x1080@100Hz 64:27 */
1063     {
1064         DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1065                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1066         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1067     },
1068     /* 78 - 1920x1080@120Hz 64:27 */
1069     {
1070         DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1071                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1072         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1073     },
1074     /* 79 - 1680x720@24Hz 64:27 */
1075     {
1076         DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 3080, 3300, 0, 720, 725, 730, 750, 0,
1077                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1079     },
1080     /* 80 - 1680x720@25Hz 64:27 */
1081     {
1082         DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 2948, 3168, 0, 720, 725, 730, 750, 0,
1083                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1084         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1085     },
1086     /* 81 - 1680x720@30Hz 64:27 */
1087     {
1088         DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 2420, 2640, 0, 720, 725, 730, 750, 0,
1089                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1090         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1091     },
1092     /* 82 - 1680x720@50Hz 64:27 */
1093     {
1094         DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1980, 2200, 0, 720, 725, 730, 750, 0,
1095                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1096         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1097     },
1098     /* 83 - 1680x720@60Hz 64:27 */
1099     {
1100         DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1980, 2200, 0, 720, 725, 730, 750, 0,
1101                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1102         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1103     },
1104     /* 84 - 1680x720@100Hz 64:27 */
1105     {
1106         DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1780, 2000, 0, 720, 725, 730, 825, 0,
1107                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1109     },
1110     /* 85 - 1680x720@120Hz 64:27 */
1111     {
1112         DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1780, 2000, 0, 720, 725, 730, 825, 0,
1113                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1114         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1115     },
1116     /* 86 - 2560x1080@24Hz 64:27 */
1117     {
1118         DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1119                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1120         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1121     },
1122     /* 87 - 2560x1080@25Hz 64:27 */
1123     {
1124         DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1125                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1126         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1127     },
1128     /* 88 - 2560x1080@30Hz 64:27 */
1129     {
1130         DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1131                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1132         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1133     },
1134     /* 89 - 2560x1080@50Hz 64:27 */
1135     {
1136         DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1137                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1139     },
1140     /* 90 - 2560x1080@60Hz 64:27 */
1141     {
1142         DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1143                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1144         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1145     },
1146     /* 91 - 2560x1080@100Hz 64:27 */
1147     {
1148         DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1149                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1150         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1151     },
1152     /* 92 - 2560x1080@120Hz 64:27 */
1153     {
1154         DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1155                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1156         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1157     },
1158     /* 93 - 3840x2160@24Hz 16:9 */
1159     {
1160         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1161                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1162         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1163     },
1164     /* 94 - 3840x2160@25Hz 16:9 */
1165     {
1166         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1167                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1169     },
1170     /* 95 - 3840x2160@30Hz 16:9 */
1171     {
1172         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1173                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1174         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1175     },
1176     /* 96 - 3840x2160@50Hz 16:9 */
1177     {
1178         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1179                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1180         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1181     },
1182     /* 97 - 3840x2160@60Hz 16:9 */
1183     {
1184         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1185                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1186         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1187     },
1188     /* 98 - 4096x2160@24Hz 256:135 */
1189     {
1190         DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1191                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1192         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135,
1193     },
1194     /* 99 - 4096x2160@25Hz 256:135 */
1195     {
1196         DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1197                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135,
1199     },
1200     /* 100 - 4096x2160@30Hz 256:135 */
1201     {
1202         DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1203                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1204         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135,
1205     },
1206     /* 101 - 4096x2160@50Hz 256:135 */
1207     {
1208         DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1209                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1210         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135,
1211     },
1212     /* 102 - 4096x2160@60Hz 256:135 */
1213     {
1214         DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1215                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1216         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135,
1217     },
1218     /* 103 - 3840x2160@24Hz 64:27 */
1219     {
1220         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1221                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1222         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1223     },
1224     /* 104 - 3840x2160@25Hz 64:27 */
1225     {
1226         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1227                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1228         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1229     },
1230     /* 105 - 3840x2160@30Hz 64:27 */
1231     {
1232         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1233                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1235     },
1236     /* 106 - 3840x2160@50Hz 64:27 */
1237     {
1238         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1239                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1240         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1241     },
1242     /* 107 - 3840x2160@60Hz 64:27 */
1243     {
1244         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1245                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1246         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1247     },
1248     /* 108 - 1280x720@48Hz 16:9 */
1249     {
1250         DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 2280, 2500, 0, 720, 725, 730, 750, 0,
1251                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1252         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1253     },
1254     /* 109 - 1280x720@48Hz 64:27 */
1255     {
1256         DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 2280, 2500, 0, 720, 725, 730, 750, 0,
1257                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1258         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1259     },
1260     /* 110 - 1680x720@48Hz 64:27 */
1261     {
1262         DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 2530, 2750, 0, 720, 725, 730, 750, 0,
1263                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1264         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1265     },
1266     /* 111 - 1920x1080@48Hz 16:9 */
1267     {
1268         DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1269                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1270         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1271     },
1272     /* 112 - 1920x1080@48Hz 64:27 */
1273     {
1274         DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1275                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1276         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1277     },
1278     /* 113 - 2560x1080@48Hz 64:27 */
1279     {
1280         DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1281                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1282         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1283     },
1284     /* 114 - 3840x2160@48Hz 16:9 */
1285     {
1286         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1287                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1288         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1289     },
1290     /* 115 - 4096x2160@48Hz 256:135 */
1291     {
1292         DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1293                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1294         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135,
1295     },
1296     /* 116 - 3840x2160@48Hz 64:27 */
1297     {
1298         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1299                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1300         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1301     },
1302     /* 117 - 3840x2160@100Hz 16:9 */
1303     {
1304         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1305                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1306         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1307     },
1308     /* 118 - 3840x2160@120Hz 16:9 */
1309     {
1310         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1311                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1312         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1313     },
1314     /* 119 - 3840x2160@100Hz 64:27 */
1315     {
1316         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1317                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1318         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1319     },
1320     /* 120 - 3840x2160@120Hz 64:27 */
1321     {
1322         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1323                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1324         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1325     },
1326     /* 121 - 5120x2160@24Hz 64:27 */
1327     {
1328         DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1329                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1330         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1331     },
1332     /* 122 - 5120x2160@25Hz 64:27 */
1333     {
1334         DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1335                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1336         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1337     },
1338     /* 123 - 5120x2160@30Hz 64:27 */
1339     {
1340         DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1341                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1342         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1343     },
1344     /* 124 - 5120x2160@48Hz 64:27 */
1345     {
1346         DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1347                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1348         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1349     },
1350     /* 125 - 5120x2160@50Hz 64:27 */
1351     {
1352         DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1353                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1354         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1355     },
1356     /* 126 - 5120x2160@60Hz 64:27 */
1357     {
1358         DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1359                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1360         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1361     },
1362     /* 127 - 5120x2160@100Hz 64:27 */
1363     {
1364         DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1365                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1366         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1367     },
1368 };
1369 
1370 /*
1371  * From CEA/CTA-861 spec.
1372  *
1373  * Do not access directly, instead always use cea_mode_for_vic().
1374  */
1375 static const struct drm_display_mode edid_cea_modes_193[] = {
1376     /* 193 - 5120x2160@120Hz 64:27 */
1377     {
1378         DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1379                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1380         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1381     },
1382     /* 194 - 7680x4320@24Hz 16:9 */
1383     {
1384         DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1385                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1386         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1387     },
1388     /* 195 - 7680x4320@25Hz 16:9 */
1389     {
1390         DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1391                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1392         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1393     },
1394     /* 196 - 7680x4320@30Hz 16:9 */
1395     {
1396         DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1397                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1398         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1399     },
1400     /* 197 - 7680x4320@48Hz 16:9 */
1401     {
1402         DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1403                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1404         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1405     },
1406     /* 198 - 7680x4320@50Hz 16:9 */
1407     {
1408         DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1409                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1410         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1411     },
1412     /* 199 - 7680x4320@60Hz 16:9 */
1413     {
1414         DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1415                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1416         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1417     },
1418     /* 200 - 7680x4320@100Hz 16:9 */
1419     {
1420         DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1421                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1422         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1423     },
1424     /* 201 - 7680x4320@120Hz 16:9 */
1425     {
1426         DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1427                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1428         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1429     },
1430     /* 202 - 7680x4320@24Hz 64:27 */
1431     {
1432         DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1433                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1434         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1435     },
1436     /* 203 - 7680x4320@25Hz 64:27 */
1437     {
1438         DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1439                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1440         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1441     },
1442     /* 204 - 7680x4320@30Hz 64:27 */
1443     {
1444         DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1445                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1446         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1447     },
1448     /* 205 - 7680x4320@48Hz 64:27 */
1449     {
1450         DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1451                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1452         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1453     },
1454     /* 206 - 7680x4320@50Hz 64:27 */
1455     {
1456         DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1457                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1458         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1459     },
1460     /* 207 - 7680x4320@60Hz 64:27 */
1461     {
1462         DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1463                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1464         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1465     },
1466     /* 208 - 7680x4320@100Hz 64:27 */
1467     {
1468         DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1469                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1470         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1471     },
1472     /* 209 - 7680x4320@120Hz 64:27 */
1473     {
1474         DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1475                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1476         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1477     },
1478     /* 210 - 10240x4320@24Hz 64:27 */
1479     {
1480         DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1481                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1482         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1483     },
1484     /* 211 - 10240x4320@25Hz 64:27 */
1485     {
1486         DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1487                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1488         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1489     },
1490     /* 212 - 10240x4320@30Hz 64:27 */
1491     {
1492         DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1493                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1494         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1495     },
1496     /* 213 - 10240x4320@48Hz 64:27 */
1497     {
1498         DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1499                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1500         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1501     },
1502     /* 214 - 10240x4320@50Hz 64:27 */
1503     {
1504         DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1505                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1506         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1507     },
1508     /* 215 - 10240x4320@60Hz 64:27 */
1509     {
1510         DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1511                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1512         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1513     },
1514     /* 216 - 10240x4320@100Hz 64:27 */
1515     {
1516         DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1517                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1518         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1519     },
1520     /* 217 - 10240x4320@120Hz 64:27 */
1521     {
1522         DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1523                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1524         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27,
1525     },
1526     /* 218 - 4096x2160@100Hz 256:135 */
1527     {
1528         DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1529                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1530         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135,
1531     },
1532     /* 219 - 4096x2160@120Hz 256:135 */
1533     {
1534         DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1535                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1536         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135,
1537     },
1538 };
1539 
1540 /*
1541  * HDMI 1.4 4k modes. Index using the VIC.
1542  */
1543 static const struct drm_display_mode edid_4k_modes[] = {
1544     /* 0 - dummy, VICs start at 1 */
1545     {},
1546     /* 1 - 3840x2160@30Hz */
1547     {
1548         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1549                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1550         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1551     },
1552     /* 2 - 3840x2160@25Hz */
1553     {
1554         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1555                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1556         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1557     },
1558     /* 3 - 3840x2160@24Hz */
1559     {
1560         DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1561                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1562         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
1563     },
1564     /* 4 - 4096x2160@24Hz (SMPTE) */
1565     {
1566         DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1567                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1568         .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135,
1569     },
1570 };
1571 
1572 /*** DDC fetch and block validation ***/
1573 
1574 static const u8 edid_header[] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00};
1575 
1576 /**
1577  * drm_edid_header_is_valid - sanity check the header of the base EDID block
1578  * @raw_edid: pointer to raw base EDID block
1579  *
1580  * Sanity check the header of the base EDID block.
1581  *
1582  * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1583  */
drm_edid_header_is_valid(const u8 * raw_edid)1584 int drm_edid_header_is_valid(const u8 *raw_edid)
1585 {
1586     int i, score = 0;
1587 
1588     for (i = 0; i < sizeof(edid_header); i++) {
1589         if (raw_edid[i] == edid_header[i]) {
1590             score++;
1591         }
1592     }
1593 
1594     return score;
1595 }
1596 EXPORT_SYMBOL(drm_edid_header_is_valid);
1597 
1598 static int edid_fixup __read_mostly = 0x6;
1599 module_param_named(edid_fixup, edid_fixup, int, 0x100);
1600 MODULE_PARM_DESC(edid_fixup, "Minimum number of valid EDID header bytes (0-8, default 6)");
1601 
1602 static int validate_displayid(u8 *displayid, int length, int idx);
1603 
drm_edid_block_checksum(const u8 * raw_edid)1604 static int drm_edid_block_checksum(const u8 *raw_edid)
1605 {
1606     int i;
1607     u8 csum = 0, crc = 0;
1608 
1609     for (i = 0; i < EDID_LENGTH - 1; i++) {
1610         csum += raw_edid[i];
1611     }
1612 
1613     crc = 0x100 - csum;
1614 
1615     return crc;
1616 }
1617 
drm_edid_block_checksum_diff(const u8 * raw_edid,u8 real_checksum)1618 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
1619 {
1620     if (raw_edid[EDID_LENGTH - 1] != real_checksum) {
1621         return true;
1622     } else {
1623         return false;
1624     }
1625 }
1626 
drm_edid_is_zero(const u8 * in_edid,int length)1627 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1628 {
1629     if (memchr_inv(in_edid, 0, length)) {
1630         return false;
1631     }
1632 
1633     return true;
1634 }
1635 
1636 /**
1637  * drm_edid_are_equal - compare two edid blobs.
1638  * @edid1: pointer to first blob
1639  * @edid2: pointer to second blob
1640  * This helper can be used during probing to determine if
1641  * edid had changed.
1642  */
drm_edid_are_equal(const struct edid * edid1,const struct edid * edid2)1643 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1644 {
1645     int edid1_len, edid2_len;
1646     bool edid1_present = edid1 != NULL;
1647     bool edid2_present = edid2 != NULL;
1648 
1649     if (edid1_present != edid2_present) {
1650         return false;
1651     }
1652 
1653     if (edid1) {
1654         edid1_len = EDID_LENGTH * (1 + edid1->extensions);
1655         edid2_len = EDID_LENGTH * (1 + edid2->extensions);
1656 
1657         if (edid1_len != edid2_len) {
1658             return false;
1659         }
1660 
1661         if (memcmp(edid1, edid2, edid1_len)) {
1662             return false;
1663         }
1664     }
1665 
1666     return true;
1667 }
1668 EXPORT_SYMBOL(drm_edid_are_equal);
1669 
1670 /**
1671  * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1672  * @raw_edid: pointer to raw EDID block
1673  * @block: type of block to validate (0 for base, extension otherwise)
1674  * @print_bad_edid: if true, dump bad EDID blocks to the console
1675  * @edid_corrupt: if true, the header or checksum is invalid
1676  *
1677  * Validate a base or extension EDID block and optionally dump bad blocks to
1678  * the console.
1679  *
1680  * Return: True if the block is valid, false otherwise.
1681  */
drm_edid_block_valid(u8 * raw_edid,int block,bool print_bad_edid,bool * edid_corrupt)1682 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, bool *edid_corrupt)
1683 {
1684     u8 csum;
1685     struct edid *edid = (struct edid *)raw_edid;
1686 
1687     if (WARN_ON(!raw_edid)) {
1688         return false;
1689     }
1690 
1691     if (edid_fixup > 0x8 || edid_fixup < 0) {
1692         edid_fixup = 0x6;
1693     }
1694 
1695     if (block == 0) {
1696         int score = drm_edid_header_is_valid(raw_edid);
1697         if (score == 0x8) {
1698             if (edid_corrupt) {
1699                 *edid_corrupt = false;
1700             }
1701         } else if (score >= edid_fixup) {
1702             /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1703              * The corrupt flag needs to be set here otherwise, the
1704              * fix-up code here will correct the problem, the
1705              * checksum is correct and the test fails
1706              */
1707             if (edid_corrupt) {
1708                 *edid_corrupt = true;
1709             }
1710             DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1711             memcpy(raw_edid, edid_header, sizeof(edid_header));
1712         } else {
1713             if (edid_corrupt) {
1714                 *edid_corrupt = true;
1715             }
1716             goto bad;
1717         }
1718     }
1719 
1720     csum = drm_edid_block_checksum(raw_edid);
1721     if (drm_edid_block_checksum_diff(raw_edid, csum)) {
1722         if (edid_corrupt) {
1723             *edid_corrupt = true;
1724         }
1725 
1726         /* allow CEA to slide through, switches mangle this */
1727         if (raw_edid[0] == CEA_EXT) {
1728             DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1729             DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1730         } else {
1731             if (print_bad_edid) {
1732                 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1733             }
1734 
1735             goto bad;
1736         }
1737     }
1738 
1739     /* per-block-type checks */
1740     switch (raw_edid[0]) {
1741         case 0: /* base */
1742             if (edid->version != 1) {
1743                 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1744                 goto bad;
1745             }
1746 
1747             if (edid->revision > 0x4) {
1748                 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1749             }
1750             break;
1751 
1752         default:
1753             break;
1754     }
1755 
1756     return true;
1757 
1758 bad:
1759     if (print_bad_edid) {
1760         if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1761             pr_notice("EDID block is all zeroes\n");
1762         } else {
1763             pr_notice("Raw EDID:\n");
1764             print_hex_dump(KERN_NOTICE, " \t", DUMP_PREFIX_NONE, 0x10, 1, raw_edid, EDID_LENGTH, false);
1765         }
1766     }
1767     return false;
1768 }
1769 EXPORT_SYMBOL(drm_edid_block_valid);
1770 
1771 /**
1772  * drm_edid_is_valid - sanity check EDID data
1773  * @edid: EDID data
1774  *
1775  * Sanity-check an entire EDID record (including extensions)
1776  *
1777  * Return: True if the EDID data is valid, false otherwise.
1778  */
drm_edid_is_valid(struct edid * edid)1779 bool drm_edid_is_valid(struct edid *edid)
1780 {
1781     int i;
1782     u8 *raw = (u8 *)edid;
1783 
1784     if (!edid) {
1785         return false;
1786     }
1787 
1788     for (i = 0; i <= edid->extensions; i++) {
1789         if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) {
1790             return false;
1791         }
1792     }
1793 
1794     return true;
1795 }
1796 EXPORT_SYMBOL(drm_edid_is_valid);
1797 
1798 #define DDC_SEGMENT_ADDR 0x30
1799 /**
1800  * drm_do_probe_ddc_edid() - get EDID information via I2C
1801  * @data: I2C device adapter
1802  * @buf: EDID data buffer to be filled
1803  * @block: 128 byte EDID block to start fetching from
1804  * @len: EDID data buffer length to fetch
1805  *
1806  * Try to fetch EDID information by calling I2C driver functions.
1807  *
1808  * Return: 0 on success or -1 on failure.
1809  */
drm_do_probe_ddc_edid(void * data,u8 * buf,unsigned int block,size_t len)1810 static int drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1811 {
1812     struct i2c_adapter *adapter = data;
1813     unsigned char start = block * EDID_LENGTH;
1814     unsigned char segment = block >> 1;
1815     unsigned char xfers = segment ? 0x3 : 0x2;
1816     int ret, retries = 0x5;
1817 
1818     /*
1819      * The core I2C driver will automatically retry the transfer if the
1820      * adapter reports EAGAIN. However, we find that bit-banging transfers
1821      * are susceptible to errors under a heavily loaded machine and
1822      * generate spurious NAKs and timeouts. Retrying the transfer
1823      * of the individual block a few times seems to overcome this.
1824      */
1825     do {
1826         struct i2c_msg msgs[] = {
1827             {
1828                 .addr = DDC_SEGMENT_ADDR,
1829                 .flags = 0,
1830                 .len = 1,
1831                 .buf = &segment,
1832             },
1833             {
1834                 .addr = DDC_ADDR,
1835                 .flags = 0,
1836                 .len = 1,
1837                 .buf = &start,
1838             },
1839             {
1840                 .addr = DDC_ADDR,
1841                 .flags = I2C_M_RD,
1842                 .len = len,
1843                 .buf = buf,
1844             }
1845         };
1846 
1847         /*
1848          * Avoid sending the segment addr to not upset non-compliant
1849          * DDC monitors.
1850          */
1851         ret = i2c_transfer(adapter, &msgs[0x3 - xfers], xfers);
1852         if (ret == -ENXIO) {
1853             DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", adapter->name);
1854             break;
1855         }
1856     } while (ret != xfers && --retries);
1857 
1858     return ret == xfers ? 0 : -1;
1859 }
1860 
connector_bad_edid(struct drm_connector * connector,u8 * edid,int num_blocks)1861 static void connector_bad_edid(struct drm_connector *connector, u8 *edid, int num_blocks)
1862 {
1863     int i;
1864     u8 num_of_ext = edid[0x7e];
1865 
1866     /* Calculate real checksum for the last edid extension block data */
1867     connector->real_edid_checksum = drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH);
1868 
1869     if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) {
1870         return;
1871     }
1872 
1873     drm_warn(connector->dev, "%s: EDID is invalid:\n", connector->name);
1874     for (i = 0; i < num_blocks; i++) {
1875         u8 *block = edid + i * EDID_LENGTH;
1876         char prefix[0x14];
1877 
1878         if (drm_edid_is_zero(block, EDID_LENGTH)) {
1879             sprintf(prefix, "\t[%02x] ZERO ", i);
1880         } else if (!drm_edid_block_valid(block, i, false, NULL)) {
1881             sprintf(prefix, "\t[%02x] BAD  ", i);
1882         } else {
1883             sprintf(prefix, "\t[%02x] GOOD ", i);
1884         }
1885 
1886         print_hex_dump(KERN_WARNING, prefix, DUMP_PREFIX_NONE, 0x10, 1, block, EDID_LENGTH, false);
1887     }
1888 }
1889 
1890 /* Get override or firmware EDID */
drm_get_override_edid(struct drm_connector * connector)1891 static struct edid *drm_get_override_edid(struct drm_connector *connector)
1892 {
1893     struct edid *override = NULL;
1894 
1895     if (connector->override_edid) {
1896         override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1897     }
1898 
1899     if (!override) {
1900         override = drm_load_edid_firmware(connector);
1901     }
1902 
1903     return IS_ERR(override) ? NULL : override;
1904 }
1905 
1906 /**
1907  * drm_do_get_edid - get EDID data using a custom EDID block read function
1908  * @connector: connector we're probing
1909  * @get_edid_block: EDID block read function
1910  * @data: private data passed to the block read function
1911  *
1912  * When the I2C adapter connected to the DDC bus is hidden behind a device that
1913  * exposes a different interface to read EDID blocks this function can be used
1914  * to get EDID data using a custom block read function.
1915  *
1916  * As in the general case the DDC bus is accessible by the kernel at the I2C
1917  * level, drivers must make all reasonable efforts to expose it as an I2C
1918  * adapter and use drm_get_edid() instead of abusing this function.
1919  *
1920  * The EDID may be overridden using debugfs override_edid or firmare EDID
1921  * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1922  * order. Having either of them bypasses actual EDID reads.
1923  *
1924  * Return: Pointer to valid EDID or NULL if we couldn't find any.
1925  */
drm_do_get_edid(struct drm_connector * connector,int (* get_edid_block)(void * data,u8 * buf,unsigned int block,size_t len),void * data)1926 struct edid *drm_do_get_edid(struct drm_connector *connector,
1927                              int (*get_edid_block)(void *data, u8 *buf, unsigned int block, size_t len), void *data)
1928 {
1929     int i, j = 0, valid_extensions = 0;
1930     u8 *edid, *new;
1931     struct edid *override;
1932 
1933     override = drm_get_override_edid(connector);
1934     if (override) {
1935         return override;
1936     }
1937 
1938     if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) {
1939         return NULL;
1940     }
1941 
1942     /* base block fetch */
1943     for (i = 0; i < 0x4; i++) {
1944         if (get_edid_block(data, edid, 0, EDID_LENGTH)) {
1945             goto out;
1946         }
1947         if (drm_edid_block_valid(edid, 0, false, &connector->edid_corrupt)) {
1948             break;
1949         }
1950         if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1951             connector->null_edid_counter++;
1952             goto carp;
1953         }
1954     }
1955     if (i == 0x4) {
1956         goto carp;
1957     }
1958 
1959     /* if there's no extensions, we're done */
1960     valid_extensions = edid[0x7e];
1961     if (valid_extensions == 0) {
1962         return (struct edid *)edid;
1963     }
1964 
1965     new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1966     if (!new) {
1967         goto out;
1968     }
1969     edid = new;
1970 
1971     for (j = 1; j <= edid[0x7e]; j++) {
1972         u8 *block = edid + j * EDID_LENGTH;
1973 
1974         for (i = 0; i < 0x4; i++) {
1975             if (get_edid_block(data, block, j, EDID_LENGTH)) {
1976                 goto out;
1977             }
1978             if (drm_edid_block_valid(block, j, false, NULL)) {
1979                 break;
1980             }
1981         }
1982 
1983         if (i == 0x4) {
1984             valid_extensions--;
1985         }
1986     }
1987 
1988     if (valid_extensions != edid[0x7e]) {
1989         u8 *base;
1990 
1991         connector_bad_edid(connector, edid, edid[0x7e] + 1);
1992 
1993         new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, GFP_KERNEL);
1994         if (!new) {
1995             goto out;
1996         }
1997 
1998         base = new;
1999         for (i = 0; i <= edid[0x7e]; i++) {
2000             u8 *block = edid + i * EDID_LENGTH;
2001 
2002             if (!drm_edid_block_valid(block, i, false, NULL)) {
2003                 continue;
2004             }
2005 
2006             memcpy(base, block, EDID_LENGTH);
2007             base += EDID_LENGTH;
2008         }
2009 
2010         new[EDID_LENGTH - 1] += new[0x7e] - valid_extensions;
2011         new[0x7e] = valid_extensions;
2012 
2013         kfree(edid);
2014         edid = new;
2015     }
2016 
2017     return (struct edid *)edid;
2018 
2019 carp:
2020     connector_bad_edid(connector, edid, 1);
2021 out:
2022     kfree(edid);
2023     return NULL;
2024 }
2025 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2026 
2027 /**
2028  * drm_probe_ddc() - probe DDC presence
2029  * Return: True -> success, false -> failure.
2030  */
drm_probe_ddc(struct i2c_adapter * adapter)2031 bool drm_probe_ddc(struct i2c_adapter *adapter)
2032 {
2033     unsigned char out;
2034 
2035     return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2036 }
2037 EXPORT_SYMBOL(drm_probe_ddc);
2038 
2039 /**
2040  * drm_get_edid - get EDID data, if available
2041  * Poke the given I2C channel to grab EDID data if possible.  If found,
2042  * attach it to the connector.
2043  *
2044  * Return: Pointer to valid EDID or NULL if we couldn't find any.
2045  */
drm_get_edid(struct drm_connector * connector,struct i2c_adapter * adapter)2046 struct edid *drm_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2047 {
2048     struct edid *edid;
2049 
2050     if (connector->force == DRM_FORCE_OFF) {
2051         return NULL;
2052     }
2053 
2054     if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) {
2055         return NULL;
2056     }
2057 
2058     edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2059     drm_connector_update_edid_property(connector, edid);
2060     return edid;
2061 }
2062 EXPORT_SYMBOL(drm_get_edid);
2063 
2064 /**
2065  * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2066  * @connector: connector we're probing
2067  * @adapter: I2C adapter to use for DDC
2068  *
2069  * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2070  * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2071  * switch DDC to the GPU which is retrieving EDID.
2072  *
2073  * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2074  */
drm_get_edid_switcheroo(struct drm_connector * connector,struct i2c_adapter * adapter)2075 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, struct i2c_adapter *adapter)
2076 {
2077     struct pci_dev *pdev = connector->dev->pdev;
2078     struct edid *edid;
2079 
2080     vga_switcheroo_lock_ddc(pdev);
2081     edid = drm_get_edid(connector, adapter);
2082     vga_switcheroo_unlock_ddc(pdev);
2083 
2084     return edid;
2085 }
2086 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2087 
2088 /**
2089  * drm_edid_duplicate - duplicate an EDID and the extensions
2090  * @edid: EDID to duplicate
2091  *
2092  * Return: Pointer to duplicated EDID or NULL on allocation failure.
2093  */
drm_edid_duplicate(const struct edid * edid)2094 struct edid *drm_edid_duplicate(const struct edid *edid)
2095 {
2096     return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2097 }
2098 EXPORT_SYMBOL(drm_edid_duplicate);
2099 
2100 /*** EDID parsing ***/
2101 
2102 /**
2103  * edid_vendor - match a string against EDID's obfuscated vendor field
2104  * @edid: EDID to match
2105  * @vendor: vendor string
2106  *
2107  * Returns true if @vendor is in @edid, false otherwise
2108  */
edid_vendor(const struct edid * edid,const char * vendor)2109 static bool edid_vendor(const struct edid *edid, const char *vendor)
2110 {
2111     char edid_vendor[3];
2112 
2113     edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 0x2) + '@';
2114     edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 0x3) | ((edid->mfg_id[1] & 0xe0) >> 0x5)) + '@';
2115     edid_vendor[0x2] = (edid->mfg_id[1] & 0x1f) + '@';
2116 
2117     return !strncmp(edid_vendor, vendor, 0x3);
2118 }
2119 
2120 /**
2121  * edid_get_quirks - return quirk flags for a given EDID
2122  * @edid: EDID to process
2123  *
2124  * This tells subsequent routines what fixes they need to apply.
2125  */
edid_get_quirks(const struct edid * edid)2126 static u32 edid_get_quirks(const struct edid *edid)
2127 {
2128     const struct edid_quirk *quirk;
2129     int i;
2130 
2131     for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2132         quirk = &edid_quirk_list[i];
2133 
2134         if (edid_vendor(edid, quirk->vendor) && (EDID_PRODUCT_ID(edid) == quirk->product_id)) {
2135             return quirk->quirks;
2136         }
2137     }
2138 
2139     return 0;
2140 }
2141 
2142 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2143 #define MODE_REFRESH_DIFF(c, t) (abs((c) - (t)))
2144 
2145 /**
2146  * edid_fixup_preferred - set preferred modes based on quirk list
2147  * @connector: has mode list to fix up
2148  * @quirks: quirks list
2149  *
2150  * Walk the mode list for @connector, clearing the preferred status
2151  * on existing modes and setting it anew for the right mode ala @quirks.
2152  */
edid_fixup_preferred(struct drm_connector * connector,u32 quirks)2153 static void edid_fixup_preferred(struct drm_connector *connector, u32 quirks)
2154 {
2155     struct drm_display_mode *t, *cur_mode, *preferred_mode;
2156     int target_refresh = 0;
2157     int cur_vrefresh, preferred_vrefresh;
2158 
2159     if (list_empty(&connector->probed_modes)) {
2160         return;
2161     }
2162 
2163     if (quirks & EDID_QUIRK_PREFER_LARGE_60) {
2164         target_refresh = 0x40;
2165     }
2166     if (quirks & EDID_QUIRK_PREFER_LARGE_75) {
2167         target_refresh = 0x4b;
2168     }
2169 
2170     preferred_mode = list_first_entry(&connector->probed_modes, struct drm_display_mode, head);
2171 
2172     list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head)
2173     {
2174         cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2175 
2176         if (cur_mode == preferred_mode) {
2177             continue;
2178         }
2179 
2180         /* Largest mode is preferred */
2181         if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) {
2182             preferred_mode = cur_mode;
2183         }
2184 
2185         cur_vrefresh = drm_mode_vrefresh(cur_mode);
2186         preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2187         /* At a given size, try to get closest to target refresh */
2188         if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2189             MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2190             preferred_mode = cur_mode;
2191         }
2192     }
2193 
2194     preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2195 }
2196 
mode_is_rb(const struct drm_display_mode * mode)2197 static bool mode_is_rb(const struct drm_display_mode *mode)
2198 {
2199     return (mode->htotal - mode->hdisplay == 0xa0) && (mode->hsync_end - mode->hdisplay == 0x50) &&
2200            (mode->hsync_end - mode->hsync_start == 0x20) && (mode->vsync_start - mode->vdisplay == 0x3);
2201 }
2202 
2203 /*
2204  * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2205  * @dev: Device to duplicate against
2206  * @hsize: Mode width
2207  * @vsize: Mode height
2208  * @fresh: Mode refresh rate
2209  * @rb: Mode reduced-blanking-ness
2210  *
2211  * Walk the DMT mode list looking for a match for the given parameters.
2212  *
2213  * Return: A newly allocated copy of the mode, or NULL if not found.
2214  */
drm_mode_find_dmt(struct drm_device * dev,int hsize,int vsize,int fresh,bool rb)2215 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, int hsize, int vsize, int fresh, bool rb)
2216 {
2217     int i;
2218 
2219     for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2220         const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2221 
2222         if (hsize != ptr->hdisplay) {
2223             continue;
2224         }
2225         if (vsize != ptr->vdisplay) {
2226             continue;
2227         }
2228         if (fresh != drm_mode_vrefresh(ptr)) {
2229             continue;
2230         }
2231         if (rb != mode_is_rb(ptr)) {
2232             continue;
2233         }
2234 
2235         return drm_mode_duplicate(dev, ptr);
2236     }
2237 
2238     return NULL;
2239 }
2240 EXPORT_SYMBOL(drm_mode_find_dmt);
2241 
is_display_descriptor(const u8 d[0x12],u8 tag)2242 static bool is_display_descriptor(const u8 d[0x12], u8 tag)
2243 {
2244     return d[0] == 0x00 && d[1] == 0x00 && d[0x2] == 0x00 && d[0x3] == tag;
2245 }
2246 
is_detailed_timing_descriptor(const u8 d[0x12])2247 static bool is_detailed_timing_descriptor(const u8 d[0x12])
2248 {
2249     return d[0] != 0x00 || d[1] != 0x00;
2250 }
2251 
2252 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2253 
cea_for_each_detailed_block(u8 * ext,detailed_cb * cb,void * closure)2254 static void cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2255 {
2256     int i, n;
2257     u8 d = ext[0x02];
2258     u8 *det_base = ext + d;
2259 
2260     if (d < 0x4 || d > 0x7f) {
2261         return;
2262     }
2263 
2264     n = (0x7f - d) / 0x12;
2265     for (i = 0; i < n; i++) {
2266         cb((struct detailed_timing *)(det_base + 0x12 * i), closure);
2267     }
2268 }
2269 
vtb_for_each_detailed_block(u8 * ext,detailed_cb * cb,void * closure)2270 static void vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2271 {
2272     unsigned int i, n = min((int)ext[0x02], 0x6);
2273     u8 *det_base = ext + 0x5;
2274 
2275     if (ext[0x01] != 1) {
2276         return; /* unknown version */
2277     }
2278 
2279     for (i = 0; i < n; i++) {
2280         cb((struct detailed_timing *)(det_base + 0x12 * i), closure);
2281     }
2282 }
2283 
drm_for_each_detailed_block(u8 * raw_edid,detailed_cb * cb,void * closure)2284 static void drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2285 {
2286     int i;
2287     struct edid *edid = (struct edid *)raw_edid;
2288 
2289     if (edid == NULL) {
2290         return;
2291     }
2292 
2293     for (i = 0; i < EDID_DETAILED_TIMINGS; i++) {
2294         cb(&(edid->detailed_timings[i]), closure);
2295     }
2296 
2297     for (i = 1; i <= raw_edid[0x7e]; i++) {
2298         u8 *ext = raw_edid + (i * EDID_LENGTH);
2299 
2300         switch (*ext) {
2301             case CEA_EXT:
2302                 cea_for_each_detailed_block(ext, cb, closure);
2303                 break;
2304             case VTB_EXT:
2305                 vtb_for_each_detailed_block(ext, cb, closure);
2306                 break;
2307             default:
2308                 break;
2309         }
2310     }
2311 }
2312 
is_rb(struct detailed_timing * t,void * data)2313 static void is_rb(struct detailed_timing *t, void *data)
2314 {
2315     u8 *r = (u8 *)t;
2316 
2317     if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) {
2318         return;
2319     }
2320 
2321     if (r[0xf] & 0x10) {
2322         *(bool *)data = true;
2323     }
2324 }
2325 
2326 /* EDID 1.4 defines this explicitly.  For EDID 1.3, we guess, badly. */
drm_monitor_supports_rb(struct edid * edid)2327 static bool drm_monitor_supports_rb(struct edid *edid)
2328 {
2329     if (edid->revision >= 0x4) {
2330         bool ret = false;
2331 
2332         drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2333         return ret;
2334     }
2335 
2336     return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2337 }
2338 
find_gtf2(struct detailed_timing * t,void * data)2339 static void find_gtf2(struct detailed_timing *t, void *data)
2340 {
2341     u8 *r = (u8 *)t;
2342 
2343     if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) {
2344         return;
2345     }
2346 
2347     if (r[0xa] == 0x02) {
2348         *(u8 **)data = r;
2349     }
2350 }
2351 
2352 /* Secondary GTF curve kicks in above some break frequency */
drm_gtf2_hbreak(struct edid * edid)2353 static int drm_gtf2_hbreak(struct edid *edid)
2354 {
2355     u8 *r = NULL;
2356 
2357     drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2358     return r ? (r[0xc] * 0x2) : 0;
2359 }
2360 
drm_gtf2_2c(struct edid * edid)2361 static int drm_gtf2_2c(struct edid *edid)
2362 {
2363     u8 *r = NULL;
2364 
2365     drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2366     return r ? r[0xd] : 0;
2367 }
2368 
drm_gtf2_m(struct edid * edid)2369 static int drm_gtf2_m(struct edid *edid)
2370 {
2371     u8 *r = NULL;
2372 
2373     drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2374     return r ? (r[0xf] << 0x8) + r[0xe] : 0;
2375 }
2376 
drm_gtf2_k(struct edid * edid)2377 static int drm_gtf2_k(struct edid *edid)
2378 {
2379     u8 *r = NULL;
2380 
2381     drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2382     return r ? r[0x10] : 0;
2383 }
2384 
drm_gtf2_2j(struct edid * edid)2385 static int drm_gtf2_2j(struct edid *edid)
2386 {
2387     u8 *r = NULL;
2388 
2389     drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2390     return r ? r[0x11] : 0;
2391 }
2392 
2393 /**
2394  * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2395  * @edid: EDID block to scan
2396  */
standard_timing_level(struct edid * edid)2397 static int standard_timing_level(struct edid *edid)
2398 {
2399     if (edid->revision >= 0x2) {
2400         if (edid->revision >= 0x4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) {
2401             return LEVEL_CVT;
2402         }
2403         if (drm_gtf2_hbreak(edid)) {
2404             return LEVEL_GTF2;
2405         }
2406         if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) {
2407             return LEVEL_GTF;
2408         }
2409     }
2410     return LEVEL_DMT;
2411 }
2412 
2413 /*
2414  * 0 is reserved.  The spec says 0x01 fill for unused timings.  Some old
2415  * monitors fill with ascii space (0x20) instead.
2416  */
bad_std_timing(u8 a,u8 b)2417 static int bad_std_timing(u8 a, u8 b)
2418 {
2419     return (a == 0x00 && b == 0x00) || (a == 0x01 && b == 0x01) || (a == 0x20 && b == 0x20);
2420 }
2421 
drm_mode_hsync(const struct drm_display_mode * mode)2422 static int drm_mode_hsync(const struct drm_display_mode *mode)
2423 {
2424     if (mode->htotal <= 0) {
2425         return 0;
2426     }
2427 
2428     return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2429 }
2430 
2431 /**
2432  * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2433  * @connector: connector of for the EDID block
2434  * @edid: EDID block to scan
2435  * @t: standard timing params
2436  *
2437  * Take the standard timing params (in this case width, aspect, and refresh)
2438  * and convert them into a real mode using CVT/GTF/DMT.
2439  */
drm_mode_std(struct drm_connector * connector,struct edid * edid,struct std_timing * t)2440 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, struct edid *edid, struct std_timing *t)
2441 {
2442     struct drm_device *dev = connector->dev;
2443     struct drm_display_mode *m, *mode = NULL;
2444     int hsize, vsize;
2445     int vrefresh_rate;
2446     unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) >> EDID_TIMING_ASPECT_SHIFT;
2447     unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) >> EDID_TIMING_VFREQ_SHIFT;
2448     int timing_level = standard_timing_level(edid);
2449 
2450     if (bad_std_timing(t->hsize, t->vfreq_aspect)) {
2451         return NULL;
2452     }
2453 
2454     /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2455     hsize = t->hsize * 0x8 + 0xf8;
2456     /* vrefresh_rate = vfreq + 60 */
2457     vrefresh_rate = vfreq + 0x3c;
2458     /* the vdisplay is calculated based on the aspect ratio */
2459     if (aspect_ratio == 0) {
2460         if (edid->revision < 0x3) {
2461             vsize = hsize;
2462         } else {
2463             vsize = (hsize * 0xa) / 0x10;
2464         }
2465     } else if (aspect_ratio == 0x1) {
2466         vsize = (hsize * 0x3) / 0x4;
2467     } else if (aspect_ratio == 0x2) {
2468         vsize = (hsize * 0x4) / 0x5;
2469     } else {
2470         vsize = (hsize * 0x9) / 0x10;
2471     }
2472 
2473     /* HDTV hack, part 1 */
2474     if (vrefresh_rate == 0x3c && ((hsize == 0x550 && vsize == 0x2fd) || (hsize == 0x558 && vsize == 0x301))) {
2475         hsize = 0x556;
2476         vsize = 0x300;
2477     }
2478 
2479     /*
2480      * If this connector already has a mode for this size and refresh
2481      * rate (because it came from detailed or CVT info), use that
2482      * instead.  This way we don't have to guess at interlace or
2483      * reduced blanking.
2484      */
2485     list_for_each_entry(m, &connector->probed_modes, head) if (m->hdisplay == hsize && m->vdisplay == vsize &&
2486                                                                drm_mode_vrefresh(m) == vrefresh_rate) return NULL;
2487 
2488     /* HDTV hack, part 2 */
2489     if (hsize == 0x556 && vsize == 0x300 && vrefresh_rate == 0x3c) {
2490         mode = drm_cvt_mode(dev, 0x556, 0x300, vrefresh_rate, 0, 0, false);
2491         if (!mode) {
2492             return NULL;
2493         }
2494         mode->hdisplay = 0x556;
2495         mode->hsync_start = mode->hsync_start - 1;
2496         mode->hsync_end = mode->hsync_end - 1;
2497         return mode;
2498     }
2499 
2500     /* check whether it can be found in default mode table */
2501     if (drm_monitor_supports_rb(edid)) {
2502         mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, true);
2503         if (mode) {
2504             return mode;
2505         }
2506     }
2507     mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2508     if (mode) {
2509         return mode;
2510     }
2511 
2512     /* okay, generate it */
2513     switch (timing_level) {
2514         case LEVEL_DMT:
2515             break;
2516         case LEVEL_GTF:
2517             mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2518             break;
2519         case LEVEL_GTF2:
2520             /*
2521              * This is potentially wrong if there's ever a monitor with
2522              * more than one ranges section, each claiming a different
2523              * secondary GTF curve.  Please don't do that.
2524              */
2525             mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2526             if (!mode) {
2527                 return NULL;
2528             }
2529             if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2530                 drm_mode_destroy(dev, mode);
2531                 mode = drm_gtf_mode_complex(dev, hsize, vsize, vrefresh_rate, 0, 0, drm_gtf2_m(edid), drm_gtf2_2c(edid),
2532                                             drm_gtf2_k(edid), drm_gtf2_2j(edid));
2533             }
2534             break;
2535         case LEVEL_CVT:
2536             mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, false);
2537             break;
2538         default:
2539             break;
2540     }
2541     return mode;
2542 }
2543 
2544 /*
2545  * EDID is delightfully ambiguous about how interlaced modes are to be
2546  * encoded.  Our internal representation is of frame height, but some
2547  * HDTV detailed timings are encoded as field height.
2548  *
2549  * The format list here is from CEA, in frame size.  Technically we
2550  * should be checking refresh rate too.  Whatever.
2551  */
drm_mode_do_interlace_quirk(struct drm_display_mode * mode,struct detailed_pixel_timing * pt)2552 static void drm_mode_do_interlace_quirk(struct drm_display_mode *mode, struct detailed_pixel_timing *pt)
2553 {
2554     int i;
2555     static const struct {
2556         int w, h;
2557     } cea_interlaced[] = {
2558         {1920, 1080}, {720, 480}, {1440, 480}, {2880, 480}, {720, 576}, {1440, 576}, {2880, 576},
2559     };
2560 
2561     if (!(pt->misc & DRM_EDID_PT_INTERLACED)) {
2562         return;
2563     }
2564 
2565     for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2566         if ((mode->hdisplay == cea_interlaced[i].w) && (mode->vdisplay == cea_interlaced[i].h / 0x2)) {
2567             mode->vdisplay *= 0x2;
2568             mode->vsync_start *= 0x2;
2569             mode->vsync_end *= 0x2;
2570             mode->vtotal *= 0x2;
2571             mode->vtotal |= 0x1;
2572         }
2573     }
2574 
2575     mode->flags |= DRM_MODE_FLAG_INTERLACE;
2576 }
2577 
2578 /**
2579  * drm_mode_detailed - create a new mode from an EDID detailed timing section
2580  * @dev: DRM device (needed to create new mode)
2581  * @edid: EDID block
2582  * @timing: EDID detailed timing info
2583  * @quirks: quirks to apply
2584  *
2585  * An EDID detailed timing block contains enough info for us to create and
2586  * return a new struct drm_display_mode.
2587  */
drm_mode_detailed(struct drm_device * dev,struct edid * edid,struct detailed_timing * timing,u32 quirks)2588 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, struct edid *edid,
2589                                                   struct detailed_timing *timing, u32 quirks)
2590 {
2591     struct drm_display_mode *mode;
2592     struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2593     unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 0x4 | pt->hactive_lo;
2594     unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 0x4 | pt->vactive_lo;
2595     unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 0x8 | pt->hblank_lo;
2596     unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 0x8 | pt->vblank_lo;
2597     unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 0x2 | pt->hsync_offset_lo;
2598     unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 0x4 | pt->hsync_pulse_width_lo;
2599     unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 0x2 | pt->vsync_offset_pulse_width_lo >> 4;
2600     unsigned vsync_pulse_width =
2601         (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 0x4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2602 
2603     /* ignore tiny modes */
2604     if (hactive < 0x40 || vactive < 0x40) {
2605         return NULL;
2606     }
2607 
2608     if (pt->misc & DRM_EDID_PT_STEREO) {
2609         DRM_DEBUG_KMS("stereo mode not supported\n");
2610         return NULL;
2611     }
2612     if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2613         DRM_DEBUG_KMS("composite sync not supported\n");
2614     }
2615 
2616     /* it is incorrect if hsync/vsync width is zero */
2617     if (!hsync_pulse_width || !vsync_pulse_width) {
2618         DRM_DEBUG_KMS("Incorrect Detailed timing. "
2619                       "Wrong Hsync/Vsync pulse width\n");
2620         return NULL;
2621     }
2622 
2623     if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2624         mode = drm_cvt_mode(dev, hactive, vactive, 0x3c, true, false, false);
2625         if (!mode) {
2626             return NULL;
2627         }
2628 
2629         goto set_size;
2630     }
2631 
2632     mode = drm_mode_create(dev);
2633     if (!mode) {
2634         return NULL;
2635     }
2636 
2637     if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) {
2638         timing->pixel_clock = cpu_to_le16(0x440);
2639     }
2640 
2641     mode->clock = le16_to_cpu(timing->pixel_clock) * 0xa;
2642 
2643     mode->hdisplay = hactive;
2644     mode->hsync_start = mode->hdisplay + hsync_offset;
2645     mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2646     mode->htotal = mode->hdisplay + hblank;
2647 
2648     mode->vdisplay = vactive;
2649     mode->vsync_start = mode->vdisplay + vsync_offset;
2650     mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2651     mode->vtotal = mode->vdisplay + vblank;
2652 
2653     /* Some EDIDs have bogus h/vtotal values */
2654     if (mode->hsync_end > mode->htotal) {
2655         mode->htotal = mode->hsync_end + 1;
2656     }
2657     if (mode->vsync_end > mode->vtotal) {
2658         mode->vtotal = mode->vsync_end + 1;
2659     }
2660 
2661     drm_mode_do_interlace_quirk(mode, pt);
2662 
2663     if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2664         pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2665     }
2666 
2667     mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2668     mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2669 
2670 set_size:
2671     mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 0x4;
2672     mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 0x8;
2673 
2674     if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2675         mode->width_mm *= 0xa;
2676         mode->height_mm *= 0xa;
2677     }
2678 
2679     if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2680         mode->width_mm = edid->width_cm * 0xa;
2681         mode->height_mm = edid->height_cm * 0xa;
2682     }
2683 
2684     mode->type = DRM_MODE_TYPE_DRIVER;
2685     drm_mode_set_name(mode);
2686 
2687     return mode;
2688 }
2689 
mode_in_hsync_range(const struct drm_display_mode * mode,struct edid * edid,u8 * t)2690 static bool mode_in_hsync_range(const struct drm_display_mode *mode, struct edid *edid, u8 *t)
2691 {
2692     int hsync, hmin, hmax;
2693 
2694     hmin = t[0x7];
2695     if (edid->revision >= 0x4) {
2696         hmin += ((t[0x4] & 0x04) ? 0xff : 0);
2697     }
2698     hmax = t[0x8];
2699     if (edid->revision >= 0x4) {
2700         hmax += ((t[0x4] & 0x08) ? 0xff : 0);
2701     }
2702     hsync = drm_mode_hsync(mode);
2703 
2704     return (hsync <= hmax && hsync >= hmin);
2705 }
2706 
mode_in_vsync_range(const struct drm_display_mode * mode,struct edid * edid,u8 * t)2707 static bool mode_in_vsync_range(const struct drm_display_mode *mode, struct edid *edid, u8 *t)
2708 {
2709     int vsync, vmin, vmax;
2710 
2711     vmin = t[0x5];
2712     if (edid->revision >= 0x4) {
2713         vmin += ((t[0x4] & 0x01) ? 0xff : 0);
2714     }
2715     vmax = t[0x6];
2716     if (edid->revision >= 0x4) {
2717         vmax += ((t[0x4] & 0x02) ? 0xff : 0);
2718     }
2719     vsync = drm_mode_vrefresh(mode);
2720 
2721     return (vsync <= vmax && vsync >= vmin);
2722 }
2723 
range_pixel_clock(struct edid * edid,u8 * t)2724 static u32 range_pixel_clock(struct edid *edid, u8 *t)
2725 {
2726     /* unspecified */
2727     if (t[0x9] == 0x0 || t[0x9] == 0xff) {
2728         return 0x0;
2729     }
2730 
2731     /* 1.4 with CVT support gives us real precision, yay */
2732     if (edid->revision >= 0x4 && t[0xa] == 0x04) {
2733         return (t[0x9] * 0x2710) - ((t[0xc] >> 0x2) * 0xfa);
2734     }
2735 
2736     /* 1.3 is pathetic, so fuzz up a bit */
2737     return t[0x9] * 0x2710 + 0x1389;
2738 }
2739 
mode_in_range(const struct drm_display_mode * mode,struct edid * edid,struct detailed_timing * timing)2740 static bool mode_in_range(const struct drm_display_mode *mode, struct edid *edid, struct detailed_timing *timing)
2741 {
2742     u32 max_clock;
2743     u8 *t = (u8 *)timing;
2744 
2745     if (!mode_in_hsync_range(mode, edid, t)) {
2746         return false;
2747     }
2748 
2749     if (!mode_in_vsync_range(mode, edid, t)) {
2750         return false;
2751     }
2752 
2753     if ((max_clock = range_pixel_clock(edid, t))) {
2754         if (mode->clock > max_clock) {
2755             return false;
2756         }
2757     }
2758 
2759     /* 1.4 max horizontal check */
2760     if (edid->revision >= 0x4 && t[0xa] == 0x04) {
2761         if (t[0xd] && mode->hdisplay > 0x8 * (t[0xd] + (0x100 * (t[0xc] & 0x3)))) {
2762             return false;
2763         }
2764     }
2765 
2766     if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) {
2767         return false;
2768     }
2769 
2770     return true;
2771 }
2772 
valid_inferred_mode(const struct drm_connector * connector,const struct drm_display_mode * mode)2773 static bool valid_inferred_mode(const struct drm_connector *connector, const struct drm_display_mode *mode)
2774 {
2775     const struct drm_display_mode *m;
2776     bool ok = false;
2777 
2778     list_for_each_entry(m, &connector->probed_modes, head)
2779     {
2780         if (mode->hdisplay == m->hdisplay && mode->vdisplay == m->vdisplay &&
2781             drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) {
2782             return false; /* duplicated */
2783         }
2784         if (mode->hdisplay <= m->hdisplay && mode->vdisplay <= m->vdisplay) {
2785             ok = true;
2786         }
2787     }
2788     return ok;
2789 }
2790 
drm_dmt_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)2791 static int drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, struct detailed_timing *timing)
2792 {
2793     int i, modes = 0;
2794     struct drm_display_mode *newmode;
2795     struct drm_device *dev = connector->dev;
2796 
2797     for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2798         if (mode_in_range(drm_dmt_modes + i, edid, timing) && valid_inferred_mode(connector, drm_dmt_modes + i)) {
2799             newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2800             if (newmode) {
2801                 drm_mode_probed_add(connector, newmode);
2802                 modes++;
2803             }
2804         }
2805     }
2806 
2807     return modes;
2808 }
2809 
2810 /* fix up 1366x768 mode from 1368x768;
2811  * GFT/CVT can't express 1366 width which isn't dividable by 8
2812  */
drm_mode_fixup_1366x768(struct drm_display_mode * mode)2813 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2814 {
2815     if (mode->hdisplay == 0x558 && mode->vdisplay == 0x300) {
2816         mode->hdisplay = 0x556;
2817         mode->hsync_start--;
2818         mode->hsync_end--;
2819         drm_mode_set_name(mode);
2820     }
2821 }
2822 
drm_gtf_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)2823 static int drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, struct detailed_timing *timing)
2824 {
2825     int i, modes = 0;
2826     struct drm_display_mode *newmode;
2827     struct drm_device *dev = connector->dev;
2828 
2829     for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2830         const struct minimode *m = &extra_modes[i];
2831 
2832         newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2833         if (!newmode) {
2834             return modes;
2835         }
2836 
2837         drm_mode_fixup_1366x768(newmode);
2838         if (!mode_in_range(newmode, edid, timing) || !valid_inferred_mode(connector, newmode)) {
2839             drm_mode_destroy(dev, newmode);
2840             continue;
2841         }
2842 
2843         drm_mode_probed_add(connector, newmode);
2844         modes++;
2845     }
2846 
2847     return modes;
2848 }
2849 
drm_cvt_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)2850 static int drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, struct detailed_timing *timing)
2851 {
2852     int i, modes = 0;
2853     struct drm_display_mode *newmode;
2854     struct drm_device *dev = connector->dev;
2855     bool rb = drm_monitor_supports_rb(edid);
2856 
2857     for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2858         const struct minimode *m = &extra_modes[i];
2859 
2860         newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2861         if (!newmode) {
2862             return modes;
2863         }
2864 
2865         drm_mode_fixup_1366x768(newmode);
2866         if (!mode_in_range(newmode, edid, timing) || !valid_inferred_mode(connector, newmode)) {
2867             drm_mode_destroy(dev, newmode);
2868             continue;
2869         }
2870 
2871         drm_mode_probed_add(connector, newmode);
2872         modes++;
2873     }
2874 
2875     return modes;
2876 }
2877 
do_inferred_modes(struct detailed_timing * timing,void * c)2878 static void do_inferred_modes(struct detailed_timing *timing, void *c)
2879 {
2880     struct detailed_mode_closure *closure = c;
2881     struct detailed_non_pixel *data = &timing->data.other_data;
2882     struct detailed_data_monitor_range *range = &data->data.range;
2883 
2884     if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) {
2885         return;
2886     }
2887 
2888     closure->modes += drm_dmt_modes_for_range(closure->connector, closure->edid, timing);
2889 
2890     if (!version_greater(closure->edid, 1, 1)) {
2891         return; /* GTF not defined yet */
2892     }
2893 
2894     switch (range->flags) {
2895         case 0x02: /* secondary gtf, XXX could do more */
2896         case 0x00: /* default gtf */
2897             closure->modes += drm_gtf_modes_for_range(closure->connector, closure->edid, timing);
2898             break;
2899         case 0x04: /* cvt, only in 1.4+ */
2900             if (!version_greater(closure->edid, 1, 0x3)) {
2901                 break;
2902             }
2903 
2904             closure->modes += drm_cvt_modes_for_range(closure->connector, closure->edid, timing);
2905             break;
2906         case 0x01: /* just the ranges, no formula */
2907         default:
2908             break;
2909     }
2910 }
2911 
add_inferred_modes(struct drm_connector * connector,struct edid * edid)2912 static int add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2913 {
2914     struct detailed_mode_closure closure = {
2915         .connector = connector,
2916         .edid = edid,
2917     };
2918 
2919     if (version_greater(edid, 1, 0)) {
2920         drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, &closure);
2921     }
2922 
2923     return closure.modes;
2924 }
2925 
drm_est3_modes(struct drm_connector * connector,struct detailed_timing * timing)2926 static int drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2927 {
2928     int i, j, m, modes = 0x0;
2929     struct drm_display_mode *mode;
2930     u8 *est = ((u8 *)timing) + 0x6;
2931 
2932     for (i = 0x0; i < 0x6; i++) {
2933         for (j = 0x7; j >= 0x0; j--) {
2934             m = (i * 0x8) + (0x7 - j);
2935             if (m >= ARRAY_SIZE(est3_modes)) {
2936                 break;
2937             }
2938             if (est[i] & (0x1 << j)) {
2939                 mode = drm_mode_find_dmt(connector->dev, est3_modes[m].w, est3_modes[m].h, est3_modes[m].r,
2940                                          est3_modes[m].rb);
2941                 if (mode) {
2942                     drm_mode_probed_add(connector, mode);
2943                     modes++;
2944                 }
2945             }
2946         }
2947     }
2948 
2949     return modes;
2950 }
2951 
do_established_modes(struct detailed_timing * timing,void * c)2952 static void do_established_modes(struct detailed_timing *timing, void *c)
2953 {
2954     struct detailed_mode_closure *closure = c;
2955 
2956     if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS)) {
2957         return;
2958     }
2959 
2960     closure->modes += drm_est3_modes(closure->connector, timing);
2961 }
2962 
2963 /**
2964  * add_established_modes - get est. modes from EDID and add them
2965  * @connector: connector to add mode(s) to
2966  * @edid: EDID block to scan
2967  *
2968  * Each EDID block contains a bitmap of the supported "established modes" list
2969  * (defined above).  Tease them out and add them to the global modes list.
2970  */
add_established_modes(struct drm_connector * connector,struct edid * edid)2971 static int add_established_modes(struct drm_connector *connector, struct edid *edid)
2972 {
2973     struct drm_device *dev = connector->dev;
2974     unsigned long est_bits = edid->established_timings.t1 | (edid->established_timings.t2 << 0x8) |
2975                              ((edid->established_timings.mfg_rsvd & 0x80) << 0x9);
2976     int i, modes = 0x0;
2977     struct detailed_mode_closure closure = {
2978         .connector = connector,
2979         .edid = edid,
2980     };
2981 
2982     for (i = 0x0; i <= EDID_EST_TIMINGS; i++) {
2983         if (est_bits & (0x1 << i)) {
2984             struct drm_display_mode *newmode;
2985 
2986             newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2987             if (newmode) {
2988                 drm_mode_probed_add(connector, newmode);
2989                 modes++;
2990             }
2991         }
2992     }
2993 
2994     if (version_greater(edid, 0x1, 0x0)) {
2995         drm_for_each_detailed_block((u8 *)edid, do_established_modes, &closure);
2996     }
2997 
2998     return modes + closure.modes;
2999 }
3000 
do_standard_modes(struct detailed_timing * timing,void * c)3001 static void do_standard_modes(struct detailed_timing *timing, void *c)
3002 {
3003     struct detailed_mode_closure *closure = c;
3004     struct detailed_non_pixel *data = &timing->data.other_data;
3005     struct drm_connector *connector = closure->connector;
3006     struct edid *edid = closure->edid;
3007     int i;
3008 
3009     if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES)) {
3010         return;
3011     }
3012 
3013     for (i = 0; i < 0x6; i++) {
3014         struct std_timing *std = &data->data.timings[i];
3015         struct drm_display_mode *newmode;
3016 
3017         newmode = drm_mode_std(connector, edid, std);
3018         if (newmode) {
3019             drm_mode_probed_add(connector, newmode);
3020             closure->modes++;
3021         }
3022     }
3023 }
3024 
3025 /**
3026  * add_standard_modes - get std. modes from EDID and add them
3027  * @connector: connector to add mode(s) to
3028  * @edid: EDID block to scan
3029  *
3030  * Standard modes can be calculated using the appropriate standard (DMT,
3031  * GTF or CVT. Grab them from @edid and add them to the list.
3032  */
add_standard_modes(struct drm_connector * connector,struct edid * edid)3033 static int add_standard_modes(struct drm_connector *connector, struct edid *edid)
3034 {
3035     int i, modes = 0;
3036     struct detailed_mode_closure closure = {
3037         .connector = connector,
3038         .edid = edid,
3039     };
3040 
3041     for (i = 0; i < EDID_STD_TIMINGS; i++) {
3042         struct drm_display_mode *newmode;
3043 
3044         newmode = drm_mode_std(connector, edid, &edid->standard_timings[i]);
3045         if (newmode) {
3046             drm_mode_probed_add(connector, newmode);
3047             modes++;
3048         }
3049     }
3050 
3051     if (version_greater(edid, 1, 0)) {
3052         drm_for_each_detailed_block((u8 *)edid, do_standard_modes, &closure);
3053     }
3054 
3055     /* XXX should also look for standard codes in VTB blocks */
3056 
3057     return modes + closure.modes;
3058 }
3059 
drm_cvt_modes(struct drm_connector * connector,struct detailed_timing * timing)3060 static int drm_cvt_modes(struct drm_connector *connector, struct detailed_timing *timing)
3061 {
3062     int i, j, modes = 0;
3063     struct drm_display_mode *newmode;
3064     struct drm_device *dev = connector->dev;
3065     struct cvt_timing *cvt;
3066     const int rates[] = {60, 85, 75, 60, 50};
3067     const u8 empty[3] = {0, 0, 0};
3068 
3069     for (i = 0; i < 0x4; i++) {
3070         int width, height;
3071 
3072         cvt = &(timing->data.other_data.data.cvt[i]);
3073 
3074         if (!memcmp(cvt->code, empty, 0x3)) {
3075             continue;
3076         }
3077 
3078         height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 0x4) + 1) * 0x2;
3079         switch (cvt->code[1] & 0x0c) {
3080             /* default - because compiler doesn't see that we've enumerated all cases */
3081             default:
3082             case 0x00:
3083                 width = height * 0x4 / 0x3;
3084                 break;
3085             case 0x04:
3086                 width = height * 0x10 / 0x9;
3087                 break;
3088             case 0x08:
3089                 width = height * 0x10 / 0xa;
3090                 break;
3091             case 0x0c:
3092                 width = height * 0xf / 0x9;
3093                 break;
3094         }
3095 
3096         for (j = 1; j < 0x5; j++) {
3097             if (cvt->code[0x2] & (1 << j)) {
3098                 newmode = drm_cvt_mode(dev, width, height, rates[j], j == 0, false, false);
3099                 if (newmode) {
3100                     drm_mode_probed_add(connector, newmode);
3101                     modes++;
3102                 }
3103             }
3104         }
3105     }
3106 
3107     return modes;
3108 }
3109 
do_cvt_mode(struct detailed_timing * timing,void * c)3110 static void do_cvt_mode(struct detailed_timing *timing, void *c)
3111 {
3112     struct detailed_mode_closure *closure = c;
3113 
3114     if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE)) {
3115         return;
3116     }
3117 
3118     closure->modes += drm_cvt_modes(closure->connector, timing);
3119 }
3120 
add_cvt_modes(struct drm_connector * connector,struct edid * edid)3121 static int add_cvt_modes(struct drm_connector *connector, struct edid *edid)
3122 {
3123     struct detailed_mode_closure closure = {
3124         .connector = connector,
3125         .edid = edid,
3126     };
3127 
3128     if (version_greater(edid, 1, 0x2)) {
3129         drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
3130     }
3131 
3132     /* XXX should also look for CVT codes in VTB blocks */
3133 
3134     return closure.modes;
3135 }
3136 
3137 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3138 
do_detailed_mode(struct detailed_timing * timing,void * c)3139 static void do_detailed_mode(struct detailed_timing *timing, void *c)
3140 {
3141     struct detailed_mode_closure *closure = c;
3142     struct drm_display_mode *newmode;
3143 
3144     if (!is_detailed_timing_descriptor((const u8 *)timing)) {
3145         return;
3146     }
3147 
3148     newmode = drm_mode_detailed(closure->connector->dev, closure->edid, timing, closure->quirks);
3149     if (!newmode) {
3150         return;
3151     }
3152 
3153     if (closure->preferred) {
3154         newmode->type |= DRM_MODE_TYPE_PREFERRED;
3155     }
3156 
3157     /*
3158      * Detailed modes are limited to 10kHz pixel clock resolution,
3159      * so fix up anything that looks like CEA/HDMI mode, but the clock
3160      * is just slightly off.
3161      */
3162     fixup_detailed_cea_mode_clock(newmode);
3163 
3164     drm_mode_probed_add(closure->connector, newmode);
3165     closure->modes++;
3166     closure->preferred = false;
3167 }
3168 
3169 /*
3170  * add_detailed_modes - Add modes from detailed timings
3171  * @connector: attached connector
3172  * @edid: EDID block to scan
3173  * @quirks: quirks to apply
3174  */
add_detailed_modes(struct drm_connector * connector,struct edid * edid,u32 quirks)3175 static int add_detailed_modes(struct drm_connector *connector, struct edid *edid, u32 quirks)
3176 {
3177     struct detailed_mode_closure closure = {
3178         .connector = connector,
3179         .edid = edid,
3180         .preferred = true,
3181         .quirks = quirks,
3182     };
3183 
3184     if (closure.preferred && !version_greater(edid, 1, 0x3)) {
3185         closure.preferred = (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3186     }
3187 
3188     drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
3189 
3190     return closure.modes;
3191 }
3192 
3193 #define AUDIO_BLOCK 0x01
3194 #define VIDEO_BLOCK 0x02
3195 #define VENDOR_BLOCK 0x03
3196 #define SPEAKER_BLOCK 0x04
3197 #define HDR_STATIC_METADATA_BLOCK 0x6
3198 #define USE_EXTENDED_TAG 0x07
3199 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
3200 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
3201 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
3202 #define EDID_BASIC_AUDIO (1 << 6)
3203 #define EDID_CEA_YCRCB444 (1 << 5)
3204 #define EDID_CEA_YCRCB422 (1 << 4)
3205 #define EDID_CEA_VCDB_QS (1 << 6)
3206 
3207 /*
3208  * Search EDID for CEA extension block.
3209  */
drm_find_edid_extension(const struct edid * edid,int ext_id,int * ext_index)3210 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id, int *ext_index)
3211 {
3212     u8 *edid_ext = NULL;
3213     int i;
3214 
3215     /* No EDID or EDID extensions */
3216     if (edid == NULL || edid->extensions == 0) {
3217         return NULL;
3218     }
3219 
3220     /* Find CEA extension */
3221     for (i = *ext_index; i < edid->extensions; i++) {
3222         edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
3223         if (edid_ext[0] == ext_id) {
3224             break;
3225         }
3226     }
3227 
3228     if (i >= edid->extensions) {
3229         return NULL;
3230     }
3231 
3232     *ext_index = i + 1;
3233 
3234     return edid_ext;
3235 }
3236 
drm_find_displayid_extension(const struct edid * edid,int * length,int * idx,int * ext_index)3237 static u8 *drm_find_displayid_extension(const struct edid *edid, int *length, int *idx, int *ext_index)
3238 {
3239     u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT, ext_index);
3240     struct displayid_hdr *base;
3241     int ret;
3242 
3243     if (!displayid) {
3244         return NULL;
3245     }
3246 
3247     /* EDID extensions block checksum isn't for us */
3248     *length = EDID_LENGTH - 1;
3249     *idx = 1;
3250 
3251     ret = validate_displayid(displayid, *length, *idx);
3252     if (ret) {
3253         return NULL;
3254     }
3255 
3256     base = (struct displayid_hdr *)&displayid[*idx];
3257     *length = *idx + sizeof(*base) + base->bytes;
3258 
3259     return displayid;
3260 }
3261 
drm_find_cea_extension(const struct edid * edid)3262 static u8 *drm_find_cea_extension(const struct edid *edid)
3263 {
3264     int length, idx;
3265     struct displayid_block *block;
3266     u8 *cea;
3267     u8 *displayid;
3268     int ext_index;
3269 
3270     /* Look for a top level CEA extension block */
3271     /* make callers iterate through multiple CEA ext blocks? */
3272     ext_index = 0;
3273     cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index);
3274     if (cea) {
3275         return cea;
3276     }
3277 
3278     /* CEA blocks can also be found embedded in a DisplayID block */
3279     ext_index = 0;
3280     for (;;) {
3281         displayid = drm_find_displayid_extension(edid, &length, &idx, &ext_index);
3282         if (!displayid) {
3283             return NULL;
3284         }
3285 
3286         idx += sizeof(struct displayid_hdr);
3287         for_each_displayid_db(displayid, block, idx, length)
3288         {
3289             if (block->tag == DATA_BLOCK_CTA) {
3290                 return (u8 *)block;
3291             }
3292         }
3293     }
3294 
3295     return NULL;
3296 }
3297 
cea_mode_for_vic(u8 vic)3298 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3299 {
3300     BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 0x7f);
3301     BUILD_BUG_ON(0xc1 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 0xdb);
3302 
3303     if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) {
3304         return &edid_cea_modes_1[vic - 1];
3305     }
3306     if (vic >= 0xc1 && vic < 0xc1 + ARRAY_SIZE(edid_cea_modes_193)) {
3307         return &edid_cea_modes_193[vic - 0xc1];
3308     }
3309     return NULL;
3310 }
3311 
cea_num_vics(void)3312 static u8 cea_num_vics(void)
3313 {
3314     return 0xc1 + ARRAY_SIZE(edid_cea_modes_193);
3315 }
3316 
cea_next_vic(u8 vic)3317 static u8 cea_next_vic(u8 vic)
3318 {
3319     if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) {
3320         vic = 0xc1;
3321     }
3322     return vic;
3323 }
3324 
3325 /*
3326  * Calculate the alternate clock for the CEA mode
3327  * (60Hz vs. 59.94Hz etc.)
3328  */
cea_mode_alternate_clock(const struct drm_display_mode * cea_mode)3329 static unsigned int cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3330 {
3331     unsigned int clock = cea_mode->clock;
3332 
3333     if (drm_mode_vrefresh(cea_mode) % 0x6 != 0) {
3334         return clock;
3335     }
3336 
3337     /*
3338      * edid_cea_modes contains the 59.94Hz
3339      * variant for 240 and 480 line modes,
3340      * and the 60Hz variant otherwise.
3341      */
3342     if (cea_mode->vdisplay == 0xf0 || cea_mode->vdisplay == 0x1e0) {
3343         clock = DIV_ROUND_CLOSEST(clock * 0x3e9, 0x3e8);
3344     } else {
3345         clock = DIV_ROUND_CLOSEST(clock * 0x3e8, 0x3e9);
3346     }
3347 
3348     return clock;
3349 }
3350 
cea_mode_alternate_timings(u8 vic,struct drm_display_mode * mode)3351 static bool cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3352 {
3353     /*
3354      * For certain VICs the spec allows the vertical
3355      * front porch to vary by one or two lines.
3356      *
3357      * cea_modes[] stores the variant with the shortest
3358      * vertical front porch. We can adjust the mode to
3359      * get the other variants by simply increasing the
3360      * vertical front porch length.
3361      */
3362     BUILD_BUG_ON(cea_mode_for_vic(0x8)->vtotal != 0x106 || cea_mode_for_vic(0x9)->vtotal != 0x106 ||
3363                  cea_mode_for_vic(0xc)->vtotal != 0x106 || cea_mode_for_vic(0xd)->vtotal != 0x106 ||
3364                  cea_mode_for_vic(0x17)->vtotal != 0x138 || cea_mode_for_vic(0x18)->vtotal != 0x138 ||
3365                  cea_mode_for_vic(0x1b)->vtotal != 0x138 || cea_mode_for_vic(0x1c)->vtotal != 0x138);
3366 
3367     if (((vic == 0x8 || vic == 0x9 || vic == 0xc || vic == 0xd) && mode->vtotal < 0x107) ||
3368         ((vic == 0x17 || vic == 0x18 || vic == 0x1b || vic == 0x1c) && mode->vtotal < 0x13a)) {
3369         mode->vsync_start++;
3370         mode->vsync_end++;
3371         mode->vtotal++;
3372 
3373         return true;
3374     }
3375 
3376     return false;
3377 }
3378 
drm_match_cea_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)3379 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, unsigned int clock_tolerance)
3380 {
3381     unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3382     u8 vic;
3383 
3384     if (!to_match->clock) {
3385         return 0;
3386     }
3387 
3388     if (to_match->picture_aspect_ratio) {
3389         match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3390     }
3391 
3392     for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3393         struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3394         unsigned int clock1, clock2;
3395 
3396         /* Check both 60Hz and 59.94Hz */
3397         clock1 = cea_mode.clock;
3398         clock2 = cea_mode_alternate_clock(&cea_mode);
3399         if (abs(to_match->clock - clock1) > clock_tolerance && abs(to_match->clock - clock2) > clock_tolerance) {
3400             continue;
3401         }
3402 
3403         do {
3404             if (drm_mode_match(to_match, &cea_mode, match_flags)) {
3405                 return vic;
3406             }
3407         } while (cea_mode_alternate_timings(vic, &cea_mode));
3408     }
3409 
3410     return 0;
3411 }
3412 
3413 /**
3414  * drm_match_cea_mode - look for a CEA mode matching given mode
3415  * @to_match: display mode
3416  *
3417  * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3418  * mode.
3419  */
drm_match_cea_mode(const struct drm_display_mode * to_match)3420 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3421 {
3422     unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3423     u8 vic;
3424 
3425     if (!to_match->clock) {
3426         return 0;
3427     }
3428 
3429     if (to_match->picture_aspect_ratio) {
3430         match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3431     }
3432 
3433     for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3434         struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3435         unsigned int clock1, clock2;
3436 
3437         /* Check both 60Hz and 59.94Hz */
3438         clock1 = cea_mode.clock;
3439         clock2 = cea_mode_alternate_clock(&cea_mode);
3440         if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) {
3441             continue;
3442         }
3443 
3444         do {
3445             if (drm_mode_match(to_match, &cea_mode, match_flags)) {
3446                 return vic;
3447             }
3448         } while (cea_mode_alternate_timings(vic, &cea_mode));
3449     }
3450 
3451     return 0;
3452 }
3453 EXPORT_SYMBOL(drm_match_cea_mode);
3454 
drm_valid_cea_vic(u8 vic)3455 static bool drm_valid_cea_vic(u8 vic)
3456 {
3457     return cea_mode_for_vic(vic) != NULL;
3458 }
3459 
drm_get_cea_aspect_ratio(const u8 video_code)3460 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3461 {
3462     const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3463 
3464     if (mode) {
3465         return mode->picture_aspect_ratio;
3466     }
3467 
3468     return HDMI_PICTURE_ASPECT_NONE;
3469 }
3470 
drm_get_hdmi_aspect_ratio(const u8 video_code)3471 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3472 {
3473     return edid_4k_modes[video_code].picture_aspect_ratio;
3474 }
3475 
3476 /*
3477  * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3478  * specific block).
3479  */
hdmi_mode_alternate_clock(const struct drm_display_mode * hdmi_mode)3480 static unsigned int hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3481 {
3482     return cea_mode_alternate_clock(hdmi_mode);
3483 }
3484 
drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)3485 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, unsigned int clock_tolerance)
3486 {
3487     unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3488     u8 vic;
3489 
3490     if (!to_match->clock) {
3491         return 0;
3492     }
3493 
3494     if (to_match->picture_aspect_ratio) {
3495         match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3496     }
3497 
3498     for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3499         const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3500         unsigned int clock1, clock2;
3501 
3502         /* Make sure to also match alternate clocks */
3503         clock1 = hdmi_mode->clock;
3504         clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3505         if (abs(to_match->clock - clock1) > clock_tolerance && abs(to_match->clock - clock2) > clock_tolerance) {
3506             continue;
3507         }
3508 
3509         if (drm_mode_match(to_match, hdmi_mode, match_flags)) {
3510             return vic;
3511         }
3512     }
3513 
3514     return 0;
3515 }
3516 
3517 /*
3518  * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3519  * @to_match: display mode
3520  *
3521  * An HDMI mode is one defined in the HDMI vendor specific block.
3522  *
3523  * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3524  */
drm_match_hdmi_mode(const struct drm_display_mode * to_match)3525 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3526 {
3527     unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3528     u8 vic;
3529 
3530     if (!to_match->clock) {
3531         return 0;
3532     }
3533 
3534     if (to_match->picture_aspect_ratio) {
3535         match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3536     }
3537 
3538     for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3539         const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3540         unsigned int clock1, clock2;
3541 
3542         /* Make sure to also match alternate clocks */
3543         clock1 = hdmi_mode->clock;
3544         clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3545         if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3546             drm_mode_match(to_match, hdmi_mode, match_flags)) {
3547             return vic;
3548         }
3549     }
3550     return 0;
3551 }
3552 
drm_valid_hdmi_vic(u8 vic)3553 static bool drm_valid_hdmi_vic(u8 vic)
3554 {
3555     return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3556 }
3557 
add_alternate_cea_modes(struct drm_connector * connector,struct edid * edid)3558 static int add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3559 {
3560     struct drm_device *dev = connector->dev;
3561     struct drm_display_mode *mode, *tmp;
3562     LIST_HEAD(list);
3563     int modes = 0;
3564 
3565     /* Don't add CEA modes if the CEA extension block is missing */
3566     if (!drm_find_cea_extension(edid)) {
3567         return 0;
3568     }
3569 
3570     /*
3571      * Go through all probed modes and create a new mode
3572      * with the alternate clock for certain CEA modes.
3573      */
3574     list_for_each_entry(mode, &connector->probed_modes, head)
3575     {
3576         const struct drm_display_mode *cea_mode = NULL;
3577         struct drm_display_mode *newmode;
3578         u8 vic = drm_match_cea_mode(mode);
3579         unsigned int clock1, clock2;
3580 
3581         if (drm_valid_cea_vic(vic)) {
3582             cea_mode = cea_mode_for_vic(vic);
3583             clock2 = cea_mode_alternate_clock(cea_mode);
3584         } else {
3585             vic = drm_match_hdmi_mode(mode);
3586             if (drm_valid_hdmi_vic(vic)) {
3587                 cea_mode = &edid_4k_modes[vic];
3588                 clock2 = hdmi_mode_alternate_clock(cea_mode);
3589             }
3590         }
3591 
3592         if (!cea_mode) {
3593             continue;
3594         }
3595 
3596         clock1 = cea_mode->clock;
3597 
3598         if (clock1 == clock2) {
3599             continue;
3600         }
3601 
3602         if (mode->clock != clock1 && mode->clock != clock2) {
3603             continue;
3604         }
3605 
3606         newmode = drm_mode_duplicate(dev, cea_mode);
3607         if (!newmode) {
3608             continue;
3609         }
3610 
3611         /* Carry over the stereo flags */
3612         newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3613 
3614         /*
3615          * The current mode could be either variant. Make
3616          * sure to pick the "other" clock for the new mode.
3617          */
3618         if (mode->clock != clock1) {
3619             newmode->clock = clock1;
3620         } else {
3621             newmode->clock = clock2;
3622         }
3623 
3624         list_add_tail(&newmode->head, &list);
3625     }
3626 
3627     list_for_each_entry_safe(mode, tmp, &list, head)
3628     {
3629         list_del(&mode->head);
3630         drm_mode_probed_add(connector, mode);
3631         modes++;
3632     }
3633 
3634     return modes;
3635 }
3636 
svd_to_vic(u8 svd)3637 static u8 svd_to_vic(u8 svd)
3638 {
3639     /* 0-6 bit vic, 7th bit native mode indicator */
3640     if ((svd >= 0x1 && svd <= 0x40) || (svd >= 0x81 && svd <= 0xc0)) {
3641         return svd & 0x7f;
3642     }
3643 
3644     return svd;
3645 }
3646 
drm_display_mode_from_vic_index(struct drm_connector * connector,const u8 * video_db,u8 video_len,u8 video_index)3647 static struct drm_display_mode *drm_display_mode_from_vic_index(struct drm_connector *connector, const u8 *video_db,
3648                                                                 u8 video_len, u8 video_index)
3649 {
3650     struct drm_device *dev = connector->dev;
3651     struct drm_display_mode *newmode;
3652     u8 vic;
3653 
3654     if (video_db == NULL || video_index >= video_len) {
3655         return NULL;
3656     }
3657 
3658     /* CEA modes are numbered 1..127 */
3659     vic = svd_to_vic(video_db[video_index]);
3660     if (!drm_valid_cea_vic(vic)) {
3661         return NULL;
3662     }
3663 
3664     newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3665     if (!newmode) {
3666         return NULL;
3667     }
3668 
3669     return newmode;
3670 }
3671 
3672 /*
3673  * do_y420vdb_modes - Parse YCBCR 420 only modes
3674  * @connector: connector corresponding to the HDMI sink
3675  * @svds: start of the data block of CEA YCBCR 420 VDB
3676  * @len: length of the CEA YCBCR 420 VDB
3677  *
3678  * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3679  * which contains modes which can be supported in YCBCR 420
3680  * output format only.
3681  */
do_y420vdb_modes(struct drm_connector * connector,const u8 * svds,u8 svds_len)3682 static int do_y420vdb_modes(struct drm_connector *connector, const u8 *svds, u8 svds_len)
3683 {
3684     int modes = 0, i;
3685     struct drm_device *dev = connector->dev;
3686     struct drm_display_info *info = &connector->display_info;
3687     struct drm_hdmi_info *hdmi = &info->hdmi;
3688 
3689     for (i = 0; i < svds_len; i++) {
3690         u8 vic = svd_to_vic(svds[i]);
3691         struct drm_display_mode *newmode;
3692 
3693         if (!drm_valid_cea_vic(vic)) {
3694             continue;
3695         }
3696 
3697         newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3698         if (!newmode) {
3699             break;
3700         }
3701         bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3702         drm_mode_probed_add(connector, newmode);
3703         modes++;
3704     }
3705 
3706     if (modes > 0) {
3707         info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3708     }
3709     return modes;
3710 }
3711 
3712 /*
3713  * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3714  * @connector: connector corresponding to the HDMI sink
3715  * @vic: CEA vic for the video mode to be added in the map
3716  *
3717  * Makes an entry for a videomode in the YCBCR 420 bitmap
3718  */
drm_add_cmdb_modes(struct drm_connector * connector,u8 svd)3719 static void drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3720 {
3721     u8 vic = svd_to_vic(svd);
3722     struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3723 
3724     if (!drm_valid_cea_vic(vic)) {
3725         return;
3726     }
3727 
3728     bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3729 }
3730 
3731 /**
3732  * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
3733  * @dev: DRM device
3734  * @video_code: CEA VIC of the mode
3735  *
3736  * Creates a new mode matching the specified CEA VIC.
3737  *
3738  * Returns: A new drm_display_mode on success or NULL on failure
3739  */
drm_display_mode_from_cea_vic(struct drm_device * dev,u8 video_code)3740 struct drm_display_mode *drm_display_mode_from_cea_vic(struct drm_device *dev, u8 video_code)
3741 {
3742     const struct drm_display_mode *cea_mode;
3743     struct drm_display_mode *newmode;
3744 
3745     cea_mode = cea_mode_for_vic(video_code);
3746     if (!cea_mode) {
3747         return NULL;
3748     }
3749 
3750     newmode = drm_mode_duplicate(dev, cea_mode);
3751     if (!newmode) {
3752         return NULL;
3753     }
3754 
3755     return newmode;
3756 }
3757 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
3758 
do_cea_modes(struct drm_connector * connector,const u8 * db,u8 len)3759 static int do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3760 {
3761     int i, modes = 0;
3762     struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3763 
3764     for (i = 0; i < len; i++) {
3765         struct drm_display_mode *mode;
3766 
3767         mode = drm_display_mode_from_vic_index(connector, db, len, i);
3768         if (mode) {
3769             /*
3770              * YCBCR420 capability block contains a bitmap which
3771              * gives the index of CEA modes from CEA VDB, which
3772              * can support YCBCR 420 sampling output also (apart
3773              * from RGB/YCBCR444 etc).
3774              * For example, if the bit 0 in bitmap is set,
3775              * first mode in VDB can support YCBCR420 output too.
3776              * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3777              */
3778             if (i < 0x40 && hdmi->y420_cmdb_map & (1ULL << i)) {
3779                 drm_add_cmdb_modes(connector, db[i]);
3780             }
3781 
3782             drm_mode_probed_add(connector, mode);
3783             modes++;
3784         }
3785     }
3786 
3787     return modes;
3788 }
3789 
3790 struct stereo_mandatory_mode {
3791     int width, height, vrefresh;
3792     unsigned int flags;
3793 };
3794 
3795 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3796     {1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM},
3797     {1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING},
3798     {1920, 1080, 50, DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF},
3799     {1920, 1080, 60, DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF},
3800     {1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM},
3801     {1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING},
3802     {1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM},
3803     {1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING}};
3804 
stereo_match_mandatory(const struct drm_display_mode * mode,const struct stereo_mandatory_mode * stereo_mode)3805 static bool stereo_match_mandatory(const struct drm_display_mode *mode, const struct stereo_mandatory_mode *stereo_mode)
3806 {
3807     unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3808 
3809     return mode->hdisplay == stereo_mode->width && mode->vdisplay == stereo_mode->height &&
3810            interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3811            drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3812 }
3813 
add_hdmi_mandatory_stereo_modes(struct drm_connector * connector)3814 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3815 {
3816     struct drm_device *dev = connector->dev;
3817     const struct drm_display_mode *mode;
3818     struct list_head stereo_modes;
3819     int modes = 0, i;
3820 
3821     INIT_LIST_HEAD(&stereo_modes);
3822 
3823     list_for_each_entry(mode, &connector->probed_modes, head)
3824     {
3825         for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3826             const struct stereo_mandatory_mode *mandatory;
3827             struct drm_display_mode *new_mode;
3828 
3829             if (!stereo_match_mandatory(mode, &stereo_mandatory_modes[i])) {
3830                 continue;
3831             }
3832 
3833             mandatory = &stereo_mandatory_modes[i];
3834             new_mode = drm_mode_duplicate(dev, mode);
3835             if (!new_mode) {
3836                 continue;
3837             }
3838 
3839             new_mode->flags |= mandatory->flags;
3840             list_add_tail(&new_mode->head, &stereo_modes);
3841             modes++;
3842         }
3843     }
3844 
3845     list_splice_tail(&stereo_modes, &connector->probed_modes);
3846 
3847     return modes;
3848 }
3849 
add_hdmi_mode(struct drm_connector * connector,u8 vic)3850 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3851 {
3852     struct drm_device *dev = connector->dev;
3853     struct drm_display_mode *newmode;
3854 
3855     if (!drm_valid_hdmi_vic(vic)) {
3856         DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3857         return 0;
3858     }
3859 
3860     newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3861     if (!newmode) {
3862         return 0;
3863     }
3864 
3865     drm_mode_probed_add(connector, newmode);
3866 
3867     return 1;
3868 }
3869 
add_3d_struct_modes(struct drm_connector * connector,u16 structure,const u8 * video_db,u8 video_len,u8 video_index)3870 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, const u8 *video_db, u8 video_len,
3871                                u8 video_index)
3872 {
3873     struct drm_display_mode *newmode;
3874     int modes = 0;
3875 
3876     if (structure & (1 << 0)) {
3877         newmode = drm_display_mode_from_vic_index(connector, video_db, video_len, video_index);
3878         if (newmode) {
3879             newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3880             drm_mode_probed_add(connector, newmode);
3881             modes++;
3882         }
3883     }
3884     if (structure & (1 << 0x6)) {
3885         newmode = drm_display_mode_from_vic_index(connector, video_db, video_len, video_index);
3886         if (newmode) {
3887             newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3888             drm_mode_probed_add(connector, newmode);
3889             modes++;
3890         }
3891     }
3892     if (structure & (1 << 0x8)) {
3893         newmode = drm_display_mode_from_vic_index(connector, video_db, video_len, video_index);
3894         if (newmode) {
3895             newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3896             drm_mode_probed_add(connector, newmode);
3897             modes++;
3898         }
3899     }
3900 
3901     return modes;
3902 }
3903 
3904 /*
3905  * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3906  * @connector: connector corresponding to the HDMI sink
3907  * @db: start of the CEA vendor specific block
3908  * @len: length of the CEA block payload, ie. one can access up to db[len]
3909  *
3910  * Parses the HDMI VSDB looking for modes to add to @connector. This function
3911  * also adds the stereo 3d modes when applicable.
3912  */
do_hdmi_vsdb_modes(struct drm_connector * connector,const u8 * db,u8 len,const u8 * video_db,u8 video_len)3913 static int do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, const u8 *video_db, u8 video_len)
3914 {
3915     struct drm_display_info *info = &connector->display_info;
3916     int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3917     u8 vic_len, hdmi_3d_len = 0;
3918     u16 mask;
3919     u16 structure_all;
3920 
3921     if (len < 0x8) {
3922         goto out;
3923     }
3924 
3925     /* no HDMI_Video_Present */
3926     if (!(db[0x8] & (0x1 << 0x5))) {
3927         goto out;
3928     }
3929 
3930     /* Latency_Fields_Present */
3931     if (db[0x8] & (0x1 << 0x7)) {
3932         offset += 0x2;
3933     }
3934 
3935     /* I_Latency_Fields_Present */
3936     if (db[0x8] & (0x1 << 0x6)) {
3937         offset += 0x2;
3938     }
3939 
3940     /* the declared length is not long enough for the 2 first bytes
3941      * of additional video format capabilities */
3942     if (len < (0x8 + offset + 0x2)) {
3943         goto out;
3944     }
3945 
3946     /* 3D_Present */
3947     offset++;
3948     if (db[0x8 + offset] & (1 << 0x7)) {
3949         modes += add_hdmi_mandatory_stereo_modes(connector);
3950 
3951         /* 3D_Multi_present */
3952         multi_present = (db[0x8 + offset] & 0x60) >> 0x5;
3953     }
3954 
3955     offset++;
3956     vic_len = db[0x8 + offset] >> 0x5;
3957     hdmi_3d_len = db[0x8 + offset] & 0x1f;
3958 
3959     for (i = 0x0; i < vic_len && len >= (0x9 + offset + i); i++) {
3960         u8 vic;
3961 
3962         vic = db[0x9 + offset + i];
3963         modes += add_hdmi_mode(connector, vic);
3964     }
3965     offset += 0x1 + vic_len;
3966 
3967     if (multi_present == 1) {
3968         multi_len = 0x2;
3969     } else if (multi_present == 0x2) {
3970         multi_len = 0x4;
3971     } else {
3972         multi_len = 0x0;
3973     }
3974 
3975     if (len < (0x8 + offset + hdmi_3d_len - 0x1)) {
3976         goto out;
3977     }
3978 
3979     if (hdmi_3d_len < multi_len) {
3980         goto out;
3981     }
3982 
3983     if (multi_present == 0x1 || multi_present == 0x2) {
3984         /* 3D_Structure_ALL */
3985         structure_all = (db[0x8 + offset] << 0x8) | db[0x9 + offset];
3986 
3987         /* check if 3D_MASK is present */
3988         if (multi_present == 0x2) {
3989             mask = (db[0xa + offset] << 0x8) | db[0xb + offset];
3990         } else {
3991             mask = 0xffff;
3992         }
3993 
3994         for (i = 0; i < 0x10; i++) {
3995             if (mask & (1 << i)) {
3996                 modes += add_3d_struct_modes(connector, structure_all, video_db, video_len, i);
3997             }
3998         }
3999     }
4000 
4001     offset += multi_len;
4002 
4003     for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4004         int vic_index;
4005         struct drm_display_mode *newmode = NULL;
4006         unsigned int newflag = 0;
4007         bool detail_present;
4008 
4009         detail_present = ((db[0x8 + offset + i] & 0x0f) > 0x7);
4010 
4011         if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) {
4012             break;
4013         }
4014 
4015         /* 2D_VIC_order_X */
4016         vic_index = db[0x8 + offset + i] >> 0x4;
4017 
4018         /* 3D_Structure_X */
4019         switch (db[0x8 + offset + i] & 0x0f) {
4020             case 0x0:
4021                 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4022                 break;
4023             case 0x6:
4024                 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4025                 break;
4026             case 0x8:
4027                 /* 3D_Detail_X */
4028                 if ((db[0x9 + offset + i] >> 0x4) == 1) {
4029                     newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4030                 }
4031                 break;
4032         }
4033 
4034         if (newflag != 0) {
4035             newmode = drm_display_mode_from_vic_index(connector, video_db, video_len, vic_index);
4036             if (newmode) {
4037                 newmode->flags |= newflag;
4038                 drm_mode_probed_add(connector, newmode);
4039                 modes++;
4040             }
4041         }
4042 
4043         if (detail_present) {
4044             i++;
4045         }
4046     }
4047 
4048 out:
4049     if (modes > 0) {
4050         info->has_hdmi_infoframe = true;
4051     }
4052     return modes;
4053 }
4054 
cea_db_payload_len(const u8 * db)4055 static int cea_db_payload_len(const u8 *db)
4056 {
4057     return db[0] & 0x1f;
4058 }
4059 
cea_db_extended_tag(const u8 * db)4060 static int cea_db_extended_tag(const u8 *db)
4061 {
4062     return db[1];
4063 }
4064 
cea_db_tag(const u8 * db)4065 static int cea_db_tag(const u8 *db)
4066 {
4067     return db[0] >> 0x5;
4068 }
4069 
cea_revision(const u8 * cea)4070 static int cea_revision(const u8 *cea)
4071 {
4072     /*
4073      * this correct for the DispID variant?
4074      * The DispID spec doesn't really specify whether
4075      * this is the revision of the CEA extension or
4076      * the DispID CEA data block. And the only value
4077      * given as an example is 0.
4078      */
4079     return cea[1];
4080 }
4081 
cea_db_offsets(const u8 * cea,int * start,int * end)4082 static int cea_db_offsets(const u8 *cea, int *start, int *end)
4083 {
4084     /* DisplayID CTA extension blocks and top-level CEA EDID
4085      * block header definitions differ in the following bytes:
4086      *   1) Byte 2 of the header specifies length differently,
4087      *   2) Byte 3 is only present in the CEA top level block.
4088      *
4089      * The different definitions for byte 2 follow.
4090      *
4091      * DisplayID CTA extension block defines byte 2 as:
4092      *   Number of payload bytes
4093      *
4094      * CEA EDID block defines byte 2 as:
4095      *   Byte number (decimal) within this block where the 18-byte
4096      *   DTDs begin. If no non-DTD data is present in this extension
4097      *   block, the value should be set to 04h (the byte after next).
4098      *   If set to 00h, there are no DTDs present in this block and
4099      *   no non-DTD data.
4100      */
4101     if (cea[0] == DATA_BLOCK_CTA) {
4102         /*
4103          * for_each_displayid_db() has already verified
4104          * that these stay within expected bounds.
4105          */
4106         *start = 0x3;
4107         *end = *start + cea[0x2];
4108     } else if (cea[0] == CEA_EXT) {
4109         /* Data block offset in CEA extension block */
4110         *start = 0x4;
4111         *end = cea[0x2];
4112         if (*end == 0) {
4113             *end = 0x7f;
4114         }
4115         if (*end < 0x4 || *end > 0x7f) {
4116             return -ERANGE;
4117         }
4118     } else {
4119         return -EOPNOTSUPP;
4120     }
4121 
4122     return 0;
4123 }
4124 
cea_db_is_hdmi_vsdb(const u8 * db)4125 static bool cea_db_is_hdmi_vsdb(const u8 *db)
4126 {
4127     int hdmi_id;
4128 
4129     if (cea_db_tag(db) != VENDOR_BLOCK) {
4130         return false;
4131     }
4132 
4133     if (cea_db_payload_len(db) < 0x5) {
4134         return false;
4135     }
4136 
4137     hdmi_id = db[0x1] | (db[0x2] << 0x8) | (db[0x3] << 0x10);
4138 
4139     return hdmi_id == HDMI_IEEE_OUI;
4140 }
4141 
cea_db_is_hdmi_forum_vsdb(const u8 * db)4142 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4143 {
4144     unsigned int oui;
4145 
4146     if (cea_db_tag(db) != VENDOR_BLOCK) {
4147         return false;
4148     }
4149 
4150     if (cea_db_payload_len(db) < 0x7) {
4151         return false;
4152     }
4153 
4154     oui = (db[0x3] << 0x10) | (db[0x2] << 0x8) | db[0x1];
4155 
4156     return oui == HDMI_FORUM_IEEE_OUI;
4157 }
4158 
cea_db_is_vcdb(const u8 * db)4159 static bool cea_db_is_vcdb(const u8 *db)
4160 {
4161     if (cea_db_tag(db) != USE_EXTENDED_TAG) {
4162         return false;
4163     }
4164 
4165     if (cea_db_payload_len(db) != 0x2) {
4166         return false;
4167     }
4168 
4169     if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) {
4170         return false;
4171     }
4172 
4173     return true;
4174 }
4175 
cea_db_is_y420cmdb(const u8 * db)4176 static bool cea_db_is_y420cmdb(const u8 *db)
4177 {
4178     if (cea_db_tag(db) != USE_EXTENDED_TAG) {
4179         return false;
4180     }
4181 
4182     if (!cea_db_payload_len(db)) {
4183         return false;
4184     }
4185 
4186     if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) {
4187         return false;
4188     }
4189 
4190     return true;
4191 }
4192 
cea_db_is_y420vdb(const u8 * db)4193 static bool cea_db_is_y420vdb(const u8 *db)
4194 {
4195     if (cea_db_tag(db) != USE_EXTENDED_TAG) {
4196         return false;
4197     }
4198 
4199     if (!cea_db_payload_len(db)) {
4200         return false;
4201     }
4202 
4203     if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) {
4204         return false;
4205     }
4206 
4207     return true;
4208 }
4209 
4210 #define for_each_cea_db(cea, i, start, end)                                           \
4211     for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); \
4212         (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4213 
drm_parse_y420cmdb_bitmap(struct drm_connector * connector,const u8 * db)4214 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, const u8 *db)
4215 {
4216     struct drm_display_info *info = &connector->display_info;
4217     struct drm_hdmi_info *hdmi = &info->hdmi;
4218     u8 map_len = cea_db_payload_len(db) - 1;
4219     u8 count;
4220     u64 map = 0;
4221 
4222     if (map_len == 0) {
4223         /* All CEA modes support ycbcr420 sampling also. */
4224         hdmi->y420_cmdb_map = U64_MAX;
4225         info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4226         return;
4227     }
4228 
4229     /*
4230      * This map indicates which of the existing CEA block modes
4231      * from VDB can support YCBCR420 output too. So if bit=0 is
4232      * set, first mode from VDB can support YCBCR420 output too.
4233      * We will parse and keep this map, before parsing VDB itself
4234      * to avoid going through the same block again and again.
4235      *
4236      * Spec is not clear about max possible size of this block.
4237      * Clamping max bitmap block size at 8 bytes. Every byte can
4238      * address 8 CEA modes, in this way this map can address
4239      * 8*8 = first 64 SVDs.
4240      */
4241     if (WARN_ON_ONCE(map_len > 0x8)) {
4242         map_len = 0x8;
4243     }
4244 
4245     for (count = 0; count < map_len; count++) {
4246         map |= (u64)db[0x2 + count] << (0x8 * count);
4247     }
4248 
4249     if (map) {
4250         info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4251     }
4252 
4253     hdmi->y420_cmdb_map = map;
4254 }
4255 
add_cea_modes(struct drm_connector * connector,struct edid * edid)4256 static int add_cea_modes(struct drm_connector *connector, struct edid *edid)
4257 {
4258     const u8 *cea = drm_find_cea_extension(edid);
4259     const u8 *db, *hdmi = NULL, *video = NULL;
4260     u8 dbl, hdmi_len, video_len = 0;
4261     int modes = 0;
4262 
4263     if (cea && cea_revision(cea) >= 0x3) {
4264         int i, start, end;
4265 
4266         if (cea_db_offsets(cea, &start, &end)) {
4267             return 0;
4268         }
4269 
4270         for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); \
4271             (i) += cea_db_payload_len(&(cea)[(i)]) + 1) {
4272             db = &cea[i];
4273             dbl = cea_db_payload_len(db);
4274 
4275             if (cea_db_tag(db) == VIDEO_BLOCK) {
4276                 video = db + 1;
4277                 video_len = dbl;
4278                 modes += do_cea_modes(connector, video, dbl);
4279             } else if (cea_db_is_hdmi_vsdb(db)) {
4280                 hdmi = db;
4281                 hdmi_len = dbl;
4282             } else if (cea_db_is_y420vdb(db)) {
4283                 const u8 *vdb420 = &db[0x2];
4284 
4285                 /* Add 4:2:0(only) modes present in EDID */
4286                 modes += do_y420vdb_modes(connector, vdb420, dbl - 1);
4287             }
4288         }
4289     }
4290 
4291     /*
4292      * We parse the HDMI VSDB after having added the cea modes as we will
4293      * be patching their flags when the sink supports stereo 3D.
4294      */
4295     if (hdmi) {
4296         modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, video_len);
4297     }
4298 
4299     return modes;
4300 }
4301 
fixup_detailed_cea_mode_clock(struct drm_display_mode * mode)4302 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4303 {
4304     const struct drm_display_mode *cea_mode;
4305     int clock1, clock2, clock;
4306     u8 vic;
4307     const char *type;
4308 
4309     /*
4310      * allow 5kHz clock difference either way to account for
4311      * the 10kHz clock resolution limit of detailed timings.
4312      */
4313     vic = drm_match_cea_mode_clock_tolerance(mode, 0x5);
4314     if (drm_valid_cea_vic(vic)) {
4315         type = "CEA";
4316         cea_mode = cea_mode_for_vic(vic);
4317         clock1 = cea_mode->clock;
4318         clock2 = cea_mode_alternate_clock(cea_mode);
4319     } else {
4320         vic = drm_match_hdmi_mode_clock_tolerance(mode, 0x5);
4321         if (drm_valid_hdmi_vic(vic)) {
4322             type = "HDMI";
4323             cea_mode = &edid_4k_modes[vic];
4324             clock1 = cea_mode->clock;
4325             clock2 = hdmi_mode_alternate_clock(cea_mode);
4326         } else {
4327             return;
4328         }
4329     }
4330 
4331     /* pick whichever is closest */
4332     if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) {
4333         clock = clock1;
4334     } else {
4335         clock = clock2;
4336     }
4337 
4338     if (mode->clock == clock) {
4339         return;
4340     }
4341 
4342     DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", type, vic, mode->clock, clock);
4343     mode->clock = clock;
4344 }
4345 
cea_db_is_hdmi_hdr_metadata_block(const u8 * db)4346 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4347 {
4348     if (cea_db_tag(db) != USE_EXTENDED_TAG) {
4349         return false;
4350     }
4351 
4352     if (db[1] != HDR_STATIC_METADATA_BLOCK) {
4353         return false;
4354     }
4355 
4356     if (cea_db_payload_len(db) < 0x3) {
4357         return false;
4358     }
4359 
4360     return true;
4361 }
4362 
eotf_supported(const u8 * edid_ext)4363 static uint8_t eotf_supported(const u8 *edid_ext)
4364 {
4365     return edid_ext[2] & (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
4366                           BIT(HDMI_EOTF_SMPTE_ST2084) | BIT(HDMI_EOTF_BT_2100_HLG));
4367 }
4368 
hdr_metadata_type(const u8 * edid_ext)4369 static uint8_t hdr_metadata_type(const u8 *edid_ext)
4370 {
4371     return edid_ext[3] & BIT(HDMI_STATIC_METADATA_TYPE1);
4372 }
4373 
drm_parse_hdr_metadata_block(struct drm_connector * connector,const u8 * db)4374 static void drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4375 {
4376     u16 len;
4377 
4378     len = cea_db_payload_len(db);
4379 
4380     connector->hdr_sink_metadata.hdmi_type1.eotf = eotf_supported(db);
4381     connector->hdr_sink_metadata.hdmi_type1.metadata_type = hdr_metadata_type(db);
4382 
4383     if (len >= 0x4) {
4384         connector->hdr_sink_metadata.hdmi_type1.max_cll = db[0x4];
4385     }
4386     if (len >= 0x5) {
4387         connector->hdr_sink_metadata.hdmi_type1.max_fall = db[0x5];
4388     }
4389     if (len >= 0x6) {
4390         connector->hdr_sink_metadata.hdmi_type1.min_cll = db[0x6];
4391     }
4392 }
4393 
drm_parse_hdmi_vsdb_audio(struct drm_connector * connector,const u8 * db)4394 static void drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
4395 {
4396     u8 len = cea_db_payload_len(db);
4397     if (len >= 0x6 && (db[0x6] & (1 << 0x7))) {
4398         connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
4399     }
4400     if (len >= 0x8) {
4401         connector->latency_present[0] = db[0x8] >> 0x7;
4402         connector->latency_present[1] = (db[0x8] >> 0x6) & 1;
4403     }
4404     if (len >= 0x9) {
4405         connector->video_latency[0] = db[0x9];
4406     }
4407     if (len >= 0xa) {
4408         connector->audio_latency[0] = db[0xa];
4409     }
4410     if (len >= 0xb) {
4411         connector->video_latency[1] = db[0xb];
4412     }
4413     if (len >= 0xc) {
4414         connector->audio_latency[1] = db[0xc];
4415     }
4416 
4417     DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4418                   "video latency %d %d, "
4419                   "audio latency %d %d\n",
4420                   connector->latency_present[0], connector->latency_present[1], connector->video_latency[0],
4421                   connector->video_latency[1], connector->audio_latency[0], connector->audio_latency[1]);
4422 }
4423 
monitor_name(struct detailed_timing * t,void * data)4424 static void monitor_name(struct detailed_timing *t, void *data)
4425 {
4426     if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME)) {
4427         return;
4428     }
4429 
4430     *(u8 **)data = t->data.other_data.data.str.str;
4431 }
4432 
get_monitor_name(struct edid * edid,char name[13])4433 static int get_monitor_name(struct edid *edid, char name[13])
4434 {
4435     char *edid_name = NULL;
4436     int mnl;
4437 
4438     if (!edid || !name) {
4439         return 0;
4440     }
4441 
4442     drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4443     for (mnl = 0; edid_name && mnl < 0xd; mnl++) {
4444         if (edid_name[mnl] == 0x0a) {
4445             break;
4446         }
4447 
4448         name[mnl] = edid_name[mnl];
4449     }
4450 
4451     return mnl;
4452 }
4453 
4454 /**
4455  * drm_edid_get_monitor_name - fetch the monitor name from the edid
4456  * @edid: monitor EDID information
4457  * @name: pointer to a character array to hold the name of the monitor
4458  * @bufsize: The size of the name buffer (should be at least 14 chars.)
4459  *
4460  */
drm_edid_get_monitor_name(struct edid * edid,char * name,int bufsize)4461 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4462 {
4463     int name_length;
4464     char buf[0xd];
4465 
4466     if (bufsize <= 0) {
4467         return;
4468     }
4469 
4470     name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4471     memcpy(name, buf, name_length);
4472     name[name_length] = '\0';
4473 }
4474 EXPORT_SYMBOL(drm_edid_get_monitor_name);
4475 
clear_eld(struct drm_connector * connector)4476 static void clear_eld(struct drm_connector *connector)
4477 {
4478     memset(connector->eld, 0, sizeof(connector->eld));
4479 
4480     connector->latency_present[0] = false;
4481     connector->latency_present[1] = false;
4482     connector->video_latency[0] = 0;
4483     connector->audio_latency[0] = 0;
4484     connector->video_latency[1] = 0;
4485     connector->audio_latency[1] = 0;
4486 }
4487 
4488 /*
4489  * drm_edid_to_eld - build ELD from EDID
4490  * @connector: connector corresponding to the HDMI/DP sink
4491  * @edid: EDID to parse
4492  *
4493  * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4494  * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4495  */
drm_edid_to_eld(struct drm_connector * connector,struct edid * edid)4496 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
4497 {
4498     uint8_t *eld = connector->eld;
4499     u8 *cea;
4500     u8 *db;
4501     int total_sad_count = 0;
4502     int mnl;
4503     int dbl;
4504 
4505     clear_eld(connector);
4506 
4507     if (!edid) {
4508         return;
4509     }
4510 
4511     cea = drm_find_cea_extension(edid);
4512     if (!cea) {
4513         DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4514         return;
4515     }
4516 
4517     mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4518     DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4519 
4520     eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4521     eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4522 
4523     eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4524 
4525     eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4526     eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4527     eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4528     eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4529 
4530     if (cea_revision(cea) >= 0x3) {
4531         int i, start, end;
4532         int sad_count;
4533 
4534         if (cea_db_offsets(cea, &start, &end)) {
4535             start = 0;
4536             end = 0;
4537         }
4538 
4539         for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); \
4540             (i) += cea_db_payload_len(&(cea)[(i)]) + 1) {
4541             db = &cea[i] ;
4542             dbl = cea_db_payload_len(db);
4543 
4544             switch (cea_db_tag(db)) {
4545                 case AUDIO_BLOCK:
4546                     /* Audio Data Block, contains SADs */
4547                     sad_count = min(dbl / 0x3, 0xf - total_sad_count);
4548                     if (sad_count >= 1) {
4549                         memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], &db[1], sad_count * 0x3);
4550                     }
4551                     total_sad_count += sad_count;
4552                     break;
4553                 case SPEAKER_BLOCK:
4554                     /* Speaker Allocation Data Block */
4555                     if (dbl >= 1) {
4556                         eld[DRM_ELD_SPEAKER] = db[1];
4557                     }
4558                     break;
4559                 case VENDOR_BLOCK:
4560                     /* HDMI Vendor-Specific Data Block */
4561                     if (cea_db_is_hdmi_vsdb(db)) {
4562                         drm_parse_hdmi_vsdb_audio(connector, db);
4563                     }
4564                     break;
4565                 default:
4566                     break;
4567             }
4568         }
4569     }
4570     eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4571 
4572     if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4573         connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
4574         eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4575     } else {
4576         eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4577     }
4578 
4579     eld[DRM_ELD_BASELINE_ELD_LEN] = DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 0x4);
4580 
4581     DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", drm_eld_size(eld), total_sad_count);
4582 }
4583 
4584 /**
4585  * drm_edid_to_sad - extracts SADs from EDID
4586  * @edid: EDID to parse
4587  * @sads: pointer that will be set to the extracted SADs
4588  *
4589  * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4590  *
4591  * Note: The returned pointer needs to be freed using kfree().
4592  *
4593  * Return: The number of found SADs or negative number on error.
4594  */
drm_edid_to_sad(struct edid * edid,struct cea_sad ** sads)4595 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4596 {
4597     int count = 0;
4598     int i, start, end, dbl;
4599     u8 *cea;
4600 
4601     cea = drm_find_cea_extension(edid);
4602     if (!cea) {
4603         DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4604         return 0;
4605     }
4606 
4607     if (cea_revision(cea) < 0x3) {
4608         DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4609         return 0;
4610     }
4611 
4612     if (cea_db_offsets(cea, &start, &end)) {
4613         DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4614         return -EPROTO;
4615     }
4616 
4617     for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); \
4618         (i) += cea_db_payload_len(&(cea)[(i)]) + 1) {
4619         u8 *db = &cea[i];
4620         if (cea_db_tag(db) == AUDIO_BLOCK) {
4621             int j;
4622 
4623             dbl = cea_db_payload_len(db);
4624 
4625             count = dbl / 0x3; /* SAD is 3B */
4626             *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4627             if (!*sads) {
4628                 return -ENOMEM;
4629             }
4630             for (j = 0; j < count; j++) {
4631                 u8 *sad = &db[1 + j * 0x3];
4632 
4633                 (*sads)[j].format = (sad[0] & 0x78) >> 0x3;
4634                 (*sads)[j].channels = sad[0] & 0x7;
4635                 (*sads)[j].freq = sad[0x1] & 0x7F;
4636                 (*sads)[j].byte2 = sad[0x2];
4637             }
4638             break;
4639         }
4640     }
4641 
4642     return count;
4643 }
4644 EXPORT_SYMBOL(drm_edid_to_sad);
4645 
4646 /**
4647  * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4648  * @edid: EDID to parse
4649  * @sadb: pointer to the speaker block
4650  *
4651  * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4652  *
4653  * Note: The returned pointer needs to be freed using kfree().
4654  *
4655  * Return: The number of found Speaker Allocation Blocks or negative number on
4656  * error.
4657  */
drm_edid_to_speaker_allocation(struct edid * edid,u8 ** sadb)4658 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4659 {
4660     int count = 0;
4661     int i, start, end, dbl;
4662     const u8 *cea;
4663 
4664     cea = drm_find_cea_extension(edid);
4665     if (!cea) {
4666         DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4667         return 0;
4668     }
4669 
4670     if (cea_revision(cea) < 0x3) {
4671         DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4672         return 0;
4673     }
4674 
4675     if (cea_db_offsets(cea, &start, &end)) {
4676         DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4677         return -EPROTO;
4678     }
4679 
4680     for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); \
4681         (i) += cea_db_payload_len(&(cea)[(i)]) + 1) {
4682         const u8 *db = &cea[i];
4683 
4684         if (cea_db_tag(db) == SPEAKER_BLOCK) {
4685             dbl = cea_db_payload_len(db);
4686             /* Speaker Allocation Data Block */
4687             if (dbl == 0x3) {
4688                 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4689                 if (!*sadb) {
4690                     return -ENOMEM;
4691                 }
4692                 count = dbl;
4693                 break;
4694             }
4695         }
4696     }
4697 
4698     return count;
4699 }
4700 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4701 
4702 /**
4703  * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4704  * @connector: connector associated with the HDMI/DP sink
4705  * @mode: the display mode
4706  *
4707  * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4708  * the sink doesn't support audio or video.
4709  */
drm_av_sync_delay(struct drm_connector * connector,const struct drm_display_mode * mode)4710 int drm_av_sync_delay(struct drm_connector *connector, const struct drm_display_mode *mode)
4711 {
4712     int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4713     int a, v;
4714 
4715     if (!connector->latency_present[0]) {
4716         return 0;
4717     }
4718     if (!connector->latency_present[1]) {
4719         i = 0;
4720     }
4721 
4722     a = connector->audio_latency[i];
4723     v = connector->video_latency[i];
4724 
4725     /*
4726      * HDMI/DP sink doesn't support audio or video?
4727      */
4728     if (a == 0xff || v == 0xff) {
4729         return 0;
4730     }
4731 
4732     /*
4733      * Convert raw EDID values to millisecond.
4734      * Treat unknown latency as 0ms.
4735      */
4736     if (a) {
4737         a = min(0x2 * (a - 1), 0x1f4);
4738     }
4739     if (v) {
4740         v = min(0x2 * (v - 1), 0x1f4);
4741     }
4742 
4743     return max(v - a, 0);
4744 }
4745 EXPORT_SYMBOL(drm_av_sync_delay);
4746 
4747 /**
4748  * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4749  * @edid: monitor EDID information
4750  *
4751  * Parse the CEA extension according to CEA-861-B.
4752  *
4753  * Drivers that have added the modes parsed from EDID to drm_display_info
4754  * should use &drm_display_info.is_hdmi instead of calling this function.
4755  *
4756  * Return: True if the monitor is HDMI, false if not or unknown.
4757  */
drm_detect_hdmi_monitor(struct edid * edid)4758 bool drm_detect_hdmi_monitor(struct edid *edid)
4759 {
4760     u8 *edid_ext;
4761     int i;
4762     int start_offset, end_offset;
4763 
4764     edid_ext = drm_find_cea_extension(edid);
4765     if (!edid_ext) {
4766         return false;
4767     }
4768 
4769     if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) {
4770         return false;
4771     }
4772 
4773     /*
4774      * Because HDMI identifier is in Vendor Specific Block,
4775      * search it from all data blocks of CEA extension.
4776      */
4777     for ((i) = (start_offset); (i) < (end_offset) && (i) + cea_db_payload_len(&(edid_ext)[(i)]) < (end_offset); \
4778         (i) += cea_db_payload_len(&(edid_ext)[(i)]) + 1) {
4779         if (cea_db_is_hdmi_vsdb(&edid_ext[i])) {
4780             return true;
4781         }
4782     }
4783 
4784     return false;
4785 }
4786 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4787 
4788 /**
4789  * drm_detect_monitor_audio - check monitor audio capability
4790  * @edid: EDID block to scan
4791  *
4792  * Monitor should have CEA extension block.
4793  * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4794  * audio' only. If there is any audio extension block and supported
4795  * audio format, assume at least 'basic audio' support, even if 'basic
4796  * audio' is not defined in EDID.
4797  *
4798  * Return: True if the monitor supports audio, false otherwise.
4799  */
drm_detect_monitor_audio(struct edid * edid)4800 bool drm_detect_monitor_audio(struct edid *edid)
4801 {
4802     u8 *edid_ext;
4803     int i, j;
4804     bool has_audio = false;
4805     int start_offset, end_offset;
4806 
4807     edid_ext = drm_find_cea_extension(edid);
4808     if (!edid_ext) {
4809         goto end;
4810     }
4811 
4812     has_audio = (edid_ext[0] == CEA_EXT &&
4813             (edid_ext[0x3] & EDID_BASIC_AUDIO) != 0);
4814 
4815     if (has_audio) {
4816         DRM_DEBUG_KMS("Monitor has basic audio support\n");
4817         goto end;
4818     }
4819 
4820     if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) {
4821         goto end;
4822     }
4823 
4824     for ((i) = (start_offset); (i) < (end_offset) && (i) + cea_db_payload_len(&(edid_ext)[(i)]) < (end_offset); \
4825         (i) += cea_db_payload_len(&(edid_ext)[(i)]) + 1) {
4826         if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4827             has_audio = true;
4828             for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 0x3) {
4829                 DRM_DEBUG_KMS("CEA audio format %d\n", (edid_ext[i + j] >> 0x3) & 0xf);
4830             }
4831             goto end;
4832         }
4833     }
4834 end:
4835     return has_audio;
4836 }
4837 EXPORT_SYMBOL(drm_detect_monitor_audio);
4838 
4839 /**
4840  * drm_default_rgb_quant_range - default RGB quantization range
4841  * @mode: display mode
4842  *
4843  * Determine the default RGB quantization range for the mode,
4844  * as specified in CEA-861.
4845  *
4846  * Return: The default RGB quantization range for the mode
4847  */
drm_default_rgb_quant_range(const struct drm_display_mode * mode)4848 enum hdmi_quantization_range drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4849 {
4850     /* All CEA modes other than VIC 1 use limited quantization range. */
4851     return drm_match_cea_mode(mode) > 1 ? HDMI_QUANTIZATION_RANGE_LIMITED : HDMI_QUANTIZATION_RANGE_FULL;
4852 }
4853 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4854 
drm_parse_vcdb(struct drm_connector * connector,const u8 * db)4855 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4856 {
4857     struct drm_display_info *info = &connector->display_info;
4858 
4859     DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[0x2]);
4860 
4861     if (db[0x2] & EDID_CEA_VCDB_QS) {
4862         info->rgb_quant_range_selectable = true;
4863     }
4864 }
4865 
4866 #ifdef CONFIG_NO_GKI
drm_get_max_frl_rate(int max_frl_rate,u8 * max_lanes,u8 * max_rate_per_lane)4867 static void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
4868 {
4869     switch (max_frl_rate) {
4870         case 1:
4871             *max_lanes = 0x3;
4872             *max_rate_per_lane = 0x3;
4873             break;
4874         case 0x2:
4875             *max_lanes = 0x3;
4876             *max_rate_per_lane = 0x6;
4877             break;
4878         case 0x3:
4879             *max_lanes = 0x4;
4880             *max_rate_per_lane = 0x6;
4881             break;
4882         case 0x4:
4883             *max_lanes = 0x4;
4884             *max_rate_per_lane = 0x8;
4885             break;
4886         case 0x5:
4887             *max_lanes = 0x4;
4888             *max_rate_per_lane = 0xa;
4889             break;
4890         case 0x6:
4891             *max_lanes = 0x4;
4892             *max_rate_per_lane = 0xc;
4893             break;
4894         case 0:
4895         default:
4896             *max_lanes = 0;
4897             *max_rate_per_lane = 0;
4898     }
4899 }
4900 #endif
4901 
drm_parse_ycbcr420_deep_color_info(struct drm_connector * connector,const u8 * db)4902 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, const u8 *db)
4903 {
4904     u8 dc_mask;
4905     struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4906 
4907     dc_mask = db[0x7] & DRM_EDID_YCBCR420_DC_MASK;
4908     hdmi->y420_dc_modes = dc_mask;
4909 }
4910 
drm_parse_hdmi_forum_vsdb(struct drm_connector * connector,const u8 * hf_vsdb)4911 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, const u8 *hf_vsdb)
4912 {
4913     struct drm_display_info *display = &connector->display_info;
4914     struct drm_hdmi_info *hdmi = &display->hdmi;
4915 
4916     display->has_hdmi_infoframe = true;
4917 
4918     if (hf_vsdb[0x6] & 0x80) {
4919         hdmi->scdc.supported = true;
4920         if (hf_vsdb[0x6] & 0x40) {
4921             hdmi->scdc.read_request = true;
4922         }
4923     }
4924 
4925     /*
4926      * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4927      * And as per the spec, three factors confirm this:
4928      * * Availability of a HF-VSDB block in EDID (check)
4929      * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4930      * * SCDC support available (let's check)
4931      * Lets check it out.
4932      */
4933 
4934     if (hf_vsdb[0x5]) {
4935         /* max clock is 5000 KHz times block value */
4936         u32 max_tmds_clock = hf_vsdb[0x5] * 0x1388;
4937         struct drm_scdc *scdc = &hdmi->scdc;
4938 
4939         if (max_tmds_clock > 0x53020) {
4940             display->max_tmds_clock = max_tmds_clock;
4941             DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", display->max_tmds_clock);
4942         }
4943 
4944         if (scdc->supported) {
4945             scdc->scrambling.supported = true;
4946 
4947             /* Few sinks support scrambling for clocks < 340M */
4948             if ((hf_vsdb[0x6] & 0x8)) {
4949                 scdc->scrambling.low_rates = true;
4950             }
4951         }
4952     }
4953 
4954 #ifdef CONFIG_NO_GKI
4955     if (hf_vsdb[0x7]) {
4956         u8 max_frl_rate;
4957         u8 dsc_max_frl_rate;
4958         u8 dsc_max_slices;
4959         struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
4960 
4961         DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
4962         max_frl_rate = (hf_vsdb[0x7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 0x4;
4963         drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, &hdmi->max_frl_rate_per_lane);
4964         hdmi_dsc->v_1p2 = hf_vsdb[0xb] & DRM_EDID_DSC_1P2;
4965 
4966         if (hdmi_dsc->v_1p2) {
4967             hdmi_dsc->native_420 = hf_vsdb[0xb] & DRM_EDID_DSC_NATIVE_420;
4968             hdmi_dsc->all_bpp = hf_vsdb[0xb] & DRM_EDID_DSC_ALL_BPP;
4969 
4970             if (hf_vsdb[0xb] & DRM_EDID_DSC_16BPC) {
4971                 hdmi_dsc->bpc_supported = 0x10;
4972             } else if (hf_vsdb[0xb] & DRM_EDID_DSC_12BPC) {
4973                 hdmi_dsc->bpc_supported = 0xc;
4974             } else if (hf_vsdb[0xb] & DRM_EDID_DSC_10BPC) {
4975                 hdmi_dsc->bpc_supported = 0xa;
4976             } else {
4977                 hdmi_dsc->bpc_supported = 0x0;
4978             }
4979 
4980             dsc_max_frl_rate = (hf_vsdb[0xc] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 0x4;
4981             drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, &hdmi_dsc->max_frl_rate_per_lane);
4982             hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
4983 
4984             dsc_max_slices = hf_vsdb[0xc] & DRM_EDID_DSC_MAX_SLICES;
4985             switch (dsc_max_slices) {
4986                 case 0x1:
4987                     hdmi_dsc->max_slices = 0x1;
4988                     hdmi_dsc->clk_per_slice = 0x154;
4989                     break;
4990                 case 0x2:
4991                     hdmi_dsc->max_slices = 0x2;
4992                     hdmi_dsc->clk_per_slice = 0x154;
4993                     break;
4994                 case 0x3:
4995                     hdmi_dsc->max_slices = 0x4;
4996                     hdmi_dsc->clk_per_slice = 0x154;
4997                     break;
4998                 case 0x4:
4999                     hdmi_dsc->max_slices = 0x8;
5000                     hdmi_dsc->clk_per_slice = 0x154;
5001                     break;
5002                 case 0x5:
5003                     hdmi_dsc->max_slices = 0x8;
5004                     hdmi_dsc->clk_per_slice = 0x190;
5005                     break;
5006                 case 0x6:
5007                     hdmi_dsc->max_slices = 0xc;
5008                     hdmi_dsc->clk_per_slice = 0x190;
5009                     break;
5010                 case 0x7:
5011                     hdmi_dsc->max_slices = 0x10;
5012                     hdmi_dsc->clk_per_slice = 0x190;
5013                     break;
5014                 case 0x0:
5015                 default:
5016                     hdmi_dsc->max_slices = 0x0;
5017                     hdmi_dsc->clk_per_slice = 0x0;
5018             }
5019         }
5020     }
5021 #endif
5022 
5023     drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
5024 }
5025 
drm_parse_hdmi_deep_color_info(struct drm_connector * connector,const u8 * hdmi)5026 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, const u8 *hdmi)
5027 {
5028     struct drm_display_info *info = &connector->display_info;
5029     unsigned int dc_bpc = 0;
5030 
5031     /* HDMI supports at least 8 bpc */
5032     info->bpc = 0x8;
5033 
5034     if (cea_db_payload_len(hdmi) < 0x6) {
5035         return;
5036     }
5037 
5038     if (hdmi[0x6] & DRM_EDID_HDMI_DC_30) {
5039         dc_bpc = 0xa;
5040         info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
5041         DRM_DEBUG("%s: HDMI sink does deep color 30.\n", connector->name);
5042     }
5043 
5044     if (hdmi[0x6] & DRM_EDID_HDMI_DC_36) {
5045         dc_bpc = 0xc;
5046         info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
5047         DRM_DEBUG("%s: HDMI sink does deep color 36.\n", connector->name);
5048     }
5049 
5050     if (hdmi[0x6] & DRM_EDID_HDMI_DC_48) {
5051         dc_bpc = 0x10;
5052         info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
5053         DRM_DEBUG("%s: HDMI sink does deep color 48.\n", connector->name);
5054     }
5055 
5056     if (dc_bpc == 0) {
5057         DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", connector->name);
5058         return;
5059     }
5060 
5061     DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", connector->name, dc_bpc);
5062     info->bpc = dc_bpc;
5063 
5064     /* YCRCB444 is optional according to spec. */
5065     if (hdmi[0x6] & DRM_EDID_HDMI_DC_Y444) {
5066         DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", connector->name);
5067     }
5068 
5069     /*
5070      * Spec says that if any deep color mode is supported at all,
5071      * then deep color 36 bit must be supported.
5072      */
5073     if (!(hdmi[0x6] & DRM_EDID_HDMI_DC_36)) {
5074         DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", connector->name);
5075     }
5076 }
5077 
drm_parse_hdmi_vsdb_video(struct drm_connector * connector,const u8 * db)5078 static void drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
5079 {
5080     struct drm_display_info *info = &connector->display_info;
5081     u8 len = cea_db_payload_len(db);
5082 
5083     info->is_hdmi = true;
5084 
5085     if (len >= 0x6) {
5086         info->dvi_dual = db[0x6] & 1;
5087     }
5088     if (len >= 0x7) {
5089         info->max_tmds_clock = db[0x7] * 0x1388;
5090     }
5091 
5092     DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5093                   "max TMDS clock %d kHz\n",
5094                   info->dvi_dual, info->max_tmds_clock);
5095 
5096     drm_parse_hdmi_deep_color_info(connector, db);
5097 }
5098 
drm_parse_cea_ext(struct drm_connector * connector,const struct edid * edid)5099 static void drm_parse_cea_ext(struct drm_connector *connector, const struct edid *edid)
5100 {
5101     struct drm_display_info *info = &connector->display_info;
5102     const u8 *edid_ext;
5103     int i, start, end;
5104 
5105     edid_ext = drm_find_cea_extension(edid);
5106     if (!edid_ext) {
5107         return;
5108     }
5109 
5110     info->cea_rev = edid_ext[1];
5111 
5112     /* The existence of a CEA block should imply RGB support */
5113     info->color_formats = DRM_COLOR_FORMAT_RGB444;
5114     if (edid_ext[0x3] & EDID_CEA_YCRCB444) {
5115         info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5116     }
5117     if (edid_ext[0x3] & EDID_CEA_YCRCB422) {
5118         info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
5119     }
5120 
5121     if (cea_db_offsets(edid_ext, &start, &end)) {
5122         return;
5123     }
5124 
5125     for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(edid_ext)[(i)]) < (end);
5126         (i) += cea_db_payload_len(&(edid_ext)[(i)]) + 1) {
5127         const u8 *db = &edid_ext[i];
5128 
5129         if (cea_db_is_hdmi_vsdb(db)) {
5130             drm_parse_hdmi_vsdb_video(connector, db);
5131         }
5132         if (cea_db_is_hdmi_forum_vsdb(db)) {
5133             drm_parse_hdmi_forum_vsdb(connector, db);
5134         }
5135         if (cea_db_is_y420cmdb(db)) {
5136             drm_parse_y420cmdb_bitmap(connector, db);
5137         }
5138         if (cea_db_is_vcdb(db)) {
5139             drm_parse_vcdb(connector, db);
5140         }
5141         if (cea_db_is_hdmi_hdr_metadata_block(db)) {
5142             drm_parse_hdr_metadata_block(connector, db);
5143         }
5144     }
5145 }
5146 
get_monitor_range(struct detailed_timing * timing,void * info_monitor_range)5147 static void get_monitor_range(struct detailed_timing *timing, void *info_monitor_range)
5148 {
5149     struct drm_monitor_range_info *monitor_range = info_monitor_range;
5150     const struct detailed_non_pixel *data = &timing->data.other_data;
5151     const struct detailed_data_monitor_range *range = &data->data.range;
5152 
5153     if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) {
5154         return;
5155     }
5156 
5157     /*
5158      * Check for flag range limits only. If flag == 1 then
5159      * no additional timing information provided.
5160      * Default GTF, GTF Secondary curve and CVT are not
5161      * supported
5162      */
5163     if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) {
5164         return;
5165     }
5166 
5167     monitor_range->min_vfreq = range->min_vfreq;
5168     monitor_range->max_vfreq = range->max_vfreq;
5169 }
5170 
drm_get_monitor_range(struct drm_connector * connector,const struct edid * edid)5171 static void drm_get_monitor_range(struct drm_connector *connector, const struct edid *edid)
5172 {
5173     struct drm_display_info *info = &connector->display_info;
5174 
5175     if (!version_greater(edid, 1, 1)) {
5176         return;
5177     }
5178 
5179     drm_for_each_detailed_block((u8 *)edid, get_monitor_range, &info->monitor_range);
5180 
5181     DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", info->monitor_range.min_vfreq,
5182                   info->monitor_range.max_vfreq);
5183 }
5184 
5185 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5186  * all of the values which would have been set from EDID
5187  */
drm_reset_display_info(struct drm_connector * connector)5188 void drm_reset_display_info(struct drm_connector *connector)
5189 {
5190     struct drm_display_info *info = &connector->display_info;
5191 
5192     info->width_mm = 0;
5193     info->height_mm = 0;
5194 
5195     info->bpc = 0;
5196     info->color_formats = 0;
5197     info->cea_rev = 0;
5198     info->max_tmds_clock = 0;
5199     info->dvi_dual = false;
5200     info->is_hdmi = false;
5201     info->has_hdmi_infoframe = false;
5202     info->rgb_quant_range_selectable = false;
5203     memset(&info->hdmi, 0, sizeof(info->hdmi));
5204 
5205     info->non_desktop = 0;
5206     memset(&info->monitor_range, 0, sizeof(info->monitor_range));
5207 }
5208 
drm_add_display_info(struct drm_connector * connector,const struct edid * edid)5209 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
5210 {
5211     struct drm_display_info *info = &connector->display_info;
5212 
5213     u32 quirks = edid_get_quirks(edid);
5214 
5215     drm_reset_display_info(connector);
5216 
5217     info->width_mm = edid->width_cm * 0xa;
5218     info->height_mm = edid->height_cm * 0xa;
5219 
5220     info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
5221 
5222     drm_get_monitor_range(connector, edid);
5223 
5224     DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
5225 
5226     if (edid->revision < 0x3) {
5227         return quirks;
5228     }
5229 
5230     if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) {
5231         return quirks;
5232     }
5233     info->color_formats |= DRM_COLOR_FORMAT_RGB444;
5234     drm_parse_cea_ext(connector, edid);
5235 
5236     /*
5237      * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5238      *
5239      * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5240      * tells us to assume 8 bpc color depth if the EDID doesn't have
5241      * extensions which tell otherwise.
5242      */
5243     if ((info->bpc == 0x0) && (edid->revision == 0x3) && (edid->input & DRM_EDID_DIGITAL_DFP_1_X)) {
5244         info->bpc = 0x8;
5245         DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", connector->name, info->bpc);
5246     }
5247 
5248     /* Only defined for 1.4 with digital displays */
5249     if (edid->revision < 0x4) {
5250         return quirks;
5251     }
5252 
5253     switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5254         case DRM_EDID_DIGITAL_DEPTH_6:
5255             info->bpc = 0x6;
5256             break;
5257         case DRM_EDID_DIGITAL_DEPTH_8:
5258             info->bpc = 0x8;
5259             break;
5260         case DRM_EDID_DIGITAL_DEPTH_10:
5261             info->bpc = 0xa;
5262             break;
5263         case DRM_EDID_DIGITAL_DEPTH_12:
5264             info->bpc = 0xc;
5265             break;
5266         case DRM_EDID_DIGITAL_DEPTH_14:
5267             info->bpc = 0xe;
5268             break;
5269         case DRM_EDID_DIGITAL_DEPTH_16:
5270             info->bpc = 0x10;
5271             break;
5272         case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5273         default:
5274             info->bpc = 0;
5275             break;
5276     }
5277 
5278     DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", connector->name, info->bpc);
5279 
5280     if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) {
5281         info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5282     }
5283     if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) {
5284         info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
5285     }
5286     return quirks;
5287 }
5288 
validate_displayid(u8 * displayid,int length,int idx)5289 static int validate_displayid(u8 *displayid, int length, int idx)
5290 {
5291     int i, dispid_length;
5292     u8 csum = 0;
5293     struct displayid_hdr *base;
5294 
5295     base = (struct displayid_hdr *)&displayid[idx];
5296 
5297     DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", base->rev, base->bytes, base->prod_id, base->ext_count);
5298 
5299     /* +1 for DispID checksum */
5300     dispid_length = sizeof(*base) + base->bytes + 1;
5301     if (dispid_length > length - idx) {
5302         return -EINVAL;
5303     }
5304 
5305     for (i = 0; i < dispid_length; i++) {
5306         csum += displayid[idx + i];
5307     }
5308     if (csum) {
5309         DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
5310         return -EINVAL;
5311     }
5312 
5313     return 0;
5314 }
5315 
drm_mode_displayid_detailed(struct drm_device * dev,struct displayid_detailed_timings_1 * timings)5316 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
5317                                                             struct displayid_detailed_timings_1 *timings)
5318 {
5319     struct drm_display_mode *mode;
5320     unsigned pixel_clock =
5321         (timings->pixel_clock[0x0] | (timings->pixel_clock[0x1] << 0x8) | (timings->pixel_clock[0x2] << 0x10)) + 1;
5322     unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 0x8) + 1;
5323     unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 0x8) + 1;
5324     unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 0x8) + 1;
5325     unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 0x8) + 1;
5326     unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 0x8) + 1;
5327     unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 0x8) + 1;
5328     unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 0x8) + 1;
5329     unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 0x8) + 1;
5330     bool hsync_positive = (timings->hsync[1] >> 0x7) & 0x1;
5331     bool vsync_positive = (timings->vsync[1] >> 0x7) & 0x1;
5332 
5333     mode = drm_mode_create(dev);
5334     if (!mode) {
5335         return NULL;
5336     }
5337 
5338     mode->clock = pixel_clock * 0xa;
5339     mode->hdisplay = hactive;
5340     mode->hsync_start = mode->hdisplay + hsync;
5341     mode->hsync_end = mode->hsync_start + hsync_width;
5342     mode->htotal = mode->hdisplay + hblank;
5343 
5344     mode->vdisplay = vactive;
5345     mode->vsync_start = mode->vdisplay + vsync;
5346     mode->vsync_end = mode->vsync_start + vsync_width;
5347     mode->vtotal = mode->vdisplay + vblank;
5348 
5349     mode->flags = 0;
5350     mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5351     mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5352     mode->type = DRM_MODE_TYPE_DRIVER;
5353 
5354     if (timings->flags & 0x80) {
5355         mode->type |= DRM_MODE_TYPE_PREFERRED;
5356     }
5357     drm_mode_set_name(mode);
5358 
5359     return mode;
5360 }
5361 
add_displayid_detailed_1_modes(struct drm_connector * connector,struct displayid_block * block)5362 static int add_displayid_detailed_1_modes(struct drm_connector *connector, struct displayid_block *block)
5363 {
5364     struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5365     int i;
5366     int num_timings;
5367     struct drm_display_mode *newmode;
5368     int num_modes = 0;
5369     /* blocks must be multiple of 20 bytes length */
5370     if (block->num_bytes % 0x14) {
5371         return 0;
5372     }
5373 
5374     num_timings = block->num_bytes / 0x14;
5375     for (i = 0; i < num_timings; i++) {
5376         struct displayid_detailed_timings_1 *timings = &det->timings[i];
5377 
5378         newmode = drm_mode_displayid_detailed(connector->dev, timings);
5379         if (!newmode) {
5380             continue;
5381         }
5382 
5383         drm_mode_probed_add(connector, newmode);
5384         num_modes++;
5385     }
5386     return num_modes;
5387 }
5388 
add_displayid_detailed_modes(struct drm_connector * connector,struct edid * edid)5389 static int add_displayid_detailed_modes(struct drm_connector *connector, struct edid *edid)
5390 {
5391     u8 *displayid;
5392     int length, idx;
5393     struct displayid_block *block;
5394     int num_modes = 0;
5395     int ext_index = 0;
5396 
5397     for (;;) {
5398         displayid = drm_find_displayid_extension(edid, &length, &idx, &ext_index);
5399         if (!displayid) {
5400             break;
5401         }
5402 
5403         idx += sizeof(struct displayid_hdr);
5404         for_each_displayid_db(displayid, block, idx, length)
5405         {
5406             switch (block->tag) {
5407                 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5408                     num_modes += add_displayid_detailed_1_modes(connector, block);
5409                     break;
5410                 default:
5411                     break;
5412             }
5413         }
5414     }
5415 
5416     return num_modes;
5417 }
5418 
5419 /**
5420  * drm_add_edid_modes - add modes from EDID data, if available
5421  * @connector: connector we're probing
5422  * @edid: EDID data
5423  *
5424  * Add the specified modes to the connector's mode list. Also fills out the
5425  * &drm_display_info structure and ELD in @connector with any information which
5426  * can be derived from the edid.
5427  *
5428  * Return: The number of modes added or 0 if we couldn't find any.
5429  */
drm_add_edid_modes(struct drm_connector * connector,struct edid * edid)5430 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5431 {
5432     int num_modes = 0;
5433     u32 quirks;
5434 
5435     if (edid == NULL) {
5436         clear_eld(connector);
5437         return 0;
5438     }
5439     if (!drm_edid_is_valid(edid)) {
5440         clear_eld(connector);
5441         drm_warn(connector->dev, "%s: EDID invalid.\n", connector->name);
5442         return 0;
5443     }
5444 
5445     drm_edid_to_eld(connector, edid);
5446 
5447     /*
5448      * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5449      * To avoid multiple parsing of same block, lets parse that map
5450      * from sink info, before parsing CEA modes.
5451      */
5452     quirks = drm_add_display_info(connector, edid);
5453 
5454     /*
5455      * EDID spec says modes should be preferred in this order:
5456      * - preferred detailed mode
5457      * - other detailed modes from base block
5458      * - detailed modes from extension blocks
5459      * - CVT 3-byte code modes
5460      * - standard timing codes
5461      * - established timing codes
5462      * - modes inferred from GTF or CVT range information
5463      *
5464      * We get this pretty much right.
5465      *
5466      * XXX order for additional mode types in extension blocks?
5467      */
5468     num_modes += add_detailed_modes(connector, edid, quirks);
5469     num_modes += add_cvt_modes(connector, edid);
5470     num_modes += add_standard_modes(connector, edid);
5471     num_modes += add_established_modes(connector, edid);
5472     num_modes += add_cea_modes(connector, edid);
5473     num_modes += add_alternate_cea_modes(connector, edid);
5474     num_modes += add_displayid_detailed_modes(connector, edid);
5475     if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) {
5476         num_modes += add_inferred_modes(connector, edid);
5477     }
5478 
5479     if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) {
5480         edid_fixup_preferred(connector, quirks);
5481     }
5482 
5483     if (quirks & EDID_QUIRK_FORCE_6BPC) {
5484         connector->display_info.bpc = 0x6;
5485     }
5486 
5487     if (quirks & EDID_QUIRK_FORCE_8BPC) {
5488         connector->display_info.bpc = 0x8;
5489     }
5490 
5491     if (quirks & EDID_QUIRK_FORCE_10BPC) {
5492         connector->display_info.bpc = 0xa;
5493     }
5494 
5495     if (quirks & EDID_QUIRK_FORCE_12BPC) {
5496         connector->display_info.bpc = 0xc;
5497     }
5498 
5499     return num_modes;
5500 }
5501 EXPORT_SYMBOL(drm_add_edid_modes);
5502 
5503 /**
5504  * drm_add_override_edid_modes - add modes from override/firmware EDID
5505  * @connector: connector we're probing
5506  *
5507  * Add modes from the override/firmware EDID, if available. Only to be used from
5508  * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
5509  * failed during drm_get_edid() and caused the override/firmware EDID to be
5510  * skipped.
5511  *
5512  * Return: The number of modes added or 0 if we couldn't find any.
5513  */
drm_add_override_edid_modes(struct drm_connector * connector)5514 int drm_add_override_edid_modes(struct drm_connector *connector)
5515 {
5516     struct edid *override;
5517     int num_modes = 0;
5518 
5519     override = drm_get_override_edid(connector);
5520     if (override) {
5521         drm_connector_update_edid_property(connector, override);
5522         num_modes = drm_add_edid_modes(connector, override);
5523         kfree(override);
5524 
5525         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", connector->base.id,
5526                       connector->name, num_modes);
5527     }
5528 
5529     return num_modes;
5530 }
5531 EXPORT_SYMBOL(drm_add_override_edid_modes);
5532 
5533 /**
5534  * drm_add_modes_noedid - add modes for the connectors without EDID
5535  * @connector: connector we're probing
5536  * @hdisplay: the horizontal display limit
5537  * @vdisplay: the vertical display limit
5538  *
5539  * Add the specified modes to the connector's mode list. Only when the
5540  * hdisplay/vdisplay is not beyond the given limit, it will be added.
5541  *
5542  * Return: The number of modes added or 0 if we couldn't find any.
5543  */
drm_add_modes_noedid(struct drm_connector * connector,int hdisplay,int vdisplay)5544 int drm_add_modes_noedid(struct drm_connector *connector, int hdisplay, int vdisplay)
5545 {
5546     int i, count, num_modes = 0;
5547     struct drm_display_mode *mode;
5548     struct drm_device *dev = connector->dev;
5549 
5550     count = ARRAY_SIZE(drm_dmt_modes);
5551     if (hdisplay < 0) {
5552         hdisplay = 0;
5553     }
5554     if (vdisplay < 0) {
5555         vdisplay = 0;
5556     }
5557 
5558     for (i = 0; i < count; i++) {
5559         const struct drm_display_mode *ptr = &drm_dmt_modes[i];
5560 
5561         if (hdisplay && vdisplay) {
5562             /*
5563              * Only when two are valid, they will be used to check
5564              * whether the mode should be added to the mode list of
5565              * the connector.
5566              */
5567             if (ptr->hdisplay > hdisplay || ptr->vdisplay > vdisplay) {
5568                 continue;
5569             }
5570         }
5571         if (drm_mode_vrefresh(ptr) > 0x3d) {
5572             continue;
5573         }
5574         mode = drm_mode_duplicate(dev, ptr);
5575         if (mode) {
5576             drm_mode_probed_add(connector, mode);
5577             num_modes++;
5578         }
5579     }
5580     return num_modes;
5581 }
5582 EXPORT_SYMBOL(drm_add_modes_noedid);
5583 
5584 /**
5585  * drm_set_preferred_mode - Sets the preferred mode of a connector
5586  * @connector: connector whose mode list should be processed
5587  * @hpref: horizontal resolution of preferred mode
5588  * @vpref: vertical resolution of preferred mode
5589  *
5590  * Marks a mode as preferred if it matches the resolution specified by @hpref
5591  * and @vpref.
5592  */
drm_set_preferred_mode(struct drm_connector * connector,int hpref,int vpref)5593 void drm_set_preferred_mode(struct drm_connector *connector, int hpref, int vpref)
5594 {
5595     struct drm_display_mode *mode;
5596 
5597     list_for_each_entry(mode, &connector->probed_modes, head)
5598     {
5599         if (mode->hdisplay == hpref && mode->vdisplay == vpref) {
5600             mode->type |= DRM_MODE_TYPE_PREFERRED;
5601         }
5602     }
5603 }
5604 EXPORT_SYMBOL(drm_set_preferred_mode);
5605 
is_hdmi2_sink(const struct drm_connector * connector)5606 static bool is_hdmi2_sink(const struct drm_connector *connector)
5607 {
5608     /*
5609      * sil-sii8620 doesn't have a connector around when
5610      * we need one, so we have to be prepared for a NULL connector.
5611      */
5612     if (!connector) {
5613         return true;
5614     }
5615 
5616     return connector->display_info.hdmi.scdc.supported ||
5617            (connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420);
5618 }
5619 
is_eotf_supported(u8 output_eotf,u8 sink_eotf)5620 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5621 {
5622     return sink_eotf & BIT(output_eotf);
5623 }
5624 
5625 /**
5626  * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5627  *                                         HDR metadata from userspace
5628  * @frame: HDMI DRM infoframe
5629  * @conn_state: Connector state containing HDR metadata
5630  *
5631  * Return: 0 on success or a negative error code on failure.
5632  */
drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe * frame,const struct drm_connector_state * conn_state)5633 int drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, const struct drm_connector_state *conn_state)
5634 {
5635     struct drm_connector *connector;
5636     struct hdr_output_metadata *hdr_metadata;
5637     int err;
5638 
5639     if (!frame || !conn_state) {
5640         return -EINVAL;
5641     }
5642 
5643     connector = conn_state->connector;
5644 
5645     if (!conn_state->hdr_output_metadata) {
5646         return -EINVAL;
5647     }
5648 
5649     hdr_metadata = conn_state->hdr_output_metadata->data;
5650 
5651     if (!hdr_metadata || !connector) {
5652         return -EINVAL;
5653     }
5654 
5655     /* Sink EOTF is Bit map while infoframe is absolute values */
5656     if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5657         DRM_DEBUG_KMS("EOTF Not Supported\n");
5658         return -EINVAL;
5659     }
5660 
5661     err = hdmi_drm_infoframe_init(frame);
5662     if (err < 0) {
5663         return err;
5664     }
5665 
5666     frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5667     frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5668 
5669     BUILD_BUG_ON(sizeof(frame->display_primaries) != sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5670     BUILD_BUG_ON(sizeof(frame->white_point) != sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5671 
5672     memcpy(&frame->display_primaries, &hdr_metadata->hdmi_metadata_type1.display_primaries,
5673            sizeof(frame->display_primaries));
5674 
5675     memcpy(&frame->white_point, &hdr_metadata->hdmi_metadata_type1.white_point, sizeof(frame->white_point));
5676 
5677     frame->max_display_mastering_luminance = hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5678     frame->min_display_mastering_luminance = hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5679     frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5680     frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5681 
5682     return 0;
5683 }
5684 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5685 
drm_mode_hdmi_vic(const struct drm_connector * connector,const struct drm_display_mode * mode)5686 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, const struct drm_display_mode *mode)
5687 {
5688     bool has_hdmi_infoframe = connector ? connector->display_info.has_hdmi_infoframe : false;
5689 
5690     if (!has_hdmi_infoframe) {
5691         return 0;
5692     }
5693 
5694     /* No HDMI VIC when signalling 3D video format */
5695     if (mode->flags & DRM_MODE_FLAG_3D_MASK) {
5696         return 0;
5697     }
5698 
5699     return drm_match_hdmi_mode(mode);
5700 }
5701 
drm_mode_cea_vic(const struct drm_connector * connector,const struct drm_display_mode * mode)5702 static u8 drm_mode_cea_vic(const struct drm_connector *connector, const struct drm_display_mode *mode)
5703 {
5704     u8 vic;
5705 
5706     /*
5707      * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5708      * we should send its VIC in vendor infoframes, else send the
5709      * VIC in AVI infoframes. Lets check if this mode is present in
5710      * HDMI 1.4b 4K modes
5711      */
5712     if (drm_mode_hdmi_vic(connector, mode)) {
5713         return 0;
5714     }
5715 
5716     vic = drm_match_cea_mode(mode);
5717     /*
5718      * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5719      * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5720      * have to make sure we dont break HDMI 1.4 sinks.
5721      */
5722     if (!is_hdmi2_sink(connector) && vic > 0x40) {
5723         return 0;
5724     }
5725 
5726     return vic;
5727 }
5728 
5729 /**
5730  * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5731  *                                              data from a DRM display mode
5732  * @frame: HDMI AVI infoframe
5733  * @connector: the connector
5734  * @mode: DRM display mode
5735  *
5736  * Return: 0 on success or a negative error code on failure.
5737  */
drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode)5738 int drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, const struct drm_connector *connector,
5739                                              const struct drm_display_mode *mode)
5740 {
5741     enum hdmi_picture_aspect picture_aspect;
5742     u8 vic, hdmi_vic;
5743 
5744     if (!frame || !mode) {
5745         return -EINVAL;
5746     }
5747 
5748     hdmi_avi_infoframe_init(frame);
5749 
5750     if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
5751         frame->pixel_repeat = 1;
5752     }
5753 
5754     vic = drm_mode_cea_vic(connector, mode);
5755     hdmi_vic = drm_mode_hdmi_vic(connector, mode);
5756 
5757     frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5758 
5759     /*
5760      * As some drivers don't support atomic, we can't use connector state.
5761      * So just initialize the frame with default values, just the same way
5762      * as it's done with other properties here.
5763      */
5764     frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5765     frame->itc = 0;
5766 
5767     /*
5768      * Populate picture aspect ratio from either
5769      * user input (if specified) or from the CEA/HDMI mode lists.
5770      */
5771     picture_aspect = mode->picture_aspect_ratio;
5772     if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5773         if (vic) {
5774             picture_aspect = drm_get_cea_aspect_ratio(vic);
5775         } else if (hdmi_vic) {
5776             picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5777         }
5778     }
5779 
5780     /*
5781      * The infoframe can't convey anything but none, 4:3
5782      * and 16:9, so if the user has asked for anything else
5783      * we can only satisfy it by specifying the right VIC.
5784      */
5785     if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
5786         if (vic) {
5787             if (picture_aspect != drm_get_cea_aspect_ratio(vic)) {
5788                 return -EINVAL;
5789             }
5790         } else if (hdmi_vic) {
5791             if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) {
5792                 return -EINVAL;
5793             }
5794         } else {
5795             return -EINVAL;
5796         }
5797 
5798         picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5799     }
5800 
5801     frame->video_code = vic;
5802     frame->picture_aspect = picture_aspect;
5803     frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5804     frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
5805 
5806     return 0;
5807 }
5808 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
5809 
5810 /* HDMI Colorspace Spec Definitions */
5811 #define FULL_COLORIMETRY_MASK 0x1FF
5812 #define NORMAL_COLORIMETRY_MASK 0x3
5813 #define EXTENDED_COLORIMETRY_MASK 0x7
5814 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5815 
5816 #define C(x) ((x) << 0)
5817 #define EC(x) ((x) << 2)
5818 #define ACE(x) ((x) << 5)
5819 
5820 #define HDMI_COLORIMETRY_NO_DATA 0x0
5821 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5822 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5823 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5824 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5825 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5826 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5827 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5828 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5829 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5830 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5831 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5832 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5833 
5834 static const u32 hdmi_colorimetry_val[] = {
5835     [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5836     [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5837     [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5838     [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5839     [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5840     [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5841     [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5842     [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5843     [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5844     [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5845     [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5846 };
5847 
5848 #undef C
5849 #undef EC
5850 #undef ACE
5851 
5852 /**
5853  * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5854  *                                       colorspace information
5855  * @frame: HDMI AVI infoframe
5856  * @conn_state: connector state
5857  */
drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe * frame,const struct drm_connector_state * conn_state)5858 void drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, const struct drm_connector_state *conn_state)
5859 {
5860     u32 colorimetry_val;
5861     u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5862 
5863     if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) {
5864         colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5865     } else {
5866         colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5867     }
5868 
5869     frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5870     /*
5871      * Extend it for ACE formats as well. Modify the infoframe
5872      * structure and extend it in drivers/video/hdmi
5873      */
5874     frame->extended_colorimetry = (colorimetry_val >> 0x2) & EXTENDED_COLORIMETRY_MASK;
5875 }
5876 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5877 
5878 /**
5879  * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5880  *                                        quantization range information
5881  * @frame: HDMI AVI infoframe
5882  * @connector: the connector
5883  * @mode: DRM display mode
5884  * @rgb_quant_range: RGB quantization range (Q)
5885  */
drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode,enum hdmi_quantization_range rgb_quant_range)5886 void drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, const struct drm_connector *connector,
5887                                         const struct drm_display_mode *mode,
5888                                         enum hdmi_quantization_range rgb_quant_range)
5889 {
5890     const struct drm_display_info *info = &connector->display_info;
5891 
5892     /*
5893      * CEA-861:
5894      * "A Source shall not send a non-zero Q value that does not correspond
5895      *  to the default RGB Quantization Range for the transmitted Picture
5896      *  unless the Sink indicates support for the Q bit in a Video
5897      *  Capabilities Data Block."
5898      *
5899      * HDMI 2.0 recommends sending non-zero Q when it does match the
5900      * default RGB quantization range for the mode, even when QS=0.
5901      */
5902     if (info->rgb_quant_range_selectable || rgb_quant_range == drm_default_rgb_quant_range(mode)) {
5903         frame->quantization_range = rgb_quant_range;
5904     } else {
5905         frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5906     }
5907 
5908     /*
5909      * CEA-861-F:
5910      * "When transmitting any RGB colorimetry, the Source should set the
5911      *  YQ-field to match the RGB Quantization Range being transmitted
5912      *  (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5913      *  set YQ=1) and the Sink shall ignore the YQ-field."
5914      *
5915      * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5916      * by non-zero YQ when receiving RGB. There doesn't seem to be any
5917      * good way to tell which version of CEA-861 the sink supports, so
5918      * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5919      * on on CEA-861-F.
5920      */
5921     if (!is_hdmi2_sink(connector) || rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) {
5922         frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5923     } else {
5924         frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_FULL;
5925     }
5926 }
5927 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5928 
5929 /**
5930  * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
5931  *                                 bar information
5932  * @frame: HDMI AVI infoframe
5933  * @conn_state: connector state
5934  */
drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe * frame,const struct drm_connector_state * conn_state)5935 void drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, const struct drm_connector_state *conn_state)
5936 {
5937     frame->right_bar = conn_state->tv.margins.right;
5938     frame->left_bar = conn_state->tv.margins.left;
5939     frame->top_bar = conn_state->tv.margins.top;
5940     frame->bottom_bar = conn_state->tv.margins.bottom;
5941 }
5942 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
5943 
s3d_structure_from_display_mode(const struct drm_display_mode * mode)5944 static enum hdmi_3d_structure s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5945 {
5946     u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5947 
5948     switch (layout) {
5949         case DRM_MODE_FLAG_3D_FRAME_PACKING:
5950             return HDMI_3D_STRUCTURE_FRAME_PACKING;
5951         case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5952             return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5953         case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5954             return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5955         case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5956             return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5957         case DRM_MODE_FLAG_3D_L_DEPTH:
5958             return HDMI_3D_STRUCTURE_L_DEPTH;
5959         case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5960             return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5961         case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5962             return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5963         case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5964             return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5965         default:
5966             return HDMI_3D_STRUCTURE_INVALID;
5967     }
5968 }
5969 
5970 /**
5971  * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5972  * data from a DRM display mode
5973  * @frame: HDMI vendor infoframe
5974  * @connector: the connector
5975  * @mode: DRM display mode
5976  *
5977  * Note that there's is a need to send HDMI vendor infoframes only when using a
5978  * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5979  * function will return -EINVAL, error that can be safely ignored.
5980  *
5981  * Return: 0 on success or a negative error code on failure.
5982  */
drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode)5983 int drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5984                                                 const struct drm_connector *connector,
5985                                                 const struct drm_display_mode *mode)
5986 {
5987     /*
5988      * sil-sii8620 doesn't have a connector around when
5989      * we need one, so we have to be prepared for a NULL connector.
5990      */
5991     bool has_hdmi_infoframe = connector ? connector->display_info.has_hdmi_infoframe : false;
5992     int err;
5993 
5994     if (!frame || !mode) {
5995         return -EINVAL;
5996     }
5997 
5998     if (!has_hdmi_infoframe) {
5999         return -EINVAL;
6000     }
6001 
6002     err = hdmi_vendor_infoframe_init(frame);
6003     if (err < 0) {
6004         return err;
6005     }
6006 
6007     /*
6008      * Even if it's not absolutely necessary to send the infoframe
6009      * (ie.vic==0 and s3d_struct==0) we will still send it if we
6010      * know that the sink can handle it. This is based on a
6011      * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
6012      * have trouble realizing that they shuld switch from 3D to 2D
6013      * mode if the source simply stops sending the infoframe when
6014      * it wants to switch from 3D to 2D.
6015      */
6016     frame->vic = drm_mode_hdmi_vic(connector, mode);
6017     frame->s3d_struct = s3d_structure_from_display_mode(mode);
6018 
6019     return 0;
6020 }
6021 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
6022 
drm_parse_tiled_block(struct drm_connector * connector,const struct displayid_block * block)6023 static void drm_parse_tiled_block(struct drm_connector *connector, const struct displayid_block *block)
6024 {
6025     const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
6026     u16 w, h;
6027     u8 tile_v_loc, tile_h_loc;
6028     u8 num_v_tile, num_h_tile;
6029     struct drm_tile_group *tg;
6030 
6031     w = tile->tile_size[0x0] | tile->tile_size[0x1] << 0x8;
6032     h = tile->tile_size[0x2] | tile->tile_size[0x3] << 0x8;
6033 
6034     num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[0x2] & 0x30);
6035     num_h_tile = (tile->topo[0] >> 0x4) | ((tile->topo[0x2] >> 0x2) & 0x30);
6036     tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[0x2] & 0x3) << 0x4);
6037     tile_h_loc = (tile->topo[1] >> 0x4) | (((tile->topo[0x2] >> 0x2) & 0x3) << 0x4);
6038 
6039     connector->has_tile = true;
6040     if (tile->tile_cap & 0x80) {
6041         connector->tile_is_single_monitor = true;
6042     }
6043 
6044     connector->num_h_tile = num_h_tile + 1;
6045     connector->num_v_tile = num_v_tile + 1;
6046     connector->tile_h_loc = tile_h_loc;
6047     connector->tile_v_loc = tile_v_loc;
6048     connector->tile_h_size = w + 1;
6049     connector->tile_v_size = h + 1;
6050 
6051     DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
6052     DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
6053     DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
6054     DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
6055 
6056     tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
6057     if (!tg) {
6058         tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
6059     }
6060     if (!tg) {
6061         return;
6062     }
6063 
6064     if (connector->tile_group != tg) {
6065         /* if we haven't got a pointer,
6066            take the reference, drop ref to old tile group */
6067         if (connector->tile_group) {
6068             drm_mode_put_tile_group(connector->dev, connector->tile_group);
6069         }
6070         connector->tile_group = tg;
6071     } else {
6072         /* if same tile group, then release the ref we just took. */
6073         drm_mode_put_tile_group(connector->dev, tg);
6074     }
6075 }
6076 
drm_displayid_parse_tiled(struct drm_connector * connector,const u8 * displayid,int length,int idx)6077 static void drm_displayid_parse_tiled(struct drm_connector *connector, const u8 *displayid, int length, int idx)
6078 {
6079     const struct displayid_block *block;
6080 
6081     idx += sizeof(struct displayid_hdr);
6082     for_each_displayid_db(displayid, block, idx, length)
6083     {
6084         DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", block->tag, block->rev, block->num_bytes);
6085 
6086         switch (block->tag) {
6087             case DATA_BLOCK_TILED_DISPLAY:
6088                 drm_parse_tiled_block(connector, block);
6089                 break;
6090             default:
6091                 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
6092                 break;
6093         }
6094     }
6095 }
6096 
drm_update_tile_info(struct drm_connector * connector,const struct edid * edid)6097 void drm_update_tile_info(struct drm_connector *connector, const struct edid *edid)
6098 {
6099     const void *displayid = NULL;
6100     int ext_index = 0;
6101     int length, idx;
6102 
6103     connector->has_tile = false;
6104     for (;;) {
6105         displayid = drm_find_displayid_extension(edid, &length, &idx, &ext_index);
6106         if (!displayid) {
6107             break;
6108         }
6109 
6110         drm_displayid_parse_tiled(connector, displayid, length, idx);
6111     }
6112 
6113     if (!connector->has_tile && connector->tile_group) {
6114         drm_mode_put_tile_group(connector->dev, connector->tile_group);
6115         connector->tile_group = NULL;
6116     }
6117 }
6118