1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_LEDC_STRUCT_H_ 15 #define _SOC_LEDC_STRUCT_H_ 16 17 #include <stdint.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 typedef volatile struct ledc_dev_s { 24 struct { 25 struct { 26 union { 27 struct { 28 uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to select one of them for high speed channel. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ 29 uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channel*/ 30 uint32_t idle_lv: 1; /*This bit is used to control the output value when high speed channel is off.*/ 31 uint32_t low_speed_update: 1; /*This bit is only useful for low speed timer channels, reserved for high speed timers*/ 32 uint32_t reserved4: 26; 33 uint32_t clk_en: 1; /*This bit is clock gating control signal. when software configure LED_PWM internal registers it controls the register clock.*/ 34 }; 35 uint32_t val; 36 } conf0; 37 union { 38 struct { 39 uint32_t hpoint: 20; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/ 40 uint32_t reserved20: 12; 41 }; 42 uint32_t val; 43 } hpoint; 44 union { 45 struct { 46 uint32_t duty: 25; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 47 uint32_t reserved25: 7; 48 }; 49 uint32_t val; 50 } duty; 51 union { 52 struct { 53 uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for high speed channel.*/ 54 uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/ 55 uint32_t duty_num: 10; /*This register is used to control the number of increased or decreased times for high speed channel.*/ 56 uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/ 57 uint32_t duty_start: 1; /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ 58 }; 59 uint32_t val; 60 } conf1; 61 union { 62 struct { 63 uint32_t duty_read: 25; /*This register represents the current duty of the output signal for high speed channel.*/ 64 uint32_t reserved25: 7; 65 }; 66 uint32_t val; 67 } duty_rd; 68 } channel[8]; 69 } channel_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/ 70 struct { 71 struct { 72 union { 73 struct { 74 uint32_t duty_resolution: 5; /*This register controls resolution of PWN duty by defining the bit width of timer's counter. The max bit width of the counter is 20.*/ 75 uint32_t clock_divider: 18; /*This register is used to configure the divider of clock at the entry of timer. The least significant eight bits represent the decimal part.*/ 76 uint32_t pause: 1; /*This bit is used to pause the counter in high speed timer*/ 77 uint32_t rst: 1; /*This bit is used to reset high speed timer the counter will be 0 after reset.*/ 78 uint32_t tick_sel: 1; /*This bit is used to choose apb_clk or ref_tick for high speed timer. 1'b1:apb_clk 0:ref_tick*/ 79 uint32_t low_speed_update: 1; /*This bit is only useful for low speed timer channels, reserved for high speed timers*/ 80 uint32_t reserved26: 5; 81 }; 82 uint32_t val; 83 } conf; 84 union { 85 struct { 86 uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in high speed timer*/ 87 uint32_t reserved20: 12; 88 }; 89 uint32_t val; 90 } value; 91 } timer[4]; 92 } timer_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/ 93 union { 94 struct { 95 uint32_t hstimer0_ovf: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/ 96 uint32_t hstimer1_ovf: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/ 97 uint32_t hstimer2_ovf: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/ 98 uint32_t hstimer3_ovf: 1; /*The interrupt raw bit for high speed channel3 counter overflow.*/ 99 uint32_t lstimer0_ovf: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/ 100 uint32_t lstimer1_ovf: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/ 101 uint32_t lstimer2_ovf: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/ 102 uint32_t lstimer3_ovf: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/ 103 uint32_t duty_chng_end_hsch0: 1; /*The interrupt raw bit for high speed channel 0 duty change done.*/ 104 uint32_t duty_chng_end_hsch1: 1; /*The interrupt raw bit for high speed channel 1 duty change done.*/ 105 uint32_t duty_chng_end_hsch2: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/ 106 uint32_t duty_chng_end_hsch3: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/ 107 uint32_t duty_chng_end_hsch4: 1; /*The interrupt raw bit for high speed channel 4 duty change done.*/ 108 uint32_t duty_chng_end_hsch5: 1; /*The interrupt raw bit for high speed channel 5 duty change done.*/ 109 uint32_t duty_chng_end_hsch6: 1; /*The interrupt raw bit for high speed channel 6 duty change done.*/ 110 uint32_t duty_chng_end_hsch7: 1; /*The interrupt raw bit for high speed channel 7 duty change done.*/ 111 uint32_t duty_chng_end_lsch0: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/ 112 uint32_t duty_chng_end_lsch1: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/ 113 uint32_t duty_chng_end_lsch2: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/ 114 uint32_t duty_chng_end_lsch3: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/ 115 uint32_t duty_chng_end_lsch4: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/ 116 uint32_t duty_chng_end_lsch5: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/ 117 uint32_t duty_chng_end_lsch6: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/ 118 uint32_t duty_chng_end_lsch7: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/ 119 uint32_t reserved24: 8; 120 }; 121 uint32_t val; 122 } int_raw; 123 union { 124 struct { 125 uint32_t hstimer0_ovf: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/ 126 uint32_t hstimer1_ovf: 1; /*The interrupt status bit for high speed channel1 counter overflow event.*/ 127 uint32_t hstimer2_ovf: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/ 128 uint32_t hstimer3_ovf: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/ 129 uint32_t lstimer0_ovf: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/ 130 uint32_t lstimer1_ovf: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/ 131 uint32_t lstimer2_ovf: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/ 132 uint32_t lstimer3_ovf: 1; /*The interrupt status bit for low speed channel3 counter overflow event.*/ 133 uint32_t duty_chng_end_hsch0: 1; /*The interrupt enable bit for high speed channel 0 duty change done event.*/ 134 uint32_t duty_chng_end_hsch1: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/ 135 uint32_t duty_chng_end_hsch2: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/ 136 uint32_t duty_chng_end_hsch3: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/ 137 uint32_t duty_chng_end_hsch4: 1; /*The interrupt status bit for high speed channel 4 duty change done event.*/ 138 uint32_t duty_chng_end_hsch5: 1; /*The interrupt status bit for high speed channel 5 duty change done event.*/ 139 uint32_t duty_chng_end_hsch6: 1; /*The interrupt status bit for high speed channel 6 duty change done event.*/ 140 uint32_t duty_chng_end_hsch7: 1; /*The interrupt status bit for high speed channel 7 duty change done event.*/ 141 uint32_t duty_chng_end_lsch0: 1; /*The interrupt status bit for low speed channel 0 duty change done event.*/ 142 uint32_t duty_chng_end_lsch1: 1; /*The interrupt status bit for low speed channel 1 duty change done event.*/ 143 uint32_t duty_chng_end_lsch2: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/ 144 uint32_t duty_chng_end_lsch3: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/ 145 uint32_t duty_chng_end_lsch4: 1; /*The interrupt status bit for low speed channel 4 duty change done event.*/ 146 uint32_t duty_chng_end_lsch5: 1; /*The interrupt status bit for low speed channel 5 duty change done event.*/ 147 uint32_t duty_chng_end_lsch6: 1; /*The interrupt status bit for low speed channel 6 duty change done event.*/ 148 uint32_t duty_chng_end_lsch7: 1; /*The interrupt status bit for low speed channel 7 duty change done event*/ 149 uint32_t reserved24: 8; 150 }; 151 uint32_t val; 152 } int_st; 153 union { 154 struct { 155 uint32_t hstimer0_ovf: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ 156 uint32_t hstimer1_ovf: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ 157 uint32_t hstimer2_ovf: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ 158 uint32_t hstimer3_ovf: 1; /*The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ 159 uint32_t lstimer0_ovf: 1; /*The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ 160 uint32_t lstimer1_ovf: 1; /*The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ 161 uint32_t lstimer2_ovf: 1; /*The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ 162 uint32_t lstimer3_ovf: 1; /*The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ 163 uint32_t duty_chng_end_hsch0: 1; /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ 164 uint32_t duty_chng_end_hsch1: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ 165 uint32_t duty_chng_end_hsch2: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ 166 uint32_t duty_chng_end_hsch3: 1; /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ 167 uint32_t duty_chng_end_hsch4: 1; /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ 168 uint32_t duty_chng_end_hsch5: 1; /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ 169 uint32_t duty_chng_end_hsch6: 1; /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ 170 uint32_t duty_chng_end_hsch7: 1; /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ 171 uint32_t duty_chng_end_lsch0: 1; /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ 172 uint32_t duty_chng_end_lsch1: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ 173 uint32_t duty_chng_end_lsch2: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ 174 uint32_t duty_chng_end_lsch3: 1; /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ 175 uint32_t duty_chng_end_lsch4: 1; /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ 176 uint32_t duty_chng_end_lsch5: 1; /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ 177 uint32_t duty_chng_end_lsch6: 1; /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ 178 uint32_t duty_chng_end_lsch7: 1; /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ 179 uint32_t reserved24: 8; 180 }; 181 uint32_t val; 182 } int_ena; 183 union { 184 struct { 185 uint32_t hstimer0_ovf: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/ 186 uint32_t hstimer1_ovf: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/ 187 uint32_t hstimer2_ovf: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/ 188 uint32_t hstimer3_ovf: 1; /*Set this bit to clear high speed channel3 counter overflow interrupt.*/ 189 uint32_t lstimer0_ovf: 1; /*Set this bit to clear low speed channel0 counter overflow interrupt.*/ 190 uint32_t lstimer1_ovf: 1; /*Set this bit to clear low speed channel1 counter overflow interrupt.*/ 191 uint32_t lstimer2_ovf: 1; /*Set this bit to clear low speed channel2 counter overflow interrupt.*/ 192 uint32_t lstimer3_ovf: 1; /*Set this bit to clear low speed channel3 counter overflow interrupt.*/ 193 uint32_t duty_chng_end_hsch0: 1; /*Set this bit to clear high speed channel 0 duty change done interrupt.*/ 194 uint32_t duty_chng_end_hsch1: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/ 195 uint32_t duty_chng_end_hsch2: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/ 196 uint32_t duty_chng_end_hsch3: 1; /*Set this bit to clear high speed channel 3 duty change done interrupt.*/ 197 uint32_t duty_chng_end_hsch4: 1; /*Set this bit to clear high speed channel 4 duty change done interrupt.*/ 198 uint32_t duty_chng_end_hsch5: 1; /*Set this bit to clear high speed channel 5 duty change done interrupt.*/ 199 uint32_t duty_chng_end_hsch6: 1; /*Set this bit to clear high speed channel 6 duty change done interrupt.*/ 200 uint32_t duty_chng_end_hsch7: 1; /*Set this bit to clear high speed channel 7 duty change done interrupt.*/ 201 uint32_t duty_chng_end_lsch0: 1; /*Set this bit to clear low speed channel 0 duty change done interrupt.*/ 202 uint32_t duty_chng_end_lsch1: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/ 203 uint32_t duty_chng_end_lsch2: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/ 204 uint32_t duty_chng_end_lsch3: 1; /*Set this bit to clear low speed channel 3 duty change done interrupt.*/ 205 uint32_t duty_chng_end_lsch4: 1; /*Set this bit to clear low speed channel 4 duty change done interrupt.*/ 206 uint32_t duty_chng_end_lsch5: 1; /*Set this bit to clear low speed channel 5 duty change done interrupt.*/ 207 uint32_t duty_chng_end_lsch6: 1; /*Set this bit to clear low speed channel 6 duty change done interrupt.*/ 208 uint32_t duty_chng_end_lsch7: 1; /*Set this bit to clear low speed channel 7 duty change done interrupt.*/ 209 uint32_t reserved24: 8; 210 }; 211 uint32_t val; 212 } int_clr; 213 union { 214 struct { 215 uint32_t apb_clk_sel: 1; /*This bit decides the slow clock for LEDC low speed channels, so we want to replace the field name with slow_clk_sel*/ 216 uint32_t reserved1: 31; 217 }; 218 struct { 219 uint32_t slow_clk_sel: 1; /*This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz, (only used by LEDC low speed channels/timers)*/ 220 uint32_t reserved: 31; 221 }; 222 uint32_t val; 223 } conf; 224 uint32_t reserved_194; 225 uint32_t reserved_198; 226 uint32_t reserved_19c; 227 uint32_t reserved_1a0; 228 uint32_t reserved_1a4; 229 uint32_t reserved_1a8; 230 uint32_t reserved_1ac; 231 uint32_t reserved_1b0; 232 uint32_t reserved_1b4; 233 uint32_t reserved_1b8; 234 uint32_t reserved_1bc; 235 uint32_t reserved_1c0; 236 uint32_t reserved_1c4; 237 uint32_t reserved_1c8; 238 uint32_t reserved_1cc; 239 uint32_t reserved_1d0; 240 uint32_t reserved_1d4; 241 uint32_t reserved_1d8; 242 uint32_t reserved_1dc; 243 uint32_t reserved_1e0; 244 uint32_t reserved_1e4; 245 uint32_t reserved_1e8; 246 uint32_t reserved_1ec; 247 uint32_t reserved_1f0; 248 uint32_t reserved_1f4; 249 uint32_t reserved_1f8; 250 uint32_t date; /*This register represents the version .*/ 251 } ledc_dev_t; 252 extern ledc_dev_t LEDC; 253 254 #ifdef __cplusplus 255 } 256 #endif 257 258 #endif /* _SOC_LEDC_STRUCT_H_ */ 259