1 /* 2 * Allwinner SoCs display driver. 3 * 4 * Copyright (C) 2016 Allwinner. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 #ifndef __DE_RTMX_TYPE_H__ 11 #define __DE_RTMX_TYPE_H__ 12 13 /* for global control */ 14 union __glb_ctl_reg_t { 15 unsigned int dwval; 16 struct { 17 unsigned int rt_en:1; 18 unsigned int r0:3; 19 unsigned int finish_irq_en:1; 20 unsigned int error_irq_en:1; 21 unsigned int r1:2; 22 unsigned int sync_rev:1; 23 unsigned int flied_rev:1; 24 unsigned int r2:2; 25 unsigned int rtwb_port:2; 26 unsigned int r3:18; 27 } bits; 28 }; 29 /* 0x0 */ 30 31 union __glb_status_reg_t { 32 unsigned int dwval; 33 struct { 34 unsigned int finish_irq:1; 35 unsigned int error_irq:1; 36 unsigned int r0:2; 37 unsigned int busy_status:1; 38 unsigned int error_status:1; 39 unsigned int r1:2; 40 unsigned int even_odd_flag:1; 41 unsigned int r2:23; 42 } bits; 43 }; 44 /* 0x4 */ 45 46 union __glb_dbuff_reg_t { 47 unsigned int dwval; 48 struct { 49 unsigned int dbuff_rdy:1; 50 unsigned int r0:31; 51 } bits; 52 }; 53 /* 0x8 */ 54 55 union __glb_size_reg_t { 56 unsigned int dwval; 57 struct { 58 unsigned int width:13; 59 unsigned int r0:3; 60 unsigned int height:13; 61 unsigned int r1:3; 62 } bits; 63 }; 64 /* 0xc */ 65 66 union __glb_auto_gate_reg_t { 67 unsigned int dwval; 68 struct { 69 unsigned int en:1; 70 unsigned int r0:30; 71 } bits; 72 }; 73 74 /* 0x14 */ 75 struct __glb_reg_t { 76 union __glb_ctl_reg_t glb_ctl; 77 union __glb_status_reg_t glb_status; 78 union __glb_dbuff_reg_t glb_dbuff; 79 union __glb_size_reg_t glb_size; 80 unsigned int r0; 81 union __glb_auto_gate_reg_t glb_gate; 82 }; 83 84 /* for video overlay */ 85 union __vi_lay_attr_reg_t { 86 unsigned int dwval; 87 struct { 88 unsigned int en:1; 89 unsigned int alpmod:2; 90 unsigned int r0:1; 91 unsigned int fcolor_en:1; 92 unsigned int r1:3; 93 unsigned int fmt:5; 94 unsigned int r2:2; 95 unsigned int ui_sel:1; 96 unsigned int alpctl:2; 97 unsigned int r3:2; 98 unsigned int brust:3; 99 unsigned int top_down:1; 100 unsigned int alpha:8; 101 } bits; 102 }; 103 /* 0x0+N*0x30(N=0,1,2,3) */ 104 105 union __vi_lay_size_reg_t { 106 unsigned int dwval; 107 struct { 108 unsigned int width:13; 109 unsigned int r0:3; 110 unsigned int height:13; 111 unsigned int r1:3; 112 } bits; 113 }; 114 /* 0x4+N*0x30(N=0,1,2,3) */ 115 116 union __vi_lay_coor_reg_t { 117 unsigned int dwval; 118 struct { 119 unsigned int x:16; 120 unsigned int y:16; 121 } bits; 122 }; 123 /* 0x8+N*0x30(N=0,1,2,3) */ 124 125 union __vi_lay_pitch_reg_t { 126 unsigned int dwval; 127 struct { 128 unsigned int pitch:32; 129 } bits; 130 }; 131 /* 0xc/0x010/0x014+N*0x30(N=0,1,2,3) */ 132 133 union __vi_lay_top_laddr_reg_t { 134 unsigned int dwval; 135 struct { 136 unsigned int top_laddr:32; 137 } bits; 138 }; 139 /* 0x018/0x01c/0x020+N*0x30(N=0,1,2,3) */ 140 141 union __vi_lay_bot_laddr_reg_t { 142 unsigned int dwval; 143 struct { 144 unsigned int bot_laddr:32; 145 } bits; 146 }; 147 /* 0x024/0x028/0x02c+N*0x30(N=0,1,2,3) */ 148 149 union __vi_lay_fcolor_reg_t { 150 unsigned int dwval; 151 struct { 152 unsigned int vb:8; 153 unsigned int ug:8; 154 unsigned int yr:8; 155 unsigned int r0:8; 156 } bits; 157 }; 158 /* 0x0c0+N*0x4(N=0,1,2,3) */ 159 160 union __vi_lay_top_haddr_reg_t { 161 unsigned int dwval; 162 struct { 163 unsigned int lay0_top_haddr:8; 164 unsigned int lay1_top_haddr:8; 165 unsigned int lay2_top_haddr:8; 166 unsigned int lay3_top_haddr:8; 167 } bits; 168 }; 169 /* 0xd0~0x0xd8 */ 170 171 union __vi_lay_bot_haddr_reg_t { 172 unsigned int dwval; 173 struct { 174 unsigned int lay0_bot_haddr:8; 175 unsigned int lay1_bot_haddr:8; 176 unsigned int lay2_bot_haddr:8; 177 unsigned int lay3_bot_haddr:8; 178 } bits; 179 }; 180 /* 0xdc~0xe4 */ 181 182 union __vi_ovl_size_reg_t { 183 unsigned int dwval; 184 struct { 185 unsigned int width:13; 186 unsigned int r0:3; 187 unsigned int height:13; 188 unsigned int r1:3; 189 } bits; 190 }; 191 /* 0xe8~0xec */ 192 193 union __vi_hori_ds_reg_t { 194 unsigned int dwval; 195 struct { 196 unsigned int m:14; 197 unsigned int r0:2; 198 unsigned int n:14; 199 unsigned int r1:2; 200 } bits; 201 }; 202 /* 0xf0~0xf4 */ 203 204 union __vi_vert_ds_reg_t { 205 unsigned int dwval; 206 struct { 207 unsigned int m:14; 208 unsigned int r0:2; 209 unsigned int n:14; 210 unsigned int r1:2; 211 } bits; 212 }; 213 /* 0xf8~0xfc */ 214 215 struct __vi_lay_reg_t { 216 union __vi_lay_attr_reg_t attr; 217 union __vi_lay_size_reg_t size; 218 union __vi_lay_coor_reg_t coor; 219 union __vi_lay_pitch_reg_t pitch[3]; 220 union __vi_lay_top_laddr_reg_t top_laddr[3]; 221 union __vi_lay_bot_laddr_reg_t bot_laddr[3]; 222 }; 223 224 struct __vi_ovl_reg_t { 225 struct __vi_lay_reg_t cfg[4]; 226 union __vi_lay_fcolor_reg_t fcolor[4]; 227 union __vi_lay_top_haddr_reg_t top_haddr[3]; 228 union __vi_lay_bot_haddr_reg_t bot_haddr[3]; 229 union __vi_ovl_size_reg_t ovl_size[2]; 230 union __vi_hori_ds_reg_t hori_ds[2]; 231 union __vi_vert_ds_reg_t vert_ds[2]; 232 }; 233 234 /* for ui overlay */ 235 union __ui_lay_attr_reg_t { 236 unsigned int dwval; 237 struct { 238 unsigned int en:1; 239 unsigned int alpmod:2; 240 unsigned int r0:1; 241 unsigned int fcolor_en:1; 242 unsigned int r1:3; 243 unsigned int fmt:5; 244 unsigned int r2:3; 245 unsigned int alpctl:2; 246 unsigned int r3:2; 247 unsigned int brust:3; 248 unsigned int top_down:1; 249 unsigned int alpha:8; 250 } bits; 251 }; 252 /* 0x0+N*0x20(N=0,1,2,3) */ 253 254 union __ui_lay_size_reg_t { 255 unsigned int dwval; 256 struct { 257 unsigned int width:13; 258 unsigned int r0:3; 259 unsigned int height:13; 260 unsigned int r1:3; 261 } bits; 262 }; 263 /* 0x4+N*0x20(N=0,1,2,3) */ 264 265 union __ui_lay_coor_reg_t { 266 unsigned int dwval; 267 struct { 268 unsigned int x:16; 269 unsigned int y:16; 270 } bits; 271 }; 272 /* 0x8+N*0x20(N=0,1,2,3) */ 273 274 union __ui_lay_pitch_reg_t { 275 unsigned int dwval; 276 struct { 277 unsigned int pitch:32; 278 } bits; 279 }; 280 /* 0xc+N*0x20(N=0,1,2,3) */ 281 282 union __ui_lay_top_laddr_reg_t { 283 unsigned int dwval; 284 struct { 285 unsigned int top_laddr:32; 286 } bits; 287 }; 288 /* 0x10+N*0x20(N=0,1,2,3) */ 289 290 union __ui_lay_bot_laddr_reg_t { 291 unsigned int dwval; 292 struct { 293 unsigned int bot_laddr:32; 294 } bits; 295 }; 296 /* 0x14+N*0x20(N=0,1,2,3) */ 297 298 union __ui_lay_fcolor_reg_t { 299 unsigned int dwval; 300 struct { 301 unsigned int blue:8; 302 unsigned int green:8; 303 unsigned int red:8; 304 unsigned int alpha:8; 305 } bits; 306 }; 307 /* 0x18+N*0x20(N=0,1,2,3) */ 308 309 union __ui_lay_top_haddr_reg_t { 310 unsigned int dwval; 311 struct { 312 unsigned int lay0_top_haddr:8; 313 unsigned int lay1_top_haddr:8; 314 unsigned int lay2_top_haddr:8; 315 unsigned int lay3_top_haddr:8; 316 } bits; 317 }; 318 /* 0x80 */ 319 320 union __ui_lay_bot_haddr_reg_t { 321 unsigned int dwval; 322 struct { 323 unsigned int lay0_bot_haddr:8; 324 unsigned int lay1_bot_haddr:8; 325 unsigned int lay2_bot_haddr:8; 326 unsigned int lay3_bot_haddr:8; 327 } bits; 328 }; 329 /* 0x84 */ 330 331 union __ui_ovl_size_reg_t { 332 unsigned int dwval; 333 struct { 334 unsigned int width:13; 335 unsigned int r0:3; 336 unsigned int height:13; 337 unsigned int r1:3; 338 } bits; 339 }; 340 /* 0x88 */ 341 342 struct __ui_lay_reg_t { 343 union __ui_lay_attr_reg_t attr; 344 union __ui_lay_size_reg_t size; 345 union __ui_lay_coor_reg_t coor; 346 union __ui_lay_pitch_reg_t pitch; 347 union __ui_lay_top_laddr_reg_t top_laddr; 348 union __ui_lay_bot_laddr_reg_t bot_laddr; 349 union __ui_lay_fcolor_reg_t fcolor; 350 unsigned int r0; 351 }; 352 353 struct __ui_ovl_reg_t { 354 struct __ui_lay_reg_t cfg[4]; 355 union __ui_lay_top_haddr_reg_t top_haddr; 356 union __ui_lay_bot_haddr_reg_t bot_haddr; 357 union __ui_ovl_size_reg_t ovl_size; 358 unsigned int res[29]; 359 }; 360 361 /* for alpha blending */ 362 union __bld_fcolor_ctl_reg_t { 363 unsigned int dwval; 364 struct { 365 unsigned int p0_fcolor_en:1; 366 unsigned int p1_fcolor_en:1; 367 unsigned int p2_fcolor_en:1; 368 unsigned int p3_fcolor_en:1; 369 unsigned int p4_fcolor_en:1; 370 unsigned int r0:3; 371 unsigned int p0_en:1; 372 unsigned int p1_en:1; 373 unsigned int p2_en:1; 374 unsigned int p3_en:1; 375 unsigned int p4_en:1; 376 unsigned int r1:19; 377 } bits; 378 }; 379 /* 0x0 */ 380 381 union __bld_fcolor_reg_t { 382 unsigned int dwval; 383 struct { 384 unsigned int blue:8; 385 unsigned int green:8; 386 unsigned int red:8; 387 unsigned int alpha:8; 388 } bits; 389 }; 390 /* 0x4+N*0x10(N=0,1,2,3,4) */ 391 392 union __bld_isize_reg_t { 393 unsigned int dwval; 394 struct { 395 unsigned int width:13; 396 unsigned int r0:3; 397 unsigned int height:13; 398 unsigned int r1:3; 399 } bits; 400 }; 401 /* 0x8+N*0x10(N=0,1,2,3,4) */ 402 403 union __bld_offset_reg_t { 404 unsigned int dwval; 405 struct { 406 unsigned int x:16; 407 unsigned int y:13; 408 } bits; 409 }; 410 /* 0xc+N*0x10(N=0,1,2,3,4) */ 411 412 union __bld_route_ctl_reg_t { 413 unsigned int dwval; 414 struct { 415 unsigned int ch0_routr_ctl:4; 416 unsigned int ch1_routr_ctl:4; 417 unsigned int ch2_routr_ctl:4; 418 unsigned int ch3_routr_ctl:4; 419 unsigned int ch4_routr_ctl:4; 420 unsigned int r0:12; 421 } bits; 422 }; 423 424 union __bld_premultiply_ctl_reg_t { 425 unsigned int dwval; 426 struct { 427 unsigned int p0_alpha_mode:1; 428 unsigned int p1_alpha_mode:1; 429 unsigned int p2_alpha_mode:1; 430 unsigned int p3_alpha_mode:1; 431 unsigned int p4_alpha_mode:1; 432 unsigned int r0:27; 433 } bits; 434 }; 435 436 union __bld_bkcolor_reg_t { 437 unsigned int dwval; 438 struct { 439 unsigned int blue:8; 440 unsigned int green:8; 441 unsigned int red:8; 442 unsigned int alpha:8; 443 } bits; 444 }; 445 446 union __bld_output_size_reg_t { 447 unsigned int dwval; 448 struct { 449 unsigned int width:13; 450 unsigned int r0:3; 451 unsigned int height:13; 452 unsigned int r1:3; 453 } bits; 454 }; 455 456 union __bld_ctl_reg_t { 457 unsigned int dwval; 458 struct { 459 unsigned int pixel_fs:4; 460 unsigned int r0:4; 461 unsigned int pixel_fd:4; 462 unsigned int r1:4; 463 unsigned int alpha_fs:4; 464 unsigned int r2:4; 465 unsigned int alpha_fd:4; 466 unsigned int r3:4; 467 } bits; 468 }; 469 470 union __bld_colorkey_ctl_reg_t { 471 unsigned int dwval; 472 struct { 473 unsigned int key0_en:1; 474 unsigned int key0_dir:2; 475 unsigned int r0:1; 476 unsigned int key1_en:1; 477 unsigned int key1_dir:2; 478 unsigned int r1:1; 479 unsigned int key2_en:1; 480 unsigned int key2_dir:2; 481 unsigned int r2:1; 482 unsigned int key3_en:1; 483 unsigned int key3_dir:2; 484 unsigned int r3:17; 485 } bits; 486 }; 487 488 union __bld_colorkey_cfg_reg_t { 489 unsigned int dwval; 490 struct { 491 unsigned int key0_blue:1; 492 unsigned int key0_green:1; 493 unsigned int key0_red:1; 494 unsigned int r0:5; 495 unsigned int key1_blue:1; 496 unsigned int key1_green:1; 497 unsigned int key1_red:1; 498 unsigned int r1:5; 499 unsigned int key2_blue:1; 500 unsigned int key2_green:1; 501 unsigned int key2_red:1; 502 unsigned int r2:5; 503 unsigned int key3_blue:1; 504 unsigned int key3_green:1; 505 unsigned int key3_red:1; 506 unsigned int r3:5; 507 } bits; 508 }; 509 510 union __bld_colorkey_max_reg_t { 511 unsigned int dwval; 512 struct { 513 unsigned int max_blue:8; 514 unsigned int max_green:8; 515 unsigned int max_red:8; 516 unsigned int r0:8; 517 } bits; 518 }; 519 520 union __bld_colorkey_min_reg_t { 521 unsigned int dwval; 522 struct { 523 unsigned int min_blue:8; 524 unsigned int min_green:8; 525 unsigned int min_red:8; 526 unsigned int r0:8; 527 } bits; 528 }; 529 530 union __bld_out_color_ctl_reg_t { 531 unsigned int dwval; 532 struct { 533 unsigned int premultiply_en:1; 534 unsigned int interlace_en:1; 535 unsigned int r0:30; 536 } bits; 537 }; 538 539 union __bld_csc_alpha_reg_t { 540 unsigned int dwval; 541 struct { 542 unsigned int en0:1; 543 unsigned int en1:1; 544 unsigned int en2:1; 545 unsigned int en3:1; 546 unsigned int r0:4; 547 unsigned int bld_mode:1; 548 unsigned int r1:23; 549 } bits; 550 }; 551 552 struct __bld_pipe_reg_t { 553 union __bld_fcolor_reg_t fcolor; 554 union __bld_isize_reg_t insize; 555 union __bld_offset_reg_t offset; 556 unsigned int r0; 557 }; 558 559 struct __bld_reg_t { 560 union __bld_fcolor_ctl_reg_t bld_fcolor_ctl; 561 struct __bld_pipe_reg_t bld_pipe_attr[5]; 562 unsigned int r0[11]; 563 union __bld_route_ctl_reg_t bld_route_ctl; 564 union __bld_premultiply_ctl_reg_t bld_premultiply_ctl; 565 union __bld_bkcolor_reg_t bld_bkcolor; 566 union __bld_output_size_reg_t bld_output_size; 567 union __bld_ctl_reg_t bld_mode[4]; 568 unsigned int r1[4]; 569 union __bld_colorkey_ctl_reg_t bld_ck_ctl; 570 union __bld_colorkey_cfg_reg_t bld_ck_cfg; 571 unsigned int r2[2]; 572 union __bld_colorkey_max_reg_t bld_ck_max[4]; 573 unsigned int r3[4]; 574 union __bld_colorkey_min_reg_t bld_ck_min[4]; 575 unsigned int r4[3]; 576 union __bld_out_color_ctl_reg_t bld_out_ctl; 577 union __bld_csc_alpha_reg_t bld_csc_ctl; 578 unsigned int res[63]; 579 }; 580 581 /* for frame buffer decoder */ 582 union __fbd_ctl_reg_t { 583 unsigned int dwval; 584 struct { 585 unsigned int fbd_en:1; 586 unsigned int fbd_fcen:1; 587 unsigned int alpha_mode:2; 588 unsigned int clk_gate:1; 589 unsigned int r0:19; 590 unsigned int alpha:8; 591 } bits; 592 }; 593 594 union __fbd_status_reg_t { 595 unsigned int dwval; 596 struct { 597 unsigned int flag:1; 598 unsigned int err0:1; 599 unsigned int err1:1; 600 unsigned int r1:29; 601 } bits; 602 }; 603 604 union __fbd_img_size_reg_t { 605 unsigned int dwval; 606 struct { 607 unsigned int width:12; 608 unsigned int r0:4; 609 unsigned int height:12; 610 unsigned int r1:4; 611 } bits; 612 }; 613 614 union __fbd_blk_size_reg_t { 615 unsigned int dwval; 616 struct { 617 unsigned int width:10; 618 unsigned int r0:6; 619 unsigned int height:10; 620 unsigned int r1:6; 621 } bits; 622 }; 623 624 union __fbd_crop0_reg_t { 625 unsigned int dwval; 626 struct { 627 unsigned int left:4; 628 unsigned int res0:12; 629 unsigned int top:4; 630 unsigned int res1:12; 631 } bits; 632 }; 633 634 union __fbd_crop1_reg_t { 635 unsigned int dwval; 636 struct { 637 unsigned int left:12; 638 unsigned int res0:4; 639 unsigned int top:12; 640 unsigned int res1:4; 641 } bits; 642 }; 643 644 union __fbd_format_reg_t { 645 unsigned int dwval; 646 struct { 647 unsigned int fmt:7; 648 unsigned int tran:1; 649 unsigned int res0:8; 650 unsigned int sbs0:2; 651 unsigned int sbs1:2; 652 unsigned int res1:12; 653 } bits; 654 }; 655 656 union __fbd_ovh_laddr_reg_t { 657 unsigned int dwval; 658 struct { 659 unsigned int fbd_laddr:32; 660 } bits; 661 }; 662 663 union __fbd_ovh_haddr_reg_t { 664 unsigned int dwval; 665 struct { 666 unsigned int fbd_haddr:8; 667 unsigned int r0:24; 668 } bits; 669 }; 670 671 union __fbd_coor_reg_t { 672 unsigned int dwval; 673 struct { 674 unsigned int fbd_coorx:16; 675 unsigned int fbd_coory:16; 676 } bits; 677 }; 678 679 union __fbd_ovl_size_reg_t { 680 unsigned int dwval; 681 struct { 682 unsigned int width:13; 683 unsigned int r0:3; 684 unsigned int height:13; 685 unsigned int r1:3; 686 } bits; 687 }; 688 689 union __fbd_ovl_bgc_reg_t { 690 unsigned int dwval; 691 struct { 692 unsigned int bgc:32; 693 } bits; 694 }; 695 696 union __fbd_ovl_fc_reg_t { 697 unsigned int dwval; 698 struct { 699 unsigned int fc:32; 700 } bits; 701 }; 702 703 union __fbd_ovl_def_col0_reg_t { 704 unsigned int dwval; 705 struct { 706 unsigned int yr:16; 707 unsigned int alpha:16; 708 } bits; 709 }; 710 711 union __fbd_ovl_def_col1_reg_t { 712 unsigned int dwval; 713 struct { 714 unsigned int ug:16; 715 unsigned int vb:16; 716 } bits; 717 }; 718 719 720 721 struct __fbd_ovl_reg_t { 722 union __fbd_ctl_reg_t fbd_ctl; 723 union __fbd_status_reg_t fbd_sts; 724 union __fbd_img_size_reg_t fbd_img_size; 725 union __fbd_blk_size_reg_t fbd_blk_size; 726 union __fbd_crop0_reg_t fbd_src_crop; 727 union __fbd_crop1_reg_t fbd_lay_crop; 728 union __fbd_format_reg_t fbd_fmt; 729 unsigned int r0; 730 union __fbd_ovh_laddr_reg_t fbd_ovh_laddr; 731 union __fbd_ovh_haddr_reg_t fbd_ovh_haddr; 732 unsigned int r1; 733 unsigned int r2; 734 union __fbd_ovl_size_reg_t fbd_ovl_size; 735 union __fbd_coor_reg_t fbd_coor; 736 union __fbd_ovl_bgc_reg_t fbd_bgc; 737 union __fbd_ovl_fc_reg_t fbd_fc; 738 unsigned int r3[4]; 739 union __fbd_ovl_def_col0_reg_t fbd_def_col0; 740 union __fbd_ovl_def_col1_reg_t fbd_def_col1; 741 }; 742 743 struct __rtmx_reg_t { 744 struct __glb_reg_t *glb_ctl; 745 struct __bld_reg_t *bld_ctl; 746 struct __vi_ovl_reg_t *vi_ovl[VI_CHN_NUM]; 747 struct __ui_ovl_reg_t *ui_ovl[UI_CHN_NUM]; 748 /* struct __fbd_ovl_reg_t *fbd_ovl[FBD_CHN_NUM]; */ 749 struct __fbd_ovl_reg_t *fbd_ovl[DE_NUM]; 750 }; 751 752 #endif 753