1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #include <stdint.h>
15 #include <string.h>
16
17 #include "esp_attr.h"
18 #include "esp_err.h"
19 #include "esp_intr_alloc.h"
20 #include "esp_debug_helpers.h"
21
22 #include "soc/cpu.h"
23 #include "soc/dport_reg.h"
24 #include "soc/gpio_periph.h"
25 #include "soc/rtc_periph.h"
26
27 #include "esp_osal/esp_osal.h"
28 #include "esp_osal/task.h"
29 #include "esp_osal/semphr.h"
30 #include "esp_osal/queue.h"
31
32
33 #define REASON_YIELD BIT(0)
34 #define REASON_FREQ_SWITCH BIT(1)
35 #define REASON_PRINT_BACKTRACE BIT(2)
36
37 static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
38 static volatile uint32_t reason[ portNUM_PROCESSORS ];
39
40 /*
41 ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
42 the ISR will cause it to switch _away_ from it. portYIELD_FROM_ISR will probably just schedule the task again, but have to check that.
43 */
esp_crosscore_isr_handle_yield(void)44 static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
45 {
46 portYIELD_FROM_ISR();
47 }
48
esp_crosscore_isr(void * arg)49 static void IRAM_ATTR esp_crosscore_isr(void *arg) {
50 uint32_t my_reason_val;
51 //A pointer to the correct reason array item is passed to this ISR.
52 volatile uint32_t *my_reason=arg;
53
54 //Clear the interrupt first.
55 if (xPortGetCoreID()==0) {
56 DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
57 } else {
58 DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, 0);
59 }
60 //Grab the reason and clear it.
61 portENTER_CRITICAL_ISR(&reason_spinlock);
62 my_reason_val=*my_reason;
63 *my_reason=0;
64 portEXIT_CRITICAL_ISR(&reason_spinlock);
65
66 //Check what we need to do.
67 if (my_reason_val & REASON_YIELD) {
68 esp_crosscore_isr_handle_yield();
69 }
70 if (my_reason_val & REASON_FREQ_SWITCH) {
71 /* Nothing to do here; the frequency switch event was already
72 * handled by a hook in xtensa_vectors.S. Could be used in the future
73 * to allow DFS features without the extra latency of the ISR hook.
74 */
75 }
76 if (my_reason_val & REASON_PRINT_BACKTRACE) {
77 esp_backtrace_print(100);
78 }
79 }
80
81 //Initialize the crosscore interrupt on this core. Call this once
82 //on each active core.
esp_crosscore_int_init(void)83 void esp_crosscore_int_init(void) {
84 portENTER_CRITICAL(&reason_spinlock);
85 reason[xPortGetCoreID()]=0;
86 portEXIT_CRITICAL(&reason_spinlock);
87 esp_err_t err;
88 if (xPortGetCoreID()==0) {
89 err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
90 } else {
91 err = esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[1], NULL);
92 }
93 assert(err == ESP_OK);
94 }
95
esp_crosscore_int_send(int core_id,uint32_t reason_mask)96 static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) {
97 assert(core_id<portNUM_PROCESSORS);
98 //Mark the reason we interrupt the other CPU
99 portENTER_CRITICAL_ISR(&reason_spinlock);
100 reason[core_id] |= reason_mask;
101 portEXIT_CRITICAL_ISR(&reason_spinlock);
102 //Poke the other CPU.
103 if (core_id==0) {
104 DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
105 } else {
106 DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, DPORT_CPU_INTR_FROM_CPU_1);
107 }
108 }
109
esp_crosscore_int_send_yield(int core_id)110 void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
111 {
112 esp_crosscore_int_send(core_id, REASON_YIELD);
113 }
114
esp_crosscore_int_send_freq_switch(int core_id)115 void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
116 {
117 esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
118 }
119
esp_crosscore_int_send_print_backtrace(int core_id)120 void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
121 {
122 esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
123 }
124