1 /* 2 * Copyright (c) 2021 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef RISCV_CORE_H 9 #define RISCV_CORE_H 10 11 #include "hpm_common.h" 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 /** 18 * @brief write fp csr 19 * 20 * @param v value to be set 21 */ 22 #define write_fcsr(v) __asm volatile("fscsr %0" : : "r"(v)) 23 24 /** 25 * @brief clear bits in csr 26 * 27 * @param csr_num specific csr 28 * @param bit bits to be cleared 29 */ 30 #define clear_csr(csr_num, bit) __asm volatile("csrc %0, %1" : : "i"(csr_num), "r"(bit)) 31 32 /** 33 * @brief set bits in csr 34 * 35 * @param csr_num specific csr 36 * @param bit bits to be set 37 */ 38 #define set_csr(csr_num, bit) __asm volatile("csrs %0, %1" : : "i"(csr_num), "r"(bit)) 39 40 /** 41 * @brief write value to csr 42 * 43 * @param csr_num specific csr 44 * @param v value to be written 45 */ 46 #define write_csr(csr_num, v) __asm volatile("csrw %0, %1" : : "i"(csr_num), "r"(v)) 47 48 /** 49 * @brief read value of specific csr 50 * 51 * @param csr_num specific csr 52 * 53 * @return csr value 54 */ 55 #define read_csr(csr_num) ({ uint32_t v; __asm volatile("csrr %0, %1" : "=r"(v) : "i"(csr_num)); v; }) 56 57 /** 58 * @brief read fp csr 59 * 60 * @return fp csr value 61 */ 62 #define read_fcsr() ({ uint32_t v; __asm volatile("frcsr %0" : "=r"(v)); v; }) 63 64 /** 65 * @brief execute fence.i 66 * 67 */ 68 #define fencei() __asm volatile("fence.i") 69 70 #ifdef __cplusplus 71 } 72 #endif 73 74 75 #endif /* RISCV_CORE_H */ 76