1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #include <soc/soc.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 #include <soc/soc.h> 24 25 typedef volatile struct { 26 struct { 27 union { 28 struct { 29 uint32_t gpio_input: 1; /**< bit[0] gpio_input_bit, R */ 30 uint32_t gpio_output: 1; /**< bit[1] gpio_output_bit, R/W */ 31 uint32_t gpio_input_en: 1; /**< bit[2] gpio_input_en_bit, R/W */ 32 uint32_t gpio_output_en: 1; /**< bit[3] gpio_output_en_bit, R/W */ 33 uint32_t gpio_pull_mode: 1; /**< bit[4] gpio_pull_mode_bit: 1:pull_up 0:pull_down*/ 34 uint32_t gpio_pull_mode_en: 1; /**< bit[5] gpio_pull_mode_en_bit, defult:1R/W */ 35 uint32_t gpio_2_func_en: 1; /**< bit[6] gpio_2_func_en_bit, R/W */ 36 uint32_t gpio_input_monitor: 1; /**< bit[7] view gpio input values, R/W */ 37 uint32_t gpio_capacity: 2; /**< bit[8:9] gpio driver capacity,R/W */ 38 39 uint32_t reserved: 22; 40 }; 41 uint32_t v; 42 } cfg; 43 } gpio_num[SOC_GPIO_NUM]; 44 45 uint32_t reserved_2[16]; 46 47 //reg0x40 int_type1 48 union { 49 struct { 50 uint32_t gpio0_int_type: 2; /**< bit[0:1]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 51 uint32_t gpio1_int_type: 2; /**< bit[2:3]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 52 uint32_t gpio2_int_type: 2; /**< bit[4:5]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 53 uint32_t gpio3_int_type: 2; /**< bit[6:7]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 54 uint32_t gpio4_int_type: 2; /**< bit[8:9]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 55 uint32_t gpio5_int_type: 2; /**< bit[10:11]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 56 uint32_t gpio6_int_type: 2; /**< bit[12:13]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 57 uint32_t gpio7_int_type: 2; /**< bit[14:15]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 58 uint32_t gpio8_int_type: 2; /**< bit[16:17]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 59 uint32_t gpio9_int_type: 2; /**< bit[18:19]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 60 uint32_t gpio10_int_type: 2; /**< bit[20:21]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 61 uint32_t gpio11_int_type: 2; /**< bit[22:23]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 62 uint32_t gpio12_int_type: 2; /**< bit[24:25]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 63 uint32_t gpio13_int_type: 2; /**< bit[26:27]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 64 uint32_t gpio14_int_type: 2; /**< bit[28:29]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 65 uint32_t gpio15_int_type: 2; /**< bit[30:31]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 66 }; 67 uint32_t v; 68 } gpio_0_15_int_type; 69 70 //reg0x41 int_type2 71 union { 72 struct { 73 uint32_t gpio16_int_type: 2; /**< bit[0:1]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 74 uint32_t gpio17_int_type: 2; /**< bit[2:3]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 75 uint32_t gpio18_int_type: 2; /**< bit[4:5]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 76 uint32_t gpio19_int_type: 2; /**< bit[6:7]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 77 uint32_t gpio20_int_type: 2; /**< bit[8:9]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 78 uint32_t gpio21_int_type: 2; /**< bit[10:11]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 79 uint32_t gpio22_int_type: 2; /**< bit[12:13]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 80 uint32_t gpio23_int_type: 2; /**< bit[14:15]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 81 uint32_t gpio24_int_type: 2; /**< bit[16:17]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 82 uint32_t gpio25_int_type: 2; /**< bit[18:19]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 83 uint32_t gpio26_int_type: 2; /**< bit[20:21]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 84 uint32_t gpio27_int_type: 2; /**< bit[22:23]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 85 uint32_t gpio28_int_type: 2; /**< bit[24:25]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 86 uint32_t gpio29_int_type: 2; /**< bit[26:27]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 87 uint32_t gpio30_int_type: 2; /**< bit[28:29]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 88 uint32_t gpio31_int_type: 2; /**< bit[30:31]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 89 }; 90 uint32_t v; 91 } gpio_16_31_int_type; 92 93 //reg0x42 int_type3 94 union { 95 struct { 96 uint32_t gpio32_int_type: 2; /**< bit[0:1]: 0:low_level; 1:high_levle; 2:rising edge; 3:falling edge R/W */ 97 uint32_t gpio33_int_type: 2; /**< bit[2:3]: 0:low_level; 1:high_levle; 2:rising edge; 3:falling edge R/W */ 98 uint32_t gpio34_int_type: 2; /**< bit[4:5]: 0:low_level; 1:high_levle; 2:rising edge; 3:falling edge R/W */ 99 uint32_t gpio35_int_type: 2; /**< bit[6:7]: 0:low_level; 1:high_levle; 2:rising edge; 3:falling edge R/W */ 100 uint32_t gpio36_int_type: 2; /**< bit[8:9]: 0:low_level; 1:high_levle; 2:rising edge; 3:falling edge R/W */ 101 uint32_t gpio37_int_type: 2; /**< bit[10:11]: 0:low_level; 1:high_levle; 2:rising edge; 3:falling edge R/W */ 102 uint32_t gpio38_int_type: 2; /**< bit[12:13]: 0:low_level; 1:high_levle; 2:rising edge; 3:falling edge R/W */ 103 uint32_t gpio39_int_type: 2; /**< bit[14:15]: 0:low_level; 1:high_levle; 2:rising edge; 3:falling edge R/W */ 104 uint32_t gpio40_int_type: 2; /**< bit[16:17]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 105 uint32_t gpio41_int_type: 2; /**< bit[18:19]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 106 uint32_t gpio42_int_type: 2; /**< bit[20:21]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 107 uint32_t gpio43_int_type: 2; /**< bit[22:23]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 108 uint32_t gpio44_int_type: 2; /**< bit[24:25]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 109 uint32_t gpio45_int_type: 2; /**< bit[26:27]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 110 uint32_t gpio46_int_type: 2; /**< bit[28:29]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 111 uint32_t gpio47_int_type: 2; /**< bit[30:31]: 0:low_level; 1:high_level; 2:rising edge; 3:falling edge R/W */ 112 113 }; 114 uint32_t v; 115 } gpio_32_47_int_type; 116 117 118 //reg0x43 int_enable1 119 union { 120 struct { 121 uint32_t gpio0_int_enable: 1; /**< bit[0]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 122 uint32_t gpio1_int_enable: 1; /**< bit[1]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 123 uint32_t gpio2_int_enable: 1; /**< bit[2]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 124 uint32_t gpio3_int_enable: 1; /**< bit[3]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 125 uint32_t gpio4_int_enable: 1; /**< bit[4]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 126 uint32_t gpio5_int_enable: 1; /**< bit[5]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 127 uint32_t gpio6_int_enable: 1; /**< bit[6]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 128 uint32_t gpio7_int_enable: 1; /**< bit[7]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 129 uint32_t gpio8_int_enable: 1; /**< bit[8]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 130 uint32_t gpio9_int_enable: 1; /**< bit[9]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 131 uint32_t gpio10_int_enable: 1; /**< bit[10]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 132 uint32_t gpio11_int_enable: 1; /**< bit[11]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 133 uint32_t gpio12_int_enable: 1; /**< bit[12]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 134 uint32_t gpio13_int_enable: 1; /**< bit[13]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 135 uint32_t gpio14_int_enable: 1; /**< bit[14]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 136 uint32_t gpio15_int_enable: 1; /**< bit[15]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 137 uint32_t gpio16_int_enable: 1; /**< bit[16]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 138 uint32_t gpio17_int_enable: 1; /**< bit[17]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 139 uint32_t gpio18_int_enable: 1; /**< bit[18]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 140 uint32_t gpio19_int_enable: 1; /**< bit[19]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 141 uint32_t gpio20_int_enable: 1; /**< bit[20]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 142 uint32_t gpio21_int_enable: 1; /**< bit[21]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 143 uint32_t gpio22_int_enable: 1; /**< bit[22]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 144 uint32_t gpio23_int_enable: 1; /**< bit[23]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 145 uint32_t gpio24_int_enable: 1; /**< bit[24]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 146 uint32_t gpio25_int_enable: 1; /**< bit[25]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 147 uint32_t gpio26_int_enable: 1; /**< bit[26]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 148 uint32_t gpio27_int_enable: 1; /**< bit[27]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 149 uint32_t gpio28_int_enable: 1; /**< bit[28]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 150 uint32_t gpio29_int_enable: 1; /**< bit[29]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 151 uint32_t gpio30_int_enable: 1; /**< bit[30]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 152 uint32_t gpio31_int_enable: 1; /**< bit[31]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 153 }; 154 uint32_t v; 155 } gpio_0_31_int_enable; 156 157 158 //reg0x44 int_enable2 159 union { 160 struct { 161 uint32_t gpio32_int_enable: 1; /**< bit[0]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 162 uint32_t gpio33_int_enable: 1; /**< bit[1]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 163 uint32_t gpio34_int_enable: 1; /**< bit[2]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 164 uint32_t gpio35_int_enable: 1; /**< bit[3]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 165 uint32_t gpio36_int_enable: 1; /**< bit[4]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 166 uint32_t gpio37_int_enable: 1; /**< bit[5]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 167 uint32_t gpio38_int_enable: 1; /**< bit[6]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 168 uint32_t gpio39_int_enable: 1; /**< bit[7]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 169 uint32_t gpio40_int_enable: 1; /**< bit[8]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 170 uint32_t gpio41_int_enable: 1; /**< bit[9]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 171 uint32_t gpio42_int_enable: 1; /**< bit[10]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 172 uint32_t gpio43_int_enable: 1; /**< bit[11]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 173 uint32_t gpio44_int_enable: 1; /**< bit[12]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 174 uint32_t gpio45_int_enable: 1; /**< bit[13]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 175 uint32_t gpio46_int_enable: 1; /**< bit[14]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 176 uint32_t gpio47_int_enable: 1; /**< bit[15]:gpio_int_enable_bit: 0:disable; 1:enable R/W */ 177 178 179 uint32_t reserved: 16; 180 }; 181 uint32_t v; 182 } gpio_32_47_int_enable; 183 184 185 //reg0x45 int_status1 186 union { 187 struct { 188 uint32_t gpio0_int_st: 1; /**< bit[0] interrupt status R */ 189 uint32_t gpio1_int_st: 1; /**< bit[1] interrupt status R */ 190 uint32_t gpio2_int_st: 1; /**< bit[2] interrupt status R */ 191 uint32_t gpio3_int_st: 1; /**< bit[3] interrupt status R */ 192 uint32_t gpio4_int_st: 1; /**< bit[4] interrupt status R */ 193 uint32_t gpio5_int_st: 1; /**< bit[5] interrupt status R */ 194 uint32_t gpio6_int_st: 1; /**< bit[6] interrupt status R */ 195 uint32_t gpio7_int_st: 1; /**< bit[7] interrupt status R */ 196 uint32_t gpio8_int_st: 1; /**< bit[8] interrupt status R */ 197 uint32_t gpio9_int_st: 1; /**< bit[9] interrupt status R */ 198 uint32_t gpio10_int_st: 1; /**< bit[10] interrupt status R */ 199 uint32_t gpio11_int_st: 1; /**< bit[11] interrupt status R */ 200 uint32_t gpio12_int_st: 1; /**< bit[12] interrupt status R */ 201 uint32_t gpio13_int_st: 1; /**< bit[13] interrupt status R */ 202 uint32_t gpio14_int_st: 1; /**< bit[14] interrupt status R */ 203 uint32_t gpio15_int_st: 1; /**< bit[15] interrupt status R */ 204 uint32_t gpio16_int_st: 1; /**< bit[16] interrupt status R */ 205 uint32_t gpio17_int_st: 1; /**< bit[17] interrupt status R */ 206 uint32_t gpio18_int_st: 1; /**< bit[18] interrupt status R */ 207 uint32_t gpio19_int_st: 1; /**< bit[19] interrupt status R */ 208 uint32_t gpio20_int_st: 1; /**< bit[20] interrupt status R */ 209 uint32_t gpio21_int_st: 1; /**< bit[21] interrupt status R */ 210 uint32_t gpio22_int_st: 1; /**< bit[22] interrupt status R */ 211 uint32_t gpio23_int_st: 1; /**< bit[23] interrupt status R */ 212 uint32_t gpio24_int_st: 1; /**< bit[24] interrupt status R */ 213 uint32_t gpio25_int_st: 1; /**< bit[25] interrupt status R */ 214 uint32_t gpio26_int_st: 1; /**< bit[26] interrupt status R */ 215 uint32_t gpio27_int_st: 1; /**< bit[27] interrupt status R */ 216 uint32_t gpio28_int_st: 1; /**< bit[28] interrupt status R */ 217 uint32_t gpio29_int_st: 1; /**< bit[29] interrupt status R */ 218 uint32_t gpio30_int_st: 1; /**< bit[30] interrupt status R */ 219 uint32_t gpio31_int_st: 1; /**< bit[31] interrupt status R */ 220 }; 221 uint32_t v; 222 }gpio_0_31_int_st; 223 224 //reg0x46 int_status2 225 union { 226 struct { 227 uint32_t gpio32_int_st: 1; /**< bit[0] interrupt status R */ 228 uint32_t gpio33_int_st: 1; /**< bit[1] interrupt status R */ 229 uint32_t gpio34_int_st: 1; /**< bit[2] interrupt status R */ 230 uint32_t gpio35_int_st: 1; /**< bit[3] interrupt status R */ 231 uint32_t gpio36_int_st: 1; /**< bit[4] interrupt status R */ 232 uint32_t gpio37_int_st: 1; /**< bit[5] interrupt status R */ 233 uint32_t gpio38_int_st: 1; /**< bit[6] interrupt status R */ 234 uint32_t gpio39_int_st: 1; /**< bit[7] interrupt status R */ 235 uint32_t gpio40_int_st: 1; /**< bit[8] interrupt status R */ 236 uint32_t gpio41_int_st: 1; /**< bit[9] interrupt status R */ 237 uint32_t gpio42_int_st: 1; /**< bit[10] interrupt status R */ 238 uint32_t gpio43_int_st: 1; /**< bit[11] interrupt status R */ 239 uint32_t gpio44_int_st: 1; /**< bit[12] interrupt status R */ 240 uint32_t gpio45_int_st: 1; /**< bit[13] interrupt status R */ 241 uint32_t gpio46_int_st: 1; /**< bit[14] interrupt status R */ 242 uint32_t gpio47_int_st: 1; /**< bit[15] interrupt status R */ 243 244 uint32_t reserved: 16; 245 246 }; 247 uint32_t v; 248 } gpio_32_47_int_st; 249 250 251 //reg0x47 int_clr1 252 union { 253 struct { 254 uint32_t gpio0_int_clr: 1; /**< bit[0], write 1 to clear W */ 255 uint32_t gpio1_int_clr: 1; /**< bit[1], write 1 to clear W */ 256 uint32_t gpio2_int_clr: 1; /**< bit[2], write 1 to clear W */ 257 uint32_t gpio3_int_clr: 1; /**< bit[3], write 1 to clear W */ 258 uint32_t gpio4_int_clr: 1; /**< bit[4], write 1 to clear W */ 259 uint32_t gpio5_int_clr: 1; /**< bit[5], write 1 to clear W */ 260 uint32_t gpio6_int_clr: 1; /**< bit[6], write 1 to clear W */ 261 uint32_t gpio7_int_clr: 1; /**< bit[7], write 1 to clear W */ 262 uint32_t gpio8_int_clr: 1; /**< bit[8], write 1 to clear W */ 263 uint32_t gpio9_int_clr: 1; /**< bit[9], write 1 to clear W */ 264 uint32_t gpio10_int_clr: 1; /**< bit[10], write 1 to clear W */ 265 uint32_t gpio11_int_clr: 1; /**< bit[11], write 1 to clear W */ 266 uint32_t gpio12_int_clr: 1; /**< bit[12], write 1 to clear W */ 267 uint32_t gpio13_int_clr: 1; /**< bit[13], write 1 to clear W */ 268 uint32_t gpio14_int_clr: 1; /**< bit[14], write 1 to clear W */ 269 uint32_t gpio15_int_clr: 1; /**< bit[15], write 1 to clear W */ 270 uint32_t gpio16_int_clr: 1; /**< bit[16], write 1 to clear W */ 271 uint32_t gpio17_int_clr: 1; /**< bit[17], write 1 to clear W */ 272 uint32_t gpio18_int_clr: 1; /**< bit[18], write 1 to clear W */ 273 uint32_t gpio19_int_clr: 1; /**< bit[19], write 1 to clear W */ 274 uint32_t gpio20_int_clr: 1; /**< bit[20], write 1 to clear W */ 275 uint32_t gpio21_int_clr: 1; /**< bit[21], write 1 to clear W */ 276 uint32_t gpio22_int_clr: 1; /**< bit[22], write 1 to clear W */ 277 uint32_t gpio23_int_clr: 1; /**< bit[23], write 1 to clear W */ 278 uint32_t gpio24_int_clr: 1; /**< bit[24], write 1 to clear W */ 279 uint32_t gpio25_int_clr: 1; /**< bit[25], write 1 to clear W */ 280 uint32_t gpio26_int_clr: 1; /**< bit[26], write 1 to clear W */ 281 uint32_t gpio27_int_clr: 1; /**< bit[27], write 1 to clear W */ 282 uint32_t gpio28_int_clr: 1; /**< bit[28], write 1 to clear W */ 283 uint32_t gpio29_int_clr: 1; /**< bit[29], write 1 to clear W */ 284 uint32_t gpio30_int_clr: 1; /**< bit[30], write 1 to clear W */ 285 uint32_t gpio31_int_clr: 1; /**< bit[31], write 1 to clear W */ 286 }; 287 uint32_t v; 288 }gpio_0_31_int_clr; 289 290 //reg0x48 int_clr2 291 union { 292 struct { 293 uint32_t gpio32_int_clr: 1; /**< bit[0], write 1 to clear W */ 294 uint32_t gpio33_int_clr: 1; /**< bit[1], write 1 to clear W */ 295 uint32_t gpio34_int_clr: 1; /**< bit[2], write 1 to clear W */ 296 uint32_t gpio35_int_clr: 1; /**< bit[3], write 1 to clear W */ 297 uint32_t gpio36_int_clr: 1; /**< bit[4], write 1 to clear W */ 298 uint32_t gpio37_int_clr: 1; /**< bit[5], write 1 to clear W */ 299 uint32_t gpio38_int_clr: 1; /**< bit[6], write 1 to clear W */ 300 uint32_t gpio39_int_clr: 1; /**< bit[7], write 1 to clear W */ 301 uint32_t gpio40_int_clr: 1; /**< bit[8], write 1 to clear W */ 302 uint32_t gpio41_int_clr: 1; /**< bit[9], write 1 to clear W */ 303 uint32_t gpio42_int_clr: 1; /**< bit[10], write 1 to clear W */ 304 uint32_t gpio43_int_clr: 1; /**< bit[11], write 1 to clear W */ 305 uint32_t gpio44_int_clr: 1; /**< bit[12], write 1 to clear W */ 306 uint32_t gpio45_int_clr: 1; /**< bit[13], write 1 to clear W */ 307 uint32_t gpio46_int_clr: 1; /**< bit[14], write 1 to clear W */ 308 uint32_t gpio47_int_clr: 1; /**< bit[15], write 1 to clear W */ 309 310 uint32_t reserved: 16; 311 312 }; 313 uint32_t v; 314 } gpio_32_47_int_clr; 315 316 } gpio_hw_t; 317 318 319 typedef volatile struct { 320 union { 321 struct { 322 uint32_t gpio_system_group0: 4; /**< bit[0:3] 0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5 R/W */ 323 uint32_t gpio_system_group1: 4; /**< bit[4:7] 0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5 R/W */ 324 uint32_t gpio_system_group2: 4; /**< bit[8:11] 0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5 R/W */ 325 uint32_t gpio_system_group3: 4; /**< bit[12:15] 0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5 R/W */ 326 uint32_t gpio_system_group4: 4; /**< bit[16:19] 0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5 R/W */ 327 uint32_t gpio_system_group5: 4; /**< bit[20:23] 0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5 R/W */ 328 uint32_t gpio_system_group6: 4; /**< bit[24:27] 0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5 R/W */ 329 uint32_t gpio_system_group7: 4; /**< bit[28:32] 0:mode1; 1:mode2; 2:mode3; 3:mode4 4:mode5 R/W */ 330 331 }; 332 uint32_t v; 333 } gpio_sys_num[SOC_GPIO_SYSTEM_GROUP_NUM]; 334 } system_gpio_func_mode_hw_t; 335 336 #ifdef __cplusplus 337 } 338 #endif 339