1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 * ************************************************************
29 */
30
31 #include "mp_precomp.h"
32 #include "phydm_precomp.h"
33
34 #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
35 RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
36 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
37 RTL8812F_SUPPORT == 1 || RTL8710C_SUPPORT == 1 ||\
38 RTL8197G_SUPPORT == 1 || RTL8814C_SUPPORT == 1 )
39
_iqk_check_if_reload(void * dm_void)40 void _iqk_check_if_reload(void *dm_void)
41 {
42 struct dm_struct *dm = (struct dm_struct *)dm_void;
43 struct dm_iqk_info *iqk_info = &dm->IQK_info;
44
45 iqk_info->is_reload = (boolean)odm_get_bb_reg(dm, R_0x1bf0, BIT(16));
46 }
47
_iqk_page_switch(void * dm_void)48 void _iqk_page_switch(void *dm_void)
49 {
50 struct dm_struct *dm = (struct dm_struct *)dm_void;
51
52 if (dm->support_ic_type == ODM_RTL8821C)
53 odm_write_4byte(dm, 0x1b00, 0xf8000008);
54 else
55 odm_write_4byte(dm, 0x1b00, 0xf800000a);
56 }
57
halrf_psd_log2base(u32 val)58 u32 halrf_psd_log2base(u32 val)
59 {
60 u8 j;
61 u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
62 u32 result, val_fractiond_b = 0;
63 u32 table_fraction[21] = {
64 0, 432, 332, 274, 232, 200, 174, 151, 132, 115,
65 100, 86, 74, 62, 51, 42, 32, 23, 15, 7, 0};
66
67 if (val == 0)
68 return 0;
69
70 tmp = val;
71
72 while (1) {
73 if (tmp == 1)
74 break;
75
76 tmp = (tmp >> 1);
77 shiftcount++;
78 }
79
80 val_integerd_b = shiftcount + 1;
81
82 tmp2 = 1;
83 for (j = 1; j <= val_integerd_b; j++)
84 tmp2 = tmp2 * 2;
85
86 tmp = (val * 100) / tmp2;
87 tindex = tmp / 5;
88
89 if (tindex > 20)
90 tindex = 20;
91
92 val_fractiond_b = table_fraction[tindex];
93
94 result = val_integerd_b * 100 - val_fractiond_b;
95
96 return result;
97 }
98 #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
99 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
100 RTL8814C_SUPPORT == 1)
halrf_iqk_xym_enable(struct dm_struct * dm,u8 xym_enable)101 void halrf_iqk_xym_enable(struct dm_struct *dm, u8 xym_enable)
102 {
103 struct dm_iqk_info *iqk_info = &dm->IQK_info;
104
105 if (xym_enable == 0)
106 iqk_info->xym_read = false;
107 else
108 iqk_info->xym_read = true;
109
110 RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s %s\n", "xym_read = ",
111 (iqk_info->xym_read ? "true" : "false"));
112 }
113
114 /*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/
halrf_iqk_xym_read(void * dm_void,u8 path,u8 xym_type)115 void halrf_iqk_xym_read(void *dm_void, u8 path, u8 xym_type)
116 {
117 struct dm_struct *dm = (struct dm_struct *)dm_void;
118 struct dm_iqk_info *iqk_info = &dm->IQK_info;
119 u8 i, start, num;
120 u32 tmp1, tmp2;
121
122 if (!iqk_info->xym_read)
123 return;
124
125 if (*dm->band_width == 0) {
126 start = 3;
127 num = 4;
128 } else if (*dm->band_width == 1) {
129 start = 2;
130 num = 6;
131 } else {
132 start = 0;
133 num = 10;
134 }
135
136 odm_write_4byte(dm, 0x1b00, 0xf8000008);
137 tmp1 = odm_read_4byte(dm, 0x1b1c);
138 odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
139
140 odm_write_4byte(dm, 0x1b00, 0xf800000a);
141 tmp2 = odm_read_4byte(dm, 0x1b1c);
142 odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
143
144 for (path = 0; path < 2; path++) {
145 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
146 switch (xym_type) {
147 case 0:
148 for (i = 0; i < num; i++) {
149 odm_write_4byte(dm, 0x1b14, 0xe6 + start + i);
150 odm_write_4byte(dm, 0x1b14, 0x0);
151 iqk_info->rx_xym[path][i] =
152 odm_read_4byte(dm, 0x1b38);
153 }
154 break;
155 case 1:
156 for (i = 0; i < num; i++) {
157 odm_write_4byte(dm, 0x1b14, 0xe6 + start + i);
158 odm_write_4byte(dm, 0x1b14, 0x0);
159 iqk_info->tx_xym[path][i] =
160 odm_read_4byte(dm, 0x1b38);
161 }
162 break;
163 case 2:
164 for (i = 0; i < 6; i++) {
165 odm_write_4byte(dm, 0x1b14, 0xe0 + i);
166 odm_write_4byte(dm, 0x1b14, 0x0);
167 iqk_info->gs1_xym[path][i] =
168 odm_read_4byte(dm, 0x1b38);
169 }
170 break;
171 case 3:
172 for (i = 0; i < 6; i++) {
173 odm_write_4byte(dm, 0x1b14, 0xe0 + i);
174 odm_write_4byte(dm, 0x1b14, 0x0);
175 iqk_info->gs2_xym[path][i] =
176 odm_read_4byte(dm, 0x1b38);
177 }
178 break;
179 case 4:
180 for (i = 0; i < 6; i++) {
181 odm_write_4byte(dm, 0x1b14, 0xe0 + i);
182 odm_write_4byte(dm, 0x1b14, 0x0);
183 iqk_info->rxk1_xym[path][i] =
184 odm_read_4byte(dm, 0x1b38);
185 }
186 break;
187 }
188 odm_write_4byte(dm, 0x1b38, 0x20000000);
189 odm_write_4byte(dm, 0x1b00, 0xf8000008);
190 odm_write_4byte(dm, 0x1b1c, tmp1);
191 odm_write_4byte(dm, 0x1b00, 0xf800000a);
192 odm_write_4byte(dm, 0x1b1c, tmp2);
193 _iqk_page_switch(dm);
194 }
195 }
196
197 /*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/
halrf_iqk_xym_show(struct dm_struct * dm,u8 xym_type)198 void halrf_iqk_xym_show(struct dm_struct *dm, u8 xym_type)
199 {
200 u8 num, path, path_num, i;
201 struct dm_iqk_info *iqk_info = &dm->IQK_info;
202
203 if (dm->rf_type == RF_1T1R)
204 path_num = 0x1;
205 else if (dm->rf_type == RF_2T2R)
206 path_num = 0x2;
207 else
208 path_num = 0x4;
209
210 if (*dm->band_width == CHANNEL_WIDTH_20)
211 num = 4;
212 else if (*dm->band_width == CHANNEL_WIDTH_40)
213 num = 6;
214 else
215 num = 10;
216
217 for (path = 0; path < path_num; path++) {
218 switch (xym_type) {
219 case 0:
220 for (i = 0; i < num; i++)
221 RF_DBG(dm, DBG_RF_IQK,
222 "[IQK]%-20s %-2d: 0x%x\n",
223 (path == 0) ? "PATH A RX-XYM " :
224 "PATH B RX-XYM", i,
225 iqk_info->rx_xym[path][i]);
226 break;
227 case 1:
228 for (i = 0; i < num; i++)
229 RF_DBG(dm, DBG_RF_IQK,
230 "[IQK]%-20s %-2d: 0x%x\n",
231 (path == 0) ? "PATH A TX-XYM " :
232 "PATH B TX-XYM", i,
233 iqk_info->tx_xym[path][i]);
234 break;
235 case 2:
236 for (i = 0; i < 6; i++)
237 RF_DBG(dm, DBG_RF_IQK,
238 "[IQK]%-20s %-2d: 0x%x\n",
239 (path == 0) ? "PATH A GS1-XYM " :
240 "PATH B GS1-XYM", i,
241 iqk_info->gs1_xym[path][i]);
242 break;
243 case 3:
244 for (i = 0; i < 6; i++)
245 RF_DBG(dm, DBG_RF_IQK,
246 "[IQK]%-20s %-2d: 0x%x\n",
247 (path == 0) ? "PATH A GS2-XYM " :
248 "PATH B GS2-XYM", i,
249 iqk_info->gs2_xym[path][i]);
250 break;
251 case 4:
252 for (i = 0; i < 6; i++)
253 RF_DBG(dm, DBG_RF_IQK,
254 "[IQK]%-20s %-2d: 0x%x\n",
255 (path == 0) ? "PATH A RXK1-XYM " :
256 "PATH B RXK1-XYM", i,
257 iqk_info->rxk1_xym[path][i]);
258 break;
259 }
260 }
261 }
262
halrf_iqk_xym_dump(void * dm_void)263 void halrf_iqk_xym_dump(void *dm_void)
264 {
265 u32 tmp1, tmp2;
266 struct dm_struct *dm = (struct dm_struct *)dm_void;
267
268 odm_write_4byte(dm, 0x1b00, 0xf8000008);
269 tmp1 = odm_read_4byte(dm, 0x1b1c);
270 odm_write_4byte(dm, 0x1b00, 0xf800000a);
271 tmp2 = odm_read_4byte(dm, 0x1b1c);
272 #if 0
273 /*halrf_iqk_xym_read(dm, xym_type);*/
274 #endif
275 odm_write_4byte(dm, 0x1b00, 0xf8000008);
276 odm_write_4byte(dm, 0x1b1c, tmp1);
277 odm_write_4byte(dm, 0x1b00, 0xf800000a);
278 odm_write_4byte(dm, 0x1b1c, tmp2);
279 _iqk_page_switch(dm);
280 }
281 #endif
halrf_iqk_info_dump(void * dm_void,u32 * _used,char * output,u32 * _out_len)282 void halrf_iqk_info_dump(void *dm_void, u32 *_used, char *output, u32 *_out_len)
283 {
284 struct dm_struct *dm = (struct dm_struct *)dm_void;
285 u32 used = *_used;
286 u32 out_len = *_out_len;
287 u8 rf_path, j, reload_iqk = 0;
288 u32 tmp;
289 /*two channel, PATH, TX/RX, 0:pass 1 :fail*/
290 boolean iqk_result[2][NUM][2];
291 struct dm_iqk_info *iqk_info = &dm->IQK_info;
292
293 if (!(dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)))
294 return;
295
296 /* IQK INFO */
297 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s\n",
298 "% IQK Info %");
299 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s\n",
300 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" :
301 "Driver-IQK");
302
303 reload_iqk = (u8)odm_get_bb_reg(dm, R_0x1bf0, BIT(16));
304 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
305 "reload", (reload_iqk) ? "True" : "False");
306
307 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
308 "rfk_forbidden", (iqk_info->rfk_forbidden) ? "True" : "False");
309 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
310 RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
311 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1||\
312 RTL8814C_SUPPORT == 1 )
313 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
314 "segment_iqk", (iqk_info->segment_iqk) ? "True" : "False");
315 #endif
316
317 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s:%d %d\n",
318 "iqk count / fail count", dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
319
320 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %d\n",
321 "channel", *dm->channel);
322
323 if (*dm->band_width == CHANNEL_WIDTH_20)
324 PDM_SNPF(out_len, used, output + used, out_len - used,
325 "%-20s: %s\n", "bandwidth", "BW_20");
326 else if (*dm->band_width == CHANNEL_WIDTH_40)
327 PDM_SNPF(out_len, used, output + used, out_len - used,
328 "%-20s: %s\n", "bandwidth", "BW_40");
329 else if (*dm->band_width == CHANNEL_WIDTH_80)
330 PDM_SNPF(out_len, used, output + used, out_len - used,
331 "%-20s: %s\n", "bandwidth", "BW_80");
332 else if (*dm->band_width == CHANNEL_WIDTH_160)
333 PDM_SNPF(out_len, used, output + used, out_len - used,
334 "%-20s: %s\n", "bandwidth", "BW_160");
335 else if (*dm->band_width == CHANNEL_WIDTH_80_80)
336 PDM_SNPF(out_len, used, output + used, out_len - used,
337 "%-20s: %s\n", "bandwidth", "BW_80_80");
338 else
339 PDM_SNPF(out_len, used, output + used, out_len - used,
340 "%-20s: %s\n", "bandwidth", "BW_UNKNOWN");
341
342 PDM_SNPF(out_len, used, output + used, out_len - used,
343 "%-20s: %llu %s\n", "progressing_time",
344 dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)");
345
346 tmp = odm_read_4byte(dm, 0x1bf0);
347 for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)
348 for (j = 0; j < 2; j++)
349 iqk_result[0][rf_path][j] = (boolean)
350 (tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))));
351
352 PDM_SNPF(out_len, used, output + used, out_len - used,
353 "%-20s: 0x%08x\n", "Reg0x1bf0", tmp);
354 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
355 "PATH_A-Tx result",
356 (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass");
357 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
358 "PATH_A-Rx result",
359 (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass");
360 #if (RTL8822B_SUPPORT == 1)
361 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
362 "PATH_B-Tx result",
363 (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass");
364 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
365 "PATH_B-Rx result",
366 (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass");
367 #endif
368 *_used = used;
369 *_out_len = out_len;
370 }
371
halrf_get_fw_version(void * dm_void)372 void halrf_get_fw_version(void *dm_void)
373 {
374 struct dm_struct *dm = (struct dm_struct *)dm_void;
375 struct _hal_rf_ *rf = &dm->rf_table;
376
377 rf->fw_ver = (dm->fw_version << 16) | dm->fw_sub_version;
378 }
379
halrf_iqk_dbg(void * dm_void)380 void halrf_iqk_dbg(void *dm_void)
381 {
382 struct dm_struct *dm = (struct dm_struct *)dm_void;
383 u8 rf_path, j;
384 u32 tmp;
385 /*two channel, PATH, TX/RX, 0:pass 1 :fail*/
386 boolean iqk_result[2][NUM][2];
387 struct dm_iqk_info *iqk_info = &dm->IQK_info;
388 struct _hal_rf_ *rf = &dm->rf_table;
389
390 /* IQK INFO */
391 RF_DBG(dm, DBG_RF_IQK, "%-20s\n", "====== IQK Info ======");
392
393 RF_DBG(dm, DBG_RF_IQK, "%-20s\n",
394 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" :
395 "Driver-IQK");
396
397 if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) {
398 halrf_get_fw_version(dm);
399 RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%x\n", "FW_VER", rf->fw_ver);
400 } else {
401 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "IQK_VER", HALRF_IQK_VER);
402 }
403
404 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "reload",
405 (iqk_info->is_reload) ? "True" : "False");
406
407 RF_DBG(dm, DBG_RF_IQK, "%-20s: %d %d\n", "iqk count / fail count",
408 dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
409
410 RF_DBG(dm, DBG_RF_IQK, "%-20s: %d\n", "channel", *dm->channel);
411
412 if (*dm->band_width == CHANNEL_WIDTH_20)
413 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_20");
414 else if (*dm->band_width == CHANNEL_WIDTH_40)
415 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_40");
416 else if (*dm->band_width == CHANNEL_WIDTH_80)
417 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_80");
418 else if (*dm->band_width == CHANNEL_WIDTH_160)
419 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_160");
420 else if (*dm->band_width == CHANNEL_WIDTH_80_80)
421 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_80_80");
422 else
423 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth",
424 "BW_UNKNOWN");
425 #if 0
426 /*
427 * RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n",
428 * "progressing_time",
429 * dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)");
430 */
431 #endif
432 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "rfk_forbidden",
433 (iqk_info->rfk_forbidden) ? "True" : "False");
434 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
435 RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
436 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1||\
437 RTL8814C_SUPPORT == 1)
438 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "segment_iqk",
439 (iqk_info->segment_iqk) ? "True" : "False");
440 #endif
441
442 RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", "progressing_time",
443 dm->rf_calibrate_info.iqk_progressing_time, "(ms)");
444
445 tmp = odm_read_4byte(dm, 0x1bf0);
446 for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)
447 for (j = 0; j < 2; j++)
448 iqk_result[0][rf_path][j] = (boolean)
449 (tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))));
450
451 RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%08x\n", "Reg0x1bf0", tmp);
452 RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%08x\n", "Reg0x1be8",
453 odm_read_4byte(dm, 0x1be8));
454 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_A-Tx result",
455 (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass");
456 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_A-Rx result",
457 (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass");
458 #if (RTL8822B_SUPPORT == 1)
459 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_B-Tx result",
460 (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass");
461 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_B-Rx result",
462 (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass");
463 #endif
464 }
465
halrf_lck_dbg(struct dm_struct * dm)466 void halrf_lck_dbg(struct dm_struct *dm)
467 {
468 RF_DBG(dm, DBG_RF_IQK, "%-20s\n", "====== LCK Info ======");
469 #if 0
470 /*RF_DBG(dm, DBG_RF_IQK, "%-20s\n",
471 * (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "LCK" : "RTK"));
472 */
473 #endif
474 RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", "progressing_time",
475 dm->rf_calibrate_info.lck_progressing_time, "(ms)");
476 }
phydm_get_iqk_cfir(void * dm_void,u8 idx,u8 path,boolean debug)477 void phydm_get_iqk_cfir(void *dm_void, u8 idx, u8 path, boolean debug)
478 {
479 struct dm_struct *dm = (struct dm_struct *)dm_void;
480
481 switch (dm->support_ic_type) {
482 #if (RTL8822B_SUPPORT == 1)
483 case ODM_RTL8822B:
484 phy_get_iqk_cfir_8822b(dm, idx, path, debug);
485 break;
486 #endif
487 #if (RTL8822C_SUPPORT == 1)
488 case ODM_RTL8822C:
489 phy_get_iqk_cfir_8822c(dm, idx, path, debug);
490 break;
491 #endif
492 #if (RTL8814B_SUPPORT == 1)
493 case ODM_RTL8814B:
494 phy_get_iqk_cfir_8814b(dm, idx, path, debug);
495 break;
496 #endif
497 #if (RTL8814C_SUPPORT == 1)
498 case ODM_RTL8814C:
499 phy_get_iqk_cfir_8814c(dm, idx, path, debug);
500 break;
501 #endif
502
503 default:
504 break;
505 }
506 }
507
508
halrf_iqk_dbg_cfir_backup(void * dm_void)509 void halrf_iqk_dbg_cfir_backup(void *dm_void)
510 {
511 struct dm_struct *dm = (struct dm_struct *)dm_void;
512 struct dm_iqk_info *iqk_info = &dm->IQK_info;
513 u8 path, idx, i;
514
515 switch (dm->support_ic_type) {
516 #if (RTL8822B_SUPPORT == 1)
517 case ODM_RTL8822B:
518 phy_iqk_dbg_cfir_backup_8822b(dm);
519 break;
520 #endif
521 #if (RTL8822C_SUPPORT == 1)
522 case ODM_RTL8822C:
523 phy_iqk_dbg_cfir_backup_8822c(dm);
524 break;
525 #endif
526 #if (RTL8814B_SUPPORT == 1)
527 case ODM_RTL8814B:
528 phy_iqk_dbg_cfir_backup_8814b(dm);
529 break;
530 #endif
531 #if (RTL8814C_SUPPORT == 1)
532 case ODM_RTL8814C:
533 phy_iqk_dbg_cfir_backup_8814c(dm);
534 break;
535 #endif
536
537 default:
538 break;
539 }
540
541 }
542
halrf_iqk_dbg_cfir_backup_update(void * dm_void)543 void halrf_iqk_dbg_cfir_backup_update(void *dm_void)
544 {
545 struct dm_struct *dm = (struct dm_struct *)dm_void;
546 struct dm_iqk_info *iqk = &dm->IQK_info;
547 u8 i, path, idx;
548 u32 bmask13_12 = BIT(13) | BIT(12);
549 u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
550 u32 data;
551
552 switch (dm->support_ic_type) {
553 #if (RTL8822B_SUPPORT == 1)
554 case ODM_RTL8822B:
555 phy_iqk_dbg_cfir_backup_update_8822b(dm);
556 break;
557 #endif
558 #if (RTL8822C_SUPPORT == 1)
559 case ODM_RTL8822C:
560 phy_iqk_dbg_cfir_backup_update_8822c(dm);
561 break;
562 #endif
563 #if (RTL8814C_SUPPORT == 1)
564 case ODM_RTL8814C:
565 phy_iqk_dbg_cfir_backup_update_8814c(dm);
566 break;
567 #endif
568
569 default:
570 break;
571 }
572 }
573
halrf_iqk_dbg_cfir_reload(void * dm_void)574 void halrf_iqk_dbg_cfir_reload(void *dm_void)
575 {
576 struct dm_struct *dm = (struct dm_struct *)dm_void;
577 struct dm_iqk_info *iqk = &dm->IQK_info;
578 u8 i, path, idx;
579 u32 bmask13_12 = BIT(13) | BIT(12);
580 u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
581 u32 data;
582
583 switch (dm->support_ic_type) {
584 #if (RTL8822B_SUPPORT == 1)
585 case ODM_RTL8822B:
586 phy_iqk_dbg_cfir_reload_8822b(dm);
587 break;
588 #endif
589 #if (RTL8822C_SUPPORT == 1)
590 case ODM_RTL8822C:
591 phy_iqk_dbg_cfir_reload_8822c(dm);
592 break;
593 #endif
594 #if (RTL8814C_SUPPORT == 1)
595 case ODM_RTL8814C:
596 phy_iqk_dbg_cfir_reload_8814c(dm);
597 break;
598 #endif
599
600 default:
601 break;
602 }
603 }
604
halrf_iqk_dbg_cfir_write(void * dm_void,u8 type,u32 path,u32 idx,u32 i,u32 data)605 void halrf_iqk_dbg_cfir_write(void *dm_void, u8 type, u32 path, u32 idx,
606 u32 i, u32 data)
607 {
608 struct dm_struct *dm = (struct dm_struct *)dm_void;
609 struct dm_iqk_info *iqk_info = &dm->IQK_info;
610
611 switch (dm->support_ic_type) {
612 #if (RTL8822B_SUPPORT == 1)
613 case ODM_RTL8822B:
614 phy_iqk_dbg_cfir_write_8822b(dm, type, path, idx, i, data);
615 break;
616 #endif
617 #if (RTL8822C_SUPPORT == 1)
618 case ODM_RTL8822C:
619 phy_iqk_dbg_cfir_write_8822c(dm, type, path, idx, i, data);
620 break;
621 #endif
622 #if (RTL8814C_SUPPORT == 1)
623 case ODM_RTL8814C:
624 phy_iqk_dbg_cfir_write_8814c(dm, type, path, idx, i, data);
625 break;
626 #endif
627
628 default:
629 break;
630 }
631 }
632
halrf_iqk_dbg_cfir_backup_show(void * dm_void)633 void halrf_iqk_dbg_cfir_backup_show(void *dm_void)
634 {
635 struct dm_struct *dm = (struct dm_struct *)dm_void;
636 struct dm_iqk_info *iqk_info = &dm->IQK_info;
637 u8 path, idx, i;
638
639 switch (dm->support_ic_type) {
640 #if (RTL8822B_SUPPORT == 1)
641 case ODM_RTL8822B:
642 phy_iqk_dbg_cfir_backup_8822b(dm);
643 break;
644 #endif
645 #if (RTL8822C_SUPPORT == 1)
646 case ODM_RTL8822C:
647 phy_iqk_dbg_cfir_backup_8822c(dm);
648 break;
649 #endif
650 #if (RTL8814C_SUPPORT == 1)
651 case ODM_RTL8814C:
652 phy_iqk_dbg_cfir_backup_8814c(dm);
653 break;
654 #endif
655
656 default:
657 break;
658 }
659 }
660
halrf_do_imr_test(void * dm_void,u8 flag_imr_test)661 void halrf_do_imr_test(void *dm_void, u8 flag_imr_test)
662 {
663 struct dm_struct *dm = (struct dm_struct *)dm_void;
664
665 if (flag_imr_test != 0x0)
666 switch (dm->support_ic_type) {
667 #if (RTL8822B_SUPPORT == 1)
668 case ODM_RTL8822B:
669 do_imr_test_8822b(dm);
670 break;
671 #endif
672 #if (RTL8821C_SUPPORT == 1)
673 case ODM_RTL8821C:
674 do_imr_test_8821c(dm);
675 break;
676 #endif
677 default:
678 break;
679 }
680 }
681
682 #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
683 RTL8814B_SUPPORT == 1 || RTL8814C_SUPPORT == 1)
halrf_iqk_debug(void * dm_void,u32 * const dm_value,u32 * _used,char * output,u32 * _out_len)684 void halrf_iqk_debug(void *dm_void, u32 *const dm_value, u32 *_used,
685 char *output, u32 *_out_len)
686 {
687 struct dm_struct *dm = (struct dm_struct *)dm_void;
688
689 #if 0
690 /*dm_value[0]=0x0: backup from SRAM & show*/
691 /*dm_value[0]=0x1: write backup CFIR to SRAM*/
692 /*dm_value[0]=0x2: reload default CFIR to SRAM*/
693 /*dm_value[0]=0x3: show backup*/
694 /*dm_value[0]=0x10: write backup CFIR real part*/
695 /*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/
696 /*dm_value[0]=0x11: write backup CFIR imag*/
697 /*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/
698 /*dm_value[0]=0x20 :xym_read enable*/
699 /*--> dm_value[1]:0:disable, 1:enable*/
700 /*if dm_value[0]=0x20 = enable, */
701 /*0x1:show rx_sym; 0x2: tx_xym; 0x3:gs1_xym; 0x4:gs2_sym; 0x5:rxk1_xym*/
702 #endif
703 if (dm_value[0] == 0x0)
704 halrf_iqk_dbg_cfir_backup(dm);
705 else if (dm_value[0] == 0x1)
706 halrf_iqk_dbg_cfir_backup_update(dm);
707 else if (dm_value[0] == 0x2)
708 halrf_iqk_dbg_cfir_reload(dm);
709 else if (dm_value[0] == 0x3)
710 halrf_iqk_dbg_cfir_backup_show(dm);
711 else if (dm_value[0] == 0x10)
712 halrf_iqk_dbg_cfir_write(dm, 0, dm_value[1], dm_value[2],
713 dm_value[3], dm_value[4]);
714 else if (dm_value[0] == 0x11)
715 halrf_iqk_dbg_cfir_write(dm, 1, dm_value[1], dm_value[2],
716 dm_value[3], dm_value[4]);
717 else if (dm_value[0] == 0x20)
718 halrf_iqk_xym_enable(dm, (u8)dm_value[1]);
719 else if (dm_value[0] == 0x21)
720 halrf_iqk_xym_show(dm, (u8)dm_value[1]);
721 else if (dm_value[0] == 0x30)
722 halrf_do_imr_test(dm, (u8)dm_value[1]);
723 }
724 #endif
725
halrf_iqk_hwtx_check(void * dm_void,boolean is_check)726 void halrf_iqk_hwtx_check(void *dm_void, boolean is_check)
727 {
728 #if 0
729 struct dm_struct *dm = (struct dm_struct *)dm_void;
730 struct dm_iqk_info *iqk_info = &dm->IQK_info;
731 u32 tmp_b04;
732
733 if (is_check) {
734 iqk_info->is_hwtx = (boolean)odm_get_bb_reg(dm, R_0xb00, BIT(8));
735 } else {
736 if (iqk_info->is_hwtx) {
737 tmp_b04 = odm_read_4byte(dm, 0xb04);
738 odm_set_bb_reg(dm, R_0xb04, BIT(3) | BIT(2), 0x0);
739 odm_write_4byte(dm, 0xb04, tmp_b04);
740 }
741 }
742 #endif
743 }
744 #endif
745
halrf_match_iqk_version(void * dm_void)746 u8 halrf_match_iqk_version(void *dm_void)
747 {
748 struct dm_struct *dm = (struct dm_struct *)dm_void;
749
750 u32 iqk_version = 0;
751 char temp[10] = {0};
752
753 odm_move_memory(dm, temp, HALRF_IQK_VER, sizeof(temp));
754 PHYDM_SSCANF(temp + 2, DCMD_HEX, &iqk_version);
755
756 if (dm->support_ic_type == ODM_RTL8822B) {
757 if (iqk_version >= 0x24 && (odm_get_hw_img_version(dm) >= 72))
758 return 1;
759 else if ((iqk_version <= 0x23) &&
760 (odm_get_hw_img_version(dm) <= 71))
761 return 1;
762 else
763 return 0;
764 }
765
766 if (dm->support_ic_type == ODM_RTL8821C) {
767 if (iqk_version >= 0x18 && (odm_get_hw_img_version(dm) >= 37))
768 return 1;
769 else
770 return 0;
771 }
772
773 return 1;
774 }
775
halrf_rf_lna_setting(void * dm_void,enum halrf_lna_set type)776 void halrf_rf_lna_setting(void *dm_void, enum halrf_lna_set type)
777 {
778 struct dm_struct *dm = (struct dm_struct *)dm_void;
779
780 switch (dm->support_ic_type) {
781 #if (RTL8188E_SUPPORT == 1)
782 case ODM_RTL8188E:
783 halrf_rf_lna_setting_8188e(dm, type);
784 break;
785 #endif
786 #if (RTL8192E_SUPPORT == 1)
787 case ODM_RTL8192E:
788 halrf_rf_lna_setting_8192e(dm, type);
789 break;
790 #endif
791 #if (RTL8192F_SUPPORT == 1)
792 case ODM_RTL8192F:
793 halrf_rf_lna_setting_8192f(dm, type);
794 break;
795 #endif
796
797 #if (RTL8723B_SUPPORT == 1)
798 case ODM_RTL8723B:
799 halrf_rf_lna_setting_8723b(dm, type);
800 break;
801 #endif
802 #if (RTL8812A_SUPPORT == 1)
803 case ODM_RTL8812:
804 halrf_rf_lna_setting_8812a(dm, type);
805 break;
806 #endif
807 #if ((RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1))
808 case ODM_RTL8881A:
809 case ODM_RTL8821:
810 halrf_rf_lna_setting_8821a(dm, type);
811 break;
812 #endif
813 #if (RTL8822B_SUPPORT == 1)
814 case ODM_RTL8822B:
815 halrf_rf_lna_setting_8822b(dm_void, type);
816 break;
817 #endif
818 #if (RTL8822C_SUPPORT == 1)
819 case ODM_RTL8822C:
820 halrf_rf_lna_setting_8822c(dm_void, type);
821 break;
822 #endif
823 #if (RTL8812F_SUPPORT == 1)
824 case ODM_RTL8812F:
825 halrf_rf_lna_setting_8812f(dm_void, type);
826 break;
827 #endif
828 #if (RTL8821C_SUPPORT == 1)
829 case ODM_RTL8821C:
830 halrf_rf_lna_setting_8821c(dm_void, type);
831 break;
832 #endif
833 #if (RTL8710C_SUPPORT == 1)
834 case ODM_RTL8710C:
835 halrf_rf_lna_setting_8710c(dm_void, type);
836 break;
837 #endif
838 #if (RTL8721D_SUPPORT == 1)
839 case ODM_RTL8721D:
840 halrf_rf_lna_setting_8721d(dm, type);
841 break;
842 #endif
843 #if (RTL8814B_SUPPORT == 1)
844 case ODM_RTL8814B:
845 break;
846 #endif
847 #if (RTL8814C_SUPPORT == 1)
848 case ODM_RTL8814C:
849 break;
850 #endif
851
852 default:
853 break;
854 }
855 }
856
halrf_support_ability_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)857 void halrf_support_ability_debug(void *dm_void, char input[][16], u32 *_used,
858 char *output, u32 *_out_len)
859 {
860 struct dm_struct *dm = (struct dm_struct *)dm_void;
861 struct _hal_rf_ *rf = &dm->rf_table;
862 u32 dm_value[10] = {0};
863 u32 used = *_used;
864 u32 out_len = *_out_len;
865 u8 i;
866
867 for (i = 0; i < 5; i++)
868 if (input[i + 1])
869 PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);
870
871 if (dm_value[0] == 100) {
872 PDM_SNPF(out_len, used, output + used, out_len - used,
873 "\n[RF Supportability]\n");
874 PDM_SNPF(out_len, used, output + used, out_len - used,
875 "00. (( %s ))Power Tracking\n",
876 ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) ?
877 ("V") : (".")));
878 PDM_SNPF(out_len, used, output + used, out_len - used,
879 "01. (( %s ))IQK\n",
880 ((rf->rf_supportability & HAL_RF_IQK) ? ("V") :
881 (".")));
882 PDM_SNPF(out_len, used, output + used, out_len - used,
883 "02. (( %s ))LCK\n",
884 ((rf->rf_supportability & HAL_RF_LCK) ? ("V") :
885 (".")));
886 PDM_SNPF(out_len, used, output + used, out_len - used,
887 "03. (( %s ))DPK\n",
888 ((rf->rf_supportability & HAL_RF_DPK) ? ("V") :
889 (".")));
890 PDM_SNPF(out_len, used, output + used, out_len - used,
891 "04. (( %s ))HAL_RF_TXGAPK\n",
892 ((rf->rf_supportability & HAL_RF_TXGAPK) ? ("V") :
893 (".")));
894 PDM_SNPF(out_len, used, output + used, out_len - used,
895 "05. (( %s ))HAL_RF_DACK\n",
896 ((rf->rf_supportability & HAL_RF_DACK) ? ("V") :
897 (".")));
898 PDM_SNPF(out_len, used, output + used, out_len - used,
899 "06. (( %s ))DPK_TRACK\n",
900 ((rf->rf_supportability & HAL_RF_DPK_TRACK) ? ("V") :
901 (".")));
902 #ifdef CONFIG_2G_BAND_SHIFT
903 PDM_SNPF(out_len, used, output + used, out_len - used,
904 "07. (( %s ))HAL_2GBAND_SHIFT\n",
905 ((rf->rf_supportability & HAL_2GBAND_SHIFT) ? ("V") :
906 (".")));
907 #endif
908 PDM_SNPF(out_len, used, output + used, out_len - used,
909 "08. (( %s ))HAL_RF_RXDCK\n",
910 ((rf->rf_supportability & HAL_RF_RXDCK) ? ("V") :
911 (".")));
912
913 } else {
914 if (dm_value[1] == 1) /* enable */
915 rf->rf_supportability |= BIT(dm_value[0]);
916 else if (dm_value[1] == 2) /* disable */
917 rf->rf_supportability &= ~(BIT(dm_value[0]));
918 else
919 PDM_SNPF(out_len, used, output + used, out_len - used,
920 "[Warning!!!] 1:enable, 2:disable\n");
921 }
922 PDM_SNPF(out_len, used, output + used, out_len - used,
923 "\nCurr-RF_supportability = 0x%x\n\n", rf->rf_supportability);
924
925 *_used = used;
926 *_out_len = out_len;
927 }
928
929 #ifdef CONFIG_2G_BAND_SHIFT
halrf_support_band_shift_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)930 void halrf_support_band_shift_debug(void *dm_void, char input[][16], u32 *_used,
931 char *output, u32 *_out_len)
932 {
933 struct dm_struct *dm = (struct dm_struct *)dm_void;
934 struct _hal_rf_ *rf = &dm->rf_table;
935 //u32 band_value[2] = {00};
936 u32 dm_value[10] = {0};
937 u32 used = *_used;
938 u32 out_len = *_out_len;
939 u8 i;
940
941 #if (RTL8192F_SUPPORT == 1)
942 for (i = 0; i < 7; i++)
943 if (input[i + 1])
944 PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);
945
946 if (!(rf->rf_supportability & HAL_2GBAND_SHIFT)) {
947 PDM_SNPF(out_len, used, output + used, out_len - used,
948 "\nCurr-RF_supportability[07. (( . ))HAL_2GBAND_SHIFT]\nNo RF Band Shift,default: 2.4G!\n");
949 } else {
950 if (dm_value[0] == 01) {
951 rf->rf_shift_band = HAL_RF_2P3;
952 halrf_lck_trigger(dm);
953 PDM_SNPF(out_len, used, output + used, out_len - used,
954 "\n[rf_shift_band] = %d\nRF Band Shift to 2.3G!\n",
955 rf->rf_shift_band);
956 } else if (dm_value[0] == 02) {
957 rf->rf_shift_band = HAL_RF_2P5;
958 halrf_lck_trigger(dm);
959 PDM_SNPF(out_len, used, output + used, out_len - used,
960 "\n[rf_shift_band] = %d\nRF Band Shift to 2.5G!\n",
961 rf->rf_shift_band);
962 } else {
963 rf->rf_shift_band = HAL_RF_2P4;
964 halrf_lck_trigger(dm);
965 PDM_SNPF(out_len, used, output + used, out_len - used,
966 "\n[rf_shift_band] = %d\nNo RF Band Shift,default: 2.4G!\n",
967 rf->rf_shift_band);
968 }
969 }
970 *_used = used;
971 *_out_len = out_len;
972 #endif
973 }
974 #endif
975
halrf_cmn_info_init(void * dm_void,enum halrf_cmninfo_init cmn_info,u32 value)976 void halrf_cmn_info_init(void *dm_void, enum halrf_cmninfo_init cmn_info,
977 u32 value)
978 {
979 struct dm_struct *dm = (struct dm_struct *)dm_void;
980 struct _hal_rf_ *rf = &dm->rf_table;
981
982 switch (cmn_info) {
983 case HALRF_CMNINFO_EEPROM_THERMAL_VALUE:
984 rf->eeprom_thermal = (u8)value;
985 break;
986 case HALRF_CMNINFO_PWT_TYPE:
987 rf->pwt_type = (u8)value;
988 break;
989 case HALRF_CMNINFO_MP_POWER_TRACKING_TYPE:
990 rf->mp_pwt_type = (u8)value;
991 break;
992 default:
993 break;
994 }
995 }
996
halrf_cmn_info_hook(void * dm_void,enum halrf_cmninfo_hook cmn_info,void * value)997 void halrf_cmn_info_hook(void *dm_void, enum halrf_cmninfo_hook cmn_info,
998 void *value)
999 {
1000 struct dm_struct *dm = (struct dm_struct *)dm_void;
1001 struct _hal_rf_ *rf = &dm->rf_table;
1002
1003 switch (cmn_info) {
1004 case HALRF_CMNINFO_CON_TX:
1005 rf->is_con_tx = (boolean *)value;
1006 break;
1007 case HALRF_CMNINFO_SINGLE_TONE:
1008 rf->is_single_tone = (boolean *)value;
1009 break;
1010 case HALRF_CMNINFO_CARRIER_SUPPRESSION:
1011 rf->is_carrier_suppresion = (boolean *)value;
1012 break;
1013 case HALRF_CMNINFO_MP_RATE_INDEX:
1014 rf->mp_rate_index = (u8 *)value;
1015 break;
1016 case HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY:
1017 rf->manual_rf_supportability = (u32 *)value;
1018 break;
1019 default:
1020 /*do nothing*/
1021 break;
1022 }
1023 }
1024
halrf_cmn_info_set(void * dm_void,u32 cmn_info,u64 value)1025 void halrf_cmn_info_set(void *dm_void, u32 cmn_info, u64 value)
1026 {
1027 /* This init variable may be changed in run time. */
1028 struct dm_struct *dm = (struct dm_struct *)dm_void;
1029 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
1030 struct _hal_rf_ *rf = &dm->rf_table;
1031
1032 switch (cmn_info) {
1033 case HALRF_CMNINFO_ABILITY:
1034 rf->rf_supportability = (u32)value;
1035 break;
1036
1037 case HALRF_CMNINFO_DPK_EN:
1038 rf->dpk_en = (u8)value;
1039 break;
1040 case HALRF_CMNINFO_RFK_FORBIDDEN:
1041 dm->IQK_info.rfk_forbidden = (boolean)value;
1042 break;
1043 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
1044 RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
1045 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1||\
1046 RTL8814C_SUPPORT == 1 )
1047 case HALRF_CMNINFO_IQK_SEGMENT:
1048 dm->IQK_info.segment_iqk = (boolean)value;
1049 break;
1050 #endif
1051 case HALRF_CMNINFO_RATE_INDEX:
1052 rf->p_rate_index = (u32)value;
1053 break;
1054 #if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
1055 case HALRF_CMNINFO_MP_PSD_POINT:
1056 rf->halrf_psd_data.point = (u32)value;
1057 break;
1058 case HALRF_CMNINFO_MP_PSD_START_POINT:
1059 rf->halrf_psd_data.start_point = (u32)value;
1060 break;
1061 case HALRF_CMNINFO_MP_PSD_STOP_POINT:
1062 rf->halrf_psd_data.stop_point = (u32)value;
1063 break;
1064 case HALRF_CMNINFO_MP_PSD_AVERAGE:
1065 rf->halrf_psd_data.average = (u32)value;
1066 break;
1067 #endif
1068 case HALRF_CMNINFO_POWER_TRACK_CONTROL:
1069 cali_info->txpowertrack_control = (u8)value;
1070 break;
1071 default:
1072 /* do nothing */
1073 break;
1074 }
1075 }
1076
halrf_cmn_info_get(void * dm_void,u32 cmn_info)1077 u64 halrf_cmn_info_get(void *dm_void, u32 cmn_info)
1078 {
1079 /* This init variable may be changed in run time. */
1080 struct dm_struct *dm = (struct dm_struct *)dm_void;
1081 struct _hal_rf_ *rf = &dm->rf_table;
1082 u64 return_value = 0;
1083
1084 switch (cmn_info) {
1085 case HALRF_CMNINFO_ABILITY:
1086 return_value = (u32)rf->rf_supportability;
1087 break;
1088 case HALRF_CMNINFO_RFK_FORBIDDEN:
1089 return_value = dm->IQK_info.rfk_forbidden;
1090 break;
1091 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
1092 RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
1093 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1||\
1094 RTL8814C_SUPPORT == 1)
1095 case HALRF_CMNINFO_IQK_SEGMENT:
1096 return_value = dm->IQK_info.segment_iqk;
1097 break;
1098 case HALRF_CMNINFO_IQK_TIMES:
1099 return_value = dm->IQK_info.iqk_times;
1100 break;
1101 #endif
1102 default:
1103 /* do nothing */
1104 break;
1105 }
1106
1107 return return_value;
1108 }
1109
halrf_supportability_init_mp(void * dm_void)1110 void halrf_supportability_init_mp(void *dm_void)
1111 {
1112 struct dm_struct *dm = (struct dm_struct *)dm_void;
1113 struct _hal_rf_ *rf = &dm->rf_table;
1114
1115 switch (dm->support_ic_type) {
1116 case ODM_RTL8814B:
1117 #if (RTL8814B_SUPPORT == 1)
1118 rf->rf_supportability =
1119 /*HAL_RF_TX_PWR_TRACK |*/
1120 HAL_RF_IQK |
1121 HAL_RF_LCK |
1122 HAL_RF_DPK |
1123 HAL_RF_DACK |
1124 /*HAL_RF_TXGAPK |*/
1125 HAL_RF_DPK_TRACK |
1126 0;
1127 #endif
1128 break;
1129 #if (RTL8822B_SUPPORT == 1)
1130 case ODM_RTL8822B:
1131 rf->rf_supportability =
1132 /*HAL_RF_TX_PWR_TRACK |*/
1133 HAL_RF_IQK |
1134 HAL_RF_LCK |
1135 /*@HAL_RF_DPK |*/
1136 0;
1137 break;
1138 #endif
1139 #if (RTL8822C_SUPPORT == 1)
1140 case ODM_RTL8822C:
1141 rf->rf_supportability =
1142 /*HAL_RF_TX_PWR_TRACK |*/
1143 HAL_RF_IQK |
1144 HAL_RF_LCK |
1145 HAL_RF_DPK |
1146 HAL_RF_DACK |
1147 HAL_RF_DPK_TRACK |
1148 HAL_RF_RXDCK |
1149 HAL_RF_TXGAPK |
1150 0;
1151 break;
1152 #endif
1153 #if (RTL8821C_SUPPORT == 1)
1154 case ODM_RTL8821C:
1155 rf->rf_supportability =
1156 /*HAL_RF_TX_PWR_TRACK |*/
1157 HAL_RF_IQK |
1158 HAL_RF_LCK |
1159 /*@HAL_RF_DPK |*/
1160 /*@HAL_RF_TXGAPK |*/
1161 0;
1162 break;
1163 #endif
1164 #if (RTL8195B_SUPPORT == 1)
1165 case ODM_RTL8195B:
1166 rf->rf_supportability =
1167 /*HAL_RF_TX_PWR_TRACK |*/
1168 HAL_RF_IQK |
1169 HAL_RF_LCK |
1170 HAL_RF_DPK |
1171 /*HAL_RF_TXGAPK |*/
1172 HAL_RF_DPK_TRACK |
1173 0;
1174 break;
1175 #endif
1176 #if (RTL8812F_SUPPORT == 1)
1177 case ODM_RTL8812F:
1178 rf->rf_supportability =
1179 /*HAL_RF_TX_PWR_TRACK |*/
1180 HAL_RF_IQK |
1181 HAL_RF_LCK |
1182 HAL_RF_DPK |
1183 HAL_RF_DACK |
1184 HAL_RF_DPK_TRACK |
1185 0;
1186 break;
1187 #endif
1188
1189 #if (RTL8198F_SUPPORT == 1)
1190 case ODM_RTL8198F:
1191 rf->rf_supportability =
1192 /*HAL_RF_TX_PWR_TRACK |*/
1193 HAL_RF_IQK |
1194 HAL_RF_LCK |
1195 HAL_RF_DPK |
1196 /*@HAL_RF_TXGAPK |*/
1197 0;
1198 break;
1199 #endif
1200
1201 #if (RTL8192F_SUPPORT == 1)
1202 case ODM_RTL8192F:
1203 rf->rf_supportability =
1204 /*HAL_RF_TX_PWR_TRACK |*/
1205 HAL_RF_IQK |
1206 HAL_RF_LCK |
1207 HAL_RF_DPK |
1208 /*@HAL_RF_TXGAPK |*/
1209 #ifdef CONFIG_2G_BAND_SHIFT
1210 /*@HAL_2GBAND_SHIFT |*/
1211 #endif
1212 0;
1213 break;
1214 #endif
1215
1216 #if (RTL8197F_SUPPORT == 1)
1217 case ODM_RTL8197F:
1218 rf->rf_supportability =
1219 /*HAL_RF_TX_PWR_TRACK |*/
1220 HAL_RF_IQK |
1221 HAL_RF_LCK |
1222 HAL_RF_DPK |
1223 /*@HAL_RF_TXGAPK |*/
1224 0;
1225 break;
1226 #endif
1227 #if (RTL8197G_SUPPORT == 1)
1228 case ODM_RTL8197G:
1229 rf->rf_supportability =
1230 /*HAL_RF_TX_PWR_TRACK |*/
1231 HAL_RF_IQK |
1232 /*HAL_RF_LCK |*/
1233 HAL_RF_DPK |
1234 /*@HAL_RF_TXGAPK |*/
1235 HAL_RF_DPK_TRACK |
1236 0;
1237 break;
1238 #endif
1239 #if (RTL8721D_SUPPORT == 1)
1240 case ODM_RTL8721D:
1241 rf->rf_supportability =
1242 HAL_RF_TX_PWR_TRACK |
1243 HAL_RF_IQK |
1244 HAL_RF_LCK |
1245 HAL_RF_DPK |
1246 HAL_RF_DPK_TRACK |
1247 /*@HAL_RF_TXGAPK |*/
1248 0;
1249 break;
1250 #endif
1251 #if (RTL8723F_SUPPORT == 1)
1252 case ODM_RTL8723F:
1253 rf->rf_supportability =
1254 HAL_RF_TX_PWR_TRACK |
1255 HAL_RF_IQK |
1256 HAL_RF_LCK |
1257 HAL_RF_DPK |
1258 HAL_RF_TXGAPK |
1259 HAL_RF_DPK_TRACK |
1260 0;
1261 break;
1262 #endif
1263 case ODM_RTL8814C:
1264 #if (RTL8814C_SUPPORT == 1)
1265 rf->rf_supportability =
1266 /*HAL_RF_TX_PWR_TRACK |*/
1267 HAL_RF_IQK |
1268 HAL_RF_LCK |
1269 HAL_RF_DPK |
1270 HAL_RF_DACK |
1271 HAL_RF_TXGAPK |
1272 HAL_RF_DPK_TRACK |
1273 0;
1274 #endif
1275 break;
1276
1277 default:
1278 rf->rf_supportability =
1279 /*HAL_RF_TX_PWR_TRACK |*/
1280 HAL_RF_IQK |
1281 HAL_RF_LCK |
1282 /*@HAL_RF_DPK |*/
1283 /*@HAL_RF_TXGAPK |*/
1284 0;
1285 break;
1286 }
1287
1288 RF_DBG(dm, DBG_RF_INIT,
1289 "IC = ((0x%x)), RF_Supportability Init MP = ((0x%x))\n",
1290 dm->support_ic_type, rf->rf_supportability);
1291 }
1292
halrf_supportability_init(void * dm_void)1293 void halrf_supportability_init(void *dm_void)
1294 {
1295 struct dm_struct *dm = (struct dm_struct *)dm_void;
1296 struct _hal_rf_ *rf = &dm->rf_table;
1297
1298 switch (dm->support_ic_type) {
1299 case ODM_RTL8814B:
1300 #if (RTL8814B_SUPPORT == 1)
1301 rf->rf_supportability =
1302 HAL_RF_TX_PWR_TRACK |
1303 HAL_RF_IQK |
1304 HAL_RF_LCK |
1305 HAL_RF_DPK |
1306 HAL_RF_DACK |
1307 HAL_RF_DPK_TRACK |
1308 0;
1309 #endif
1310 break;
1311 #if (RTL8822B_SUPPORT == 1)
1312 case ODM_RTL8822B:
1313 rf->rf_supportability =
1314 HAL_RF_TX_PWR_TRACK |
1315 HAL_RF_IQK |
1316 HAL_RF_LCK |
1317 /*@HAL_RF_DPK |*/
1318 0;
1319 break;
1320 #endif
1321 #if (RTL8822C_SUPPORT == 1)
1322 case ODM_RTL8822C:
1323 rf->rf_supportability =
1324 HAL_RF_TX_PWR_TRACK |
1325 HAL_RF_IQK |
1326 HAL_RF_LCK |
1327 HAL_RF_DPK |
1328 HAL_RF_DACK |
1329 HAL_RF_DPK_TRACK |
1330 HAL_RF_RXDCK |
1331 HAL_RF_TXGAPK |
1332 0;
1333 break;
1334 #endif
1335 #if (RTL8821C_SUPPORT == 1)
1336 case ODM_RTL8821C:
1337 rf->rf_supportability =
1338 HAL_RF_TX_PWR_TRACK |
1339 HAL_RF_IQK |
1340 HAL_RF_LCK |
1341 /*@HAL_RF_DPK |*/
1342 /*@HAL_RF_TXGAPK |*/
1343 0;
1344 break;
1345 #endif
1346 #if (RTL8195B_SUPPORT == 1)
1347 case ODM_RTL8195B:
1348 rf->rf_supportability =
1349 HAL_RF_TX_PWR_TRACK |
1350 HAL_RF_IQK |
1351 HAL_RF_LCK |
1352 HAL_RF_DPK |
1353 /*HAL_RF_TXGAPK |*/
1354 HAL_RF_DPK_TRACK |
1355 0;
1356 break;
1357 #endif
1358 #if (RTL8812F_SUPPORT == 1)
1359 case ODM_RTL8812F:
1360 rf->rf_supportability =
1361 HAL_RF_TX_PWR_TRACK |
1362 HAL_RF_IQK |
1363 HAL_RF_LCK |
1364 HAL_RF_DPK |
1365 HAL_RF_DACK |
1366 HAL_RF_DPK_TRACK |
1367 0;
1368 break;
1369 #endif
1370
1371 #if (RTL8198F_SUPPORT == 1)
1372 case ODM_RTL8198F:
1373 rf->rf_supportability =
1374 HAL_RF_TX_PWR_TRACK |
1375 HAL_RF_IQK |
1376 HAL_RF_LCK |
1377 HAL_RF_DPK |
1378 /*@HAL_RF_TXGAPK |*/
1379 0;
1380 break;
1381 #endif
1382
1383 #if (RTL8192F_SUPPORT == 1)
1384 case ODM_RTL8192F:
1385 rf->rf_supportability =
1386 HAL_RF_TX_PWR_TRACK |
1387 HAL_RF_IQK |
1388 HAL_RF_LCK |
1389 HAL_RF_DPK |
1390 /*@HAL_RF_TXGAPK |*/
1391 #ifdef CONFIG_2G_BAND_SHIFT
1392 /*@HAL_2GBAND_SHIFT |*/
1393 #endif
1394 0;
1395 break;
1396 #endif
1397
1398 #if (RTL8197F_SUPPORT == 1)
1399 case ODM_RTL8197F:
1400 rf->rf_supportability =
1401 HAL_RF_TX_PWR_TRACK |
1402 HAL_RF_IQK |
1403 HAL_RF_LCK |
1404 HAL_RF_DPK |
1405 /*@HAL_RF_TXGAPK |*/
1406 0;
1407 break;
1408 #endif
1409 #if (RTL8197G_SUPPORT == 1)
1410 case ODM_RTL8197G:
1411 rf->rf_supportability =
1412 HAL_RF_TX_PWR_TRACK |
1413 HAL_RF_IQK |
1414 /*HAL_RF_LCK |*/
1415 HAL_RF_DPK |
1416 /*@HAL_RF_TXGAPK |*/
1417 HAL_RF_DPK_TRACK |
1418 #ifdef CONFIG_2G_BAND_SHIFT
1419 HAL_2GBAND_SHIFT |
1420 #endif
1421 0;
1422 break;
1423 #endif
1424 #if (RTL8721D_SUPPORT == 1)
1425 case ODM_RTL8721D:
1426 rf->rf_supportability =
1427 HAL_RF_TX_PWR_TRACK |
1428 HAL_RF_IQK |
1429 HAL_RF_LCK |
1430 HAL_RF_DPK |
1431 HAL_RF_DPK_TRACK |
1432 /*@HAL_RF_TXGAPK |*/
1433 0;
1434 break;
1435 #endif
1436 #if (RTL8723F_SUPPORT == 1)
1437 case ODM_RTL8723F:
1438 rf->rf_supportability =
1439 HAL_RF_TX_PWR_TRACK |
1440 HAL_RF_IQK |
1441 HAL_RF_LCK |
1442 HAL_RF_DPK |
1443 HAL_RF_TXGAPK |
1444 HAL_RF_DPK_TRACK |
1445 0;
1446 break;
1447 #endif
1448 case ODM_RTL8814C:
1449 #if (RTL8814C_SUPPORT == 1)
1450 rf->rf_supportability =
1451 HAL_RF_TX_PWR_TRACK |
1452 HAL_RF_IQK |
1453 HAL_RF_LCK |
1454 HAL_RF_DPK |
1455 HAL_RF_DACK |
1456 HAL_RF_DPK_TRACK |
1457 HAL_RF_TXGAPK |
1458 0;
1459 #endif
1460 break;
1461
1462 default:
1463 rf->rf_supportability =
1464 HAL_RF_TX_PWR_TRACK |
1465 HAL_RF_IQK |
1466 HAL_RF_LCK |
1467 /*@HAL_RF_DPK |*/
1468 0;
1469 break;
1470 }
1471
1472 RF_DBG(dm, DBG_RF_INIT,
1473 "IC = ((0x%x)), RF_Supportability Init = ((0x%x))\n",
1474 dm->support_ic_type, rf->rf_supportability);
1475 }
1476
halrf_watchdog(void * dm_void)1477 void halrf_watchdog(void *dm_void)
1478 {
1479 struct dm_struct *dm = (struct dm_struct *)dm_void;
1480 struct _hal_rf_ *rf = &dm->rf_table;
1481 #if 0
1482 /*RF_DBG(dm, DBG_RF_TMP, "%s\n", __func__);*/
1483 #endif
1484 if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
1485 rf->is_tssi_in_progress)
1486 return;
1487
1488 if (!(dm->support_ic_type & ODM_RTL8723F))
1489 phydm_rf_watchdog(dm);
1490
1491 halrf_dpk_track(dm);
1492 #if (RTL8723F_SUPPORT == 1)
1493 if (dm->support_ic_type & ODM_RTL8723F){
1494 halrf_xtal_thermal_track(dm);
1495 halrf_powertracking_thermal(dm);
1496 }
1497 #endif
1498 }
1499
1500 #if 0
1501 void
1502 halrf_iqk_init(
1503 void *dm_void
1504 )
1505 {
1506 struct dm_struct *dm = (struct dm_struct *)dm_void;
1507 struct _hal_rf_ *rf = &dm->rf_table;
1508
1509 switch (dm->support_ic_type) {
1510 #if (RTL8814B_SUPPORT == 1)
1511 case ODM_RTL8814B:
1512 break;
1513 #endif
1514 #if (RTL8822B_SUPPORT == 1)
1515 case ODM_RTL8822B:
1516 _iq_calibrate_8822b_init(dm);
1517 break;
1518 #endif
1519 #if (RTL8822C_SUPPORT == 1)
1520 case ODM_RTL8822C:
1521 _iq_calibrate_8822c_init(dm);
1522 break;
1523 #endif
1524 #if (RTL8821C_SUPPORT == 1)
1525 case ODM_RTL8821C:
1526 break;
1527 #endif
1528
1529 default:
1530 break;
1531 }
1532 }
1533 #endif
1534
halrf_rfk_power_save(void * dm_void,boolean is_power_save)1535 void halrf_rfk_power_save(void *dm_void, boolean is_power_save)
1536 {
1537 struct dm_struct *dm = (struct dm_struct *)dm_void;
1538 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1539
1540 switch (dm->support_ic_type) {
1541 #if (RTL8822C_SUPPORT == 1)
1542 case ODM_RTL8822C:
1543 halrf_rfk_power_save_8822c(dm, is_power_save);
1544 break;
1545 #endif
1546
1547 #if (RTL8723F_SUPPORT == 1)
1548 case ODM_RTL8723F:
1549 halrf_rfk_power_save_8723f(dm, is_power_save);
1550 break;
1551 #endif
1552 #if (RTL8814C_SUPPORT == 1)
1553 case ODM_RTL8814C:
1554 break;
1555 #endif
1556
1557 default:
1558 break;
1559 }
1560 }
1561
1562
1563
halrf_reload_iqk(void * dm_void,boolean reset)1564 void halrf_reload_iqk(void *dm_void, boolean reset)
1565 {
1566 struct dm_struct *dm = (struct dm_struct *)dm_void;
1567 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1568 u8 i, ch;
1569 u32 tmp;
1570 u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
1571
1572 halrf_rfk_power_save(dm, false);
1573 switch (dm->support_ic_type) {
1574 #if (RTL8822C_SUPPORT == 1)
1575 case ODM_RTL8822C:
1576 iqk_reload_iqk_8822c(dm, reset);
1577 break;
1578 #endif
1579 #if (RTL8195B_SUPPORT == 1)
1580 case ODM_RTL8195B:
1581 iqk_reload_iqk_8195b(dm, reset);
1582 break;
1583 #endif
1584 #if (RTL8814C_SUPPORT == 1)
1585 case ODM_RTL8814C:
1586 iqk_reload_iqk_8814c(dm, reset);
1587 break;
1588 #endif
1589
1590 default:
1591 break;
1592 }
1593 halrf_rfk_power_save(dm, true);
1594 }
1595
halrf_rfk_handshake(void * dm_void,boolean is_before_k)1596 void halrf_rfk_handshake(void *dm_void, boolean is_before_k)
1597 {
1598 struct dm_struct *dm = (struct dm_struct *)dm_void;
1599
1600 if (!dm->mp_mode)
1601 return;
1602
1603 if (*dm->mp_mode)
1604 return;
1605
1606 switch (dm->support_ic_type) {
1607 #if (RTL8822C_SUPPORT == 1)
1608 case ODM_RTL8822C:
1609 halrf_rfk_handshake_8822c(dm, is_before_k);
1610 break;
1611 #endif
1612 #if (RTL8710C_SUPPORT == 1)
1613 case ODM_RTL8710C:
1614 halrf_rfk_handshake_8710c(dm, is_before_k);
1615 break;
1616 #endif
1617 #if (RTL8723F_SUPPORT == 1)
1618 case ODM_RTL8723F:
1619 halrf_rfk_handshake_8723f(dm, is_before_k);
1620 break;
1621 #endif
1622 #if (RTL8814C_SUPPORT == 1)
1623 case ODM_RTL8814C:
1624 break;
1625 #endif
1626
1627 default:
1628 break;
1629 }
1630 }
1631
halrf_bbreset(void * dm_void)1632 void halrf_bbreset(void *dm_void)
1633 {
1634 struct dm_struct *dm = (struct dm_struct *)dm_void;
1635
1636
1637 switch (dm->support_ic_type) {
1638 #if (RTL8814B_SUPPORT == 1)
1639 case ODM_RTL8814B:
1640 phydm_bb_reset_8814b(dm);
1641 break;
1642 #endif
1643 #if (RTL8814C_SUPPORT == 1)
1644 case ODM_RTL8814C:
1645 phydm_bb_reset_8814c(dm);
1646 break;
1647 #endif
1648
1649 default:
1650 break;
1651 }
1652 }
1653
halrf_rf_k_connect_trigger(void * dm_void,boolean is_recovery,enum halrf_k_segment_time seg_time)1654 void halrf_rf_k_connect_trigger(void *dm_void, boolean is_recovery,
1655 enum halrf_k_segment_time seg_time)
1656 {
1657 struct dm_struct *dm = (struct dm_struct *)dm_void;
1658 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1659 struct _hal_rf_ *rf = &dm->rf_table;
1660
1661 if (!dm->mp_mode)
1662 return;
1663
1664 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
1665 rf->is_carrier_suppresion) {
1666 if (*dm->mp_mode &
1667 (*rf->is_con_tx || *rf->is_single_tone ||
1668 *rf->is_carrier_suppresion))
1669 return;
1670 }
1671
1672 /*[TX GAP K]*/
1673 halrf_txgapk_trigger(dm);
1674
1675 /*[LOK, IQK]*/
1676 halrf_segment_iqk_trigger(dm, true, seg_time);
1677
1678 /*[TSSI Trk]*/
1679 halrf_tssi_trigger(dm);
1680 /*[DPK]*/
1681 #if 1
1682 if(dpk_info->is_dpk_by_channel == true)
1683 halrf_dpk_trigger(dm);
1684 else
1685 halrf_dpk_reload(dm);
1686 #endif
1687 //ADDA restore to MP_UI setting;
1688 config_halrf_path_adda_setting_trigger(dm);
1689
1690 halrf_spur_compensation(dm);
1691
1692 halrf_bbreset(dm);
1693 }
1694
config_halrf_path_adda_setting_trigger(void * dm_void)1695 void config_halrf_path_adda_setting_trigger(void *dm_void)
1696 {
1697 struct dm_struct *dm = (struct dm_struct *)dm_void;
1698
1699 #if (RTL8814B_SUPPORT == 1)
1700 if (dm->support_ic_type & ODM_RTL8814B)
1701 config_phydm_path_adda_setting_8814b(dm);
1702 #endif
1703 #if (RTL8814C_SUPPORT == 1)
1704 if (dm->support_ic_type & ODM_RTL8814C)
1705 config_phydm_path_adda_setting_8814c(dm);
1706 #endif
1707
1708
1709 }
1710
halrf_dack_restore(void * dm_void)1711 void halrf_dack_restore(void *dm_void)
1712 {
1713 struct dm_struct *dm = (struct dm_struct *)dm_void;
1714 struct _hal_rf_ *rf = &dm->rf_table;
1715
1716 if (!(rf->rf_supportability & HAL_RF_DACK))
1717 return;
1718 switch (dm->support_ic_type) {
1719 #if (RTL8822C_SUPPORT == 1)
1720 case ODM_RTL8822C:
1721 halrf_dack_restore_8822c(dm);
1722 break;
1723 #endif
1724 #if (RTL8814C_SUPPORT == 1)
1725 case ODM_RTL8814C:
1726 //halrf_dack_restore_8814c(dm);
1727 break;
1728 #endif
1729
1730 default:
1731 break;
1732 }
1733 }
halrf_dack_trigger(void * dm_void,boolean force)1734 void halrf_dack_trigger(void *dm_void, boolean force)
1735 {
1736 struct dm_struct *dm = (struct dm_struct *)dm_void;
1737 struct _hal_rf_ *rf = &dm->rf_table;
1738
1739 u64 start_time;
1740
1741 if (!(rf->rf_supportability & HAL_RF_DACK))
1742 return;
1743
1744 start_time = odm_get_current_time(dm);
1745
1746 switch (dm->support_ic_type) {
1747 #if (RTL8822C_SUPPORT == 1)
1748 case ODM_RTL8822C:
1749 halrf_dac_cal_8822c(dm, force);
1750 break;
1751 #endif
1752 #if (RTL8812F_SUPPORT == 1)
1753 case ODM_RTL8812F:
1754 halrf_dac_cal_8812f(dm);
1755 break;
1756 #endif
1757 #if (RTL8814B_SUPPORT == 1)
1758 case ODM_RTL8814B:
1759 halrf_dac_cal_8814b(dm);
1760 break;
1761 #endif
1762 #if (RTL8814C_SUPPORT == 1)
1763 case ODM_RTL8814C:
1764 halrf_dac_cal_8814c(dm);
1765 break;
1766 #endif
1767
1768 default:
1769 break;
1770 }
1771 rf->dpk_progressing_time = odm_get_progressing_time(dm, start_time);
1772 RF_DBG(dm, DBG_RF_DACK, "[DACK]DACK progressing_time = %lld ms\n",
1773 rf->dpk_progressing_time);
1774 }
1775
1776
halrf_dack_dbg(void * dm_void)1777 void halrf_dack_dbg(void *dm_void)
1778 {
1779 struct dm_struct *dm = (struct dm_struct *)dm_void;
1780 struct _hal_rf_ *rf = &dm->rf_table;
1781
1782 u64 start_time;
1783
1784 if (!(rf->rf_supportability & HAL_RF_DACK))
1785 return;
1786
1787 switch (dm->support_ic_type) {
1788 #if (RTL8822C_SUPPORT == 1)
1789 case ODM_RTL8822C:
1790 halrf_dack_dbg_8822c(dm);
1791 break;
1792 #endif
1793 default:
1794 break;
1795 }
1796 }
1797
1798
halrf_segment_iqk_trigger(void * dm_void,boolean clear,boolean segment_iqk)1799 void halrf_segment_iqk_trigger(void *dm_void, boolean clear,
1800 boolean segment_iqk)
1801 {
1802 struct dm_struct *dm = (struct dm_struct *)dm_void;
1803 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1804 struct _hal_rf_ *rf = &dm->rf_table;
1805 u64 start_time;
1806
1807 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1808 if (odm_check_power_status(dm) == false)
1809 return;
1810 #endif
1811
1812 if (!dm->mp_mode)
1813 return;
1814
1815 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
1816 rf->is_carrier_suppresion) {
1817 if (*dm->mp_mode &
1818 (*rf->is_con_tx || *rf->is_single_tone ||
1819 *rf->is_carrier_suppresion))
1820 return;
1821 }
1822
1823 if (!(rf->rf_supportability & HAL_RF_IQK))
1824 return;
1825
1826 #if DISABLE_BB_RF
1827 return;
1828 #endif
1829 if (iqk_info->rfk_forbidden)
1830 return;
1831
1832 rf->rfk_type = RF01_IQK;
1833 halrf_rfk_handshake(dm, true);
1834
1835 if (!dm->rf_calibrate_info.is_iqk_in_progress) {
1836 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1837 dm->rf_calibrate_info.is_iqk_in_progress = true;
1838 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1839 start_time = odm_get_current_time(dm);
1840 dm->IQK_info.segment_iqk = segment_iqk;
1841
1842 halrf_rfk_power_save(dm, false);
1843 switch (dm->support_ic_type) {
1844 #if (RTL8822B_SUPPORT == 1)
1845 case ODM_RTL8822B:
1846 phy_iq_calibrate_8822b(dm, clear, segment_iqk);
1847 break;
1848 #endif
1849 #if (RTL8822C_SUPPORT == 1)
1850 case ODM_RTL8822C:
1851 phy_iq_calibrate_8822c(dm, clear, segment_iqk);
1852 break;
1853 #endif
1854 #if (RTL8821C_SUPPORT == 1)
1855 case ODM_RTL8821C:
1856 phy_iq_calibrate_8821c(dm, clear, segment_iqk);
1857 break;
1858 #endif
1859 #if (RTL8814B_SUPPORT == 1)
1860 case ODM_RTL8814B:
1861 phy_iq_calibrate_8814b(dm, clear, segment_iqk);
1862 break;
1863 #endif
1864 #if (RTL8195B_SUPPORT == 1)
1865 case ODM_RTL8195B:
1866 phy_iq_calibrate_8195b(dm, clear, segment_iqk);
1867 break;
1868 #endif
1869 #if (RTL8710C_SUPPORT == 1)
1870 case ODM_RTL8710C:
1871 phy_iq_calibrate_8710c(dm, clear, segment_iqk);
1872 break;
1873 #endif
1874 #if (RTL8198F_SUPPORT == 1)
1875 case ODM_RTL8198F:
1876 phy_iq_calibrate_8198f(dm, clear, segment_iqk);
1877 break;
1878 #endif
1879 #if (RTL8812F_SUPPORT == 1)
1880 case ODM_RTL8812F:
1881 phy_iq_calibrate_8812f(dm, clear, segment_iqk);
1882 break;
1883 #endif
1884 #if (RTL8197G_SUPPORT == 1)
1885 case ODM_RTL8197G:
1886 phy_iq_calibrate_8197g(dm, clear, segment_iqk);
1887 break;
1888 #endif
1889 #if (RTL8188E_SUPPORT == 1)
1890 case ODM_RTL8188E:
1891 phy_iq_calibrate_8188e(dm, false);
1892 break;
1893 #endif
1894 #if (RTL8188F_SUPPORT == 1)
1895 case ODM_RTL8188F:
1896 phy_iq_calibrate_8188f(dm, false);
1897 break;
1898 #endif
1899 #if (RTL8192E_SUPPORT == 1)
1900 case ODM_RTL8192E:
1901 phy_iq_calibrate_8192e(dm, false);
1902 break;
1903 #endif
1904 #if (RTL8197F_SUPPORT == 1)
1905 case ODM_RTL8197F:
1906 phy_iq_calibrate_8197f(dm, false);
1907 break;
1908 #endif
1909 #if (RTL8192F_SUPPORT == 1)
1910 case ODM_RTL8192F:
1911 phy_iq_calibrate_8192f(dm, false);
1912 break;
1913 #endif
1914 #if (RTL8703B_SUPPORT == 1)
1915 case ODM_RTL8703B:
1916 phy_iq_calibrate_8703b(dm, false);
1917 break;
1918 #endif
1919 #if (RTL8710B_SUPPORT == 1)
1920 case ODM_RTL8710B:
1921 phy_iq_calibrate_8710b(dm, false);
1922 break;
1923 #endif
1924 #if (RTL8723B_SUPPORT == 1)
1925 case ODM_RTL8723B:
1926 phy_iq_calibrate_8723b(dm, false);
1927 break;
1928 #endif
1929 #if (RTL8723D_SUPPORT == 1)
1930 case ODM_RTL8723D:
1931 phy_iq_calibrate_8723d(dm, false);
1932 break;
1933 #endif
1934 #if (RTL8721D_SUPPORT == 1)
1935 case ODM_RTL8721D:
1936 phy_iq_calibrate_8721d(dm, false);
1937 break;
1938 #endif
1939 #if (RTL8812A_SUPPORT == 1)
1940 case ODM_RTL8812:
1941 phy_iq_calibrate_8812a(dm, false);
1942 break;
1943 #endif
1944 #if (RTL8821A_SUPPORT == 1)
1945 case ODM_RTL8821:
1946 phy_iq_calibrate_8821a(dm, false);
1947 break;
1948 #endif
1949 #if (RTL8814A_SUPPORT == 1)
1950 case ODM_RTL8814A:
1951 phy_iq_calibrate_8814a(dm, false);
1952 break;
1953 #endif
1954 #if (RTL8723F_SUPPORT == 1)
1955 case ODM_RTL8723F:
1956 phy_iq_calibrate_8723f(dm, false);
1957 break;
1958 #endif
1959 #if (RTL8814C_SUPPORT == 1)
1960 case ODM_RTL8814C:
1961 phy_iq_calibrate_8814c(dm, clear, segment_iqk);
1962 break;
1963 #endif
1964
1965
1966 default:
1967 break;
1968 }
1969
1970 halrf_rfk_power_save(dm, true);
1971 dm->rf_calibrate_info.iqk_progressing_time =
1972 odm_get_progressing_time(dm, start_time);
1973 RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK progressing_time = %lld ms\n",
1974 dm->rf_calibrate_info.iqk_progressing_time);
1975
1976 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1977 dm->rf_calibrate_info.is_iqk_in_progress = false;
1978 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1979
1980 halrf_rfk_handshake(dm, false);
1981 } else {
1982 RF_DBG(dm, DBG_RF_IQK,
1983 "== Return the IQK CMD, because RFKs in Progress ==\n");
1984 }
1985 }
1986
1987
halrf_iqk_trigger(void * dm_void,boolean is_recovery)1988 void halrf_iqk_trigger(void *dm_void, boolean is_recovery)
1989 {
1990 struct dm_struct *dm = (struct dm_struct *)dm_void;
1991 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1992 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1993 struct _hal_rf_ *rf = &dm->rf_table;
1994 u64 start_time;
1995
1996 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1997 if (odm_check_power_status(dm) == false)
1998 return;
1999 #endif
2000
2001 if (!dm->mp_mode)
2002 return;
2003
2004 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
2005 rf->is_carrier_suppresion) {
2006 if (*dm->mp_mode &
2007 (*rf->is_con_tx || *rf->is_single_tone ||
2008 *rf->is_carrier_suppresion))
2009 return;
2010 }
2011
2012 if (!(rf->rf_supportability & HAL_RF_IQK))
2013 return;
2014
2015 #if DISABLE_BB_RF
2016 return;
2017 #endif
2018
2019 if (iqk_info->rfk_forbidden)
2020 return;
2021
2022 rf->rfk_type = RF01_IQK;
2023 halrf_rfk_handshake(dm, true);
2024
2025 if (!dm->rf_calibrate_info.is_iqk_in_progress) {
2026 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2027 dm->rf_calibrate_info.is_iqk_in_progress = true;
2028 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2029 start_time = odm_get_current_time(dm);
2030 halrf_rfk_power_save(dm, false);
2031 switch (dm->support_ic_type) {
2032 #if (RTL8188E_SUPPORT == 1)
2033 case ODM_RTL8188E:
2034 phy_iq_calibrate_8188e(dm, is_recovery);
2035 break;
2036 #endif
2037 #if (RTL8188F_SUPPORT == 1)
2038 case ODM_RTL8188F:
2039 phy_iq_calibrate_8188f(dm, is_recovery);
2040 break;
2041 #endif
2042 #if (RTL8192E_SUPPORT == 1)
2043 case ODM_RTL8192E:
2044 phy_iq_calibrate_8192e(dm, is_recovery);
2045 break;
2046 #endif
2047 #if (RTL8197F_SUPPORT == 1)
2048 case ODM_RTL8197F:
2049 phy_iq_calibrate_8197f(dm, is_recovery);
2050 break;
2051 #endif
2052 #if (RTL8192F_SUPPORT == 1)
2053 case ODM_RTL8192F:
2054 phy_iq_calibrate_8192f(dm, is_recovery);
2055 break;
2056 #endif
2057 #if (RTL8703B_SUPPORT == 1)
2058 case ODM_RTL8703B:
2059 phy_iq_calibrate_8703b(dm, is_recovery);
2060 break;
2061 #endif
2062 #if (RTL8710B_SUPPORT == 1)
2063 case ODM_RTL8710B:
2064 phy_iq_calibrate_8710b(dm, is_recovery);
2065 break;
2066 #endif
2067 #if (RTL8723B_SUPPORT == 1)
2068 case ODM_RTL8723B:
2069 phy_iq_calibrate_8723b(dm, is_recovery);
2070 break;
2071 #endif
2072 #if (RTL8723D_SUPPORT == 1)
2073 case ODM_RTL8723D:
2074 phy_iq_calibrate_8723d(dm, is_recovery);
2075 break;
2076 #endif
2077 #if (RTL8721D_SUPPORT == 1)
2078 case ODM_RTL8721D:
2079 phy_iq_calibrate_8721d(dm, is_recovery);
2080 break;
2081 #endif
2082 #if (RTL8812A_SUPPORT == 1)
2083 case ODM_RTL8812:
2084 phy_iq_calibrate_8812a(dm, is_recovery);
2085 break;
2086 #endif
2087 #if (RTL8821A_SUPPORT == 1)
2088 case ODM_RTL8821:
2089 phy_iq_calibrate_8821a(dm, is_recovery);
2090 break;
2091 #endif
2092 #if (RTL8814A_SUPPORT == 1)
2093 case ODM_RTL8814A:
2094 phy_iq_calibrate_8814a(dm, is_recovery);
2095 break;
2096 #endif
2097 #if (RTL8822B_SUPPORT == 1)
2098 case ODM_RTL8822B:
2099 phy_iq_calibrate_8822b(dm, false, false);
2100 break;
2101 #endif
2102 #if (RTL8822C_SUPPORT == 1)
2103 case ODM_RTL8822C:
2104 phy_iq_calibrate_8822c(dm, false, false);
2105 break;
2106 #endif
2107 #if (RTL8821C_SUPPORT == 1)
2108 case ODM_RTL8821C:
2109 phy_iq_calibrate_8821c(dm, false, false);
2110 break;
2111 #endif
2112 #if (RTL8814B_SUPPORT == 1)
2113 case ODM_RTL8814B:
2114 phy_iq_calibrate_8814b(dm, false, false);
2115 break;
2116 #endif
2117 #if (RTL8195B_SUPPORT == 1)
2118 case ODM_RTL8195B:
2119 phy_iq_calibrate_8195b(dm, false, false);
2120 break;
2121 #endif
2122 #if (RTL8710C_SUPPORT == 1)
2123 case ODM_RTL8710C:
2124 phy_iq_calibrate_8710c(dm, false, false);
2125 break;
2126 #endif
2127 #if (RTL8198F_SUPPORT == 1)
2128 case ODM_RTL8198F:
2129 phy_iq_calibrate_8198f(dm, false, false);
2130 break;
2131 #endif
2132 #if (RTL8812F_SUPPORT == 1)
2133 case ODM_RTL8812F:
2134 phy_iq_calibrate_8812f(dm, false, false);
2135 break;
2136 #endif
2137 #if (RTL8197G_SUPPORT == 1)
2138 case ODM_RTL8197G:
2139 phy_iq_calibrate_8197g(dm, false, false);
2140 break;
2141 #endif
2142 #if (RTL8723F_SUPPORT == 1)
2143 case ODM_RTL8723F:
2144 phy_iq_calibrate_8723f(dm, is_recovery);
2145 break;
2146 #endif
2147 #if (RTL8814C_SUPPORT == 1)
2148 case ODM_RTL8814C:
2149 phy_iq_calibrate_8814c(dm, false, false);
2150 break;
2151 #endif
2152
2153 default:
2154 break;
2155 }
2156
2157 halrf_rfk_power_save(dm, true);
2158 rf->iqk_progressing_time = odm_get_progressing_time(dm, start_time);
2159 RF_DBG(dm, DBG_RF_LCK, "[IQK]Trigger IQK progressing_time = %lld ms\n",
2160 rf->iqk_progressing_time);
2161 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2162 dm->rf_calibrate_info.is_iqk_in_progress = false;
2163 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2164
2165 halrf_rfk_handshake(dm, false);
2166 } else {
2167 RF_DBG(dm, DBG_RF_IQK,
2168 "== Return the IQK CMD, because RFKs in Progress ==\n");
2169 }
2170 }
2171
halrf_lck_trigger(void * dm_void)2172 void halrf_lck_trigger(void *dm_void)
2173 {
2174 struct dm_struct *dm = (struct dm_struct *)dm_void;
2175 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2176 struct _hal_rf_ *rf = &dm->rf_table;
2177 u64 start_time;
2178
2179 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
2180 if (odm_check_power_status(dm) == false)
2181 return;
2182 #endif
2183
2184 if (!dm->mp_mode)
2185 return;
2186
2187 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
2188 rf->is_carrier_suppresion) {
2189 if (*dm->mp_mode &
2190 (*rf->is_con_tx || *rf->is_single_tone ||
2191 *rf->is_carrier_suppresion))
2192 return;
2193 }
2194
2195 if (!(rf->rf_supportability & HAL_RF_LCK))
2196 return;
2197
2198 #if DISABLE_BB_RF
2199 return;
2200 #endif
2201 if (iqk_info->rfk_forbidden)
2202 return;
2203 while (*dm->is_scan_in_process) {
2204 RF_DBG(dm, DBG_RF_LCK, "[LCK]scan is in process, bypass LCK\n");
2205 return;
2206 }
2207
2208 if (!dm->rf_calibrate_info.is_lck_in_progress) {
2209 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2210 dm->rf_calibrate_info.is_lck_in_progress = true;
2211 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2212 start_time = odm_get_current_time(dm);
2213 switch (dm->support_ic_type) {
2214 #if (RTL8188E_SUPPORT == 1)
2215 case ODM_RTL8188E:
2216 phy_lc_calibrate_8188e(dm);
2217 break;
2218 #endif
2219 #if (RTL8188F_SUPPORT == 1)
2220 case ODM_RTL8188F:
2221 phy_lc_calibrate_8188f(dm);
2222 break;
2223 #endif
2224 #if (RTL8192E_SUPPORT == 1)
2225 case ODM_RTL8192E:
2226 phy_lc_calibrate_8192e(dm);
2227 break;
2228 #endif
2229 #if (RTL8197F_SUPPORT == 1)
2230 case ODM_RTL8197F:
2231 phy_lc_calibrate_8197f(dm);
2232 break;
2233 #endif
2234 #if (RTL8192F_SUPPORT == 1)
2235 case ODM_RTL8192F:
2236 phy_lc_calibrate_8192f(dm);
2237 break;
2238 #endif
2239 #if (RTL8703B_SUPPORT == 1)
2240 case ODM_RTL8703B:
2241 phy_lc_calibrate_8703b(dm);
2242 break;
2243 #endif
2244 #if (RTL8710B_SUPPORT == 1)
2245 case ODM_RTL8710B:
2246 phy_lc_calibrate_8710b(dm);
2247 break;
2248 #endif
2249 #if (RTL8721D_SUPPORT == 1)
2250 case ODM_RTL8721D:
2251 phy_lc_calibrate_8721d(dm);
2252 break;
2253 #endif
2254 #if (RTL8723B_SUPPORT == 1)
2255 case ODM_RTL8723B:
2256 phy_lc_calibrate_8723b(dm);
2257 break;
2258 #endif
2259 #if (RTL8723D_SUPPORT == 1)
2260 case ODM_RTL8723D:
2261 phy_lc_calibrate_8723d(dm);
2262 break;
2263 #endif
2264 #if (RTL8812A_SUPPORT == 1)
2265 case ODM_RTL8812:
2266 phy_lc_calibrate_8812a(dm);
2267 break;
2268 #endif
2269 #if (RTL8821A_SUPPORT == 1)
2270 case ODM_RTL8821:
2271 phy_lc_calibrate_8821a(dm);
2272 break;
2273 #endif
2274 #if (RTL8814A_SUPPORT == 1)
2275 case ODM_RTL8814A:
2276 phy_lc_calibrate_8814a(dm);
2277 break;
2278 #endif
2279 #if (RTL8822B_SUPPORT == 1)
2280 case ODM_RTL8822B:
2281 phy_lc_calibrate_8822b(dm);
2282 break;
2283 #endif
2284 #if (RTL8822C_SUPPORT == 1)
2285 case ODM_RTL8822C:
2286 phy_lc_calibrate_8822c(dm);
2287 break;
2288 #endif
2289 #if (RTL8812F_SUPPORT == 1)
2290 case ODM_RTL8812F:
2291 phy_lc_calibrate_8812f(dm);
2292 break;
2293 #endif
2294 #if (RTL8821C_SUPPORT == 1)
2295 case ODM_RTL8821C:
2296 phy_lc_calibrate_8821c(dm);
2297 break;
2298 #endif
2299 #if (RTL8814B_SUPPORT == 1)
2300 case ODM_RTL8814B:
2301 phy_lc_calibrate_8814b(dm);
2302 break;
2303 #endif
2304 #if (RTL8197G_SUPPORT == 1)
2305 case ODM_RTL8197G:
2306 phy_lc_calibrate_8197g(dm);
2307 break;
2308 #endif
2309 #if (RTL8198F_SUPPORT == 1)
2310 case ODM_RTL8198F:
2311 phy_lc_calibrate_8198f(dm);
2312 break;
2313 #endif
2314 #if (RTL8710C_SUPPORT == 1)
2315 case ODM_RTL8710C:
2316 phy_lc_calibrate_8710c(dm);
2317 break;
2318 #endif
2319 #if (RTL8723F_SUPPORT == 1)
2320 case ODM_RTL8723F:
2321 phy_lc_calibrate_8723f(dm);
2322 break;
2323 #endif
2324 #if (RTL8814C_SUPPORT == 1)
2325 case ODM_RTL8814C:
2326 phy_lc_calibrate_8814c(dm);
2327 break;
2328 #endif
2329
2330
2331 default:
2332 break;
2333 }
2334 dm->rf_calibrate_info.lck_progressing_time =
2335 odm_get_progressing_time(dm, start_time);
2336 RF_DBG(dm, DBG_RF_LCK, "[LCK]LCK progressing_time = %lld ms\n",
2337 dm->rf_calibrate_info.lck_progressing_time);
2338 #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
2339 halrf_lck_dbg(dm);
2340 #endif
2341 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2342 dm->rf_calibrate_info.is_lck_in_progress = false;
2343 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2344 } else {
2345 RF_DBG(dm, DBG_RF_LCK,
2346 "[LCK]= Return the LCK CMD, because RFK is in Progress =\n");
2347 }
2348 }
2349
halrf_aac_check(struct dm_struct * dm)2350 void halrf_aac_check(struct dm_struct *dm)
2351 {
2352 switch (dm->support_ic_type) {
2353 #if (RTL8821C_SUPPORT == 1)
2354 case ODM_RTL8821C:
2355 #if 0
2356 aac_check_8821c(dm);
2357 #endif
2358 break;
2359 #endif
2360 #if (RTL8822B_SUPPORT == 1)
2361 case ODM_RTL8822B:
2362 #if 1
2363 aac_check_8822b(dm);
2364 #endif
2365 break;
2366 #endif
2367 default:
2368 break;
2369 }
2370 }
2371
halrf_rxdck(void * dm_void)2372 void halrf_rxdck(void *dm_void)
2373 {
2374 struct dm_struct *dm = (struct dm_struct *)dm_void;
2375 struct _hal_rf_ *rf = &dm->rf_table;
2376
2377 if (!(rf->rf_supportability & HAL_RF_RXDCK))
2378 return;
2379
2380 switch (dm->support_ic_type) {
2381 case ODM_RTL8822C:
2382 #if (RTL8822C_SUPPORT == 1)
2383 halrf_rxdck_8822c(dm);
2384 break;
2385 #endif
2386 default:
2387 break;
2388 }
2389 }
2390
halrf_x2k_check(struct dm_struct * dm)2391 void halrf_x2k_check(struct dm_struct *dm)
2392 {
2393
2394 switch (dm->support_ic_type) {
2395 case ODM_RTL8821C:
2396 #if (RTL8821C_SUPPORT == 1)
2397 #endif
2398 break;
2399 case ODM_RTL8822C:
2400 #if (RTL8822C_SUPPORT == 1)
2401 phy_x2_check_8822c(dm);
2402 break;
2403 #endif
2404 case ODM_RTL8812F:
2405 #if (RTL8812F_SUPPORT == 1)
2406 phy_x2_check_8812f(dm);
2407 break;
2408 #endif
2409 case ODM_RTL8723F:
2410 #if (RTL8723F_SUPPORT == 1)
2411 phy_x2_check_8723f(dm);
2412 break;
2413 #endif
2414
2415 default:
2416 break;
2417 }
2418 }
2419
halrf_set_rfsupportability(void * dm_void)2420 void halrf_set_rfsupportability(void *dm_void)
2421 {
2422 struct dm_struct *dm = (struct dm_struct *)dm_void;
2423 struct _hal_rf_ *rf = &dm->rf_table;
2424
2425 if (!dm->mp_mode)
2426 return;
2427
2428 if (rf->manual_rf_supportability &&
2429 *rf->manual_rf_supportability != 0xffffffff) {
2430 rf->rf_supportability = *rf->manual_rf_supportability;
2431 } else if (*dm->mp_mode) {
2432 halrf_supportability_init_mp(dm);
2433 } else {
2434 halrf_supportability_init(dm);
2435 }
2436 }
2437
halrf_rfe_definition(struct dm_struct * dm)2438 void halrf_rfe_definition(struct dm_struct *dm)
2439 {
2440 struct _hal_rf_ *rf = &dm->rf_table;
2441
2442 switch (dm->support_ic_type) {
2443 case ODM_RTL8822C:
2444 #if (RTL8822C_SUPPORT == 1)
2445 if (dm->rfe_type == 21 || dm->rfe_type == 22) {
2446 rf->ext_pa_5g = 1;
2447 rf->ext_lna_5g = 1;
2448 }
2449 break;
2450 #endif
2451 default:
2452 break;
2453 }
2454 }
2455
halrf_init(void * dm_void)2456 void halrf_init(void *dm_void)
2457 {
2458 struct dm_struct *dm = (struct dm_struct *)dm_void;
2459 struct _hal_rf_ *rf = &dm->rf_table;
2460
2461 RF_DBG(dm, DBG_RF_INIT, "HALRF_Init\n");
2462 rf->aac_checked = false;
2463 halrf_init_debug_setting(dm);
2464 halrf_set_rfsupportability(dm);
2465 halrf_rfe_definition(dm);
2466 #if 1
2467 /*Init all RF funciton*/
2468 halrf_aac_check(dm);
2469 halrf_dack_trigger(dm, false);
2470 halrf_x2k_check(dm);
2471 #endif
2472
2473 /*power trim, thrmal trim, pa bias*/
2474 phydm_config_new_kfree(dm);
2475
2476 /*TSSI Init*/
2477 halrf_tssi_dck(dm, true);
2478 halrf_tssi_get_efuse(dm);
2479 halrf_tssi_set_de(dm);
2480 #if (RTL8723F_SUPPORT == 1)
2481 halrf_do_tssi(dm);
2482 halrf_rx_port_ctl_8723f(dm);
2483 #endif
2484
2485 /*TX Gap K*/
2486 halrf_txgapk_write_gain_table(dm);
2487 }
2488
halrf_dpk_trigger(void * dm_void)2489 void halrf_dpk_trigger(void *dm_void)
2490 {
2491 struct dm_struct *dm = (struct dm_struct *)dm_void;
2492 struct _hal_rf_ *rf = &dm->rf_table;
2493 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2494 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2495
2496 u64 start_time;
2497
2498 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
2499 if (odm_check_power_status(dm) == false)
2500 return;
2501 #endif
2502
2503 if (!dm->mp_mode)
2504 return;
2505
2506 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
2507 rf->is_carrier_suppresion) {
2508 if (*dm->mp_mode &
2509 (*rf->is_con_tx || *rf->is_single_tone ||
2510 *rf->is_carrier_suppresion))
2511 return;
2512 }
2513
2514 if (!(rf->rf_supportability & HAL_RF_DPK))
2515 return;
2516
2517 #if DISABLE_BB_RF
2518 return;
2519 #endif
2520
2521 if (iqk_info->rfk_forbidden)
2522 return;
2523
2524 rf->rfk_type = RF03_DPK;
2525 halrf_rfk_handshake(dm, true);
2526
2527 if (!rf->is_dpk_in_progress) {
2528 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2529 rf->is_dpk_in_progress = true;
2530 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2531 start_time = odm_get_current_time(dm);
2532 halrf_rfk_power_save(dm, false);
2533 switch (dm->support_ic_type) {
2534 #if (RTL8822C_SUPPORT == 1)
2535 case ODM_RTL8822C:
2536 do_dpk_8822c(dm);
2537 break;
2538 #endif
2539 #if (RTL8814C_SUPPORT == 1)
2540 case ODM_RTL8814C:
2541 do_dpk_8814c(dm);
2542 break;
2543 #endif
2544
2545 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2546 #if (RTL8197F_SUPPORT == 1)
2547 case ODM_RTL8197F:
2548 do_dpk_8197f(dm);
2549 break;
2550 #endif
2551 #if (RTL8192F_SUPPORT == 1)
2552 case ODM_RTL8192F:
2553 do_dpk_8192f(dm);
2554 break;
2555 #endif
2556
2557 #if (RTL8198F_SUPPORT == 1)
2558 case ODM_RTL8198F:
2559 do_dpk_8198f(dm);
2560 break;
2561 #endif
2562 #if (RTL8812F_SUPPORT == 1)
2563 case ODM_RTL8812F:
2564 do_dpk_8812f(dm);
2565 break;
2566 #endif
2567 #if (RTL8197G_SUPPORT == 1)
2568 case ODM_RTL8197G:
2569 do_dpk_8197g(dm);
2570 break;
2571 #endif
2572
2573 #endif
2574
2575 #if (RTL8814B_SUPPORT == 1)
2576 case ODM_RTL8814B:
2577 do_dpk_8814b(dm);
2578 break;
2579 #endif
2580 #if (RTL8723F_SUPPORT == 1)
2581 case ODM_RTL8723F:
2582 do_dpk_8723f(dm);
2583 break;
2584 #endif
2585
2586 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2587 #if (RTL8195B_SUPPORT == 1)
2588 case ODM_RTL8195B:
2589 do_dpk_8195b(dm);
2590 break;
2591 #endif
2592 #if (RTL8721D_SUPPORT == 1)
2593 case ODM_RTL8721D:
2594 do_dpk_8721d(dm);
2595 break;
2596 #endif
2597
2598 #endif
2599 default:
2600 break;
2601 }
2602 halrf_rfk_power_save(dm, true);
2603 rf->dpk_progressing_time = odm_get_progressing_time(dm, start_time);
2604 RF_DBG(dm, DBG_RF_DPK, "[DPK]DPK progressing_time = %lld ms\n",
2605 rf->dpk_progressing_time);
2606
2607 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2608 rf->is_dpk_in_progress = false;
2609 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2610
2611 halrf_rfk_handshake(dm, false);
2612 } else {
2613 RF_DBG(dm, DBG_RF_DPK,
2614 "== Return the DPK CMD, because RFKs in Progress ==\n");
2615 }
2616 }
2617
halrf_set_dpkbychannel(void * dm_void,boolean dpk_by_ch)2618 void halrf_set_dpkbychannel(void *dm_void, boolean dpk_by_ch)
2619 {
2620 struct dm_struct *dm = (struct dm_struct *)dm_void;
2621 struct _hal_rf_ *rf = &dm->rf_table;
2622 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2623 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2624
2625
2626 switch (dm->support_ic_type) {
2627 #if (RTL8814B_SUPPORT == 1)
2628 case ODM_RTL8814B:
2629 dpk_set_dpkbychannel_8814b(dm, dpk_by_ch);
2630 break;
2631 #endif
2632
2633 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2634 #if (RTL8195B_SUPPORT == 1)
2635 case ODM_RTL8195B:
2636 dpk_set_dpkbychannel_8195b(dm,dpk_by_ch);
2637 break;
2638 #endif
2639 #endif
2640 #if (RTL8814C_SUPPORT == 1)
2641 case ODM_RTL8814C:
2642 dpk_set_dpkbychannel_8814c(dm, dpk_by_ch);
2643 break;
2644 #endif
2645
2646 default:
2647 if (dpk_by_ch)
2648 dpk_info->is_dpk_by_channel = 1;
2649 else
2650 dpk_info->is_dpk_by_channel = 0;
2651 break;
2652 }
2653
2654 }
2655
halrf_set_dpkenable(void * dm_void,boolean is_dpk_enable)2656 void halrf_set_dpkenable(void *dm_void, boolean is_dpk_enable)
2657 {
2658 struct dm_struct *dm = (struct dm_struct *)dm_void;
2659 struct _hal_rf_ *rf = &dm->rf_table;
2660 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2661 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2662
2663
2664 switch (dm->support_ic_type) {
2665 #if (RTL8814B_SUPPORT == 1)
2666 case ODM_RTL8814B:
2667 dpk_set_is_dpk_enable_8814b(dm, is_dpk_enable);
2668 break;
2669 #endif
2670
2671 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2672 #if (RTL8195B_SUPPORT == 1)
2673 case ODM_RTL8195B:
2674 dpk_set_is_dpk_enable_8195b(dm, is_dpk_enable);
2675 break;
2676 #endif
2677
2678 #if (RTL8721D_SUPPORT == 1)
2679 case ODM_RTL8721D:
2680 dpk_set_is_dpk_enable_8721d(dm, is_dpk_enable);
2681 break;
2682 #endif
2683
2684 #endif
2685 #if (RTL8814C_SUPPORT == 1)
2686 case ODM_RTL8814C:
2687 dpk_set_is_dpk_enable_8814c(dm, is_dpk_enable);
2688 break;
2689 #endif
2690
2691 default:
2692 break;
2693 }
2694
2695 }
halrf_get_dpkbychannel(void * dm_void)2696 boolean halrf_get_dpkbychannel(void *dm_void)
2697 {
2698 struct dm_struct *dm = (struct dm_struct *)dm_void;
2699 struct _hal_rf_ *rf = &dm->rf_table;
2700 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2701 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2702 boolean is_dpk_by_channel = true;
2703
2704 switch (dm->support_ic_type) {
2705 #if (RTL8814B_SUPPORT == 1)
2706 case ODM_RTL8814B:
2707 is_dpk_by_channel = dpk_get_dpkbychannel_8814b(dm);
2708 break;
2709 #endif
2710
2711 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2712 #if (RTL8195B_SUPPORT == 1)
2713 case ODM_RTL8195B:
2714 is_dpk_by_channel = dpk_get_dpkbychannel_8195b(dm);
2715 break;
2716 #endif
2717 #endif
2718
2719 #if (RTL8814C_SUPPORT == 1)
2720 case ODM_RTL8814C:
2721 is_dpk_by_channel = dpk_get_dpkbychannel_8814c(dm);
2722 break;
2723 #endif
2724
2725
2726 default:
2727 break;
2728 }
2729 return is_dpk_by_channel;
2730
2731 }
2732
2733
halrf_get_dpkenable(void * dm_void)2734 boolean halrf_get_dpkenable(void *dm_void)
2735 {
2736 struct dm_struct *dm = (struct dm_struct *)dm_void;
2737 struct _hal_rf_ *rf = &dm->rf_table;
2738 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2739 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2740 boolean is_dpk_enable = true;
2741
2742
2743 switch (dm->support_ic_type) {
2744 #if (RTL8814B_SUPPORT == 1)
2745 case ODM_RTL8814B:
2746 is_dpk_enable = dpk_get_is_dpk_enable_8814b(dm);
2747 break;
2748 #endif
2749
2750 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2751 #if (RTL8195B_SUPPORT == 1)
2752 case ODM_RTL8195B:
2753 is_dpk_enable = dpk_get_is_dpk_enable_8195b(dm);
2754 break;
2755 #endif
2756 #endif
2757 #if (RTL8814C_SUPPORT == 1)
2758 case ODM_RTL8814C:
2759 is_dpk_enable = dpk_get_is_dpk_enable_8814c(dm);
2760 break;
2761 #endif
2762
2763 default:
2764 break;
2765 }
2766 return is_dpk_enable;
2767
2768 }
2769
halrf_dpk_result_check(void * dm_void)2770 u8 halrf_dpk_result_check(void *dm_void)
2771 {
2772 struct dm_struct *dm = (struct dm_struct *)dm_void;
2773 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2774
2775 u8 result = 0;
2776
2777 switch (dm->support_ic_type) {
2778 #if (RTL8822C_SUPPORT == 1)
2779 case ODM_RTL8822C:
2780 if (dpk_info->dpk_path_ok == 0x3)
2781 result = 1;
2782 else
2783 result = 0;
2784 break;
2785 #endif
2786
2787 #if (RTL8195B_SUPPORT == 1)
2788 case ODM_RTL8195B:
2789 if (dpk_info->dpk_path_ok == 0x1)
2790 result = 1;
2791 else
2792 result = 0;
2793 break;
2794 #endif
2795
2796 #if (RTL8721D_SUPPORT == 1)
2797 case ODM_RTL8721D:
2798 if (dpk_info->dpk_path_ok == 0x1)
2799 result = 1;
2800 else
2801 result = 0;
2802 break;
2803 #endif
2804
2805 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2806
2807 #if (RTL8197F_SUPPORT == 1)
2808 case ODM_RTL8197F:
2809 if (dpk_info->dpk_path_ok == 0x3)
2810 result = 1;
2811 else
2812 result = 0;
2813 break;
2814 #endif
2815
2816 #if (RTL8192F_SUPPORT == 1)
2817 case ODM_RTL8192F:
2818 if (dpk_info->dpk_path_ok == 0x3)
2819 result = 1;
2820 else
2821 result = 0;
2822 break;
2823 #endif
2824
2825 #if (RTL8198F_SUPPORT == 1)
2826 case ODM_RTL8198F:
2827 if (dpk_info->dpk_path_ok == 0xf)
2828 result = 1;
2829 else
2830 result = 0;
2831 break;
2832 #endif
2833
2834 #if (RTL8814B_SUPPORT == 1)
2835 case ODM_RTL8814B:
2836 if (dpk_info->dpk_path_ok == 0xf)
2837 result = 1;
2838 else
2839 result = 0;
2840 break;
2841 #endif
2842 #if (RTL8814C_SUPPORT == 1)
2843 case ODM_RTL8814C:
2844 if (dpk_info->dpk_path_ok == 0xf)
2845 result = 1;
2846 else
2847 result = 0;
2848 break;
2849 #endif
2850
2851
2852 #if (RTL8812F_SUPPORT == 1)
2853 case ODM_RTL8812F:
2854 if (dpk_info->dpk_path_ok == 0x3)
2855 result = 1;
2856 else
2857 result = 0;
2858 break;
2859 #endif
2860
2861 #if (RTL8197G_SUPPORT == 1)
2862 case ODM_RTL8197G:
2863 if (dpk_info->dpk_path_ok == 0x3)
2864 result = 1;
2865 else
2866 result = 0;
2867 break;
2868 #endif
2869
2870 #endif
2871 default:
2872 break;
2873 }
2874 return result;
2875 }
2876
halrf_dpk_sram_read(void * dm_void)2877 void halrf_dpk_sram_read(void *dm_void)
2878 {
2879 struct dm_struct *dm = (struct dm_struct *)dm_void;
2880
2881 u8 path, group;
2882
2883 switch (dm->support_ic_type) {
2884 #if (RTL8822C_SUPPORT == 1)
2885 case ODM_RTL8822C:
2886 dpk_coef_read_8822c(dm);
2887 break;
2888 #endif
2889
2890 #if (RTL8195B_SUPPORT == 1)
2891 case ODM_RTL8195B:
2892 dpk_sram_read_8195b(dm);
2893 break;
2894 #endif
2895
2896 #if (RTL8721D_SUPPORT == 1)
2897 case ODM_RTL8721D:
2898 dpk_sram_read_8721d(dm);
2899 break;
2900 #endif
2901
2902 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2903
2904 #if (RTL8197F_SUPPORT == 1)
2905 case ODM_RTL8197F:
2906 dpk_sram_read_8197f(dm);
2907 break;
2908 #endif
2909
2910 #if (RTL8192F_SUPPORT == 1)
2911 case ODM_RTL8192F:
2912 dpk_sram_read_8192f(dm);
2913 break;
2914 #endif
2915
2916 #if (RTL8198F_SUPPORT == 1)
2917 case ODM_RTL8198F:
2918 dpk_sram_read_8198f(dm);
2919 break;
2920 #endif
2921
2922 #if (RTL8814B_SUPPORT == 1)
2923 case ODM_RTL8814B:
2924 dpk_sram_read_8814b(dm);
2925 break;
2926 #endif
2927
2928 #if (RTL8812F_SUPPORT == 1)
2929 case ODM_RTL8812F:
2930 dpk_coef_read_8812f(dm);
2931 break;
2932 #endif
2933
2934 #if (RTL8197G_SUPPORT == 1)
2935 case ODM_RTL8197G:
2936 dpk_sram_read_8197g(dm);
2937 break;
2938 #endif
2939
2940 #if (RTL8814C_SUPPORT == 1)
2941 case ODM_RTL8814C:
2942 dpk_sram_read_8814c(dm);
2943 break;
2944 #endif
2945
2946 #endif
2947
2948 default:
2949 break;
2950 }
2951 }
2952
halrf_dpk_enable_disable(void * dm_void)2953 void halrf_dpk_enable_disable(void *dm_void)
2954 {
2955 struct dm_struct *dm = (struct dm_struct *)dm_void;
2956 struct _hal_rf_ *rf = &dm->rf_table;
2957
2958 if (!(rf->rf_supportability & HAL_RF_DPK))
2959 return;
2960
2961 if (!rf->is_dpk_in_progress) {
2962 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2963 rf->is_dpk_in_progress = true;
2964 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2965
2966 switch (dm->support_ic_type) {
2967 #if (RTL8822C_SUPPORT == 1)
2968 case ODM_RTL8822C:
2969 dpk_enable_disable_8822c(dm);
2970 break;
2971 #endif
2972 #if (RTL8195B_SUPPORT == 1)
2973 case ODM_RTL8195B:
2974 dpk_enable_disable_8195b(dm);
2975 break;
2976 #endif
2977 #if (RTL8721D_SUPPORT == 1)
2978 case ODM_RTL8721D:
2979 phy_dpk_enable_disable_8721d(dm);
2980 break;
2981 #endif
2982
2983 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2984
2985 #if (RTL8197F_SUPPORT == 1)
2986 case ODM_RTL8197F:
2987 phy_dpk_enable_disable_8197f(dm);
2988 break;
2989 #endif
2990 #if (RTL8192F_SUPPORT == 1)
2991 case ODM_RTL8192F:
2992 phy_dpk_enable_disable_8192f(dm);
2993 break;
2994 #endif
2995
2996 #if (RTL8198F_SUPPORT == 1)
2997 case ODM_RTL8198F:
2998 dpk_enable_disable_8198f(dm);
2999 break;
3000 #endif
3001
3002 #if (RTL8814B_SUPPORT == 1)
3003 case ODM_RTL8814B:
3004 dpk_enable_disable_8814b(dm);
3005 break;
3006 #endif
3007
3008 #if (RTL8812F_SUPPORT == 1)
3009 case ODM_RTL8812F:
3010 dpk_enable_disable_8812f(dm);
3011 break;
3012 #endif
3013
3014 #if (RTL8197G_SUPPORT == 1)
3015 case ODM_RTL8197G:
3016 dpk_enable_disable_8197g(dm);
3017 break;
3018 #endif
3019
3020 #if (RTL8723F_SUPPORT == 1)
3021 case ODM_RTL8723F:
3022 dpk_enable_disable_8723f(dm);
3023 break;
3024 #endif
3025 #if (RTL8814C_SUPPORT == 1)
3026 case ODM_RTL8814C:
3027 dpk_enable_disable_8814c(dm);
3028 break;
3029 #endif
3030
3031 #endif
3032 default:
3033 break;
3034 }
3035
3036 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
3037 rf->is_dpk_in_progress = false;
3038 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
3039 } else {
3040 RF_DBG(dm, DBG_RF_DPK,
3041 "== Return the DPK CMD, because RFKs in Progress ==\n");
3042 }
3043 }
3044
halrf_dpk_track(void * dm_void)3045 void halrf_dpk_track(void *dm_void)
3046 {
3047 struct dm_struct *dm = (struct dm_struct *)dm_void;
3048 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3049 struct _hal_rf_ *rf = &dm->rf_table;
3050
3051 if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
3052 dm->is_psd_in_process || (dpk_info->dpk_path_ok == 0) ||
3053 !(rf->rf_supportability & HAL_RF_DPK_TRACK) || rf->is_tssi_in_progress
3054 || rf->is_txgapk_in_progress)
3055 return;
3056
3057 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3058 if (*dm->is_fcs_mode_enable)
3059 return;
3060 #endif
3061
3062 switch (dm->support_ic_type) {
3063 #if (RTL8814B_SUPPORT == 1)
3064 case ODM_RTL8814B:
3065 dpk_track_8814b(dm);
3066 break;
3067 #endif
3068
3069 #if (RTL8822C_SUPPORT == 1)
3070 case ODM_RTL8822C:
3071 dpk_track_8822c(dm);
3072 break;
3073 #endif
3074
3075 #if (RTL8195B_SUPPORT == 1)
3076 case ODM_RTL8195B:
3077 dpk_track_8195b(dm);
3078 break;
3079 #endif
3080
3081 #if (RTL8721D_SUPPORT == 1)
3082 case ODM_RTL8721D:
3083 phy_dpk_track_8721d(dm);
3084 break;
3085 #endif
3086
3087 #if (RTL8723F_SUPPORT == 1)
3088 case ODM_RTL8723F:
3089 dpk_track_8723f(dm);
3090 break;
3091 #endif
3092
3093 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
3094
3095 #if (RTL8197F_SUPPORT == 1)
3096 case ODM_RTL8197F:
3097 phy_dpk_track_8197f(dm);
3098 break;
3099 #endif
3100
3101 #if (RTL8192F_SUPPORT == 1)
3102 case ODM_RTL8192F:
3103 phy_dpk_track_8192f(dm);
3104 break;
3105 #endif
3106
3107 #if (RTL8198F_SUPPORT == 1)
3108 case ODM_RTL8198F:
3109 dpk_track_8198f(dm);
3110 break;
3111 #endif
3112
3113 #if (RTL8812F_SUPPORT == 1)
3114 case ODM_RTL8812F:
3115 dpk_track_8812f(dm);
3116 break;
3117 #endif
3118
3119 #if (RTL8197G_SUPPORT == 1)
3120 case ODM_RTL8197G:
3121 dpk_track_8197g(dm);
3122 break;
3123 #endif
3124
3125 #endif
3126 #if (RTL8814C_SUPPORT == 1)
3127 case ODM_RTL8814C:
3128 dpk_track_8814c(dm);
3129 break;
3130 #endif
3131
3132 default:
3133 break;
3134 }
3135 }
3136
halrf_set_dpk_track(void * dm_void,u8 enable)3137 void halrf_set_dpk_track(void *dm_void, u8 enable)
3138 {
3139 struct dm_struct *dm = (struct dm_struct *)dm_void;
3140 struct _hal_rf_ *rf = &(dm->rf_table);
3141
3142 if (enable)
3143 rf->rf_supportability = rf->rf_supportability | HAL_RF_DPK_TRACK;
3144 else
3145 rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK_TRACK;
3146 }
3147
halrf_dpk_reload(void * dm_void)3148 void halrf_dpk_reload(void *dm_void)
3149 {
3150 struct dm_struct *dm = (struct dm_struct *)dm_void;
3151 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3152
3153 switch (dm->support_ic_type) {
3154 #if (RTL8195B_SUPPORT == 1)
3155 case ODM_RTL8195B:
3156 if (dpk_info->dpk_path_ok > 0)
3157 dpk_reload_8195b(dm);
3158 break;
3159 #endif
3160 #if (RTL8721D_SUPPORT == 1)
3161 case ODM_RTL8721D:
3162 if (dpk_info->dpk_path_ok > 0)
3163 dpk_reload_8721d(dm);
3164 break;
3165 #endif
3166
3167 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
3168
3169 #if (RTL8197F_SUPPORT == 1)
3170 case ODM_RTL8197F:
3171 if (dpk_info->dpk_path_ok > 0)
3172 dpk_reload_8197f(dm);
3173 break;
3174 #endif
3175
3176 #if (RTL8192F_SUPPORT == 1)
3177 case ODM_RTL8192F:
3178 if (dpk_info->dpk_path_ok > 0)
3179 dpk_reload_8192f(dm);
3180
3181 break;
3182 #endif
3183
3184 #if (RTL8198F_SUPPORT == 1)
3185 case ODM_RTL8198F:
3186 if (dpk_info->dpk_path_ok > 0)
3187 dpk_reload_8198f(dm);
3188 break;
3189 #endif
3190
3191 #if (RTL8814B_SUPPORT == 1)
3192 case ODM_RTL8814B:
3193 if (dpk_info->dpk_path_ok > 0)
3194 dpk_reload_8814b(dm);
3195 break;
3196 #endif
3197
3198 #if (RTL8814C_SUPPORT == 1)
3199 case ODM_RTL8814C:
3200 if (dpk_info->dpk_path_ok > 0)
3201 dpk_reload_8814c(dm);
3202 break;
3203 #endif
3204
3205
3206 #endif
3207 default:
3208 break;
3209 }
3210 }
3211
halrf_dpk_switch(void * dm_void,u8 enable)3212 void halrf_dpk_switch(void *dm_void, u8 enable)
3213 {
3214 struct dm_struct *dm = (struct dm_struct *)dm_void;
3215 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3216 struct _hal_rf_ *rf = &dm->rf_table;
3217
3218 if (enable) {
3219 rf->rf_supportability = rf->rf_supportability | HAL_RF_DPK;
3220 dpk_info->is_dpk_enable = true;
3221 halrf_dpk_enable_disable(dm);
3222 halrf_dpk_trigger(dm);
3223 halrf_set_dpk_track(dm, 1);
3224 } else {
3225 halrf_set_dpk_track(dm, 0);
3226 dpk_info->is_dpk_enable = false;
3227 halrf_dpk_enable_disable(dm);
3228 rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK;
3229 }
3230 }
3231
_halrf_dpk_info_by_chip(void * dm_void,u32 * _used,char * output,u32 * _out_len)3232 void _halrf_dpk_info_by_chip(void *dm_void, u32 *_used, char *output, u32 *_out_len)
3233 {
3234 struct dm_struct *dm = (struct dm_struct *)dm_void;
3235
3236 u32 used = *_used;
3237 u32 out_len = *_out_len;
3238
3239 switch (dm->support_ic_type) {
3240 #if (RTL8822C_SUPPORT == 1)
3241 case ODM_RTL8822C:
3242 dpk_info_by_8822c(dm, &used, output, &out_len);
3243 break;
3244 #endif
3245
3246 #if (RTL8812F_SUPPORT == 1)
3247 case ODM_RTL8812F:
3248 dpk_info_by_8812f(dm, &used, output, &out_len);
3249 break;
3250 #endif
3251
3252 #if (RTL8197G_SUPPORT == 1)
3253 case ODM_RTL8197G:
3254 dpk_info_by_8197g(dm, &used, output, &out_len);
3255 break;
3256 #endif
3257
3258 default:
3259 break;
3260 }
3261
3262 *_used = used;
3263 *_out_len = out_len;
3264 }
3265
_halrf_display_dpk_info(void * dm_void,u32 * _used,char * output,u32 * _out_len)3266 void _halrf_display_dpk_info(void *dm_void, u32 *_used, char *output, u32 *_out_len)
3267 {
3268 struct dm_struct *dm = (struct dm_struct *)dm_void;
3269 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3270 struct _hal_rf_ *rf = &(dm->rf_table);
3271
3272 u32 used = *_used;
3273 u32 out_len = *_out_len;
3274 char *ic_name = NULL;
3275 u8 path;
3276
3277 switch (dm->support_ic_type) {
3278
3279 #if (RTL8822C_SUPPORT)
3280 case ODM_RTL8822C:
3281 ic_name = "8822C";
3282 break;
3283 #endif
3284
3285 #if (RTL8814B_SUPPORT)
3286 case ODM_RTL8814B:
3287 ic_name = "8814B";
3288 break;
3289 #endif
3290
3291 #if (RTL8812F_SUPPORT)
3292 case ODM_RTL8812F:
3293 ic_name = "8812F";
3294 break;
3295 #endif
3296
3297 #if (RTL8198F_SUPPORT)
3298 case ODM_RTL8198F:
3299 ic_name = "8198F";
3300 break;
3301 #endif
3302
3303 #if (RTL8197F_SUPPORT)
3304 case ODM_RTL8197F:
3305 ic_name = "8197F";
3306 break;
3307 #endif
3308
3309 #if (RTL8192F_SUPPORT)
3310 case ODM_RTL8192F:
3311 ic_name = "8192F";
3312 break;
3313 #endif
3314
3315 #if (RTL8197G_SUPPORT)
3316 case ODM_RTL8197G:
3317 ic_name = "8197G";
3318 break;
3319 #endif
3320
3321 #if (RTL8710B_SUPPORT)
3322 case ODM_RTL8721D:
3323 ic_name = "8721D";
3324 break;
3325 #endif
3326
3327 #if (RTL8195B_SUPPORT)
3328 case ODM_RTL8195B:
3329 ic_name = "8195B";
3330 break;
3331 #endif
3332 #if (RTL8814C_SUPPORT)
3333 case ODM_RTL8814C:
3334 ic_name = "8814C";
3335 break;
3336 #endif
3337 default:
3338 break;
3339 }
3340
3341 PDM_SNPF(out_len, used, output + used, out_len - used,
3342 "\n===============[ DPK info %s ]===============\n", ic_name);
3343
3344 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s %s\n",
3345 "DPK type", (dm->fw_offload_ability & PHYDM_RF_DPK_OFFLOAD) ? "FW" : "Driver",
3346 (dpk_info->is_dpk_by_channel) ? "(By channel)" : "(By group)");
3347
3348 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d (%d)\n",
3349 "FW Ver (Sub Ver)", dm->fw_version, dm->fw_sub_version);
3350
3351 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3352 "DPK Ver", HALRF_DPK_VER);
3353
3354 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3355 "RFK init ver", HALRF_RFK_INIT_VER);
3356
3357 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d (RFE type:%d)\n",
3358 "Ext_PA 2G / 5G", dm->ext_pa, dm->ext_pa_5g, dm->rfe_type);
3359
3360 if ((dpk_info->dpk_ch == 0) && (dpk_info->thermal_dpk[0] == 0)) {
3361 PDM_SNPF(out_len, used, output + used, out_len - used, "\n %-25s\n",
3362 "No DPK had been done before!!!");
3363 return;
3364 }
3365
3366 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d\n",
3367 "DPK Cal / OK / Reload", dpk_info->dpk_cal_cnt, dpk_info->dpk_ok_cnt,
3368 dpk_info->dpk_reload_cnt);
3369
3370 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3371 "RFK H2C timeout", (rf->is_rfk_h2c_timeout) ? "Yes" : "No");
3372
3373 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3374 "DPD Reload", (dpk_info->dpk_status & BIT(0)) ? "Yes" : "No");
3375
3376 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3377 "DPD status", dpk_info->is_dpk_enable ? "Enable" : "Disable");
3378
3379 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3380 "DPD track status", (rf->rf_supportability & HAL_RF_DPK_TRACK) ? "Enable" : "Disable");
3381
3382 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s / %s / %d / %s\n",
3383 "TSSI / Band / CH / BW", dpk_info->is_tssi_mode == 1 ? "On" : "Off",
3384 dpk_info->dpk_band == 0 ? "2G" : "5G", dpk_info->dpk_ch,
3385 dpk_info->dpk_bw == 3 ? "20M" : (dpk_info->dpk_bw == 2 ? "40M" : "80M"));
3386
3387 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s / %s / %s / %s\n",
3388 "DPK result (path)", dpk_info->dpk_path_ok & BIT(0) ? "OK" : "Fail",
3389 (dm->support_ic_type & ODM_IC_2SS) ? ((dpk_info->dpk_path_ok & BIT(1)) >> 1 ? "OK" : "Fail") : "NA",
3390 (dm->support_ic_type & ODM_IC_3SS) ? ((dpk_info->dpk_path_ok & BIT(2)) >> 2 ? "OK" : "Fail") : "NA",
3391 (dm->support_ic_type & ODM_IC_4SS) ? ((dpk_info->dpk_path_ok & BIT(3)) >> 3 ? "OK" : "Fail") : "NA");
3392 #if 0
3393 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d / %d\n",
3394 "DPK thermal (path)", dpk_info->thermal_dpk[0], dpk_info->thermal_dpk[1],
3395 dpk_info->thermal_dpk[2], dpk_info->thermal_dpk[3]);
3396 #endif
3397 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = ",
3398 "DPK thermal (path)");
3399 for (path = 0; path < KPATH; path++) {
3400 PDM_SNPF(out_len, used, output + used, out_len - used,
3401 path == (KPATH - 1) ? "%d\n" : "%d / ",
3402 dpk_info->thermal_dpk[path]);
3403 }
3404
3405 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
3406 "DPK bkup GNT control", dpk_info->gnt_control);
3407
3408 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
3409 "DPK bkup GNT value", dpk_info->gnt_value);
3410
3411 _halrf_dpk_info_by_chip(dm, &used, output, &out_len);
3412
3413 *_used = used;
3414 *_out_len = out_len;
3415 }
3416
halrf_dpk_debug_cmd(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)3417 void halrf_dpk_debug_cmd(void *dm_void, char input[][16], u32 *_used,
3418 char *output, u32 *_out_len)
3419 {
3420 struct dm_struct *dm = (struct dm_struct *)dm_void;
3421 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3422 struct _hal_rf_ *rf = &(dm->rf_table);
3423
3424 char *cmd[5] = {"-h", "on", "off", "info", "switch"};
3425 u32 used = *_used;
3426 u32 out_len = *_out_len;
3427 u8 i;
3428
3429 if ((strcmp(input[2], cmd[4]) != 0)) {
3430 if (!(rf->rf_supportability & HAL_RF_DPK)) {
3431 PDM_SNPF(out_len, used, output + used, out_len - used,
3432 "DPK is Unsupported!!!\n");
3433 return;
3434 }
3435 }
3436
3437 if ((strcmp(input[2], cmd[0]) == 0)) {
3438 for (i = 1; i < 4; i++) {
3439 PDM_SNPF(out_len, used, output + used, out_len - used,
3440 " %s\n", cmd[i]);
3441 }
3442 } else if ((strcmp(input[2], cmd[1]) == 0)) {
3443 PDM_SNPF(out_len, used, output + used, out_len - used,
3444 "DPK is Enabled!!\n");
3445 dpk_info->is_dpk_enable = true;
3446 halrf_dpk_enable_disable(dm);
3447 } else if ((strcmp(input[2], cmd[2]) == 0)){
3448 PDM_SNPF(out_len, used, output + used, out_len - used,
3449 "DPK is Disabled!!\n");
3450 dpk_info->is_dpk_enable = false;
3451 halrf_dpk_enable_disable(dm);
3452 } else if ((strcmp(input[2], cmd[3]) == 0))
3453 _halrf_display_dpk_info(dm, &used, output, &out_len);
3454 else if ((strcmp(input[2], cmd[4]) == 0) && (strcmp(input[3], cmd[1]) == 0)) {
3455 PDM_SNPF(out_len, used, output + used, out_len - used,
3456 "DPK Switch on!!\n");
3457 halrf_dpk_switch(dm, 1);
3458 } else if ((strcmp(input[2], cmd[4]) == 0) && (strcmp(input[3], cmd[2]) == 0)) {
3459 PDM_SNPF(out_len, used, output + used, out_len - used,
3460 "DPK Switch off!!\n");
3461 halrf_dpk_switch(dm, 0);
3462 } else {
3463 PDM_SNPF(out_len, used, output + used, out_len - used,
3464 "DPK Trigger start!!\n");
3465 halrf_dpk_trigger(dm);
3466 PDM_SNPF(out_len, used, output + used, out_len - used,
3467 "DPK Trigger finish!!\n");
3468 }
3469 }
3470
halrf_dpk_c2h_report_transfer(void * dm_void,boolean is_ok,u8 * buf,u8 buf_size)3471 void halrf_dpk_c2h_report_transfer(void *dm_void, boolean is_ok, u8 *buf, u8 buf_size)
3472 {
3473 struct dm_struct *dm = (struct dm_struct *)dm_void;
3474 struct _hal_rf_ *rf = &dm->rf_table;
3475 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3476
3477 if (!(rf->rf_supportability & HAL_RF_DPK))
3478 return;
3479
3480 switch (dm->support_ic_type) {
3481 #if (RTL8822C_SUPPORT == 1)
3482 case ODM_RTL8822C:
3483 dpk_c2h_report_transfer_8822c(dm, is_ok, buf, buf_size);
3484 break;
3485 #endif
3486 default:
3487 break;
3488 }
3489 }
3490
halrf_dpk_info_rsvd_page(void * dm_void,u8 * buf,u32 * buf_size)3491 void halrf_dpk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size)
3492 {
3493 struct dm_struct *dm = (struct dm_struct *)dm_void;
3494 struct _hal_rf_ *rf = &dm->rf_table;
3495 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3496
3497 if (!(rf->rf_supportability & HAL_RF_DPK) || rf->is_dpk_in_progress)
3498 return;
3499
3500 switch (dm->support_ic_type) {
3501 #if (RTL8822C_SUPPORT == 1)
3502 case ODM_RTL8822C:
3503 dpk_info_rsvd_page_8822c(dm, buf, buf_size);
3504 break;
3505 #endif
3506 default:
3507 break;
3508 }
3509 }
3510
halrf_iqk_info_rsvd_page(void * dm_void,u8 * buf,u32 * buf_size)3511 void halrf_iqk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size)
3512 {
3513 struct dm_struct *dm = (struct dm_struct *)dm_void;
3514 struct _hal_rf_ *rf = &dm->rf_table;
3515
3516 if (!(rf->rf_supportability & HAL_RF_IQK))
3517 return;
3518
3519 if (dm->rf_calibrate_info.is_iqk_in_progress)
3520 return;
3521
3522 switch (dm->support_ic_type) {
3523 #if (RTL8822C_SUPPORT == 1)
3524 case ODM_RTL8822C:
3525 iqk_info_rsvd_page_8822c(dm, buf, buf_size);
3526 break;
3527 #endif
3528 #if (RTL8195B_SUPPORT == 1)
3529 case ODM_RTL8195B:
3530 iqk_info_rsvd_page_8195b(dm, buf, buf_size);
3531 break;
3532 #endif
3533
3534 default:
3535 break;
3536 }
3537 }
3538
3539 enum hal_status
halrf_config_rfk_with_header_file(void * dm_void,u32 config_type)3540 halrf_config_rfk_with_header_file(void *dm_void, u32 config_type)
3541 {
3542 struct dm_struct *dm = (struct dm_struct *)dm_void;
3543 enum hal_status result = HAL_STATUS_SUCCESS;
3544 #if 0
3545 #if (RTL8822B_SUPPORT == 1)
3546 if (dm->support_ic_type == ODM_RTL8822B) {
3547 if (config_type == CONFIG_BB_RF_CAL_INIT)
3548 odm_read_and_config_mp_8822b_cal_init(dm);
3549 }
3550 #endif
3551 #endif
3552 #if (RTL8197G_SUPPORT == 1)
3553 if (dm->support_ic_type == ODM_RTL8197G) {
3554 if (config_type == CONFIG_BB_RF_CAL_INIT)
3555 odm_read_and_config_mp_8197g_cal_init(dm);
3556 }
3557 #endif
3558 #if (RTL8198F_SUPPORT == 1)
3559 if (dm->support_ic_type == ODM_RTL8198F) {
3560 if (config_type == CONFIG_BB_RF_CAL_INIT)
3561 odm_read_and_config_mp_8198f_cal_init(dm);
3562 }
3563 #endif
3564 #if (RTL8812F_SUPPORT == 1)
3565 if (dm->support_ic_type == ODM_RTL8812F) {
3566 if (config_type == CONFIG_BB_RF_CAL_INIT)
3567 odm_read_and_config_mp_8812f_cal_init(dm);
3568 }
3569 #endif
3570 #if (RTL8822C_SUPPORT == 1)
3571 if (dm->support_ic_type == ODM_RTL8822C) {
3572 if (config_type == CONFIG_BB_RF_CAL_INIT)
3573 odm_read_and_config_mp_8822c_cal_init(dm);
3574 }
3575 #endif
3576 #if (RTL8814B_SUPPORT == 1)
3577 if (dm->support_ic_type == ODM_RTL8814B) {
3578 if (config_type == CONFIG_BB_RF_CAL_INIT)
3579 odm_read_and_config_mp_8814b_cal_init(dm);
3580 }
3581 #endif
3582 #if (RTL8195B_SUPPORT == 1)
3583 if (dm->support_ic_type == ODM_RTL8195B) {
3584 if (config_type == CONFIG_BB_RF_CAL_INIT)
3585 odm_read_and_config_mp_8195b_cal_init(dm);
3586 }
3587 #endif
3588 #if (RTL8721D_SUPPORT == 1)
3589 if (dm->support_ic_type == ODM_RTL8721D) {
3590 if (config_type == CONFIG_BB_RF_CAL_INIT)
3591 odm_read_and_config_mp_8721d_cal_init(dm);
3592 }
3593 #endif
3594 #if (RTL8723F_SUPPORT == 1)
3595 if (dm->support_ic_type == ODM_RTL8723F) {
3596 if (config_type == CONFIG_BB_RF_CAL_INIT)
3597 odm_read_and_config_mp_8723f_cal_init(dm);
3598 }
3599 #endif
3600 #if (RTL8814C_SUPPORT == 1)
3601 if (dm->support_ic_type == ODM_RTL8814C) {
3602 if (config_type == CONFIG_BB_RF_CAL_INIT)
3603 odm_read_and_config_mp_8814c_cal_init(dm);
3604 }
3605 #endif
3606
3607
3608 #if 1
3609 if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
3610 result = phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_END, 0, 0, 0, (enum rf_path)0, 0);
3611 RF_DBG(dm, DBG_RF_IQK,"phy param offload end!result = %d", result);
3612 }
3613 #endif
3614 return result;
3615 }
3616
halrf_txgapk_trigger(void * dm_void)3617 void halrf_txgapk_trigger(void *dm_void)
3618 {
3619 struct dm_struct *dm = (struct dm_struct *)dm_void;
3620 struct _hal_rf_ *rf = &dm->rf_table;
3621 u64 start_time = 0x0;
3622
3623 if (!(rf->rf_supportability & HAL_RF_TXGAPK))
3624 return;
3625
3626 rf->rfk_type = RF04_TXGAPK;
3627 halrf_rfk_handshake(dm, true);
3628
3629 start_time = odm_get_current_time(dm);
3630 rf->is_txgapk_in_progress = true;
3631 halrf_rfk_power_save(dm, false);
3632
3633 switch (dm->support_ic_type) {
3634
3635 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
3636 #if (RTL8195B_SUPPORT == 1)
3637 case ODM_RTL8195B:
3638 /*phy_txgap_calibrate_8195b(dm, false);*/
3639 break;
3640 #endif
3641 #if (RTL8721D_SUPPORT == 1)
3642 case ODM_RTL8721D:
3643 /*phy_txgap_calibrate_8721d(dm, false);*/
3644 break;
3645 #endif
3646
3647 #endif
3648
3649 #if (RTL8814B_SUPPORT == 1)
3650 case ODM_RTL8814B:
3651 /*phy_txgap_calibrate_8814b(dm, false);*/
3652 break;
3653 #endif
3654
3655 #if (RTL8814C_SUPPORT == 1)
3656 case ODM_RTL8814C:
3657 halrf_txgapk_8814c(dm);
3658 break;
3659 #endif
3660
3661
3662 #if (RTL8822C_SUPPORT == 1)
3663 case ODM_RTL8822C:
3664 halrf_txgapk_8822c(dm);
3665 break;
3666 #endif
3667
3668 #if (RTL8723F_SUPPORT == 1)
3669 case ODM_RTL8723F:
3670 halrf_txgapk_8723f(dm);
3671 break;
3672 #endif
3673
3674 default:
3675 break;
3676 }
3677 halrf_rfk_power_save(dm, true);
3678 rf->is_txgapk_in_progress = false;
3679
3680 halrf_rfk_handshake(dm, false);
3681
3682 rf->dpk_progressing_time =
3683 odm_get_progressing_time(dm_void, start_time);
3684 RF_DBG(dm, DBG_RF_TXGAPK, "[TGGC]TXGAPK progressing_time = %lld ms\n",
3685 rf->dpk_progressing_time);
3686 }
3687
halrf_spur_compensation(void * dm_void)3688 void halrf_spur_compensation(void *dm_void)
3689 {
3690 struct dm_struct *dm = (struct dm_struct *)dm_void;
3691
3692 switch (dm->support_ic_type) {
3693 #if (RTL8723F_SUPPORT == 1)
3694 case ODM_RTL8723F:
3695 halrf_rfk_power_save(dm, false);
3696 halrf_spur_compensation_8723f(dm);
3697 halrf_rfk_power_save(dm, true);
3698 break;
3699 #endif
3700 default:
3701 break;
3702 }
3703 }
3704
halrf_tssi_get_efuse(void * dm_void)3705 void halrf_tssi_get_efuse(void *dm_void)
3706 {
3707 struct dm_struct *dm = (struct dm_struct *)dm_void;
3708
3709 #if (RTL8822C_SUPPORT == 1)
3710 if (dm->support_ic_type & ODM_RTL8822C) {
3711 halrf_tssi_get_efuse_8822c(dm);
3712 halrf_get_efuse_thermal_pwrtype_8822c(dm);
3713 }
3714 #endif
3715
3716 #if (RTL8812F_SUPPORT == 1)
3717 if (dm->support_ic_type & ODM_RTL8812F) {
3718 halrf_tssi_get_efuse_8812f(dm);
3719 }
3720 #endif
3721
3722 #if (RTL8814B_SUPPORT == 1)
3723 if (dm->support_ic_type & ODM_RTL8814B) {
3724 halrf_tssi_get_efuse_8814b(dm);
3725 halrf_get_efuse_thermal_pwrtype_8814b(dm);
3726 }
3727 #endif
3728
3729 #if (RTL8197G_SUPPORT == 1)
3730 if (dm->support_ic_type & ODM_RTL8197G) {
3731 halrf_tssi_get_efuse_8197g(dm);
3732 }
3733 #endif
3734
3735 #if (RTL8723F_SUPPORT == 1)
3736 if (dm->support_ic_type & ODM_RTL8723F) {
3737 halrf_tssi_get_efuse_8723f(dm);
3738 }
3739 #endif
3740
3741 #if (RTL8814C_SUPPORT == 1)
3742 if (dm->support_ic_type & ODM_RTL8814C) {
3743 halrf_tssi_get_efuse_8814c(dm);
3744 halrf_get_efuse_thermal_pwrtype_8814c(dm);
3745 }
3746 #endif
3747
3748 }
3749
halrf_do_rxbb_dck(void * dm_void)3750 void halrf_do_rxbb_dck(void *dm_void)
3751 {
3752 struct dm_struct *dm = (struct dm_struct *)dm_void;
3753
3754
3755 #if (RTL8814B_SUPPORT == 1)
3756 if (dm->support_ic_type == ODM_RTL8814B)
3757 halrf_do_rxbb_dck_8814b(dm);
3758 #endif
3759 #if (RTL8814C_SUPPORT == 1)
3760 if (dm->support_ic_type == ODM_RTL8814C)
3761 halrf_do_rxbb_dck_8814c(dm);
3762 #endif
3763
3764
3765 }
3766
halrf_do_tssi(void * dm_void)3767 void halrf_do_tssi(void *dm_void)
3768 {
3769 struct dm_struct *dm = (struct dm_struct *)dm_void;
3770
3771 #if (RTL8822C_SUPPORT == 1)
3772 if (dm->support_ic_type == ODM_RTL8822C)
3773 halrf_do_tssi_8822c(dm);
3774 #endif
3775
3776 #if (RTL8812F_SUPPORT == 1)
3777 if (dm->support_ic_type == ODM_RTL8812F)
3778 halrf_do_tssi_8812f(dm);
3779 #endif
3780
3781 #if (RTL8197G_SUPPORT == 1)
3782 if (dm->support_ic_type == ODM_RTL8197G)
3783 halrf_do_tssi_8197g(dm);
3784 #endif
3785
3786 #if (RTL8723F_SUPPORT == 1)
3787 if (dm->support_ic_type == ODM_RTL8723F) {
3788 halrf_rfk_power_save(dm, false);
3789 halrf_do_tssi_8723f(dm);
3790 halrf_rfk_power_save(dm, true);
3791 }
3792 #endif
3793
3794 #if (RTL8814C_SUPPORT == 1)
3795 if (dm->support_ic_type == ODM_RTL8814C)
3796 halrf_tssi_trigger_bit_reset_8814c(dm);
3797 #endif
3798
3799 }
3800
halrf_do_tssi_by_manual(void * dm_void,u8 path)3801 u8 halrf_do_tssi_by_manual(void *dm_void, u8 path)
3802 {
3803 struct dm_struct *dm = (struct dm_struct *)dm_void;
3804
3805 #if (RTL8814B_SUPPORT == 1)
3806 if (dm->support_ic_type & ODM_RTL8814B)
3807 return halrf_do_tssi_8814b(dm, path);
3808 #endif
3809
3810 #if (RTL8814C_SUPPORT == 1)
3811 if (dm->support_ic_type & ODM_RTL8814C)
3812 return halrf_do_tssi_8814c(dm, path);
3813 #endif
3814
3815 return 0;
3816 }
3817
halrf_set_tssi_enable(void * dm_void,boolean enable)3818 void halrf_set_tssi_enable(void *dm_void, boolean enable)
3819 {
3820 struct dm_struct *dm = (struct dm_struct *)dm_void;
3821 struct _hal_rf_ *rf = &(dm->rf_table);
3822
3823 if (enable == 1) {
3824 rf->power_track_type = 4;
3825 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);
3826 } else {
3827 rf->power_track_type = 0;
3828 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
3829 }
3830 }
3831
3832
halrf_do_thermal(void * dm_void)3833 void halrf_do_thermal(void *dm_void)
3834 {
3835 struct dm_struct *dm = (struct dm_struct *)dm_void;
3836
3837 #if (RTL8822C_SUPPORT == 1)
3838 if (dm->support_ic_type & ODM_RTL8822C)
3839 halrf_do_thermal_8822c(dm);
3840 #endif
3841 }
3842
3843
3844
halrf_set_tssi_value(void * dm_void,u32 tssi_value)3845 u32 halrf_set_tssi_value(void *dm_void, u32 tssi_value)
3846 {
3847 struct dm_struct *dm = (struct dm_struct *)dm_void;
3848
3849 #if (RTL8822C_SUPPORT == 1)
3850 if (dm->support_ic_type & ODM_RTL8822C)
3851 return halrf_set_tssi_value_8822c(dm, tssi_value);
3852 #endif
3853
3854 #if (RTL8814B_SUPPORT == 1)
3855 if (dm->support_ic_type & ODM_RTL8814B)
3856 return halrf_set_tssi_value_8814b(dm, tssi_value);
3857 #endif
3858 #if (RTL8723F_SUPPORT == 1)
3859 if (dm->support_ic_type & ODM_RTL8723F)
3860 return halrf_tssi_set_de_8723f(dm, tssi_value);
3861 #endif
3862 #if (RTL8814C_SUPPORT == 1)
3863 if (dm->support_ic_type & ODM_RTL8814C)
3864 return halrf_set_tssi_value_8814c(dm, tssi_value);
3865 #endif
3866
3867 return 0;
3868 }
3869
halrf_set_tssi_power(void * dm_void,s8 power)3870 void halrf_set_tssi_power(void *dm_void, s8 power)
3871 {
3872 struct dm_struct *dm = (struct dm_struct *)dm_void;
3873
3874 #if (RTL8822C_SUPPORT == 1)
3875 /*halrf_set_tssi_poewr_8822c(dm, power);*/
3876 #endif
3877 }
3878
halrf_tssi_set_de_for_tx_verify(void * dm_void,u32 tssi_de,u8 path)3879 void halrf_tssi_set_de_for_tx_verify(void *dm_void, u32 tssi_de, u8 path)
3880 {
3881 struct dm_struct *dm = (struct dm_struct *)dm_void;
3882
3883 #if (RTL8822C_SUPPORT == 1)
3884 if (dm->support_ic_type & ODM_RTL8822C)
3885 halrf_tssi_set_de_for_tx_verify_8822c(dm, tssi_de, path);
3886 #endif
3887
3888 #if (RTL8814B_SUPPORT == 1)
3889 if (dm->support_ic_type & ODM_RTL8814B)
3890 halrf_tssi_set_de_for_tx_verify_8814b(dm, tssi_de, path);
3891 #endif
3892
3893 #if (RTL8812F_SUPPORT == 1)
3894 if (dm->support_ic_type & ODM_RTL8812F)
3895 halrf_tssi_set_de_for_tx_verify_8812f(dm, tssi_de, path);
3896 #endif
3897
3898 #if (RTL8197G_SUPPORT == 1)
3899 if (dm->support_ic_type & ODM_RTL8197G)
3900 halrf_tssi_set_de_for_tx_verify_8197g(dm, tssi_de, path);
3901 #endif
3902
3903 #if (RTL8723F_SUPPORT == 1)
3904 if (dm->support_ic_type & ODM_RTL8723F)
3905 halrf_tssi_set_de_for_tx_verify_8723f(dm, tssi_de, path);
3906 #endif
3907 #if (RTL8814C_SUPPORT == 1)
3908 if (dm->support_ic_type & ODM_RTL8814C)
3909 halrf_tssi_set_de_for_tx_verify_8814c(dm, tssi_de, path);
3910 #endif
3911
3912 }
3913
halrf_tssi_turn_target_power(void * dm_void,s16 power_offset,u8 path)3914 u32 halrf_tssi_turn_target_power(void *dm_void, s16 power_offset, u8 path)
3915 {
3916 struct dm_struct *dm = (struct dm_struct *)dm_void;
3917 u32 pout = 0;
3918
3919 if (dm->mp_mode) {
3920 if (*dm->mp_mode) {
3921 #if (RTL8723F_SUPPORT == 1)
3922 if (dm->support_ic_type & ODM_RTL8723F)
3923 pout = halrf_tssi_set_powerbyrate_pout_8723f(dm, power_offset, path);
3924 #endif
3925 }
3926 }
3927 return pout;
3928 }
3929
halrf_tssi_set_power_offset(void * dm_void,s16 power_offset,u8 path)3930 void halrf_tssi_set_power_offset(void *dm_void, s16 power_offset, u8 path)
3931 {
3932 struct dm_struct *dm = (struct dm_struct *)dm_void;
3933
3934 #if (RTL8723F_SUPPORT == 1)
3935 if (dm->support_ic_type & ODM_RTL8723F)
3936 _halrf_tssi_set_powerlevel_8723f(dm, power_offset, path);
3937 #endif
3938
3939 }
3940
halrf_query_tssi_value(void * dm_void)3941 u32 halrf_query_tssi_value(void *dm_void)
3942 {
3943 struct dm_struct *dm = (struct dm_struct *)dm_void;
3944
3945 #if (RTL8822C_SUPPORT == 1)
3946 if (dm->support_ic_type & ODM_RTL8822C)
3947 return halrf_query_tssi_value_8822c(dm);
3948 #endif
3949
3950 #if (RTL8814B_SUPPORT == 1)
3951 if (dm->support_ic_type & ODM_RTL8814B)
3952 return halrf_query_tssi_value_8814b(dm);
3953 #endif
3954 #if (RTL8814C_SUPPORT == 1)
3955 if (dm->support_ic_type & ODM_RTL8814C)
3956 return halrf_query_tssi_value_8814c(dm);
3957 #endif
3958
3959 return 0;
3960 }
3961
halrf_tssi_cck(void * dm_void)3962 void halrf_tssi_cck(void *dm_void)
3963 {
3964 struct dm_struct *dm = (struct dm_struct *)dm_void;
3965
3966 #if (RTL8822C_SUPPORT == 1)
3967 /*halrf_tssi_cck_8822c(dm);*/
3968 if (dm->support_ic_type & ODM_RTL8822C)
3969 halrf_thermal_cck_8822c(dm);
3970 #endif
3971
3972 }
3973
halrf_thermal_cck(void * dm_void)3974 void halrf_thermal_cck(void *dm_void)
3975 {
3976 struct dm_struct *dm = (struct dm_struct *)dm_void;
3977
3978 #if (RTL8822C_SUPPORT == 1)
3979 if (dm->support_ic_type & ODM_RTL8822C)
3980 halrf_thermal_cck_8822c(dm);
3981 #endif
3982
3983 }
3984
halrf_tssi_set_de(void * dm_void)3985 void halrf_tssi_set_de(void *dm_void)
3986 {
3987 struct dm_struct *dm = (struct dm_struct *)dm_void;
3988
3989 #if (RTL8814B_SUPPORT == 1)
3990 if (dm->support_ic_type & ODM_RTL8814B)
3991 halrf_tssi_set_de_8814b(dm);
3992 #endif
3993 #if (RTL8814C_SUPPORT == 1)
3994 if (dm->support_ic_type & ODM_RTL8814C)
3995 halrf_tssi_set_de_8814c(dm);
3996 #endif
3997
3998 }
3999
halrf_tssi_dck(void * dm_void,u8 direct_do)4000 void halrf_tssi_dck(void *dm_void, u8 direct_do)
4001 {
4002 struct dm_struct *dm = (struct dm_struct *)dm_void;
4003
4004 halrf_rfk_handshake(dm, true);
4005
4006 #if (RTL8814B_SUPPORT == 1)
4007 if (dm->support_ic_type & ODM_RTL8814B) {
4008 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
4009 if (dm->rfe_type == 1 || dm->rfe_type == 4 || dm->rfe_type == 5)
4010 return;
4011 #else
4012 if (dm->rfe_type == 1 || dm->rfe_type == 6)
4013 return;
4014 #endif
4015 halrf_tssi_dck_8814b(dm, direct_do);
4016 }
4017 #endif
4018
4019 #if (RTL8822C_SUPPORT == 1)
4020 if (dm->support_ic_type & ODM_RTL8822C)
4021 halrf_tssi_dck_8822c(dm);
4022 #endif
4023
4024 #if (RTL8812F_SUPPORT == 1)
4025 if (dm->support_ic_type & ODM_RTL8812F)
4026 halrf_tssi_dck_8812f(dm);
4027 #endif
4028
4029 #if (RTL8197G_SUPPORT == 1)
4030 if (dm->support_ic_type == ODM_RTL8197G)
4031 halrf_tssi_dck_8197g(dm);
4032 #endif
4033 #if (RTL8814C_SUPPORT == 1)
4034 if (dm->support_ic_type & ODM_RTL8814C) {
4035 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
4036 if (dm->rfe_type == 1 || dm->rfe_type == 4 || dm->rfe_type == 5)
4037 return;
4038 #else
4039 if (dm->rfe_type == 1 || dm->rfe_type == 6)
4040 return;
4041 #endif
4042 halrf_tssi_dck_8814c(dm, direct_do);
4043 }
4044 #endif
4045
4046
4047 halrf_rfk_handshake(dm, false);
4048
4049 }
4050
halrf_calculate_tssi_codeword(void * dm_void)4051 void halrf_calculate_tssi_codeword(void *dm_void)
4052 {
4053 struct dm_struct *dm = (struct dm_struct *)dm_void;
4054
4055 #if (RTL8814B_SUPPORT == 1)
4056 if (dm->support_ic_type & ODM_RTL8814B)
4057 halrf_calculate_tssi_codeword_8814b(dm, RF_PATH_A);
4058 #endif
4059
4060 #if (RTL8822C_SUPPORT == 1)
4061 if (dm->support_ic_type & ODM_RTL8822C)
4062 halrf_calculate_tssi_codeword_8822c(dm);
4063 #endif
4064 #if (RTL8814C_SUPPORT == 1)
4065 if (dm->support_ic_type & ODM_RTL8814C)
4066 halrf_calculate_tssi_codeword_8814c(dm, RF_PATH_A);
4067 #endif
4068
4069 }
4070
halrf_set_tssi_codeword(void * dm_void)4071 void halrf_set_tssi_codeword(void *dm_void)
4072 {
4073 struct dm_struct *dm = (struct dm_struct *)dm_void;
4074 struct _hal_rf_ *rf = &dm->rf_table;
4075 #if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
4076 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
4077 #endif
4078
4079 #if (RTL8814B_SUPPORT == 1)
4080 if (dm->support_ic_type & ODM_RTL8814B)
4081 halrf_set_tssi_codeword_8814b(dm, tssi->tssi_codeword);
4082 #endif
4083
4084 #if (RTL8822C_SUPPORT == 1)
4085 if (dm->support_ic_type & ODM_RTL8822C)
4086 halrf_set_tssi_codeword_8822c(dm, tssi->tssi_codeword);
4087 #endif
4088
4089 #if (RTL8814C_SUPPORT == 1)
4090 if (dm->support_ic_type & ODM_RTL8814C)
4091 halrf_set_tssi_codeword_8814c(dm, tssi->tssi_codeword);
4092 #endif
4093
4094 }
4095
halrf_get_tssi_codeword_for_txindex(void * dm_void)4096 u8 halrf_get_tssi_codeword_for_txindex(void *dm_void)
4097 {
4098 struct dm_struct *dm = (struct dm_struct *)dm_void;
4099
4100 #if (RTL8814B_SUPPORT == 1)
4101 if (dm->support_ic_type & ODM_RTL8814B) {
4102 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
4103 return 80;
4104 #else
4105 return 60;
4106 #endif
4107 }
4108 #endif
4109
4110 #if (RTL8822C_SUPPORT == 1)
4111 if (dm->support_ic_type & ODM_RTL8822C)
4112 return 64;
4113 #endif
4114
4115 #if (RTL8812F_SUPPORT == 1)
4116 if (dm->support_ic_type & ODM_RTL8812F)
4117 return 100;
4118 #endif
4119
4120 #if (RTL8197G_SUPPORT == 1)
4121 if (dm->support_ic_type & ODM_RTL8197G)
4122 return 100;
4123 #endif
4124 #if (RTL8814C_SUPPORT == 1)
4125 if (dm->support_ic_type & ODM_RTL8814C) {
4126 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
4127 return 80;
4128 #else
4129 return 60;
4130 #endif
4131 }
4132 #endif
4133 return 60;
4134 }
4135
halrf_tssi_clean_de(void * dm_void)4136 void halrf_tssi_clean_de(
4137 void *dm_void)
4138 {
4139 struct dm_struct *dm = (struct dm_struct *)dm_void;
4140
4141 #if (RTL8812F_SUPPORT == 1)
4142 if (dm->support_ic_type & ODM_RTL8812F)
4143 halrf_tssi_clean_de_8812f(dm);
4144 #endif
4145
4146 #if (RTL8814B_SUPPORT == 1)
4147 if (dm->support_ic_type & ODM_RTL8814B)
4148 halrf_tssi_clean_de_8814b(dm);
4149 #endif
4150
4151 #if (RTL8197G_SUPPORT == 1)
4152 if (dm->support_ic_type & ODM_RTL8197G)
4153 halrf_tssi_clean_de_8197g(dm);
4154 #endif
4155 #if (RTL8814C_SUPPORT == 1)
4156 if (dm->support_ic_type & ODM_RTL8814C)
4157 halrf_tssi_clean_de_8814c(dm);
4158 #endif
4159 }
4160
halrf_tssi_trigger_de(void * dm_void,u8 path)4161 u32 halrf_tssi_trigger_de(void *dm_void, u8 path)
4162 {
4163 struct dm_struct *dm = (struct dm_struct *)dm_void;
4164
4165 #if (RTL8812F_SUPPORT == 1)
4166 if (dm->support_ic_type & ODM_RTL8812F)
4167 return halrf_tssi_trigger_de_8812f(dm, path);
4168 #endif
4169
4170 #if (RTL8814B_SUPPORT == 1)
4171 if (dm->support_ic_type & ODM_RTL8814B)
4172 return halrf_tssi_trigger_de_8814b(dm, path);
4173 #endif
4174
4175 #if (RTL8197G_SUPPORT == 1)
4176 if (dm->support_ic_type & ODM_RTL8197G)
4177 return halrf_tssi_trigger_de_8197g(dm, path);
4178 #endif
4179
4180 #if (RTL8814C_SUPPORT == 1)
4181 if (dm->support_ic_type & ODM_RTL8814C)
4182 return halrf_tssi_trigger_de_8814c(dm, path);
4183 #endif
4184 return 0;
4185 }
4186
halrf_tssi_get_de(void * dm_void,u8 path)4187 u32 halrf_tssi_get_de(void *dm_void, u8 path)
4188 {
4189 struct dm_struct *dm = (struct dm_struct *)dm_void;
4190
4191 #if (RTL8822C_SUPPORT == 1)
4192 if (dm->support_ic_type & ODM_RTL8822C)
4193 return halrf_tssi_get_de_8822c(dm, path);
4194 #endif
4195
4196 #if (RTL8812F_SUPPORT == 1)
4197 if (dm->support_ic_type & ODM_RTL8812F)
4198 return halrf_tssi_get_de_8812f(dm, path);
4199 #endif
4200
4201 #if (RTL8814B_SUPPORT == 1)
4202 if (dm->support_ic_type & ODM_RTL8814B)
4203 return halrf_tssi_get_de_8814b(dm, path);
4204 #endif
4205
4206 #if (RTL8197G_SUPPORT == 1)
4207 if (dm->support_ic_type & ODM_RTL8197G)
4208 return halrf_tssi_get_de_8197g(dm, path);
4209 #endif
4210 #if (RTL8814C_SUPPORT == 1)
4211 if (dm->support_ic_type & ODM_RTL8814C)
4212 return halrf_tssi_get_de_8814c(dm, path);
4213 #endif
4214 return 0;
4215 }
4216
halrf_get_online_tssi_de(void * dm_void,u8 path,s32 pout)4217 u32 halrf_get_online_tssi_de(void *dm_void, u8 path, s32 pout)
4218 {
4219 struct dm_struct *dm = (struct dm_struct *)dm_void;
4220
4221 #if (RTL8723F_SUPPORT == 1)
4222 if (dm->support_ic_type & ODM_RTL8723F)
4223 return halrf_get_online_tssi_de_8723f(dm, path, pout);
4224 #endif
4225 return 0;
4226 }
4227
halrf_tssi_trigger(void * dm_void)4228 void halrf_tssi_trigger(void *dm_void)
4229 {
4230 struct dm_struct *dm = (struct dm_struct *)dm_void;
4231 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
4232 struct _hal_rf_ *rf = &(dm->rf_table);
4233
4234 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
4235 if (*dm->mp_mode == 1) {
4236 if (cali_info->txpowertrack_control == 0 ||
4237 cali_info->txpowertrack_control == 1) {
4238 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4239 "[TSSI]======>%s MP Mode UI chose thermal tracking. return !!!\n", __func__);
4240 return;
4241 }
4242 } else {
4243 if (rf->power_track_type >= 0 && rf->power_track_type <= 3) {
4244 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4245 "[TSSI]======>%s Normal Mode efues is thermal tracking. return !!!\n", __func__);
4246 return;
4247 }
4248 }
4249 #endif
4250
4251 halrf_calculate_tssi_codeword(dm);
4252 halrf_set_tssi_codeword(dm);
4253 halrf_tssi_dck(dm, false);
4254 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
4255 halrf_tssi_get_efuse(dm);
4256 #endif
4257 halrf_tssi_set_de(dm);
4258 halrf_do_tssi(dm);
4259 }
4260
halrf_txgapk_write_gain_table(void * dm_void)4261 void halrf_txgapk_write_gain_table(void *dm_void)
4262 {
4263 struct dm_struct *dm = (struct dm_struct *)dm_void;
4264
4265 #if (RTL8822C_SUPPORT == 1)
4266 if (dm->support_ic_type & ODM_RTL8822C)
4267 halrf_txgapk_save_all_tx_gain_table_8822c(dm);
4268 #endif
4269 #if (RTL8814C_SUPPORT == 1)
4270 if (dm->support_ic_type & ODM_RTL8814C)
4271 halrf_txgapk_save_all_tx_gain_table_8814c(dm);
4272 #endif
4273
4274 }
4275
halrf_txgapk_reload_tx_gain(void * dm_void)4276 void halrf_txgapk_reload_tx_gain(void *dm_void)
4277 {
4278 struct dm_struct *dm = (struct dm_struct *)dm_void;
4279
4280 #if (RTL8822C_SUPPORT == 1)
4281 if (dm->support_ic_type & ODM_RTL8822C)
4282 halrf_txgapk_reload_tx_gain_8822c(dm);
4283 #endif
4284 /*
4285 #if (RTL8814C_SUPPORT == 1)
4286 if (dm->support_ic_type & ODM_RTL8814C)
4287 halrf_txgapk_reload_tx_gain_8814c(dm);
4288 #endif
4289 */
4290 }
4291
halrf_txgap_enable_disable(void * dm_void,u8 enable)4292 void halrf_txgap_enable_disable(void *dm_void, u8 enable)
4293 {
4294 struct dm_struct *dm = (struct dm_struct *)dm_void;
4295 struct _hal_rf_ *rf = &(dm->rf_table);
4296
4297 if (enable) {
4298 rf->rf_supportability = rf->rf_supportability | HAL_RF_TXGAPK;
4299 halrf_txgapk_trigger(dm);
4300 } else {
4301 rf->rf_supportability = rf->rf_supportability & ~HAL_RF_TXGAPK;
4302 halrf_txgapk_reload_tx_gain(dm);
4303 }
4304 }
4305
4306 #if (RTL8723F_SUPPORT == 1)
_halrf_get_power_offset_by_thermal_8723f(void * dm_void,u8 path,s8 thermal_detla)4307 s8 _halrf_get_power_offset_by_thermal_8723f(void *dm_void, u8 path, s8 thermal_detla)
4308 {
4309 struct dm_struct *dm = (struct dm_struct *)dm_void;
4310 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
4311 u8 channel = *dm->channel;
4312 u8 tx_rate = phydm_get_tx_rate(dm);
4313 s8 power_offset = 0;
4314 u8 i = 0;
4315 u8 thermal_up_a[DELTA_SWINGIDX_SIZE] = {0}, thermal_down_a[DELTA_SWINGIDX_SIZE] = {0};
4316 u8 thermal_up_b[DELTA_SWINGIDX_SIZE] = {0}, thermal_down_b[DELTA_SWINGIDX_SIZE] = {0};
4317 u8 txagc_offset_2g_cck_a_p[] = {
4318 0, 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 5,
4319 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6};
4320 u8 txagc_offset_2g_cck_a_n[] = {
4321 0, 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 5,
4322 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6};
4323 u8 txagc_offset_2g_cck_b_p[] = {
4324 0, 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5,
4325 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6};
4326 u8 txagc_offset_2g_cck_b_n[] = {
4327 0, 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5,
4328 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6};
4329 u8 txagc_offset_2ga_p[] = {
4330 0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6,
4331 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7};
4332 u8 txagc_offset_2ga_n[] = {
4333 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4,
4334 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6};
4335 u8 txagc_offset_2gb_p[] = {
4336 0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5,
4337 5, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7};
4338 u8 txagc_offset_2gb_n[] = {
4339 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4,
4340 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6};
4341 u8 txagc_offset_5ga_n[][30] = {
4342 {0, 0, 2, 2, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6,
4343 6, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8},
4344 {0, 0, 2, 2, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6,
4345 6, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8},
4346 {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6,
4347 6, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8},
4348 };
4349 u8 txagc_offset_5ga_p[][30] = {
4350 {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6, 8,
4351 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8},
4352 {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6, 8,
4353 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9},
4354 {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 6, 6, 6, 6, 7, 7, 8,
4355 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9},
4356 };
4357 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"[RF][TSSI] ======>%s\n", __func__);
4358
4359 if (channel >= 1 && channel <= 14) {
4360 if (IS_CCK_RATE(tx_rate)) {
4361 odm_move_memory(dm, thermal_up_a, txagc_offset_2g_cck_a_p, sizeof(thermal_up_a));
4362 odm_move_memory(dm, thermal_down_a, txagc_offset_2g_cck_a_n, sizeof(thermal_down_a));
4363 odm_move_memory(dm, thermal_up_b, txagc_offset_2g_cck_b_p, sizeof(thermal_up_b));
4364 odm_move_memory(dm, thermal_down_b, txagc_offset_2g_cck_b_n, sizeof(thermal_down_b));
4365 } else {
4366 odm_move_memory(dm, thermal_up_a, txagc_offset_2ga_p, sizeof(thermal_up_a));
4367 odm_move_memory(dm, thermal_down_a, txagc_offset_2ga_n, sizeof(thermal_down_a));
4368 odm_move_memory(dm, thermal_up_b, txagc_offset_2gb_p, sizeof(thermal_up_b));
4369 odm_move_memory(dm, thermal_down_b, txagc_offset_2gb_n, sizeof(thermal_down_b));
4370 }
4371 }
4372
4373 if (channel >= 36 && channel <= 64) {
4374 odm_move_memory(dm, thermal_up_a, txagc_offset_5ga_p[0], sizeof(thermal_up_a));
4375 odm_move_memory(dm, thermal_down_a, txagc_offset_5ga_n[0], sizeof(thermal_down_a));
4376 } else if (channel >= 100 && channel <= 144) {
4377 odm_move_memory(dm, thermal_up_a, txagc_offset_5ga_p[1], sizeof(thermal_up_a));
4378 odm_move_memory(dm, thermal_down_a, txagc_offset_5ga_n[1], sizeof(thermal_down_a));
4379 } else if (channel >= 149 && channel <= 177) {
4380 odm_move_memory(dm, thermal_up_a, txagc_offset_5ga_p[2], sizeof(thermal_up_a));
4381 odm_move_memory(dm, thermal_down_a, txagc_offset_5ga_n[2], sizeof(thermal_down_a));
4382 }
4383
4384 if(thermal_detla < 0) {
4385 if (thermal_detla < -29)
4386 i = 29;
4387 else
4388 i = (u8)(-1 * thermal_detla);
4389
4390 if (path ==0 )
4391 power_offset = thermal_down_a[i];
4392 else
4393 power_offset = thermal_down_b[i];
4394
4395 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"[RF][TSSI] Temp is lower\n");
4396 } else {
4397 if (thermal_detla >= 30)
4398 i = 29;
4399 else
4400 i = thermal_detla;
4401
4402 if (path ==0 )
4403 power_offset = thermal_up_a[i];
4404 else
4405 power_offset = thermal_up_b[i];
4406 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"[RF][TSSI] Temp is higher\n");
4407 }
4408
4409 return power_offset;
4410 }
4411
halrf_powertracking_thermal(void * dm_void)4412 void halrf_powertracking_thermal(void *dm_void)
4413 {
4414 struct dm_struct *dm = (struct dm_struct *)dm_void;
4415 struct _hal_rf_ *rf = &dm->rf_table;
4416 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
4417 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
4418 s8 thermal_value = 0, thermal_detla = 0;
4419 s8 power_offset0 = 0, power_offset1 = 0;
4420 u8 thermal_base = 0, temp[2] = {0};
4421 u8 path;
4422 u8 rate = phydm_get_tx_rate(dm);
4423 //RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"[RF][TSSI] ======>%s\n", __func__);
4424
4425 if(rf->is_tssi_in_progress == 1)
4426 return;
4427 if (*dm->mp_mode == 1) {
4428 if (cali_info->txpowertrack_control <= 2) {
4429 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"[RF][TSSI] return!! txpowertrack_control = %d\n",
4430 cali_info->txpowertrack_control);
4431 return;
4432 }
4433 } else {
4434 if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) {
4435 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4436 "[RF][TSSI] ===>is_txpowertracking is false, return!!\n");
4437 return;
4438 }
4439 }
4440
4441 if (odm_get_bb_reg(dm, R_0x4318, BIT30) == 1){
4442 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"[RF][TSSI] return!! txpowertrack_control = %d, 0x4318 = 0x%x\n",
4443 cali_info->txpowertrack_control,odm_get_bb_reg(dm, R_0x4318, MASKDWORD));
4444 return;
4445 }
4446 path = (u8)odm_get_bb_reg(dm, 0x1884, BIT(20));
4447 thermal_base = tssi->thermal_cal;
4448 thermal_value = (s8)odm_get_rf_reg(dm, 0, RF_0x42, 0x7E);/*path0*/
4449 thermal_detla = (s8)(thermal_value - thermal_base);
4450 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][TSSI] thermal_value = 0x%x, thermal_base = 0x%x\n",
4451 thermal_value, thermal_base);
4452 power_offset0 = _halrf_get_power_offset_by_thermal_8723f(dm, 0, thermal_detla);
4453 power_offset1 = _halrf_get_power_offset_by_thermal_8723f(dm, 1, thermal_detla);
4454
4455 if (rate == ODM_MGN_1M || rate == ODM_MGN_2M || rate == ODM_MGN_5_5M || rate == ODM_MGN_11M){
4456 temp[0] = tssi->txagc_offset_thermaltrack[0] -0x18 + 4*(power_offset0);/*s0*/
4457 temp[1] = tssi->txagc_offset_thermaltrack[1] - 0x8 + 4*(power_offset1);/*s1*/
4458 } else {
4459 temp[0] = tssi->txagc_offset_thermaltrack[0] + 4*(power_offset0);
4460 temp[1] = tssi->txagc_offset_thermaltrack[1] + 4*(power_offset1);
4461 }
4462 /*S0:in the same index,cck_pwr-ofdm_pwr=7dB*/
4463 odm_set_bb_reg(dm, R_0x4388, MASKBYTE0, temp[0]);/*s0*/
4464 /*S1:in the same index,cck_pwr-ofdm_pwr=5dB*/
4465 odm_set_bb_reg(dm, R_0x4388, MASKBYTE2, temp[1]);/*s1*/
4466
4467 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][TSSI] current_Path = %d, tx_rate = 0x%x\n", path, rate);
4468 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][TSSI] txagc_offset = 0x%x\n",
4469 tssi->txagc_offset_thermaltrack[path]);
4470 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4471 "[RF][TSSI] thermal_detla = %d, thermal_offset_s0 = 0x%x, thermal_offset_s1 = 0x%x\n",
4472 thermal_detla, power_offset0, power_offset1);
4473 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"[RF][TSSI] 0x4388 = 0x%x\n",
4474 odm_get_bb_reg(dm, R_0x4388, MASKDWORD));
4475
4476
4477 }
halrf_xtal_thermal_track(void * dm_void)4478 void halrf_xtal_thermal_track(void *dm_void)
4479 {
4480 struct dm_struct *dm = (struct dm_struct *)dm_void;
4481 struct _hal_rf_ *rf = &dm->rf_table;
4482 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
4483 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
4484 s8 *delta_swing_table_xtal_up = NULL;
4485 u8 xtal_offset_eanble = 0, i =0;
4486 s8 thermal_value = 0, thermal_detla = 0;
4487 u8 thermal_base = 0;
4488 s8 xtal_table_up[DELTA_SWINGIDX_SIZE] = {0};
4489 s8 xtal_table_down[DELTA_SWINGIDX_SIZE] = {0};
4490 u32 reg_val = 0, crystal_cap = 0;
4491
4492 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4493 "[RF][xtal] ======>%s\n", __func__);
4494
4495 if ( dm->support_ic_type == ODM_RTL8723F) {
4496 if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
4497 dm->is_psd_in_process || rf->is_tssi_in_progress ||
4498 !(rf->rf_supportability & HAL_RF_DPK_TRACK) ||
4499 rf->is_txgapk_in_progress)
4500 return;
4501
4502 if(tssi->thermal[0] == 0xff) {
4503 //RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][xtal] thermal 0xFF, return!\n");
4504 return;
4505 } else {
4506 thermal_base = tssi->thermal[0];
4507 //RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][xtal] thermal_base = 0x%x\n", thermal_base);
4508 }
4509
4510 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][xtal] thermal_base = 0x%x\n", thermal_base);
4511
4512 thermal_value = (s8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x42, 0x7E); /* 0x42: RF Reg[6:1]*/
4513
4514 thermal_detla = (s8)(thermal_value - thermal_base);
4515
4516 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][xtal] cali_info->xtal_offset = 0x%x\n", cali_info->xtal_offset);
4517
4518 cali_info->xtal_offset_last = cali_info->xtal_offset;
4519 /*
4520 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4521 "[RF][Xtal] cali_info->delta_swing_table_xtal_p = %d\n", cali_info->delta_swing_table_xtal_p[2]);
4522 */
4523 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4524 "[RF][Xtal] thermal_value = 0x%x, thermal_detla = 0x%x, xtal_offset_last = 0x%x\n",
4525 thermal_value, thermal_detla, cali_info->xtal_offset_last);
4526 odm_move_memory(dm, xtal_table_up, cali_info->delta_swing_table_xtal_p, sizeof(xtal_table_up));//(void *)
4527 odm_move_memory(dm, xtal_table_down, cali_info->delta_swing_table_xtal_n, sizeof(xtal_table_down));
4528 /*
4529 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4530 "[RF][Xtal] xtal_table_up[1] = %d\n", xtal_table_up[1]);*/
4531 if(thermal_detla < 0) {
4532
4533 if (thermal_detla < -29)
4534 i = 29;
4535 else
4536 i = (u8)(-1 * thermal_detla);
4537 cali_info->xtal_offset = xtal_table_down[i];
4538 } else {
4539
4540 if (thermal_detla >= 30)
4541 i = 29;
4542 else
4543 i = thermal_detla;
4544
4545 cali_info->xtal_offset = xtal_table_up[i];
4546 }
4547
4548 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4549 "[RF][Xtal] xtal_offset = %d\n", cali_info->xtal_offset);
4550 if (cali_info->xtal_offset_last == cali_info->xtal_offset)
4551 xtal_offset_eanble = 0;
4552 else
4553 xtal_offset_eanble = 1;
4554 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4555 "[RF][Xtal] xtal_offset_eanble = %d\n", xtal_offset_eanble);
4556 if (xtal_offset_eanble != 0) {
4557 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
4558 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4559 "[RF][Xtal] R_0x103c[16:10] = 0x%x\n", odm_get_mac_reg(dm, R_0x103c, 0x0001FC00));
4560
4561 crystal_cap = dm->dm_cfo_track.crystal_cap_default & 0x7F;
4562 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4563 "[RF][Xtal] DEFAULT crystal_cap = 0x%x\n", crystal_cap);
4564 reg_val = crystal_cap + cali_info->xtal_offset;
4565 //reg_val = (u32)(odm_get_mac_reg(dm, R_0x103c, 0x0001FC00) + cali_info->xtal_offset);
4566 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4567 "[RF][Xtal] reg_val = 0x%x\n", reg_val);
4568 /* write 0x103c[23:17] = 0x103c[16:10] = crystal_cap */
4569 crystal_cap = reg_val | (reg_val << 7);
4570 odm_set_mac_reg(dm, R_0x103c, 0x00FFFC00, crystal_cap);
4571 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4572 "[RF][Xtal] R_0x103c[16:10] = 0x%x\n", odm_get_mac_reg(dm, R_0x103c, 0x0001FC00));
4573 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4574 "[RF][Xtal] R_0x103c[23:17] = 0x%x\n", odm_get_mac_reg(dm, R_0x103c, 0x00FE0000));
4575 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
4576 }
4577 //odm_set_rf_reg(dm, RF_PATH_A, RF_0x42, 0x30000, 0x3);
4578 //delay
4579 }
4580 /*RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
4581 "[RF][xtal] <======%s\n", __func__);*/
4582 }
4583 #endif
4584
_halrf_dump_subpage(void * dm_void,u32 * _used,char * output,u32 * _out_len,u8 page)4585 void _halrf_dump_subpage(void *dm_void, u32 *_used, char *output, u32 *_out_len, u8 page)
4586 {
4587 struct dm_struct *dm = (struct dm_struct *)dm_void;
4588
4589 u32 used = *_used;
4590 u32 out_len = *_out_len;
4591 u32 addr;
4592
4593 PDM_SNPF(out_len, used, output + used, out_len - used,
4594 "\n===============[ Subpage_%d start]===============\n", page);
4595
4596 RF_DBG(dm, DBG_RF_RFK, " ===============[ Subpage_%d start]===============\n", page);
4597
4598 odm_set_bb_reg(dm, R_0x1b00, BIT(2) | BIT(1), page);
4599
4600 for (addr = 0x1b00; addr < 0x1c00; addr += 0x10) {
4601 PDM_SNPF(out_len, used, output + used, out_len - used,
4602 " 0x%x : 0x%08x 0x%08x 0x%08x 0x%08x\n", addr,
4603 odm_get_bb_reg(dm, addr, MASKDWORD),
4604 odm_get_bb_reg(dm, addr + 0x4, MASKDWORD),
4605 odm_get_bb_reg(dm, addr + 0x8, MASKDWORD),
4606 odm_get_bb_reg(dm, addr + 0xc, MASKDWORD));
4607 RF_DBG(dm, DBG_RF_RFK, " 0x%x : 0x%08x 0x%08x 0x%08x 0x%08x\n", addr,
4608 odm_get_bb_reg(dm, addr, MASKDWORD),
4609 odm_get_bb_reg(dm, addr + 0x4, MASKDWORD),
4610 odm_get_bb_reg(dm, addr + 0x8, MASKDWORD),
4611 odm_get_bb_reg(dm, addr + 0xc, MASKDWORD));
4612 }
4613
4614 *_used = used;
4615 *_out_len = out_len;
4616 }
4617
halrf_dump_rfk_reg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)4618 void halrf_dump_rfk_reg(void *dm_void, char input[][16], u32 *_used,
4619 char *output, u32 *_out_len)
4620 {
4621 struct dm_struct *dm = (struct dm_struct *)dm_void;
4622 struct _hal_rf_ *rf = &dm->rf_table;
4623
4624 char help[] = "-h";
4625 u32 var1[10] = {0};
4626 u32 used = *_used;
4627 u32 out_len = *_out_len;
4628 u32 reg_1b00, supportability;
4629 u8 page;
4630
4631 if (!(dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES))) {
4632 PDM_SNPF(out_len, used, output + used, out_len - used,
4633 "CMD is Unsupported due to IC type!!!\n");
4634 RF_DBG(dm, DBG_RF_RFK, "[RFK] CMD is Unsupported due to IC type!!!\n");
4635 return;
4636 } else if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
4637 dm->is_psd_in_process || rf->is_tssi_in_progress || rf->is_txgapk_in_progress) {
4638 PDM_SNPF(out_len, used, output + used, out_len - used,
4639 "Bypass CMD due to RFK is doing!!!\n");
4640 RF_DBG(dm, DBG_RF_RFK, "[RFK] Bypass CMD due to RFK is doing!!!\n");
4641 return;
4642 }
4643
4644 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4645 if (*dm->is_fcs_mode_enable) {
4646 PDM_SNPF(out_len, used, output + used, out_len - used,
4647 "Bypass CMD due to FCS mode!!!\n");
4648 RF_DBG(dm, DBG_RF_RFK, "[RFK] Bypass CMD due to FCS mode!!!\n");
4649 return;
4650 }
4651 #endif
4652 supportability = rf->rf_supportability;
4653
4654 /*to avoid DPK track interruption*/
4655 rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK_TRACK;
4656
4657 reg_1b00 = odm_get_bb_reg(dm, R_0x1b00, MASKDWORD);
4658
4659 if (input[2])
4660 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[0]);
4661
4662 if ((strcmp(input[2], help) == 0))
4663 PDM_SNPF(out_len, used, output + used, out_len - used,
4664 "dump subpage {0:Page0, 1:Page1, 2:Page2, 3:Page3, 4:all}\n");
4665 else if (var1[0] > 4)
4666 PDM_SNPF(out_len, used, output + used, out_len - used,
4667 "Wrong subpage number!!\n");
4668 else if (var1[0] == 4) {
4669 for (page = 0; page < 4; page++)
4670 _halrf_dump_subpage(dm, &used, output, &out_len, page);
4671 } else
4672 _halrf_dump_subpage(dm, &used, output, &out_len, (u8)var1[0]);
4673
4674 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, reg_1b00);
4675
4676 rf->rf_supportability = supportability;
4677
4678 *_used = used;
4679 *_out_len = out_len;
4680 }
4681
4682 /*Golbal function*/
halrf_reload_bp(void * dm_void,u32 * bp_reg,u32 * bp,u32 num)4683 void halrf_reload_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num)
4684 {
4685 struct dm_struct *dm = (struct dm_struct *)dm_void;
4686 u32 i;
4687
4688 for (i = 0; i < num; i++)
4689 odm_write_4byte(dm, bp_reg[i], bp[i]);
4690 }
4691
halrf_reload_bprf(void * dm_void,u32 * bp_reg,u32 bp[][4],u32 num,u8 ss)4692 void halrf_reload_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num,
4693 u8 ss)
4694 {
4695 struct dm_struct *dm = (struct dm_struct *)dm_void;
4696 u32 i, path;
4697
4698 for (i = 0; i < num; i++) {
4699 for (path = 0; path < ss; path++)
4700 odm_set_rf_reg(dm, (enum rf_path)path, bp_reg[i],
4701 MASK20BITS, bp[i][path]);
4702 }
4703 }
4704
halrf_bp(void * dm_void,u32 * bp_reg,u32 * bp,u32 num)4705 void halrf_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num)
4706 {
4707 struct dm_struct *dm = (struct dm_struct *)dm_void;
4708 u32 i;
4709
4710 for (i = 0; i < num; i++)
4711 bp[i] = odm_read_4byte(dm, bp_reg[i]);
4712 }
4713
halrf_bprf(void * dm_void,u32 * bp_reg,u32 bp[][4],u32 num,u8 ss)4714 void halrf_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num, u8 ss)
4715 {
4716 struct dm_struct *dm = (struct dm_struct *)dm_void;
4717 u32 i, path;
4718
4719 for (i = 0; i < num; i++) {
4720 for (path = 0; path < ss; path++) {
4721 bp[i][path] =
4722 odm_get_rf_reg(dm, (enum rf_path)path,
4723 bp_reg[i], MASK20BITS);
4724 }
4725 }
4726 }
4727
halrf_swap(void * dm_void,u32 * v1,u32 * v2)4728 void halrf_swap(void *dm_void, u32 *v1, u32 *v2)
4729 {
4730 struct dm_struct *dm = (struct dm_struct *)dm_void;
4731 u32 temp;
4732
4733 temp = *v1;
4734 *v1 = *v2;
4735 *v2 = temp;
4736 }
4737
halrf_bubble(void * dm_void,u32 * v1,u32 * v2)4738 void halrf_bubble(void *dm_void, u32 *v1, u32 *v2)
4739 {
4740 struct dm_struct *dm = (struct dm_struct *)dm_void;
4741 u32 temp;
4742
4743 if (*v1 >= 0x200 && *v2 >= 0x200) {
4744 if (*v1 > *v2)
4745 halrf_swap(dm, v1, v2);
4746 } else if (*v1 < 0x200 && *v2 < 0x200) {
4747 if (*v1 > *v2)
4748 halrf_swap(dm, v1, v2);
4749 } else if (*v1 < 0x200 && *v2 >= 0x200) {
4750 halrf_swap(dm, v1, v2);
4751 }
4752 }
4753
halrf_b_sort(void * dm_void,u32 * iv,u32 * qv)4754 void halrf_b_sort(void *dm_void, u32 *iv, u32 *qv)
4755 {
4756 struct dm_struct *dm = (struct dm_struct *)dm_void;
4757 u32 temp;
4758 u32 i, j;
4759
4760 RF_DBG(dm, DBG_RF_DACK, "[DACK]bubble!!!!!!!!!!!!");
4761 for (i = 0; i < SN - 1; i++) {
4762 for (j = 0; j < (SN - 1 - i) ; j++) {
4763 halrf_bubble(dm, &iv[j], &iv[j + 1]);
4764 halrf_bubble(dm, &qv[j], &qv[j + 1]);
4765 }
4766 }
4767 }
4768
halrf_minmax_compare(void * dm_void,u32 value,u32 * min,u32 * max)4769 void halrf_minmax_compare(void *dm_void, u32 value, u32 *min,
4770 u32 *max)
4771 {
4772 struct dm_struct *dm = (struct dm_struct *)dm_void;
4773
4774 if (value >= 0x200) {
4775 if (*min >= 0x200) {
4776 if (*min > value)
4777 *min = value;
4778 } else {
4779 *min = value;
4780 }
4781 if (*max >= 0x200) {
4782 if (*max < value)
4783 *max = value;
4784 }
4785 } else {
4786 if (*min < 0x200) {
4787 if (*min > value)
4788 *min = value;
4789 }
4790
4791 if (*max >= 0x200) {
4792 *max = value;
4793 } else {
4794 if (*max < value)
4795 *max = value;
4796 }
4797 }
4798 }
4799
halrf_delta(void * dm_void,u32 v1,u32 v2)4800 u32 halrf_delta(void *dm_void, u32 v1, u32 v2)
4801 {
4802 struct dm_struct *dm = (struct dm_struct *)dm_void;
4803
4804 if (v1 >= 0x200 && v2 >= 0x200) {
4805 if (v1 > v2)
4806 return v1 - v2;
4807 else
4808 return v2 - v1;
4809 } else if (v1 >= 0x200 && v2 < 0x200) {
4810 return v2 + (0x400 - v1);
4811 } else if (v1 < 0x200 && v2 >= 0x200) {
4812 return v1 + (0x400 - v2);
4813 }
4814
4815 if (v1 > v2)
4816 return v1 - v2;
4817 else
4818 return v2 - v1;
4819 }
4820
halrf_compare(void * dm_void,u32 value)4821 boolean halrf_compare(void *dm_void, u32 value)
4822 {
4823 struct dm_struct *dm = (struct dm_struct *)dm_void;
4824
4825 boolean fail = false;
4826
4827 if (value >= 0x200 && (0x400 - value) > 0x64)
4828 fail = true;
4829 else if (value < 0x200 && value > 0x64)
4830 fail = true;
4831
4832 if (fail)
4833 RF_DBG(dm, DBG_RF_DACK, "[DACK]overflow!!!!!!!!!!!!!!!");
4834 return fail;
4835 }
4836
halrf_mode(void * dm_void,u32 * i_value,u32 * q_value)4837 void halrf_mode(void *dm_void, u32 *i_value, u32 *q_value)
4838 {
4839 struct dm_struct *dm = (struct dm_struct *)dm_void;
4840 u32 iv[SN], qv[SN], im[SN], qm[SN], temp, temp1, temp2;
4841 u32 p, m, t;
4842 u32 i_max = 0, q_max = 0, i_min = 0x0, q_min = 0x0, c = 0x0;
4843 u32 i_delta, q_delta;
4844 u8 i, j, ii = 0, qi = 0;
4845 boolean fail = false;
4846
4847 ODM_delay_ms(10);
4848 for (i = 0; i < SN; i++) {
4849 im[i] = 0;
4850 qm[i] = 0;
4851 }
4852 i = 0;
4853 c = 0;
4854 while (i < SN && c < 1000) {
4855 c++;
4856 temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
4857 iv[i] = (temp & 0x3ff000) >> 12;
4858 qv[i] = temp & 0x3ff;
4859
4860 fail = false;
4861 if (halrf_compare(dm, iv[i]))
4862 fail = true;
4863 if (halrf_compare(dm, qv[i]))
4864 fail = true;
4865 if (!fail)
4866 i++;
4867 }
4868 c = 0;
4869 do {
4870 c++;
4871 i_min = iv[0];
4872 i_max = iv[0];
4873 q_min = qv[0];
4874 q_max = qv[0];
4875 for (i = 0; i < SN; i++) {
4876 halrf_minmax_compare(dm, iv[i], &i_min, &i_max);
4877 halrf_minmax_compare(dm, qv[i], &q_min, &q_max);
4878 }
4879 RF_DBG(dm, DBG_RF_DACK, "[DACK]i_min=0x%x, i_max=0x%x",
4880 i_min, i_max);
4881 RF_DBG(dm, DBG_RF_DACK, "[DACK]q_min=0x%x, q_max=0x%x",
4882 q_min, q_max);
4883 if (i_max < 0x200 && i_min < 0x200)
4884 i_delta = i_max - i_min;
4885 else if (i_max >= 0x200 && i_min >= 0x200)
4886 i_delta = i_max - i_min;
4887 else
4888 i_delta = i_max + (0x400 - i_min);
4889
4890 if (q_max < 0x200 && q_min < 0x200)
4891 q_delta = q_max - q_min;
4892 else if (q_max >= 0x200 && q_min >= 0x200)
4893 q_delta = q_max - q_min;
4894 else
4895 q_delta = q_max + (0x400 - q_min);
4896 RF_DBG(dm, DBG_RF_DACK, "[DACK]i_delta=0x%x, q_delta=0x%x",
4897 i_delta, q_delta);
4898 halrf_b_sort(dm, iv, qv);
4899 if (i_delta > 5 || q_delta > 5) {
4900 temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
4901 iv[0] = (temp & 0x3ff000) >> 12;
4902 qv[0] = temp & 0x3ff;
4903 temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
4904 iv[SN - 1] = (temp & 0x3ff000) >> 12;
4905 qv[SN - 1] = temp & 0x3ff;
4906 } else {
4907 break;
4908 }
4909 } while (c < 100);
4910 #if 1
4911 #if 0
4912 for (i = 0; i < SN; i++)
4913 RF_DBG(dm, DBG_RF_DACK, "[DACK]iv[%d] = 0x%x\n", i, iv[i]);
4914 for (i = 0; i < SN; i++)
4915 RF_DBG(dm, DBG_RF_DACK, "[DACK]qv[%d] = 0x%x\n", i, qv[i]);
4916 #endif
4917 /*i*/
4918 m = 0;
4919 p = 0;
4920 for (i = 10; i < SN - 10; i++) {
4921 if (iv[i] > 0x200)
4922 m = (0x400 - iv[i]) + m;
4923 else
4924 p = iv[i] + p;
4925 }
4926
4927 if (p > m) {
4928 t = p - m;
4929 t = t / (SN - 20);
4930 } else {
4931 t = m - p;
4932 t = t / (SN - 20);
4933 if (t != 0x0)
4934 t = 0x400 - t;
4935 }
4936 *i_value = t;
4937 /*q*/
4938 m = 0;
4939 p = 0;
4940 for (i = 10; i < SN - 10; i++) {
4941 if (qv[i] > 0x200)
4942 m = (0x400 - qv[i]) + m;
4943 else
4944 p = qv[i] + p;
4945 }
4946 if (p > m) {
4947 t = p - m;
4948 t = t / (SN - 20);
4949 } else {
4950 t = m - p;
4951 t = t / (SN - 20);
4952 if (t != 0x0)
4953 t = 0x400 - t;
4954 }
4955 *q_value = t;
4956 #endif
4957 }
halrf_delay_10us(u16 v1)4958 void halrf_delay_10us(u16 v1)
4959 {
4960 u16 i = 0;
4961
4962 for (i = 0; i < v1; i++)
4963 ODM_delay_us(10);
4964 }
4965
4966