1 /* 2 * Copyright (c) 2022 ASR Microelectronics (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __DUET_I2S_H 17 #define __DUET_I2S_H 18 19 #ifdef __cplusplus 20 extern "c" { 21 #endif 22 23 #include <errno.h> 24 #include "duet.h" 25 26 /* Interrupt status register fields */ 27 #define I2S_INTERRUPT_TXFO (1 << 5) 28 #define I2S_INTERRUPT_TXFE (1 << 4) 29 #define I2S_INTERRUPT_RXFO (1 << 1) 30 #define I2S_INTERRUPT_RXDA (1 << 0) 31 32 /* I2S protocal mode */ 33 #define I2S_MODE_LEFT_ALIGN (0) 34 #define I2S_MODE_RIGHT_ALIGN (1) 35 #define I2S_MODE_PHILIPS (2) 36 37 #define I2S_TX_BLOCK_EN (1) 38 #define I2S_RX_BLOCK_EN (1) 39 #define I2S_TX_CHAN_EN (1) 40 #define I2S_RX_CHAN_EN (1) 41 42 #define I2S_FIFO_TRIGGERL_LEVEL_1 (1) 43 #define I2S_FIFO_TRIGGERL_LEVEL_2 (2) 44 #define I2S_FIFO_TRIGGERL_LEVEL_3 (3) 45 #define I2S_FIFO_TRIGGERL_LEVEL_4 (4) 46 #define I2S_FIFO_TRIGGERL_LEVEL_5 (5) 47 #define I2S_FIFO_TRIGGERL_LEVEL_6 (6) 48 #define I2S_FIFO_TRIGGERL_LEVEL_7 (7) 49 #define I2S_FIFO_TRIGGERL_LEVEL_8 (8) 50 #define I2S_FIFO_TRIGGERL_LEVEL_9 (9) 51 #define I2S_FIFO_TRIGGERL_LEVEL_10 (10) 52 #define I2S_FIFO_TRIGGERL_LEVEL_11 (11) 53 #define I2S_FIFO_TRIGGERL_LEVEL_12 (12) 54 #define I2S_FIFO_TRIGGERL_LEVEL_13 (13) 55 #define I2S_FIFO_TRIGGERL_LEVEL_14 (14) 56 #define I2S_FIFO_TRIGGERL_LEVEL_15 (15) 57 #define I2S_FIFO_TRIGGERL_LEVEL_16 (16) 58 59 #define I2S_FIFO_TRIGGER_LEVEL_MASK (0xf) 60 61 #define I2S_HW_SHIFT_LEFT_4 (0) 62 #define I2S_HW_SHIFT_LEFT_8 (1) 63 #define I2S_HW_SHIFT_LEFT_12 (2) 64 #define I2S_HW_SHIFT_LEFT_16 (3) 65 #define I2S_HW_SHIFT_LEFT_20 (4) 66 #define I2S_HW_SHIFT_RIGHT_4 (5) 67 #define I2S_HW_SHIFT_RIGHT_8 (6) 68 #define I2S_HW_SHIFT_RIGHT_12 (7) 69 #define I2S_HW_SHIFT_RIGHT_16 (8) 70 #define I2S_HW_SHIFT_RIGHT_20 (9) 71 72 #define I2S_HW_SHIFT_PADDING_1 (1<<4) 73 #define I2S_HW_SHIFT_PADDING_0 (0) 74 75 /* I2S module parameters */ 76 #define I2S_WORDSIZE_DONT_CARE (0) 77 #define I2S_WORDSIZE_12bit (1) 78 #define I2S_WORDSIZE_16bit (2) 79 #define I2S_WORDSIZE_20bit (3) 80 #define I2S_WORDSIZE_24bit (4) 81 #define I2S_WORDSIZE_32bit (5) 82 83 #define I2S_FIFO_DEPTH (16) 84 #define I2S_APB_DATA_WIDTH (32) 85 86 #define I2S_RX_WORDSIZE_MASK (0x7) 87 #define I2S_TX_WORDSIZE_MASK (0x7) 88 89 #define I2S_ROLE_MASTER (1) 90 #define I2S_ROLE_SLAVE (0) 91 92 #define I2S_MCLK_SRC_FREQ72 (72000000) // for sample rate 44.1KHz only 93 #define I2S_MCLK_SRC_FREQ96 (96000000) // for sample rate 44.1KHz only 94 #define I2S_MCLK_SRC_FREQ120 (120000000) // for sample rate 44.1/96/48/32/16/8KHZ 95 96 #define I2S_SAMPLE_RATE_44P1K (44100) 97 #define I2S_SAMPLE_RATE_96K (96000) 98 #define I2S_SAMPLE_RATE_48K (48000) 99 #define I2S_SAMPLE_RATE_32K (32000) 100 #define I2S_SAMPLE_RATE_16K (16000) 101 #define I2S_SAMPLE_RATE_8K (8000) 102 103 typedef void (*duet_i2s_callback_func)(uint32_t, uint32_t); 104 extern duet_i2s_callback_func g_duet_i2s_callback_handler; 105 106 typedef struct { 107 uint32_t i2s_sample_rate; 108 uint32_t i2s_mclk_src; 109 uint32_t i2s_ws; 110 uint8_t i2s_role; 111 uint8_t i2s_word_size; 112 uint8_t i2s_tx_en; 113 uint8_t i2s_rx_en; 114 uint8_t i2s_fifo_threshold; 115 uint8_t i2s_mode; 116 } duet_i2s_dev_t; 117 i2s_get_interrupt_status(I2S_TypeDef * I2Sx,uint32_t i2s_interrupt)118 __STATIC_INLINE ITstatus i2s_get_interrupt_status(I2S_TypeDef *I2Sx, uint32_t i2s_interrupt) 119 { 120 return (I2Sx->ISR & i2s_interrupt) ? SET : RESET; 121 } 122 123 void duet_i2s_send_data(I2S_TypeDef *I2Sx, uint32_t *left_chan_data, uint32_t *right_chan_data, uint32_t len); 124 125 void duet_i2s_struct_init(duet_i2s_dev_t *pI2S_struct); 126 127 void duet_i2s_interrupt_config(I2S_TypeDef *I2Sx, uint32_t i2s_interrupt, uint32_t new_state); 128 void duet_i2s_interrupt_clear(I2S_TypeDef *I2Sx, uint32_t i2s_interrupt); 129 void duet_i2s_cmd(I2S_TypeDef *I2Sx, uint32_t new_state); 130 131 void duet_i2s_tx_block_cmd(I2S_TypeDef *I2Sx, uint32_t new_state); 132 void duet_i2s_rx_block_cmd(I2S_TypeDef *I2Sx, uint32_t new_state); 133 void duet_i2s_tx_channel_cmd(I2S_TypeDef *I2Sx, uint32_t new_state); 134 void duet_i2s_rx_channel_cmd(I2S_TypeDef *I2Sx, uint32_t new_state); 135 void duet_i2s_master_clock_cmd(I2S_TypeDef *I2Sx, uint32_t new_state); 136 int duet_i2s_init(I2S_TypeDef *I2Sx, duet_i2s_dev_t *pI2S_struct); 137 uint32_t duet_i2s_receive_data(I2S_TypeDef *I2Sx, uint8_t lr); 138 139 #ifdef __cplusplus 140 } 141 #endif 142 143 #endif /* __DUET_I2S_H */ 144