1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
35 #include <linux/pm.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vga_switcheroo.h>
40 #include <linux/vt.h>
41 #include <acpi/video.h>
42
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_ioctl.h>
45 #include <drm/drm_irq.h>
46 #include <drm/drm_managed.h>
47 #include <drm/drm_probe_helper.h>
48
49 #include "display/intel_acpi.h"
50 #include "display/intel_audio.h"
51 #include "display/intel_bw.h"
52 #include "display/intel_cdclk.h"
53 #include "display/intel_csr.h"
54 #include "display/intel_display_debugfs.h"
55 #include "display/intel_display_types.h"
56 #include "display/intel_dp.h"
57 #include "display/intel_fbdev.h"
58 #include "display/intel_hotplug.h"
59 #include "display/intel_overlay.h"
60 #include "display/intel_pipe_crc.h"
61 #include "display/intel_sprite.h"
62 #include "display/intel_vga.h"
63
64 #include "gem/i915_gem_context.h"
65 #include "gem/i915_gem_ioctls.h"
66 #include "gem/i915_gem_mman.h"
67 #include "gt/intel_gt.h"
68 #include "gt/intel_gt_pm.h"
69 #include "gt/intel_rc6.h"
70
71 #include "i915_debugfs.h"
72 #include "i915_drv.h"
73 #include "i915_ioc32.h"
74 #include "i915_irq.h"
75 #include "i915_memcpy.h"
76 #include "i915_perf.h"
77 #include "i915_query.h"
78 #include "i915_suspend.h"
79 #include "i915_switcheroo.h"
80 #include "i915_sysfs.h"
81 #include "i915_trace.h"
82 #include "i915_vgpu.h"
83 #include "intel_dram.h"
84 #include "intel_gvt.h"
85 #include "intel_memory_region.h"
86 #include "intel_pm.h"
87 #include "vlv_suspend.h"
88
89 static struct drm_driver driver;
90
i915_get_bridge_dev(struct drm_i915_private * dev_priv)91 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
92 {
93 int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
94
95 dev_priv->bridge_dev =
96 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
97 if (!dev_priv->bridge_dev) {
98 drm_err(&dev_priv->drm, "bridge device not found\n");
99 return -1;
100 }
101 return 0;
102 }
103
104 /* Allocate space for the MCH regs if needed, return nonzero on error */
105 static int
intel_alloc_mchbar_resource(struct drm_i915_private * dev_priv)106 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
107 {
108 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
109 u32 temp_lo, temp_hi = 0;
110 u64 mchbar_addr;
111 int ret;
112
113 if (INTEL_GEN(dev_priv) >= 4)
114 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
115 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
116 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
117
118 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
119 #ifdef CONFIG_PNP
120 if (mchbar_addr &&
121 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
122 return 0;
123 #endif
124
125 /* Get some space for it */
126 dev_priv->mch_res.name = "i915 MCHBAR";
127 dev_priv->mch_res.flags = IORESOURCE_MEM;
128 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
129 &dev_priv->mch_res,
130 MCHBAR_SIZE, MCHBAR_SIZE,
131 PCIBIOS_MIN_MEM,
132 0, pcibios_align_resource,
133 dev_priv->bridge_dev);
134 if (ret) {
135 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
136 dev_priv->mch_res.start = 0;
137 return ret;
138 }
139
140 if (INTEL_GEN(dev_priv) >= 4)
141 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
142 upper_32_bits(dev_priv->mch_res.start));
143
144 pci_write_config_dword(dev_priv->bridge_dev, reg,
145 lower_32_bits(dev_priv->mch_res.start));
146 return 0;
147 }
148
149 /* Setup MCHBAR if possible, return true if we should disable it again */
150 static void
intel_setup_mchbar(struct drm_i915_private * dev_priv)151 intel_setup_mchbar(struct drm_i915_private *dev_priv)
152 {
153 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
154 u32 temp;
155 bool enabled;
156
157 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
158 return;
159
160 dev_priv->mchbar_need_disable = false;
161
162 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
163 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
164 enabled = !!(temp & DEVEN_MCHBAR_EN);
165 } else {
166 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
167 enabled = temp & 1;
168 }
169
170 /* If it's already enabled, don't have to do anything */
171 if (enabled)
172 return;
173
174 if (intel_alloc_mchbar_resource(dev_priv))
175 return;
176
177 dev_priv->mchbar_need_disable = true;
178
179 /* Space is allocated or reserved, so enable it. */
180 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
181 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
182 temp | DEVEN_MCHBAR_EN);
183 } else {
184 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
185 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
186 }
187 }
188
189 static void
intel_teardown_mchbar(struct drm_i915_private * dev_priv)190 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
191 {
192 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
193
194 if (dev_priv->mchbar_need_disable) {
195 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
196 u32 deven_val;
197
198 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
199 &deven_val);
200 deven_val &= ~DEVEN_MCHBAR_EN;
201 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
202 deven_val);
203 } else {
204 u32 mchbar_val;
205
206 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
207 &mchbar_val);
208 mchbar_val &= ~1;
209 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
210 mchbar_val);
211 }
212 }
213
214 if (dev_priv->mch_res.start)
215 release_resource(&dev_priv->mch_res);
216 }
217
i915_workqueues_init(struct drm_i915_private * dev_priv)218 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
219 {
220 /*
221 * The i915 workqueue is primarily used for batched retirement of
222 * requests (and thus managing bo) once the task has been completed
223 * by the GPU. i915_retire_requests() is called directly when we
224 * need high-priority retirement, such as waiting for an explicit
225 * bo.
226 *
227 * It is also used for periodic low-priority events, such as
228 * idle-timers and recording error state.
229 *
230 * All tasks on the workqueue are expected to acquire the dev mutex
231 * so there is no point in running more than one instance of the
232 * workqueue at any time. Use an ordered one.
233 */
234 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
235 if (dev_priv->wq == NULL)
236 goto out_err;
237
238 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
239 if (dev_priv->hotplug.dp_wq == NULL)
240 goto out_free_wq;
241
242 return 0;
243
244 out_free_wq:
245 destroy_workqueue(dev_priv->wq);
246 out_err:
247 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
248
249 return -ENOMEM;
250 }
251
i915_workqueues_cleanup(struct drm_i915_private * dev_priv)252 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
253 {
254 destroy_workqueue(dev_priv->hotplug.dp_wq);
255 destroy_workqueue(dev_priv->wq);
256 }
257
258 /*
259 * We don't keep the workarounds for pre-production hardware, so we expect our
260 * driver to fail on these machines in one way or another. A little warning on
261 * dmesg may help both the user and the bug triagers.
262 *
263 * Our policy for removing pre-production workarounds is to keep the
264 * current gen workarounds as a guide to the bring-up of the next gen
265 * (workarounds have a habit of persisting!). Anything older than that
266 * should be removed along with the complications they introduce.
267 */
intel_detect_preproduction_hw(struct drm_i915_private * dev_priv)268 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
269 {
270 bool pre = false;
271
272 pre |= IS_HSW_EARLY_SDV(dev_priv);
273 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
274 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
275 pre |= IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_A0);
276 pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
277
278 if (pre) {
279 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
280 "It may not be fully functional.\n");
281 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
282 }
283 }
284
sanitize_gpu(struct drm_i915_private * i915)285 static void sanitize_gpu(struct drm_i915_private *i915)
286 {
287 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
288 __intel_gt_reset(&i915->gt, ALL_ENGINES);
289 }
290
291 /**
292 * i915_driver_early_probe - setup state not requiring device access
293 * @dev_priv: device private
294 *
295 * Initialize everything that is a "SW-only" state, that is state not
296 * requiring accessing the device or exposing the driver via kernel internal
297 * or userspace interfaces. Example steps belonging here: lock initialization,
298 * system memory allocation, setting up device specific attributes and
299 * function hooks not requiring accessing the device.
300 */
i915_driver_early_probe(struct drm_i915_private * dev_priv)301 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
302 {
303 int ret = 0;
304
305 if (i915_inject_probe_failure(dev_priv))
306 return -ENODEV;
307
308 intel_device_info_subplatform_init(dev_priv);
309
310 intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
311 intel_uncore_init_early(&dev_priv->uncore, dev_priv);
312
313 spin_lock_init(&dev_priv->irq_lock);
314 spin_lock_init(&dev_priv->gpu_error.lock);
315 mutex_init(&dev_priv->backlight_lock);
316
317 mutex_init(&dev_priv->sb_lock);
318 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
319
320 mutex_init(&dev_priv->av_mutex);
321 mutex_init(&dev_priv->wm.wm_mutex);
322 mutex_init(&dev_priv->pps_mutex);
323 mutex_init(&dev_priv->hdcp_comp_mutex);
324
325 i915_memcpy_init_early(dev_priv);
326 intel_runtime_pm_init_early(&dev_priv->runtime_pm);
327
328 ret = i915_workqueues_init(dev_priv);
329 if (ret < 0)
330 return ret;
331
332 ret = vlv_suspend_init(dev_priv);
333 if (ret < 0)
334 goto err_workqueues;
335
336 intel_wopcm_init_early(&dev_priv->wopcm);
337
338 intel_gt_init_early(&dev_priv->gt, dev_priv);
339
340 i915_gem_init_early(dev_priv);
341
342 /* This must be called before any calls to HAS_PCH_* */
343 intel_detect_pch(dev_priv);
344
345 intel_pm_setup(dev_priv);
346 ret = intel_power_domains_init(dev_priv);
347 if (ret < 0)
348 goto err_gem;
349 intel_irq_init(dev_priv);
350 intel_init_display_hooks(dev_priv);
351 intel_init_clock_gating_hooks(dev_priv);
352 intel_init_audio_hooks(dev_priv);
353
354 intel_detect_preproduction_hw(dev_priv);
355
356 return 0;
357
358 err_gem:
359 i915_gem_cleanup_early(dev_priv);
360 intel_gt_driver_late_release(&dev_priv->gt);
361 vlv_suspend_cleanup(dev_priv);
362 err_workqueues:
363 i915_workqueues_cleanup(dev_priv);
364 return ret;
365 }
366
367 /**
368 * i915_driver_late_release - cleanup the setup done in
369 * i915_driver_early_probe()
370 * @dev_priv: device private
371 */
i915_driver_late_release(struct drm_i915_private * dev_priv)372 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
373 {
374 intel_irq_fini(dev_priv);
375 intel_power_domains_cleanup(dev_priv);
376 i915_gem_cleanup_early(dev_priv);
377 intel_gt_driver_late_release(&dev_priv->gt);
378 vlv_suspend_cleanup(dev_priv);
379 i915_workqueues_cleanup(dev_priv);
380
381 cpu_latency_qos_remove_request(&dev_priv->sb_qos);
382 mutex_destroy(&dev_priv->sb_lock);
383
384 i915_params_free(&dev_priv->params);
385 }
386
387 /**
388 * i915_driver_mmio_probe - setup device MMIO
389 * @dev_priv: device private
390 *
391 * Setup minimal device state necessary for MMIO accesses later in the
392 * initialization sequence. The setup here should avoid any other device-wide
393 * side effects or exposing the driver via kernel internal or user space
394 * interfaces.
395 */
i915_driver_mmio_probe(struct drm_i915_private * dev_priv)396 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
397 {
398 int ret;
399
400 if (i915_inject_probe_failure(dev_priv))
401 return -ENODEV;
402
403 if (i915_get_bridge_dev(dev_priv))
404 return -EIO;
405
406 ret = intel_uncore_init_mmio(&dev_priv->uncore);
407 if (ret < 0)
408 goto err_bridge;
409
410 /* Try to make sure MCHBAR is enabled before poking at it */
411 intel_setup_mchbar(dev_priv);
412
413 ret = intel_gt_init_mmio(&dev_priv->gt);
414 if (ret)
415 goto err_uncore;
416
417 /* As early as possible, scrub existing GPU state before clobbering */
418 sanitize_gpu(dev_priv);
419
420 return 0;
421
422 err_uncore:
423 intel_teardown_mchbar(dev_priv);
424 intel_uncore_fini_mmio(&dev_priv->uncore);
425 err_bridge:
426 pci_dev_put(dev_priv->bridge_dev);
427
428 return ret;
429 }
430
431 /**
432 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
433 * @dev_priv: device private
434 */
i915_driver_mmio_release(struct drm_i915_private * dev_priv)435 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
436 {
437 intel_teardown_mchbar(dev_priv);
438 intel_uncore_fini_mmio(&dev_priv->uncore);
439 pci_dev_put(dev_priv->bridge_dev);
440 }
441
intel_sanitize_options(struct drm_i915_private * dev_priv)442 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
443 {
444 intel_gvt_sanitize_options(dev_priv);
445 }
446
447 /**
448 * i915_set_dma_info - set all relevant PCI dma info as configured for the
449 * platform
450 * @i915: valid i915 instance
451 *
452 * Set the dma max segment size, device and coherent masks. The dma mask set
453 * needs to occur before i915_ggtt_probe_hw.
454 *
455 * A couple of platforms have special needs. Address them as well.
456 *
457 */
i915_set_dma_info(struct drm_i915_private * i915)458 static int i915_set_dma_info(struct drm_i915_private *i915)
459 {
460 struct pci_dev *pdev = i915->drm.pdev;
461 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
462 int ret;
463
464 GEM_BUG_ON(!mask_size);
465
466 /*
467 * We don't have a max segment size, so set it to the max so sg's
468 * debugging layer doesn't complain
469 */
470 dma_set_max_seg_size(&pdev->dev, UINT_MAX);
471
472 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(mask_size));
473 if (ret)
474 goto mask_err;
475
476 /* overlay on gen2 is broken and can't address above 1G */
477 if (IS_GEN(i915, 2))
478 mask_size = 30;
479
480 /*
481 * 965GM sometimes incorrectly writes to hardware status page (HWS)
482 * using 32bit addressing, overwriting memory if HWS is located
483 * above 4GB.
484 *
485 * The documentation also mentions an issue with undefined
486 * behaviour if any general state is accessed within a page above 4GB,
487 * which also needs to be handled carefully.
488 */
489 if (IS_I965G(i915) || IS_I965GM(i915))
490 mask_size = 32;
491
492 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(mask_size));
493 if (ret)
494 goto mask_err;
495
496 return 0;
497
498 mask_err:
499 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
500 return ret;
501 }
502
503 /**
504 * i915_driver_hw_probe - setup state requiring device access
505 * @dev_priv: device private
506 *
507 * Setup state that requires accessing the device, but doesn't require
508 * exposing the driver via kernel internal or userspace interfaces.
509 */
i915_driver_hw_probe(struct drm_i915_private * dev_priv)510 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
511 {
512 struct pci_dev *pdev = dev_priv->drm.pdev;
513 int ret;
514
515 if (i915_inject_probe_failure(dev_priv))
516 return -ENODEV;
517
518 intel_device_info_runtime_init(dev_priv);
519
520 if (HAS_PPGTT(dev_priv)) {
521 if (intel_vgpu_active(dev_priv) &&
522 !intel_vgpu_has_full_ppgtt(dev_priv)) {
523 i915_report_error(dev_priv,
524 "incompatible vGPU found, support for isolated ppGTT required\n");
525 return -ENXIO;
526 }
527 }
528
529 if (HAS_EXECLISTS(dev_priv)) {
530 /*
531 * Older GVT emulation depends upon intercepting CSB mmio,
532 * which we no longer use, preferring to use the HWSP cache
533 * instead.
534 */
535 if (intel_vgpu_active(dev_priv) &&
536 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
537 i915_report_error(dev_priv,
538 "old vGPU host found, support for HWSP emulation required\n");
539 return -ENXIO;
540 }
541 }
542
543 intel_sanitize_options(dev_priv);
544
545 /* needs to be done before ggtt probe */
546 intel_dram_edram_detect(dev_priv);
547
548 ret = i915_set_dma_info(dev_priv);
549 if (ret)
550 return ret;
551
552 i915_perf_init(dev_priv);
553
554 ret = i915_ggtt_probe_hw(dev_priv);
555 if (ret)
556 goto err_perf;
557
558 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb");
559 if (ret)
560 goto err_ggtt;
561
562 ret = i915_ggtt_init_hw(dev_priv);
563 if (ret)
564 goto err_ggtt;
565
566 ret = intel_memory_regions_hw_probe(dev_priv);
567 if (ret)
568 goto err_ggtt;
569
570 intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
571
572 ret = i915_ggtt_enable_hw(dev_priv);
573 if (ret) {
574 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
575 goto err_mem_regions;
576 }
577
578 pci_set_master(pdev);
579
580 intel_gt_init_workarounds(dev_priv);
581
582 /* On the 945G/GM, the chipset reports the MSI capability on the
583 * integrated graphics even though the support isn't actually there
584 * according to the published specs. It doesn't appear to function
585 * correctly in testing on 945G.
586 * This may be a side effect of MSI having been made available for PEG
587 * and the registers being closely associated.
588 *
589 * According to chipset errata, on the 965GM, MSI interrupts may
590 * be lost or delayed, and was defeatured. MSI interrupts seem to
591 * get lost on g4x as well, and interrupt delivery seems to stay
592 * properly dead afterwards. So we'll just disable them for all
593 * pre-gen5 chipsets.
594 *
595 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
596 * interrupts even when in MSI mode. This results in spurious
597 * interrupt warnings if the legacy irq no. is shared with another
598 * device. The kernel then disables that interrupt source and so
599 * prevents the other device from working properly.
600 */
601 if (INTEL_GEN(dev_priv) >= 5) {
602 if (pci_enable_msi(pdev) < 0)
603 drm_dbg(&dev_priv->drm, "can't enable MSI");
604 }
605
606 ret = intel_gvt_init(dev_priv);
607 if (ret)
608 goto err_msi;
609
610 intel_opregion_setup(dev_priv);
611 /*
612 * Fill the dram structure to get the system raw bandwidth and
613 * dram info. This will be used for memory latency calculation.
614 */
615 intel_dram_detect(dev_priv);
616
617 intel_bw_init_hw(dev_priv);
618
619 return 0;
620
621 err_msi:
622 if (pdev->msi_enabled)
623 pci_disable_msi(pdev);
624 err_mem_regions:
625 intel_memory_regions_driver_release(dev_priv);
626 err_ggtt:
627 i915_ggtt_driver_release(dev_priv);
628 err_perf:
629 i915_perf_fini(dev_priv);
630 return ret;
631 }
632
633 /**
634 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
635 * @dev_priv: device private
636 */
i915_driver_hw_remove(struct drm_i915_private * dev_priv)637 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
638 {
639 struct pci_dev *pdev = dev_priv->drm.pdev;
640
641 i915_perf_fini(dev_priv);
642
643 if (pdev->msi_enabled)
644 pci_disable_msi(pdev);
645 }
646
647 /**
648 * i915_driver_register - register the driver with the rest of the system
649 * @dev_priv: device private
650 *
651 * Perform any steps necessary to make the driver available via kernel
652 * internal or userspace interfaces.
653 */
i915_driver_register(struct drm_i915_private * dev_priv)654 static void i915_driver_register(struct drm_i915_private *dev_priv)
655 {
656 struct drm_device *dev = &dev_priv->drm;
657
658 i915_gem_driver_register(dev_priv);
659 i915_pmu_register(dev_priv);
660
661 intel_vgpu_register(dev_priv);
662
663 /* Reveal our presence to userspace */
664 if (drm_dev_register(dev, 0) == 0) {
665 i915_debugfs_register(dev_priv);
666 intel_display_debugfs_register(dev_priv);
667 i915_setup_sysfs(dev_priv);
668
669 /* Depends on sysfs having been initialized */
670 i915_perf_register(dev_priv);
671 } else
672 drm_err(&dev_priv->drm,
673 "Failed to register driver for userspace access!\n");
674
675 if (HAS_DISPLAY(dev_priv)) {
676 /* Must be done after probing outputs */
677 intel_opregion_register(dev_priv);
678 acpi_video_register();
679 }
680
681 intel_gt_driver_register(&dev_priv->gt);
682
683 intel_audio_init(dev_priv);
684
685 /*
686 * Some ports require correctly set-up hpd registers for detection to
687 * work properly (leading to ghost connected connector status), e.g. VGA
688 * on gm45. Hence we can only set up the initial fbdev config after hpd
689 * irqs are fully enabled. We do it last so that the async config
690 * cannot run before the connectors are registered.
691 */
692 intel_fbdev_initial_config_async(dev);
693
694 /*
695 * We need to coordinate the hotplugs with the asynchronous fbdev
696 * configuration, for which we use the fbdev->async_cookie.
697 */
698 if (HAS_DISPLAY(dev_priv))
699 drm_kms_helper_poll_init(dev);
700
701 intel_power_domains_enable(dev_priv);
702 intel_runtime_pm_enable(&dev_priv->runtime_pm);
703
704 intel_register_dsm_handler();
705
706 if (i915_switcheroo_register(dev_priv))
707 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
708 }
709
710 /**
711 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
712 * @dev_priv: device private
713 */
i915_driver_unregister(struct drm_i915_private * dev_priv)714 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
715 {
716 i915_switcheroo_unregister(dev_priv);
717
718 intel_unregister_dsm_handler();
719
720 intel_runtime_pm_disable(&dev_priv->runtime_pm);
721 intel_power_domains_disable(dev_priv);
722
723 intel_fbdev_unregister(dev_priv);
724 intel_audio_deinit(dev_priv);
725
726 /*
727 * After flushing the fbdev (incl. a late async config which will
728 * have delayed queuing of a hotplug event), then flush the hotplug
729 * events.
730 */
731 drm_kms_helper_poll_fini(&dev_priv->drm);
732
733 intel_gt_driver_unregister(&dev_priv->gt);
734 acpi_video_unregister();
735 intel_opregion_unregister(dev_priv);
736
737 i915_perf_unregister(dev_priv);
738 i915_pmu_unregister(dev_priv);
739
740 i915_teardown_sysfs(dev_priv);
741 drm_dev_unplug(&dev_priv->drm);
742
743 i915_gem_driver_unregister(dev_priv);
744 }
745
i915_welcome_messages(struct drm_i915_private * dev_priv)746 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
747 {
748 if (drm_debug_enabled(DRM_UT_DRIVER)) {
749 struct drm_printer p = drm_debug_printer("i915 device info:");
750
751 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
752 INTEL_DEVID(dev_priv),
753 INTEL_REVID(dev_priv),
754 intel_platform_name(INTEL_INFO(dev_priv)->platform),
755 intel_subplatform(RUNTIME_INFO(dev_priv),
756 INTEL_INFO(dev_priv)->platform),
757 INTEL_GEN(dev_priv));
758
759 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
760 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
761 intel_gt_info_print(&dev_priv->gt.info, &p);
762 }
763
764 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
765 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
766 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
767 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
768 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
769 drm_info(&dev_priv->drm,
770 "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
771 }
772
773 static struct drm_i915_private *
i915_driver_create(struct pci_dev * pdev,const struct pci_device_id * ent)774 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
775 {
776 const struct intel_device_info *match_info =
777 (struct intel_device_info *)ent->driver_data;
778 struct intel_device_info *device_info;
779 struct drm_i915_private *i915;
780
781 i915 = devm_drm_dev_alloc(&pdev->dev, &driver,
782 struct drm_i915_private, drm);
783 if (IS_ERR(i915))
784 return i915;
785
786 i915->drm.pdev = pdev;
787 pci_set_drvdata(pdev, i915);
788
789 /* Device parameters start as a copy of module parameters. */
790 i915_params_copy(&i915->params, &i915_modparams);
791
792 /* Setup the write-once "constant" device info */
793 device_info = mkwrite_device_info(i915);
794 memcpy(device_info, match_info, sizeof(*device_info));
795 RUNTIME_INFO(i915)->device_id = pdev->device;
796
797 BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
798
799 return i915;
800 }
801
802 /**
803 * i915_driver_probe - setup chip and create an initial config
804 * @pdev: PCI device
805 * @ent: matching PCI ID entry
806 *
807 * The driver probe routine has to do several things:
808 * - drive output discovery via intel_modeset_init()
809 * - initialize the memory manager
810 * - allocate initial config memory
811 * - setup the DRM framebuffer with the allocated memory
812 */
i915_driver_probe(struct pci_dev * pdev,const struct pci_device_id * ent)813 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
814 {
815 const struct intel_device_info *match_info =
816 (struct intel_device_info *)ent->driver_data;
817 struct drm_i915_private *i915;
818 int ret;
819
820 i915 = i915_driver_create(pdev, ent);
821 if (IS_ERR(i915))
822 return PTR_ERR(i915);
823
824 /* Disable nuclear pageflip by default on pre-ILK */
825 if (!i915->params.nuclear_pageflip && match_info->gen < 5)
826 i915->drm.driver_features &= ~DRIVER_ATOMIC;
827
828 /*
829 * Check if we support fake LMEM -- for now we only unleash this for
830 * the live selftests(test-and-exit).
831 */
832 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
833 if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
834 if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
835 i915->params.fake_lmem_start) {
836 mkwrite_device_info(i915)->memory_regions =
837 REGION_SMEM | REGION_LMEM | REGION_STOLEN;
838 mkwrite_device_info(i915)->is_dgfx = true;
839 GEM_BUG_ON(!HAS_LMEM(i915));
840 GEM_BUG_ON(!IS_DGFX(i915));
841 }
842 }
843 #endif
844
845 ret = pci_enable_device(pdev);
846 if (ret)
847 goto out_fini;
848
849 ret = i915_driver_early_probe(i915);
850 if (ret < 0)
851 goto out_pci_disable;
852
853 disable_rpm_wakeref_asserts(&i915->runtime_pm);
854
855 intel_vgpu_detect(i915);
856
857 ret = i915_driver_mmio_probe(i915);
858 if (ret < 0)
859 goto out_runtime_pm_put;
860
861 ret = i915_driver_hw_probe(i915);
862 if (ret < 0)
863 goto out_cleanup_mmio;
864
865 ret = intel_modeset_init_noirq(i915);
866 if (ret < 0)
867 goto out_cleanup_hw;
868
869 ret = intel_irq_install(i915);
870 if (ret)
871 goto out_cleanup_modeset;
872
873 ret = intel_modeset_init_nogem(i915);
874 if (ret)
875 goto out_cleanup_irq;
876
877 ret = i915_gem_init(i915);
878 if (ret)
879 goto out_cleanup_modeset2;
880
881 ret = intel_modeset_init(i915);
882 if (ret)
883 goto out_cleanup_gem;
884
885 i915_driver_register(i915);
886
887 enable_rpm_wakeref_asserts(&i915->runtime_pm);
888
889 i915_welcome_messages(i915);
890
891 i915->do_release = true;
892
893 return 0;
894
895 out_cleanup_gem:
896 i915_gem_suspend(i915);
897 i915_gem_driver_remove(i915);
898 i915_gem_driver_release(i915);
899 out_cleanup_modeset2:
900 /* FIXME clean up the error path */
901 intel_modeset_driver_remove(i915);
902 intel_irq_uninstall(i915);
903 intel_modeset_driver_remove_noirq(i915);
904 goto out_cleanup_modeset;
905 out_cleanup_irq:
906 intel_irq_uninstall(i915);
907 out_cleanup_modeset:
908 intel_modeset_driver_remove_nogem(i915);
909 out_cleanup_hw:
910 i915_driver_hw_remove(i915);
911 intel_memory_regions_driver_release(i915);
912 i915_ggtt_driver_release(i915);
913 out_cleanup_mmio:
914 i915_driver_mmio_release(i915);
915 out_runtime_pm_put:
916 enable_rpm_wakeref_asserts(&i915->runtime_pm);
917 i915_driver_late_release(i915);
918 out_pci_disable:
919 pci_disable_device(pdev);
920 out_fini:
921 i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
922 return ret;
923 }
924
i915_driver_remove(struct drm_i915_private * i915)925 void i915_driver_remove(struct drm_i915_private *i915)
926 {
927 disable_rpm_wakeref_asserts(&i915->runtime_pm);
928
929 i915_driver_unregister(i915);
930
931 /* Flush any external code that still may be under the RCU lock */
932 synchronize_rcu();
933
934 i915_gem_suspend(i915);
935
936 drm_atomic_helper_shutdown(&i915->drm);
937
938 intel_gvt_driver_remove(i915);
939
940 intel_modeset_driver_remove(i915);
941
942 intel_irq_uninstall(i915);
943
944 intel_modeset_driver_remove_noirq(i915);
945
946 i915_reset_error_state(i915);
947 i915_gem_driver_remove(i915);
948
949 intel_modeset_driver_remove_nogem(i915);
950
951 i915_driver_hw_remove(i915);
952
953 enable_rpm_wakeref_asserts(&i915->runtime_pm);
954 }
955
i915_driver_release(struct drm_device * dev)956 static void i915_driver_release(struct drm_device *dev)
957 {
958 struct drm_i915_private *dev_priv = to_i915(dev);
959 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
960
961 if (!dev_priv->do_release)
962 return;
963
964 disable_rpm_wakeref_asserts(rpm);
965
966 i915_gem_driver_release(dev_priv);
967
968 intel_memory_regions_driver_release(dev_priv);
969 i915_ggtt_driver_release(dev_priv);
970 i915_gem_drain_freed_objects(dev_priv);
971
972 i915_driver_mmio_release(dev_priv);
973
974 enable_rpm_wakeref_asserts(rpm);
975 intel_runtime_pm_driver_release(rpm);
976
977 i915_driver_late_release(dev_priv);
978 }
979
i915_driver_open(struct drm_device * dev,struct drm_file * file)980 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
981 {
982 struct drm_i915_private *i915 = to_i915(dev);
983 int ret;
984
985 ret = i915_gem_open(i915, file);
986 if (ret)
987 return ret;
988
989 return 0;
990 }
991
992 /**
993 * i915_driver_lastclose - clean up after all DRM clients have exited
994 * @dev: DRM device
995 *
996 * Take care of cleaning up after all DRM clients have exited. In the
997 * mode setting case, we want to restore the kernel's initial mode (just
998 * in case the last client left us in a bad state).
999 *
1000 * Additionally, in the non-mode setting case, we'll tear down the GTT
1001 * and DMA structures, since the kernel won't be using them, and clea
1002 * up any GEM state.
1003 */
i915_driver_lastclose(struct drm_device * dev)1004 static void i915_driver_lastclose(struct drm_device *dev)
1005 {
1006 intel_fbdev_restore_mode(dev);
1007 vga_switcheroo_process_delayed_switch();
1008 }
1009
i915_driver_postclose(struct drm_device * dev,struct drm_file * file)1010 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1011 {
1012 struct drm_i915_file_private *file_priv = file->driver_priv;
1013
1014 i915_gem_context_close(file);
1015
1016 kfree_rcu(file_priv, rcu);
1017
1018 /* Catch up with all the deferred frees from "this" client */
1019 i915_gem_flush_free_objects(to_i915(dev));
1020 }
1021
intel_suspend_encoders(struct drm_i915_private * dev_priv)1022 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1023 {
1024 struct drm_device *dev = &dev_priv->drm;
1025 struct intel_encoder *encoder;
1026
1027 drm_modeset_lock_all(dev);
1028 for_each_intel_encoder(dev, encoder)
1029 if (encoder->suspend)
1030 encoder->suspend(encoder);
1031 drm_modeset_unlock_all(dev);
1032 }
1033
suspend_to_idle(struct drm_i915_private * dev_priv)1034 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1035 {
1036 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1037 if (acpi_target_system_state() < ACPI_STATE_S3)
1038 return true;
1039 #endif
1040 return false;
1041 }
1042
i915_drm_prepare(struct drm_device * dev)1043 static int i915_drm_prepare(struct drm_device *dev)
1044 {
1045 struct drm_i915_private *i915 = to_i915(dev);
1046
1047 /*
1048 * NB intel_display_suspend() may issue new requests after we've
1049 * ostensibly marked the GPU as ready-to-sleep here. We need to
1050 * split out that work and pull it forward so that after point,
1051 * the GPU is not woken again.
1052 */
1053 i915_gem_suspend(i915);
1054
1055 return 0;
1056 }
1057
i915_drm_suspend(struct drm_device * dev)1058 static int i915_drm_suspend(struct drm_device *dev)
1059 {
1060 struct drm_i915_private *dev_priv = to_i915(dev);
1061 struct pci_dev *pdev = dev_priv->drm.pdev;
1062 pci_power_t opregion_target_state;
1063
1064 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1065
1066 /* We do a lot of poking in a lot of registers, make sure they work
1067 * properly. */
1068 intel_power_domains_disable(dev_priv);
1069
1070 drm_kms_helper_poll_disable(dev);
1071
1072 pci_save_state(pdev);
1073
1074 intel_display_suspend(dev);
1075
1076 intel_dp_mst_suspend(dev_priv);
1077
1078 intel_runtime_pm_disable_interrupts(dev_priv);
1079 intel_hpd_cancel_work(dev_priv);
1080
1081 intel_suspend_encoders(dev_priv);
1082
1083 intel_suspend_hw(dev_priv);
1084
1085 i915_ggtt_suspend(&dev_priv->ggtt);
1086
1087 i915_save_state(dev_priv);
1088
1089 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1090 intel_opregion_suspend(dev_priv, opregion_target_state);
1091
1092 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1093
1094 dev_priv->suspend_count++;
1095
1096 intel_csr_ucode_suspend(dev_priv);
1097
1098 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1099
1100 return 0;
1101 }
1102
1103 static enum i915_drm_suspend_mode
get_suspend_mode(struct drm_i915_private * dev_priv,bool hibernate)1104 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1105 {
1106 if (hibernate)
1107 return I915_DRM_SUSPEND_HIBERNATE;
1108
1109 if (suspend_to_idle(dev_priv))
1110 return I915_DRM_SUSPEND_IDLE;
1111
1112 return I915_DRM_SUSPEND_MEM;
1113 }
1114
i915_drm_suspend_late(struct drm_device * dev,bool hibernation)1115 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1116 {
1117 struct drm_i915_private *dev_priv = to_i915(dev);
1118 struct pci_dev *pdev = dev_priv->drm.pdev;
1119 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1120 int ret;
1121
1122 disable_rpm_wakeref_asserts(rpm);
1123
1124 i915_gem_suspend_late(dev_priv);
1125
1126 intel_uncore_suspend(&dev_priv->uncore);
1127
1128 intel_power_domains_suspend(dev_priv,
1129 get_suspend_mode(dev_priv, hibernation));
1130
1131 intel_display_power_suspend_late(dev_priv);
1132
1133 ret = vlv_suspend_complete(dev_priv);
1134 if (ret) {
1135 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1136 intel_power_domains_resume(dev_priv);
1137
1138 goto out;
1139 }
1140
1141 pci_disable_device(pdev);
1142 /*
1143 * During hibernation on some platforms the BIOS may try to access
1144 * the device even though it's already in D3 and hang the machine. So
1145 * leave the device in D0 on those platforms and hope the BIOS will
1146 * power down the device properly. The issue was seen on multiple old
1147 * GENs with different BIOS vendors, so having an explicit blacklist
1148 * is inpractical; apply the workaround on everything pre GEN6. The
1149 * platforms where the issue was seen:
1150 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1151 * Fujitsu FSC S7110
1152 * Acer Aspire 1830T
1153 */
1154 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1155 pci_set_power_state(pdev, PCI_D3hot);
1156
1157 out:
1158 enable_rpm_wakeref_asserts(rpm);
1159 if (!dev_priv->uncore.user_forcewake_count)
1160 intel_runtime_pm_driver_release(rpm);
1161
1162 return ret;
1163 }
1164
i915_suspend_switcheroo(struct drm_i915_private * i915,pm_message_t state)1165 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1166 {
1167 int error;
1168
1169 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1170 state.event != PM_EVENT_FREEZE))
1171 return -EINVAL;
1172
1173 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1174 return 0;
1175
1176 error = i915_drm_suspend(&i915->drm);
1177 if (error)
1178 return error;
1179
1180 return i915_drm_suspend_late(&i915->drm, false);
1181 }
1182
i915_drm_resume(struct drm_device * dev)1183 static int i915_drm_resume(struct drm_device *dev)
1184 {
1185 struct drm_i915_private *dev_priv = to_i915(dev);
1186 int ret;
1187
1188 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1189
1190 sanitize_gpu(dev_priv);
1191
1192 ret = i915_ggtt_enable_hw(dev_priv);
1193 if (ret)
1194 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1195
1196 i915_ggtt_resume(&dev_priv->ggtt);
1197
1198 intel_csr_ucode_resume(dev_priv);
1199
1200 i915_restore_state(dev_priv);
1201 intel_pps_unlock_regs_wa(dev_priv);
1202
1203 intel_init_pch_refclk(dev_priv);
1204
1205 /*
1206 * Interrupts have to be enabled before any batches are run. If not the
1207 * GPU will hang. i915_gem_init_hw() will initiate batches to
1208 * update/restore the context.
1209 *
1210 * drm_mode_config_reset() needs AUX interrupts.
1211 *
1212 * Modeset enabling in intel_modeset_init_hw() also needs working
1213 * interrupts.
1214 */
1215 intel_runtime_pm_enable_interrupts(dev_priv);
1216
1217 drm_mode_config_reset(dev);
1218
1219 i915_gem_resume(dev_priv);
1220
1221 intel_modeset_init_hw(dev_priv);
1222 intel_init_clock_gating(dev_priv);
1223
1224 spin_lock_irq(&dev_priv->irq_lock);
1225 if (dev_priv->display.hpd_irq_setup)
1226 dev_priv->display.hpd_irq_setup(dev_priv);
1227 spin_unlock_irq(&dev_priv->irq_lock);
1228
1229 intel_dp_mst_resume(dev_priv);
1230
1231 intel_display_resume(dev);
1232
1233 drm_kms_helper_poll_enable(dev);
1234
1235 /*
1236 * ... but also need to make sure that hotplug processing
1237 * doesn't cause havoc. Like in the driver load code we don't
1238 * bother with the tiny race here where we might lose hotplug
1239 * notifications.
1240 * */
1241 intel_hpd_init(dev_priv);
1242
1243 intel_opregion_resume(dev_priv);
1244
1245 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1246
1247 intel_power_domains_enable(dev_priv);
1248
1249 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1250
1251 return 0;
1252 }
1253
i915_drm_resume_early(struct drm_device * dev)1254 static int i915_drm_resume_early(struct drm_device *dev)
1255 {
1256 struct drm_i915_private *dev_priv = to_i915(dev);
1257 struct pci_dev *pdev = dev_priv->drm.pdev;
1258 int ret;
1259
1260 /*
1261 * We have a resume ordering issue with the snd-hda driver also
1262 * requiring our device to be power up. Due to the lack of a
1263 * parent/child relationship we currently solve this with an early
1264 * resume hook.
1265 *
1266 * FIXME: This should be solved with a special hdmi sink device or
1267 * similar so that power domains can be employed.
1268 */
1269
1270 /*
1271 * Note that we need to set the power state explicitly, since we
1272 * powered off the device during freeze and the PCI core won't power
1273 * it back up for us during thaw. Powering off the device during
1274 * freeze is not a hard requirement though, and during the
1275 * suspend/resume phases the PCI core makes sure we get here with the
1276 * device powered on. So in case we change our freeze logic and keep
1277 * the device powered we can also remove the following set power state
1278 * call.
1279 */
1280 ret = pci_set_power_state(pdev, PCI_D0);
1281 if (ret) {
1282 drm_err(&dev_priv->drm,
1283 "failed to set PCI D0 power state (%d)\n", ret);
1284 return ret;
1285 }
1286
1287 /*
1288 * Note that pci_enable_device() first enables any parent bridge
1289 * device and only then sets the power state for this device. The
1290 * bridge enabling is a nop though, since bridge devices are resumed
1291 * first. The order of enabling power and enabling the device is
1292 * imposed by the PCI core as described above, so here we preserve the
1293 * same order for the freeze/thaw phases.
1294 *
1295 * TODO: eventually we should remove pci_disable_device() /
1296 * pci_enable_enable_device() from suspend/resume. Due to how they
1297 * depend on the device enable refcount we can't anyway depend on them
1298 * disabling/enabling the device.
1299 */
1300 if (pci_enable_device(pdev))
1301 return -EIO;
1302
1303 pci_set_master(pdev);
1304
1305 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1306
1307 ret = vlv_resume_prepare(dev_priv, false);
1308 if (ret)
1309 drm_err(&dev_priv->drm,
1310 "Resume prepare failed: %d, continuing anyway\n", ret);
1311
1312 intel_uncore_resume_early(&dev_priv->uncore);
1313
1314 intel_gt_check_and_clear_faults(&dev_priv->gt);
1315
1316 intel_display_power_resume_early(dev_priv);
1317
1318 intel_power_domains_resume(dev_priv);
1319
1320 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1321
1322 return ret;
1323 }
1324
i915_resume_switcheroo(struct drm_i915_private * i915)1325 int i915_resume_switcheroo(struct drm_i915_private *i915)
1326 {
1327 int ret;
1328
1329 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1330 return 0;
1331
1332 ret = i915_drm_resume_early(&i915->drm);
1333 if (ret)
1334 return ret;
1335
1336 return i915_drm_resume(&i915->drm);
1337 }
1338
i915_pm_prepare(struct device * kdev)1339 static int i915_pm_prepare(struct device *kdev)
1340 {
1341 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1342
1343 if (!i915) {
1344 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1345 return -ENODEV;
1346 }
1347
1348 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1349 return 0;
1350
1351 return i915_drm_prepare(&i915->drm);
1352 }
1353
i915_pm_suspend(struct device * kdev)1354 static int i915_pm_suspend(struct device *kdev)
1355 {
1356 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1357
1358 if (!i915) {
1359 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1360 return -ENODEV;
1361 }
1362
1363 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1364 return 0;
1365
1366 return i915_drm_suspend(&i915->drm);
1367 }
1368
i915_pm_suspend_late(struct device * kdev)1369 static int i915_pm_suspend_late(struct device *kdev)
1370 {
1371 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1372
1373 /*
1374 * We have a suspend ordering issue with the snd-hda driver also
1375 * requiring our device to be power up. Due to the lack of a
1376 * parent/child relationship we currently solve this with an late
1377 * suspend hook.
1378 *
1379 * FIXME: This should be solved with a special hdmi sink device or
1380 * similar so that power domains can be employed.
1381 */
1382 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1383 return 0;
1384
1385 return i915_drm_suspend_late(&i915->drm, false);
1386 }
1387
i915_pm_poweroff_late(struct device * kdev)1388 static int i915_pm_poweroff_late(struct device *kdev)
1389 {
1390 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1391
1392 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1393 return 0;
1394
1395 return i915_drm_suspend_late(&i915->drm, true);
1396 }
1397
i915_pm_resume_early(struct device * kdev)1398 static int i915_pm_resume_early(struct device *kdev)
1399 {
1400 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1401
1402 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1403 return 0;
1404
1405 return i915_drm_resume_early(&i915->drm);
1406 }
1407
i915_pm_resume(struct device * kdev)1408 static int i915_pm_resume(struct device *kdev)
1409 {
1410 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1411
1412 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1413 return 0;
1414
1415 return i915_drm_resume(&i915->drm);
1416 }
1417
1418 /* freeze: before creating the hibernation_image */
i915_pm_freeze(struct device * kdev)1419 static int i915_pm_freeze(struct device *kdev)
1420 {
1421 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1422 int ret;
1423
1424 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1425 ret = i915_drm_suspend(&i915->drm);
1426 if (ret)
1427 return ret;
1428 }
1429
1430 ret = i915_gem_freeze(i915);
1431 if (ret)
1432 return ret;
1433
1434 return 0;
1435 }
1436
i915_pm_freeze_late(struct device * kdev)1437 static int i915_pm_freeze_late(struct device *kdev)
1438 {
1439 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1440 int ret;
1441
1442 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1443 ret = i915_drm_suspend_late(&i915->drm, true);
1444 if (ret)
1445 return ret;
1446 }
1447
1448 ret = i915_gem_freeze_late(i915);
1449 if (ret)
1450 return ret;
1451
1452 return 0;
1453 }
1454
1455 /* thaw: called after creating the hibernation image, but before turning off. */
i915_pm_thaw_early(struct device * kdev)1456 static int i915_pm_thaw_early(struct device *kdev)
1457 {
1458 return i915_pm_resume_early(kdev);
1459 }
1460
i915_pm_thaw(struct device * kdev)1461 static int i915_pm_thaw(struct device *kdev)
1462 {
1463 return i915_pm_resume(kdev);
1464 }
1465
1466 /* restore: called after loading the hibernation image. */
i915_pm_restore_early(struct device * kdev)1467 static int i915_pm_restore_early(struct device *kdev)
1468 {
1469 return i915_pm_resume_early(kdev);
1470 }
1471
i915_pm_restore(struct device * kdev)1472 static int i915_pm_restore(struct device *kdev)
1473 {
1474 return i915_pm_resume(kdev);
1475 }
1476
intel_runtime_suspend(struct device * kdev)1477 static int intel_runtime_suspend(struct device *kdev)
1478 {
1479 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1480 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1481 int ret;
1482
1483 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1484 return -ENODEV;
1485
1486 drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
1487
1488 disable_rpm_wakeref_asserts(rpm);
1489
1490 /*
1491 * We are safe here against re-faults, since the fault handler takes
1492 * an RPM reference.
1493 */
1494 i915_gem_runtime_suspend(dev_priv);
1495
1496 intel_gt_runtime_suspend(&dev_priv->gt);
1497
1498 intel_runtime_pm_disable_interrupts(dev_priv);
1499
1500 intel_uncore_suspend(&dev_priv->uncore);
1501
1502 intel_display_power_suspend(dev_priv);
1503
1504 ret = vlv_suspend_complete(dev_priv);
1505 if (ret) {
1506 drm_err(&dev_priv->drm,
1507 "Runtime suspend failed, disabling it (%d)\n", ret);
1508 intel_uncore_runtime_resume(&dev_priv->uncore);
1509
1510 intel_runtime_pm_enable_interrupts(dev_priv);
1511
1512 intel_gt_runtime_resume(&dev_priv->gt);
1513
1514 enable_rpm_wakeref_asserts(rpm);
1515
1516 return ret;
1517 }
1518
1519 enable_rpm_wakeref_asserts(rpm);
1520 intel_runtime_pm_driver_release(rpm);
1521
1522 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1523 drm_err(&dev_priv->drm,
1524 "Unclaimed access detected prior to suspending\n");
1525
1526 rpm->suspended = true;
1527
1528 /*
1529 * FIXME: We really should find a document that references the arguments
1530 * used below!
1531 */
1532 if (IS_BROADWELL(dev_priv)) {
1533 /*
1534 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1535 * being detected, and the call we do at intel_runtime_resume()
1536 * won't be able to restore them. Since PCI_D3hot matches the
1537 * actual specification and appears to be working, use it.
1538 */
1539 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1540 } else {
1541 /*
1542 * current versions of firmware which depend on this opregion
1543 * notification have repurposed the D1 definition to mean
1544 * "runtime suspended" vs. what you would normally expect (D3)
1545 * to distinguish it from notifications that might be sent via
1546 * the suspend path.
1547 */
1548 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1549 }
1550
1551 assert_forcewakes_inactive(&dev_priv->uncore);
1552
1553 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1554 intel_hpd_poll_init(dev_priv);
1555
1556 drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
1557 return 0;
1558 }
1559
intel_runtime_resume(struct device * kdev)1560 static int intel_runtime_resume(struct device *kdev)
1561 {
1562 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1563 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1564 int ret;
1565
1566 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1567 return -ENODEV;
1568
1569 drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
1570
1571 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1572 disable_rpm_wakeref_asserts(rpm);
1573
1574 intel_opregion_notify_adapter(dev_priv, PCI_D0);
1575 rpm->suspended = false;
1576 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1577 drm_dbg(&dev_priv->drm,
1578 "Unclaimed access during suspend, bios?\n");
1579
1580 intel_display_power_resume(dev_priv);
1581
1582 ret = vlv_resume_prepare(dev_priv, true);
1583
1584 intel_uncore_runtime_resume(&dev_priv->uncore);
1585
1586 intel_runtime_pm_enable_interrupts(dev_priv);
1587
1588 /*
1589 * No point of rolling back things in case of an error, as the best
1590 * we can do is to hope that things will still work (and disable RPM).
1591 */
1592 intel_gt_runtime_resume(&dev_priv->gt);
1593
1594 /*
1595 * On VLV/CHV display interrupts are part of the display
1596 * power well, so hpd is reinitialized from there. For
1597 * everyone else do it here.
1598 */
1599 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1600 intel_hpd_init(dev_priv);
1601
1602 intel_enable_ipc(dev_priv);
1603
1604 enable_rpm_wakeref_asserts(rpm);
1605
1606 if (ret)
1607 drm_err(&dev_priv->drm,
1608 "Runtime resume failed, disabling it (%d)\n", ret);
1609 else
1610 drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
1611
1612 return ret;
1613 }
1614
1615 const struct dev_pm_ops i915_pm_ops = {
1616 /*
1617 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1618 * PMSG_RESUME]
1619 */
1620 .prepare = i915_pm_prepare,
1621 .suspend = i915_pm_suspend,
1622 .suspend_late = i915_pm_suspend_late,
1623 .resume_early = i915_pm_resume_early,
1624 .resume = i915_pm_resume,
1625
1626 /*
1627 * S4 event handlers
1628 * @freeze, @freeze_late : called (1) before creating the
1629 * hibernation image [PMSG_FREEZE] and
1630 * (2) after rebooting, before restoring
1631 * the image [PMSG_QUIESCE]
1632 * @thaw, @thaw_early : called (1) after creating the hibernation
1633 * image, before writing it [PMSG_THAW]
1634 * and (2) after failing to create or
1635 * restore the image [PMSG_RECOVER]
1636 * @poweroff, @poweroff_late: called after writing the hibernation
1637 * image, before rebooting [PMSG_HIBERNATE]
1638 * @restore, @restore_early : called after rebooting and restoring the
1639 * hibernation image [PMSG_RESTORE]
1640 */
1641 .freeze = i915_pm_freeze,
1642 .freeze_late = i915_pm_freeze_late,
1643 .thaw_early = i915_pm_thaw_early,
1644 .thaw = i915_pm_thaw,
1645 .poweroff = i915_pm_suspend,
1646 .poweroff_late = i915_pm_poweroff_late,
1647 .restore_early = i915_pm_restore_early,
1648 .restore = i915_pm_restore,
1649
1650 /* S0ix (via runtime suspend) event handlers */
1651 .runtime_suspend = intel_runtime_suspend,
1652 .runtime_resume = intel_runtime_resume,
1653 };
1654
1655 static const struct file_operations i915_driver_fops = {
1656 .owner = THIS_MODULE,
1657 .open = drm_open,
1658 .release = drm_release_noglobal,
1659 .unlocked_ioctl = drm_ioctl,
1660 .mmap = i915_gem_mmap,
1661 .poll = drm_poll,
1662 .read = drm_read,
1663 .compat_ioctl = i915_ioc32_compat_ioctl,
1664 .llseek = noop_llseek,
1665 };
1666
1667 static int
i915_gem_reject_pin_ioctl(struct drm_device * dev,void * data,struct drm_file * file)1668 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1669 struct drm_file *file)
1670 {
1671 return -ENODEV;
1672 }
1673
1674 static const struct drm_ioctl_desc i915_ioctls[] = {
1675 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1676 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1677 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1678 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1679 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1680 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1681 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1682 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1683 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1684 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1685 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1686 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1687 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1688 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1689 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1690 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1691 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1692 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1693 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
1694 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1695 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1696 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1697 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1698 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1699 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1700 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1701 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1702 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1703 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1704 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1705 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1706 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1707 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1708 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1709 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1710 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1711 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1712 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1713 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1714 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1715 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1716 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1717 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1718 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1719 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1720 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1721 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1722 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1723 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1724 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1725 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1726 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1727 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1728 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1729 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1730 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1731 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1732 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1733 };
1734
1735 static struct drm_driver driver = {
1736 /* Don't use MTRRs here; the Xserver or userspace app should
1737 * deal with them for Intel hardware.
1738 */
1739 .driver_features =
1740 DRIVER_GEM |
1741 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1742 DRIVER_SYNCOBJ_TIMELINE,
1743 .release = i915_driver_release,
1744 .open = i915_driver_open,
1745 .lastclose = i915_driver_lastclose,
1746 .postclose = i915_driver_postclose,
1747
1748 .gem_close_object = i915_gem_close_object,
1749 .gem_free_object_unlocked = i915_gem_free_object,
1750
1751 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1752 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1753 .gem_prime_export = i915_gem_prime_export,
1754 .gem_prime_import = i915_gem_prime_import,
1755
1756 .dumb_create = i915_gem_dumb_create,
1757 .dumb_map_offset = i915_gem_dumb_mmap_offset,
1758
1759 .ioctls = i915_ioctls,
1760 .num_ioctls = ARRAY_SIZE(i915_ioctls),
1761 .fops = &i915_driver_fops,
1762 .name = DRIVER_NAME,
1763 .desc = DRIVER_DESC,
1764 .date = DRIVER_DATE,
1765 .major = DRIVER_MAJOR,
1766 .minor = DRIVER_MINOR,
1767 .patchlevel = DRIVER_PATCHLEVEL,
1768 };
1769