1 /* 2 * Copyright (c) 2022 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 /* 9 * Note: 10 * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, 11 * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that 12 * expected SoC function can be enabled on these IOs. 13 * 14 */ 15 #include "board.h" 16 init_uart_pins(UART_Type * ptr)17void init_uart_pins(UART_Type *ptr) 18 { 19 if (ptr == HPM_UART0) { 20 HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; 21 HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; 22 /* PY port IO needs to configure PIOC */ 23 HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; 24 HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; 25 } else if (ptr == HPM_UART1) { 26 HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_UART1_TXD; 27 HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_UART1_RXD; 28 } else if (ptr == HPM_UART2) { 29 HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_UART2_TXD; 30 HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_UART2_RXD; 31 } 32 } 33 init_i2c_pins_as_gpio(I2C_Type * ptr)34void init_i2c_pins_as_gpio(I2C_Type *ptr) 35 { 36 if (ptr == HPM_I2C0) { 37 /* I2C0 */ 38 HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_GPIO_C_13; 39 HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_GPIO_C_14; 40 } else { 41 while (1) { 42 } 43 } 44 } 45 init_i2c_pins(I2C_Type * ptr)46void init_i2c_pins(I2C_Type *ptr) 47 { 48 if (ptr == HPM_I2C0) { 49 HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_I2C0_SCL 50 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; 51 HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_I2C0_SDA 52 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; 53 HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); 54 HPM_IOC->PAD[IOC_PAD_PC14].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); 55 } else if (ptr == HPM_I2C3) { 56 HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_I2C3_SCL 57 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; 58 HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_I2C3_SDA 59 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; 60 HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); 61 HPM_IOC->PAD[IOC_PAD_PC12].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); 62 } else { 63 while (1) { 64 } 65 } 66 } 67 init_sdram_pins(void)68void init_sdram_pins(void) 69 { 70 HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 71 HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 72 HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 73 HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 74 HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 75 HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 76 HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 77 HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 78 HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 79 HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 80 HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 81 HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 82 HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 83 HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 84 HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 85 HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 86 87 HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 88 HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 89 HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 90 HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 91 HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 92 HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 93 HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 94 HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 95 HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 96 HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 97 HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 98 HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 99 HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 100 HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 101 HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 102 HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 103 104 HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 105 HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 106 HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 107 HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 108 HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 109 HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 110 HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); 111 } 112 init_gpio_pins(void)113void init_gpio_pins(void) 114 { 115 /* configure pad setting: pull enable and pull up, schmitt trigger enable */ 116 /* enable schmitt trigger to eliminate jitter of pin used as button */ 117 uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); 118 119 /* Button */ 120 #ifdef USING_GPIO0_FOR_GPIOZ 121 HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; 122 HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; 123 /* PZ port IO needs to configure BIOC as well */ 124 HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_PZ_02; 125 #endif 126 } 127 init_spi_pins(SPI_Type * ptr)128void init_spi_pins(SPI_Type *ptr) 129 { 130 if (ptr == HPM_SPI3) { 131 HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_SPI3_CSN; 132 HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_SPI3_MOSI; 133 HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_SPI3_MISO; 134 HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); 135 } 136 } 137 init_spi_pins_with_gpio_as_cs(SPI_Type * ptr)138void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) 139 { 140 if (ptr == HPM_SPI3) { 141 HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_GPIO_C_18; 142 HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_SPI3_MOSI; 143 HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_SPI3_MISO; 144 HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); 145 } 146 } 147 init_pins(void)148void init_pins(void) 149 { 150 init_uart_pins(BOARD_CONSOLE_BASE); 151 init_sdram_pins(); 152 } 153 init_gptmr_pins(GPTMR_Type * ptr)154void init_gptmr_pins(GPTMR_Type *ptr) 155 { 156 if (ptr == HPM_GPTMR2) { 157 HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0; 158 HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_GPTMR2_COMP_0; 159 } 160 } 161 init_hall_trgm_pins(void)162void init_hall_trgm_pins(void) 163 { 164 HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_TRGM0_P_06; 165 HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_TRGM0_P_07; 166 HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PB28_FUNC_CTL_TRGM0_P_08; 167 } 168 init_qei_trgm_pins(void)169void init_qei_trgm_pins(void) 170 { 171 HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_TRGM0_P_09; 172 HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_TRGM0_P_10; 173 } 174 init_butn_pins(void)175void init_butn_pins(void) 176 { 177 /* HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; */ 178 /* HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; */ 179 } 180 init_acmp_pins(void)181void init_acmp_pins(void) 182 { 183 /* configure to CMP1_INN5 function */ 184 HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 185 /* configure to ACMP_COMP_1 function */ 186 HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_ACMP_COMP_1; 187 } 188 init_enet_pins(ENET_Type * ptr)189void init_enet_pins(ENET_Type *ptr) 190 { 191 if (ptr == HPM_ENET0) { 192 HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_ETH0_MDC; 193 HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_ETH0_MDIO; 194 195 HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_ETH0_RXD_0; 196 HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_ETH0_RXD_1; 197 HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_ETH0_RXDV; 198 199 HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_ETH0_TXD_0; 200 HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_ETH0_TXD_1; 201 HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_ETH0_TXEN; 202 203 HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PAD_FUNC_CTL_LOOP_BACK_MASK | IOC_PA22_FUNC_CTL_ETH0_REFCLK; 204 } 205 } 206 init_pwm_pins(PWM_Type * ptr)207void init_pwm_pins(PWM_Type *ptr) 208 { 209 if (ptr == HPM_PWM0) { 210 HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_PWM0_P_5; 211 HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_PWM0_P_3; 212 HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PC01_FUNC_CTL_PWM0_P_1; 213 HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_PWM0_P_4; 214 HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_PWM0_P_2; 215 HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_PWM0_P_0; 216 } 217 } 218 init_adc_pins(void)219void init_adc_pins(void) 220 { 221 HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 222 HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 223 HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 224 HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 225 } 226 init_adc_bldc_pins(void)227void init_adc_bldc_pins(void) 228 { 229 HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 230 HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 231 HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 232 } 233 init_usb_pins(void)234void init_usb_pins(void) 235 { 236 HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_GPIO_C_23; 237 HPM_IOC->PAD[IOC_PAD_PC23].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); 238 } 239 init_can_pins(CAN_Type * ptr)240void init_can_pins(CAN_Type *ptr) 241 { 242 if (ptr == HPM_CAN1) { 243 HPM_IOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_CAN1_TXD; 244 HPM_IOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_CAN1_RXD; 245 /* PZ port IO needs to configure BIOC as well */ 246 HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_SOC_PZ_04; 247 HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_SOC_PZ_05; 248 } 249 } 250 init_sdxc_pins(SDXC_Type * ptr,bool use_1v8)251void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) 252 { 253 uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); 254 uint32_t clk_pad_ctl = IOC_PAD_PAD_CTL_DS_SET(7); 255 uint32_t pad_ctl = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); 256 257 /* SDXC0.CLK */ 258 HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = func_ctl; 259 HPM_IOC->PAD[IOC_PAD_PA11].PAD_CTL = clk_pad_ctl; 260 261 /* SDXC0.CMD */ 262 HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = func_ctl; 263 HPM_IOC->PAD[IOC_PAD_PA10].PAD_CTL = pad_ctl; 264 265 /* SDXC0.CD */ 266 HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = func_ctl; 267 HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = pad_ctl; 268 269 /* SDXC0.DATA0 */ 270 HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = func_ctl; 271 HPM_IOC->PAD[IOC_PAD_PA12].PAD_CTL = pad_ctl; 272 /* SDXC0.DATA1 */ 273 HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = func_ctl; 274 HPM_IOC->PAD[IOC_PAD_PA13].PAD_CTL = pad_ctl; 275 /* SDXC0.DATA2 */ 276 HPM_IOC->PAD[IOC_PAD_PA08].FUNC_CTL = func_ctl; 277 HPM_IOC->PAD[IOC_PAD_PA08].PAD_CTL = pad_ctl; 278 /* SDXC0.DATA3 */ 279 HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = func_ctl; 280 HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = pad_ctl; 281 } 282 init_clk_obs_pins(void)283void init_clk_obs_pins(void) 284 { 285 /* HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; */ 286 } 287 init_led_pins(void)288void init_led_pins(void) 289 { 290 /* Pull up */ 291 uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); 292 293 HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_GPIO_A_07; 294 HPM_IOC->PAD[IOC_PAD_PA07].PAD_CTL = pad_ctl; 295 } 296 init_dac_pins(DAC_Type * ptr)297void init_dac_pins(DAC_Type *ptr) 298 { 299 if (ptr == HPM_DAC) { 300 HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 301 } 302 } 303 init_trgmux_pins(uint32_t pin)304void init_trgmux_pins(uint32_t pin) 305 { 306 /* all trgmux pin ALT_SELECT fixed to 16*/ 307 HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16); 308 } 309