1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/export.h>
3 #include <linux/bitops.h>
4 #include <linux/elf.h>
5 #include <linux/mm.h>
6
7 #include <linux/io.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/random.h>
11 #include <linux/topology.h>
12 #include <asm/processor.h>
13 #include <asm/apic.h>
14 #include <asm/cacheinfo.h>
15 #include <asm/cpu.h>
16 #include <asm/spec-ctrl.h>
17 #include <asm/smp.h>
18 #include <asm/numa.h>
19 #include <asm/pci-direct.h>
20 #include <asm/delay.h>
21 #include <asm/debugreg.h>
22 #include <asm/resctrl.h>
23
24 #ifdef CONFIG_X86_64
25 # include <asm/mmconfig.h>
26 # include <asm/set_memory.h>
27 #endif
28
29 #include "cpu.h"
30
31 static const int amd_erratum_383[];
32 static const int amd_erratum_400[];
33 static const int amd_erratum_1054[];
34 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
35
36 /*
37 * nodes_per_socket: Stores the number of nodes per socket.
38 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
39 * Node Identifiers[10:8]
40 */
41 static u32 nodes_per_socket = 1;
42
rdmsrl_amd_safe(unsigned msr,unsigned long long * p)43 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
44 {
45 u32 gprs[8] = { 0 };
46 int err;
47
48 WARN_ONCE((boot_cpu_data.x86 != 0xf),
49 "%s should only be used on K8!\n", __func__);
50
51 gprs[1] = msr;
52 gprs[7] = 0x9c5a203a;
53
54 err = rdmsr_safe_regs(gprs);
55
56 *p = gprs[0] | ((u64)gprs[2] << 32);
57
58 return err;
59 }
60
wrmsrl_amd_safe(unsigned msr,unsigned long long val)61 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
62 {
63 u32 gprs[8] = { 0 };
64
65 WARN_ONCE((boot_cpu_data.x86 != 0xf),
66 "%s should only be used on K8!\n", __func__);
67
68 gprs[0] = (u32)val;
69 gprs[1] = msr;
70 gprs[2] = val >> 32;
71 gprs[7] = 0x9c5a203a;
72
73 return wrmsr_safe_regs(gprs);
74 }
75
76 /*
77 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
78 * misexecution of code under Linux. Owners of such processors should
79 * contact AMD for precise details and a CPU swap.
80 *
81 * See http://www.multimania.com/poulot/k6bug.html
82 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
83 * (Publication # 21266 Issue Date: August 1998)
84 *
85 * The following test is erm.. interesting. AMD neglected to up
86 * the chip setting when fixing the bug but they also tweaked some
87 * performance at the same time..
88 */
89
90 #ifdef CONFIG_X86_32
91 extern __visible void vide(void);
92 __asm__(".text\n"
93 ".globl vide\n"
94 ".type vide, @function\n"
95 ".align 4\n"
96 "vide: ret\n");
97 #endif
98
init_amd_k5(struct cpuinfo_x86 * c)99 static void init_amd_k5(struct cpuinfo_x86 *c)
100 {
101 #ifdef CONFIG_X86_32
102 /*
103 * General Systems BIOSen alias the cpu frequency registers
104 * of the Elan at 0x000df000. Unfortunately, one of the Linux
105 * drivers subsequently pokes it, and changes the CPU speed.
106 * Workaround : Remove the unneeded alias.
107 */
108 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
109 #define CBAR_ENB (0x80000000)
110 #define CBAR_KEY (0X000000CB)
111 if (c->x86_model == 9 || c->x86_model == 10) {
112 if (inl(CBAR) & CBAR_ENB)
113 outl(0 | CBAR_KEY, CBAR);
114 }
115 #endif
116 }
117
init_amd_k6(struct cpuinfo_x86 * c)118 static void init_amd_k6(struct cpuinfo_x86 *c)
119 {
120 #ifdef CONFIG_X86_32
121 u32 l, h;
122 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
123
124 if (c->x86_model < 6) {
125 /* Based on AMD doc 20734R - June 2000 */
126 if (c->x86_model == 0) {
127 clear_cpu_cap(c, X86_FEATURE_APIC);
128 set_cpu_cap(c, X86_FEATURE_PGE);
129 }
130 return;
131 }
132
133 if (c->x86_model == 6 && c->x86_stepping == 1) {
134 const int K6_BUG_LOOP = 1000000;
135 int n;
136 void (*f_vide)(void);
137 u64 d, d2;
138
139 pr_info("AMD K6 stepping B detected - ");
140
141 /*
142 * It looks like AMD fixed the 2.6.2 bug and improved indirect
143 * calls at the same time.
144 */
145
146 n = K6_BUG_LOOP;
147 f_vide = vide;
148 OPTIMIZER_HIDE_VAR(f_vide);
149 d = rdtsc();
150 while (n--)
151 f_vide();
152 d2 = rdtsc();
153 d = d2-d;
154
155 if (d > 20*K6_BUG_LOOP)
156 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
157 else
158 pr_cont("probably OK (after B9730xxxx).\n");
159 }
160
161 /* K6 with old style WHCR */
162 if (c->x86_model < 8 ||
163 (c->x86_model == 8 && c->x86_stepping < 8)) {
164 /* We can only write allocate on the low 508Mb */
165 if (mbytes > 508)
166 mbytes = 508;
167
168 rdmsr(MSR_K6_WHCR, l, h);
169 if ((l&0x0000FFFF) == 0) {
170 unsigned long flags;
171 l = (1<<0)|((mbytes/4)<<1);
172 local_irq_save(flags);
173 wbinvd();
174 wrmsr(MSR_K6_WHCR, l, h);
175 local_irq_restore(flags);
176 pr_info("Enabling old style K6 write allocation for %d Mb\n",
177 mbytes);
178 }
179 return;
180 }
181
182 if ((c->x86_model == 8 && c->x86_stepping > 7) ||
183 c->x86_model == 9 || c->x86_model == 13) {
184 /* The more serious chips .. */
185
186 if (mbytes > 4092)
187 mbytes = 4092;
188
189 rdmsr(MSR_K6_WHCR, l, h);
190 if ((l&0xFFFF0000) == 0) {
191 unsigned long flags;
192 l = ((mbytes>>2)<<22)|(1<<16);
193 local_irq_save(flags);
194 wbinvd();
195 wrmsr(MSR_K6_WHCR, l, h);
196 local_irq_restore(flags);
197 pr_info("Enabling new style K6 write allocation for %d Mb\n",
198 mbytes);
199 }
200
201 return;
202 }
203
204 if (c->x86_model == 10) {
205 /* AMD Geode LX is model 10 */
206 /* placeholder for any needed mods */
207 return;
208 }
209 #endif
210 }
211
init_amd_k7(struct cpuinfo_x86 * c)212 static void init_amd_k7(struct cpuinfo_x86 *c)
213 {
214 #ifdef CONFIG_X86_32
215 u32 l, h;
216
217 /*
218 * Bit 15 of Athlon specific MSR 15, needs to be 0
219 * to enable SSE on Palomino/Morgan/Barton CPU's.
220 * If the BIOS didn't enable it already, enable it here.
221 */
222 if (c->x86_model >= 6 && c->x86_model <= 10) {
223 if (!cpu_has(c, X86_FEATURE_XMM)) {
224 pr_info("Enabling disabled K7/SSE Support.\n");
225 msr_clear_bit(MSR_K7_HWCR, 15);
226 set_cpu_cap(c, X86_FEATURE_XMM);
227 }
228 }
229
230 /*
231 * It's been determined by AMD that Athlons since model 8 stepping 1
232 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
233 * As per AMD technical note 27212 0.2
234 */
235 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
236 rdmsr(MSR_K7_CLK_CTL, l, h);
237 if ((l & 0xfff00000) != 0x20000000) {
238 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
239 l, ((l & 0x000fffff)|0x20000000));
240 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
241 }
242 }
243
244 /* calling is from identify_secondary_cpu() ? */
245 if (!c->cpu_index)
246 return;
247
248 /*
249 * Certain Athlons might work (for various values of 'work') in SMP
250 * but they are not certified as MP capable.
251 */
252 /* Athlon 660/661 is valid. */
253 if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
254 (c->x86_stepping == 1)))
255 return;
256
257 /* Duron 670 is valid */
258 if ((c->x86_model == 7) && (c->x86_stepping == 0))
259 return;
260
261 /*
262 * Athlon 662, Duron 671, and Athlon >model 7 have capability
263 * bit. It's worth noting that the A5 stepping (662) of some
264 * Athlon XP's have the MP bit set.
265 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
266 * more.
267 */
268 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
269 ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
270 (c->x86_model > 7))
271 if (cpu_has(c, X86_FEATURE_MP))
272 return;
273
274 /* If we get here, not a certified SMP capable AMD system. */
275
276 /*
277 * Don't taint if we are running SMP kernel on a single non-MP
278 * approved Athlon
279 */
280 WARN_ONCE(1, "WARNING: This combination of AMD"
281 " processors is not suitable for SMP.\n");
282 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
283 #endif
284 }
285
286 #ifdef CONFIG_NUMA
287 /*
288 * To workaround broken NUMA config. Read the comment in
289 * srat_detect_node().
290 */
nearby_node(int apicid)291 static int nearby_node(int apicid)
292 {
293 int i, node;
294
295 for (i = apicid - 1; i >= 0; i--) {
296 node = __apicid_to_node[i];
297 if (node != NUMA_NO_NODE && node_online(node))
298 return node;
299 }
300 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
301 node = __apicid_to_node[i];
302 if (node != NUMA_NO_NODE && node_online(node))
303 return node;
304 }
305 return first_node(node_online_map); /* Shouldn't happen */
306 }
307 #endif
308
309 /*
310 * Fix up cpu_core_id for pre-F17h systems to be in the
311 * [0 .. cores_per_node - 1] range. Not really needed but
312 * kept so as not to break existing setups.
313 */
legacy_fixup_core_id(struct cpuinfo_x86 * c)314 static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
315 {
316 u32 cus_per_node;
317
318 if (c->x86 >= 0x17)
319 return;
320
321 cus_per_node = c->x86_max_cores / nodes_per_socket;
322 c->cpu_core_id %= cus_per_node;
323 }
324
325 /*
326 * Fixup core topology information for
327 * (1) AMD multi-node processors
328 * Assumption: Number of cores in each internal node is the same.
329 * (2) AMD processors supporting compute units
330 */
amd_get_topology(struct cpuinfo_x86 * c)331 static void amd_get_topology(struct cpuinfo_x86 *c)
332 {
333 int cpu = smp_processor_id();
334
335 /* get information required for multi-node processors */
336 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
337 int err;
338 u32 eax, ebx, ecx, edx;
339
340 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
341
342 c->cpu_die_id = ecx & 0xff;
343
344 if (c->x86 == 0x15)
345 c->cu_id = ebx & 0xff;
346
347 if (c->x86 >= 0x17) {
348 c->cpu_core_id = ebx & 0xff;
349
350 if (smp_num_siblings > 1)
351 c->x86_max_cores /= smp_num_siblings;
352 }
353
354 /*
355 * In case leaf B is available, use it to derive
356 * topology information.
357 */
358 err = detect_extended_topology(c);
359 if (!err)
360 c->x86_coreid_bits = get_count_order(c->x86_max_cores);
361
362 cacheinfo_amd_init_llc_id(c, cpu);
363
364 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
365 u64 value;
366
367 rdmsrl(MSR_FAM10H_NODE_ID, value);
368 c->cpu_die_id = value & 7;
369
370 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
371 } else
372 return;
373
374 if (nodes_per_socket > 1) {
375 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
376 legacy_fixup_core_id(c);
377 }
378 }
379
380 /*
381 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
382 * Assumes number of cores is a power of two.
383 */
amd_detect_cmp(struct cpuinfo_x86 * c)384 static void amd_detect_cmp(struct cpuinfo_x86 *c)
385 {
386 unsigned bits;
387 int cpu = smp_processor_id();
388
389 bits = c->x86_coreid_bits;
390 /* Low order bits define the core id (index of core in socket) */
391 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
392 /* Convert the initial APIC ID into the socket ID */
393 c->phys_proc_id = c->initial_apicid >> bits;
394 /* use socket ID also for last level cache */
395 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;
396 }
397
amd_detect_ppin(struct cpuinfo_x86 * c)398 static void amd_detect_ppin(struct cpuinfo_x86 *c)
399 {
400 unsigned long long val;
401
402 if (!cpu_has(c, X86_FEATURE_AMD_PPIN))
403 return;
404
405 /* When PPIN is defined in CPUID, still need to check PPIN_CTL MSR */
406 if (rdmsrl_safe(MSR_AMD_PPIN_CTL, &val))
407 goto clear_ppin;
408
409 /* PPIN is locked in disabled mode, clear feature bit */
410 if ((val & 3UL) == 1UL)
411 goto clear_ppin;
412
413 /* If PPIN is disabled, try to enable it */
414 if (!(val & 2UL)) {
415 wrmsrl_safe(MSR_AMD_PPIN_CTL, val | 2UL);
416 rdmsrl_safe(MSR_AMD_PPIN_CTL, &val);
417 }
418
419 /* If PPIN_EN bit is 1, return from here; otherwise fall through */
420 if (val & 2UL)
421 return;
422
423 clear_ppin:
424 clear_cpu_cap(c, X86_FEATURE_AMD_PPIN);
425 }
426
amd_get_nb_id(int cpu)427 u16 amd_get_nb_id(int cpu)
428 {
429 return per_cpu(cpu_llc_id, cpu);
430 }
431 EXPORT_SYMBOL_GPL(amd_get_nb_id);
432
amd_get_nodes_per_socket(void)433 u32 amd_get_nodes_per_socket(void)
434 {
435 return nodes_per_socket;
436 }
437 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
438
srat_detect_node(struct cpuinfo_x86 * c)439 static void srat_detect_node(struct cpuinfo_x86 *c)
440 {
441 #ifdef CONFIG_NUMA
442 int cpu = smp_processor_id();
443 int node;
444 unsigned apicid = c->apicid;
445
446 node = numa_cpu_node(cpu);
447 if (node == NUMA_NO_NODE)
448 node = per_cpu(cpu_llc_id, cpu);
449
450 /*
451 * On multi-fabric platform (e.g. Numascale NumaChip) a
452 * platform-specific handler needs to be called to fixup some
453 * IDs of the CPU.
454 */
455 if (x86_cpuinit.fixup_cpu_id)
456 x86_cpuinit.fixup_cpu_id(c, node);
457
458 if (!node_online(node)) {
459 /*
460 * Two possibilities here:
461 *
462 * - The CPU is missing memory and no node was created. In
463 * that case try picking one from a nearby CPU.
464 *
465 * - The APIC IDs differ from the HyperTransport node IDs
466 * which the K8 northbridge parsing fills in. Assume
467 * they are all increased by a constant offset, but in
468 * the same order as the HT nodeids. If that doesn't
469 * result in a usable node fall back to the path for the
470 * previous case.
471 *
472 * This workaround operates directly on the mapping between
473 * APIC ID and NUMA node, assuming certain relationship
474 * between APIC ID, HT node ID and NUMA topology. As going
475 * through CPU mapping may alter the outcome, directly
476 * access __apicid_to_node[].
477 */
478 int ht_nodeid = c->initial_apicid;
479
480 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
481 node = __apicid_to_node[ht_nodeid];
482 /* Pick a nearby node */
483 if (!node_online(node))
484 node = nearby_node(apicid);
485 }
486 numa_set_node(cpu, node);
487 #endif
488 }
489
early_init_amd_mc(struct cpuinfo_x86 * c)490 static void early_init_amd_mc(struct cpuinfo_x86 *c)
491 {
492 #ifdef CONFIG_SMP
493 unsigned bits, ecx;
494
495 /* Multi core CPU? */
496 if (c->extended_cpuid_level < 0x80000008)
497 return;
498
499 ecx = cpuid_ecx(0x80000008);
500
501 c->x86_max_cores = (ecx & 0xff) + 1;
502
503 /* CPU telling us the core id bits shift? */
504 bits = (ecx >> 12) & 0xF;
505
506 /* Otherwise recompute */
507 if (bits == 0) {
508 while ((1 << bits) < c->x86_max_cores)
509 bits++;
510 }
511
512 c->x86_coreid_bits = bits;
513 #endif
514 }
515
bsp_init_amd(struct cpuinfo_x86 * c)516 static void bsp_init_amd(struct cpuinfo_x86 *c)
517 {
518
519 #ifdef CONFIG_X86_64
520 if (c->x86 >= 0xf) {
521 unsigned long long tseg;
522
523 /*
524 * Split up direct mapping around the TSEG SMM area.
525 * Don't do it for gbpages because there seems very little
526 * benefit in doing so.
527 */
528 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
529 unsigned long pfn = tseg >> PAGE_SHIFT;
530
531 pr_debug("tseg: %010llx\n", tseg);
532 if (pfn_range_is_mapped(pfn, pfn + 1))
533 set_memory_4k((unsigned long)__va(tseg), 1);
534 }
535 }
536 #endif
537
538 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
539
540 if (c->x86 > 0x10 ||
541 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
542 u64 val;
543
544 rdmsrl(MSR_K7_HWCR, val);
545 if (!(val & BIT(24)))
546 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
547 }
548 }
549
550 if (c->x86 == 0x15) {
551 unsigned long upperbit;
552 u32 cpuid, assoc;
553
554 cpuid = cpuid_edx(0x80000005);
555 assoc = cpuid >> 16 & 0xff;
556 upperbit = ((cpuid >> 24) << 10) / assoc;
557
558 va_align.mask = (upperbit - 1) & PAGE_MASK;
559 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
560
561 /* A random value per boot for bit slice [12:upper_bit) */
562 va_align.bits = get_random_int() & va_align.mask;
563 }
564
565 if (cpu_has(c, X86_FEATURE_MWAITX))
566 use_mwaitx_delay();
567
568 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
569 u32 ecx;
570
571 ecx = cpuid_ecx(0x8000001e);
572 __max_die_per_package = nodes_per_socket = ((ecx >> 8) & 7) + 1;
573 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
574 u64 value;
575
576 rdmsrl(MSR_FAM10H_NODE_ID, value);
577 __max_die_per_package = nodes_per_socket = ((value >> 3) & 7) + 1;
578 }
579
580 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
581 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
582 c->x86 >= 0x15 && c->x86 <= 0x17) {
583 unsigned int bit;
584
585 switch (c->x86) {
586 case 0x15: bit = 54; break;
587 case 0x16: bit = 33; break;
588 case 0x17: bit = 10; break;
589 default: return;
590 }
591 /*
592 * Try to cache the base value so further operations can
593 * avoid RMW. If that faults, do not enable SSBD.
594 */
595 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
596 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
597 setup_force_cpu_cap(X86_FEATURE_SSBD);
598 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
599 }
600 }
601
602 resctrl_cpu_detect(c);
603 }
604
early_detect_mem_encrypt(struct cpuinfo_x86 * c)605 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
606 {
607 u64 msr;
608
609 /*
610 * BIOS support is required for SME and SEV.
611 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by
612 * the SME physical address space reduction value.
613 * If BIOS has not enabled SME then don't advertise the
614 * SME feature (set in scattered.c).
615 * For SEV: If BIOS has not enabled SEV then don't advertise the
616 * SEV and SEV_ES feature (set in scattered.c).
617 *
618 * In all cases, since support for SME and SEV requires long mode,
619 * don't advertise the feature under CONFIG_X86_32.
620 */
621 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
622 /* Check if memory encryption is enabled */
623 rdmsrl(MSR_K8_SYSCFG, msr);
624 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
625 goto clear_all;
626
627 /*
628 * Always adjust physical address bits. Even though this
629 * will be a value above 32-bits this is still done for
630 * CONFIG_X86_32 so that accurate values are reported.
631 */
632 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
633
634 if (IS_ENABLED(CONFIG_X86_32))
635 goto clear_all;
636
637 rdmsrl(MSR_K7_HWCR, msr);
638 if (!(msr & MSR_K7_HWCR_SMMLOCK))
639 goto clear_sev;
640
641 return;
642
643 clear_all:
644 setup_clear_cpu_cap(X86_FEATURE_SME);
645 clear_sev:
646 setup_clear_cpu_cap(X86_FEATURE_SEV);
647 setup_clear_cpu_cap(X86_FEATURE_SEV_ES);
648 }
649 }
650
early_init_amd(struct cpuinfo_x86 * c)651 static void early_init_amd(struct cpuinfo_x86 *c)
652 {
653 u64 value;
654 u32 dummy;
655
656 early_init_amd_mc(c);
657
658 #ifdef CONFIG_X86_32
659 if (c->x86 == 6)
660 set_cpu_cap(c, X86_FEATURE_K7);
661 #endif
662
663 if (c->x86 >= 0xf)
664 set_cpu_cap(c, X86_FEATURE_K8);
665
666 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
667
668 /*
669 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
670 * with P/T states and does not stop in deep C-states
671 */
672 if (c->x86_power & (1 << 8)) {
673 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
674 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
675 }
676
677 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
678 if (c->x86_power & BIT(12))
679 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
680
681 #ifdef CONFIG_X86_64
682 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
683 #else
684 /* Set MTRR capability flag if appropriate */
685 if (c->x86 == 5)
686 if (c->x86_model == 13 || c->x86_model == 9 ||
687 (c->x86_model == 8 && c->x86_stepping >= 8))
688 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
689 #endif
690 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
691 /*
692 * ApicID can always be treated as an 8-bit value for AMD APIC versions
693 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
694 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
695 * after 16h.
696 */
697 if (boot_cpu_has(X86_FEATURE_APIC)) {
698 if (c->x86 > 0x16)
699 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
700 else if (c->x86 >= 0xf) {
701 /* check CPU config space for extended APIC ID */
702 unsigned int val;
703
704 val = read_pci_config(0, 24, 0, 0x68);
705 if ((val >> 17 & 0x3) == 0x3)
706 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
707 }
708 }
709 #endif
710
711 /*
712 * This is only needed to tell the kernel whether to use VMCALL
713 * and VMMCALL. VMMCALL is never executed except under virt, so
714 * we can set it unconditionally.
715 */
716 set_cpu_cap(c, X86_FEATURE_VMMCALL);
717
718 /* F16h erratum 793, CVE-2013-6885 */
719 if (c->x86 == 0x16 && c->x86_model <= 0xf)
720 msr_set_bit(MSR_AMD64_LS_CFG, 15);
721
722 /*
723 * Check whether the machine is affected by erratum 400. This is
724 * used to select the proper idle routine and to enable the check
725 * whether the machine is affected in arch_post_acpi_init(), which
726 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
727 */
728 if (cpu_has_amd_erratum(c, amd_erratum_400))
729 set_cpu_bug(c, X86_BUG_AMD_E400);
730
731 early_detect_mem_encrypt(c);
732
733 /* Re-enable TopologyExtensions if switched off by BIOS */
734 if (c->x86 == 0x15 &&
735 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) &&
736 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
737
738 if (msr_set_bit(0xc0011005, 54) > 0) {
739 rdmsrl(0xc0011005, value);
740 if (value & BIT_64(54)) {
741 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
742 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
743 }
744 }
745 }
746
747 if (cpu_has(c, X86_FEATURE_TOPOEXT))
748 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
749 }
750
init_amd_k8(struct cpuinfo_x86 * c)751 static void init_amd_k8(struct cpuinfo_x86 *c)
752 {
753 u32 level;
754 u64 value;
755
756 /* On C+ stepping K8 rep microcode works well for copy/memset */
757 level = cpuid_eax(1);
758 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
759 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
760
761 /*
762 * Some BIOSes incorrectly force this feature, but only K8 revision D
763 * (model = 0x14) and later actually support it.
764 * (AMD Erratum #110, docId: 25759).
765 */
766 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
767 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
768 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
769 value &= ~BIT_64(32);
770 wrmsrl_amd_safe(0xc001100d, value);
771 }
772 }
773
774 if (!c->x86_model_id[0])
775 strcpy(c->x86_model_id, "Hammer");
776
777 #ifdef CONFIG_SMP
778 /*
779 * Disable TLB flush filter by setting HWCR.FFDIS on K8
780 * bit 6 of msr C001_0015
781 *
782 * Errata 63 for SH-B3 steppings
783 * Errata 122 for all steppings (F+ have it disabled by default)
784 */
785 msr_set_bit(MSR_K7_HWCR, 6);
786 #endif
787 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
788 }
789
init_amd_gh(struct cpuinfo_x86 * c)790 static void init_amd_gh(struct cpuinfo_x86 *c)
791 {
792 #ifdef CONFIG_MMCONF_FAM10H
793 /* do this for boot cpu */
794 if (c == &boot_cpu_data)
795 check_enable_amd_mmconf_dmi();
796
797 fam10h_check_enable_mmcfg();
798 #endif
799
800 /*
801 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
802 * is always needed when GART is enabled, even in a kernel which has no
803 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
804 * If it doesn't, we do it here as suggested by the BKDG.
805 *
806 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
807 */
808 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
809
810 /*
811 * On family 10h BIOS may not have properly enabled WC+ support, causing
812 * it to be converted to CD memtype. This may result in performance
813 * degradation for certain nested-paging guests. Prevent this conversion
814 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
815 *
816 * NOTE: we want to use the _safe accessors so as not to #GP kvm
817 * guests on older kvm hosts.
818 */
819 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
820
821 if (cpu_has_amd_erratum(c, amd_erratum_383))
822 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
823 }
824
init_amd_ln(struct cpuinfo_x86 * c)825 static void init_amd_ln(struct cpuinfo_x86 *c)
826 {
827 /*
828 * Apply erratum 665 fix unconditionally so machines without a BIOS
829 * fix work.
830 */
831 msr_set_bit(MSR_AMD64_DE_CFG, 31);
832 }
833
834 static bool rdrand_force;
835
rdrand_cmdline(char * str)836 static int __init rdrand_cmdline(char *str)
837 {
838 if (!str)
839 return -EINVAL;
840
841 if (!strcmp(str, "force"))
842 rdrand_force = true;
843 else
844 return -EINVAL;
845
846 return 0;
847 }
848 early_param("rdrand", rdrand_cmdline);
849
clear_rdrand_cpuid_bit(struct cpuinfo_x86 * c)850 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c)
851 {
852 /*
853 * Saving of the MSR used to hide the RDRAND support during
854 * suspend/resume is done by arch/x86/power/cpu.c, which is
855 * dependent on CONFIG_PM_SLEEP.
856 */
857 if (!IS_ENABLED(CONFIG_PM_SLEEP))
858 return;
859
860 /*
861 * The nordrand option can clear X86_FEATURE_RDRAND, so check for
862 * RDRAND support using the CPUID function directly.
863 */
864 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force)
865 return;
866
867 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62);
868
869 /*
870 * Verify that the CPUID change has occurred in case the kernel is
871 * running virtualized and the hypervisor doesn't support the MSR.
872 */
873 if (cpuid_ecx(1) & BIT(30)) {
874 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n");
875 return;
876 }
877
878 clear_cpu_cap(c, X86_FEATURE_RDRAND);
879 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n");
880 }
881
init_amd_jg(struct cpuinfo_x86 * c)882 static void init_amd_jg(struct cpuinfo_x86 *c)
883 {
884 /*
885 * Some BIOS implementations do not restore proper RDRAND support
886 * across suspend and resume. Check on whether to hide the RDRAND
887 * instruction support via CPUID.
888 */
889 clear_rdrand_cpuid_bit(c);
890 }
891
init_amd_bd(struct cpuinfo_x86 * c)892 static void init_amd_bd(struct cpuinfo_x86 *c)
893 {
894 u64 value;
895
896 /*
897 * The way access filter has a performance penalty on some workloads.
898 * Disable it on the affected CPUs.
899 */
900 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
901 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
902 value |= 0x1E;
903 wrmsrl_safe(MSR_F15H_IC_CFG, value);
904 }
905 }
906
907 /*
908 * Some BIOS implementations do not restore proper RDRAND support
909 * across suspend and resume. Check on whether to hide the RDRAND
910 * instruction support via CPUID.
911 */
912 clear_rdrand_cpuid_bit(c);
913 }
914
init_spectral_chicken(struct cpuinfo_x86 * c)915 void init_spectral_chicken(struct cpuinfo_x86 *c)
916 {
917 #ifdef CONFIG_CPU_UNRET_ENTRY
918 u64 value;
919
920 /*
921 * On Zen2 we offer this chicken (bit) on the altar of Speculation.
922 *
923 * This suppresses speculation from the middle of a basic block, i.e. it
924 * suppresses non-branch predictions.
925 *
926 * We use STIBP as a heuristic to filter out Zen2 from the rest of F17H
927 */
928 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_AMD_STIBP)) {
929 if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) {
930 value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT;
931 wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value);
932 }
933 }
934 #endif
935 }
936
init_amd_zn(struct cpuinfo_x86 * c)937 static void init_amd_zn(struct cpuinfo_x86 *c)
938 {
939 set_cpu_cap(c, X86_FEATURE_ZEN);
940
941 #ifdef CONFIG_NUMA
942 node_reclaim_distance = 32;
943 #endif
944
945 /* Fix up CPUID bits, but only if not virtualised. */
946 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
947
948 /* Erratum 1076: CPB feature bit not being set in CPUID. */
949 if (!cpu_has(c, X86_FEATURE_CPB))
950 set_cpu_cap(c, X86_FEATURE_CPB);
951
952 /*
953 * Zen3 (Fam19 model < 0x10) parts are not susceptible to
954 * Branch Type Confusion, but predate the allocation of the
955 * BTC_NO bit.
956 */
957 if (c->x86 == 0x19 && !cpu_has(c, X86_FEATURE_BTC_NO))
958 set_cpu_cap(c, X86_FEATURE_BTC_NO);
959 }
960 }
961
init_amd(struct cpuinfo_x86 * c)962 static void init_amd(struct cpuinfo_x86 *c)
963 {
964 early_init_amd(c);
965
966 /*
967 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
968 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
969 */
970 clear_cpu_cap(c, 0*32+31);
971
972 if (c->x86 >= 0x10)
973 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
974
975 /* get apicid instead of initial apic id from cpuid */
976 c->apicid = hard_smp_processor_id();
977
978 /* K6s reports MCEs but don't actually have all the MSRs */
979 if (c->x86 < 6)
980 clear_cpu_cap(c, X86_FEATURE_MCE);
981
982 switch (c->x86) {
983 case 4: init_amd_k5(c); break;
984 case 5: init_amd_k6(c); break;
985 case 6: init_amd_k7(c); break;
986 case 0xf: init_amd_k8(c); break;
987 case 0x10: init_amd_gh(c); break;
988 case 0x12: init_amd_ln(c); break;
989 case 0x15: init_amd_bd(c); break;
990 case 0x16: init_amd_jg(c); break;
991 case 0x17: init_spectral_chicken(c);
992 fallthrough;
993 case 0x19: init_amd_zn(c); break;
994 }
995
996 /*
997 * Enable workaround for FXSAVE leak on CPUs
998 * without a XSaveErPtr feature
999 */
1000 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))
1001 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
1002
1003 cpu_detect_cache_sizes(c);
1004
1005 amd_detect_cmp(c);
1006 amd_get_topology(c);
1007 srat_detect_node(c);
1008 amd_detect_ppin(c);
1009
1010 init_amd_cacheinfo(c);
1011
1012 if (cpu_has(c, X86_FEATURE_XMM2)) {
1013 /*
1014 * Use LFENCE for execution serialization. On families which
1015 * don't have that MSR, LFENCE is already serializing.
1016 * msr_set_bit() uses the safe accessors, too, even if the MSR
1017 * is not present.
1018 */
1019 msr_set_bit(MSR_AMD64_DE_CFG,
1020 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
1021
1022 /* A serializing LFENCE stops RDTSC speculation */
1023 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
1024 }
1025
1026 /*
1027 * Family 0x12 and above processors have APIC timer
1028 * running in deep C states.
1029 */
1030 if (c->x86 > 0x11)
1031 set_cpu_cap(c, X86_FEATURE_ARAT);
1032
1033 /* 3DNow or LM implies PREFETCHW */
1034 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
1035 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
1036 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
1037
1038 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
1039 if (!cpu_has(c, X86_FEATURE_XENPV))
1040 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
1041
1042 /*
1043 * Turn on the Instructions Retired free counter on machines not
1044 * susceptible to erratum #1054 "Instructions Retired Performance
1045 * Counter May Be Inaccurate".
1046 */
1047 if (cpu_has(c, X86_FEATURE_IRPERF) &&
1048 !cpu_has_amd_erratum(c, amd_erratum_1054))
1049 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
1050
1051 check_null_seg_clears_base(c);
1052 }
1053
1054 #ifdef CONFIG_X86_32
amd_size_cache(struct cpuinfo_x86 * c,unsigned int size)1055 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1056 {
1057 /* AMD errata T13 (order #21922) */
1058 if (c->x86 == 6) {
1059 /* Duron Rev A0 */
1060 if (c->x86_model == 3 && c->x86_stepping == 0)
1061 size = 64;
1062 /* Tbird rev A1/A2 */
1063 if (c->x86_model == 4 &&
1064 (c->x86_stepping == 0 || c->x86_stepping == 1))
1065 size = 256;
1066 }
1067 return size;
1068 }
1069 #endif
1070
cpu_detect_tlb_amd(struct cpuinfo_x86 * c)1071 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
1072 {
1073 u32 ebx, eax, ecx, edx;
1074 u16 mask = 0xfff;
1075
1076 if (c->x86 < 0xf)
1077 return;
1078
1079 if (c->extended_cpuid_level < 0x80000006)
1080 return;
1081
1082 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1083
1084 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
1085 tlb_lli_4k[ENTRIES] = ebx & mask;
1086
1087 /*
1088 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
1089 * characteristics from the CPUID function 0x80000005 instead.
1090 */
1091 if (c->x86 == 0xf) {
1092 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1093 mask = 0xff;
1094 }
1095
1096 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1097 if (!((eax >> 16) & mask))
1098 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
1099 else
1100 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
1101
1102 /* a 4M entry uses two 2M entries */
1103 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
1104
1105 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1106 if (!(eax & mask)) {
1107 /* Erratum 658 */
1108 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
1109 tlb_lli_2m[ENTRIES] = 1024;
1110 } else {
1111 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1112 tlb_lli_2m[ENTRIES] = eax & 0xff;
1113 }
1114 } else
1115 tlb_lli_2m[ENTRIES] = eax & mask;
1116
1117 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
1118 }
1119
1120 static const struct cpu_dev amd_cpu_dev = {
1121 .c_vendor = "AMD",
1122 .c_ident = { "AuthenticAMD" },
1123 #ifdef CONFIG_X86_32
1124 .legacy_models = {
1125 { .family = 4, .model_names =
1126 {
1127 [3] = "486 DX/2",
1128 [7] = "486 DX/2-WB",
1129 [8] = "486 DX/4",
1130 [9] = "486 DX/4-WB",
1131 [14] = "Am5x86-WT",
1132 [15] = "Am5x86-WB"
1133 }
1134 },
1135 },
1136 .legacy_cache_size = amd_size_cache,
1137 #endif
1138 .c_early_init = early_init_amd,
1139 .c_detect_tlb = cpu_detect_tlb_amd,
1140 .c_bsp_init = bsp_init_amd,
1141 .c_init = init_amd,
1142 .c_x86_vendor = X86_VENDOR_AMD,
1143 };
1144
1145 cpu_dev_register(amd_cpu_dev);
1146
1147 /*
1148 * AMD errata checking
1149 *
1150 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
1151 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
1152 * have an OSVW id assigned, which it takes as first argument. Both take a
1153 * variable number of family-specific model-stepping ranges created by
1154 * AMD_MODEL_RANGE().
1155 *
1156 * Example:
1157 *
1158 * const int amd_erratum_319[] =
1159 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
1160 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
1161 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
1162 */
1163
1164 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
1165 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
1166 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1167 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1168 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
1169 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
1170 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
1171
1172 static const int amd_erratum_400[] =
1173 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
1174 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
1175
1176 static const int amd_erratum_383[] =
1177 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
1178
1179 /* #1054: Instructions Retired Performance Counter May Be Inaccurate */
1180 static const int amd_erratum_1054[] =
1181 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
1182
cpu_has_amd_erratum(struct cpuinfo_x86 * cpu,const int * erratum)1183 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
1184 {
1185 int osvw_id = *erratum++;
1186 u32 range;
1187 u32 ms;
1188
1189 if (osvw_id >= 0 && osvw_id < 65536 &&
1190 cpu_has(cpu, X86_FEATURE_OSVW)) {
1191 u64 osvw_len;
1192
1193 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
1194 if (osvw_id < osvw_len) {
1195 u64 osvw_bits;
1196
1197 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
1198 osvw_bits);
1199 return osvw_bits & (1ULL << (osvw_id & 0x3f));
1200 }
1201 }
1202
1203 /* OSVW unavailable or ID unknown, match family-model-stepping range */
1204 ms = (cpu->x86_model << 4) | cpu->x86_stepping;
1205 while ((range = *erratum++))
1206 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
1207 (ms >= AMD_MODEL_RANGE_START(range)) &&
1208 (ms <= AMD_MODEL_RANGE_END(range)))
1209 return true;
1210
1211 return false;
1212 }
1213
set_dr_addr_mask(unsigned long mask,int dr)1214 void set_dr_addr_mask(unsigned long mask, int dr)
1215 {
1216 if (!boot_cpu_has(X86_FEATURE_BPEXT))
1217 return;
1218
1219 switch (dr) {
1220 case 0:
1221 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
1222 break;
1223 case 1:
1224 case 2:
1225 case 3:
1226 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
1227 break;
1228 default:
1229 break;
1230 }
1231 }
1232