1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
24 *
25 */
26
27 #include <linux/gpio/consumer.h>
28 #include <linux/gpio/machine.h>
29 #include <linux/mfd/intel_soc_pmic.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/pinctrl/machine.h>
32 #include <linux/slab.h>
33
34 #include <asm/intel-mid.h>
35 #include <asm/unaligned.h>
36
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_edid.h>
39
40 #include <video/mipi_display.h>
41
42 #include "i915_drv.h"
43 #include "intel_display_types.h"
44 #include "intel_dsi.h"
45 #include "intel_sideband.h"
46
47 #define MIPI_TRANSFER_MODE_SHIFT 0
48 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
49 #define MIPI_PORT_SHIFT 3
50
51 /* base offsets for gpio pads */
52 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
53 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
54 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
55 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
56 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
57 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
58 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
59 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
60 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
61 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100
62 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0
63 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0
64
65 #define VLV_GPIO_PCONF0(base_offset) (base_offset)
66 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8)
67
68 struct gpio_map {
69 u16 base_offset;
70 bool init;
71 };
72
73 static struct gpio_map vlv_gpio_table[] = {
74 { VLV_GPIO_NC_0_HV_DDI0_HPD },
75 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
76 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
77 { VLV_GPIO_NC_3_PANEL0_VDDEN },
78 { VLV_GPIO_NC_4_PANEL0_BKLTEN },
79 { VLV_GPIO_NC_5_PANEL0_BKLTCTL },
80 { VLV_GPIO_NC_6_HV_DDI1_HPD },
81 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
82 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
83 { VLV_GPIO_NC_9_PANEL1_VDDEN },
84 { VLV_GPIO_NC_10_PANEL1_BKLTEN },
85 { VLV_GPIO_NC_11_PANEL1_BKLTCTL },
86 };
87
88 struct i2c_adapter_lookup {
89 u16 slave_addr;
90 struct intel_dsi *intel_dsi;
91 acpi_handle dev_handle;
92 };
93
94 #define CHV_GPIO_IDX_START_N 0
95 #define CHV_GPIO_IDX_START_E 73
96 #define CHV_GPIO_IDX_START_SW 100
97 #define CHV_GPIO_IDX_START_SE 198
98
99 #define CHV_VBT_MAX_PINS_PER_FMLY 15
100
101 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8)
102 #define CHV_GPIO_GPIOEN (1 << 15)
103 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8)
104 #define CHV_GPIO_GPIOCFG_GPO (1 << 8)
105 #define CHV_GPIO_GPIOCFG_GPI (2 << 8)
106 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8)
107 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1)
108
109 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4)
110 #define CHV_GPIO_CFGLOCK (1 << 31)
111
112 /* ICL DSI Display GPIO Pins */
113 #define ICL_GPIO_DDSP_HPD_A 0
114 #define ICL_GPIO_L_VDDEN_1 1
115 #define ICL_GPIO_L_BKLTEN_1 2
116 #define ICL_GPIO_DDPA_CTRLCLK_1 3
117 #define ICL_GPIO_DDPA_CTRLDATA_1 4
118 #define ICL_GPIO_DDSP_HPD_B 5
119 #define ICL_GPIO_L_VDDEN_2 6
120 #define ICL_GPIO_L_BKLTEN_2 7
121 #define ICL_GPIO_DDPA_CTRLCLK_2 8
122 #define ICL_GPIO_DDPA_CTRLDATA_2 9
123
intel_dsi_seq_port_to_port(struct intel_dsi * intel_dsi,u8 seq_port)124 static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi,
125 u8 seq_port)
126 {
127 /*
128 * If single link DSI is being used on any port, the VBT sequence block
129 * send packet apparently always has 0 for the port. Just use the port
130 * we have configured, and ignore the sequence block port.
131 */
132 if (hweight8(intel_dsi->ports) == 1)
133 return ffs(intel_dsi->ports) - 1;
134
135 if (seq_port) {
136 if (intel_dsi->ports & BIT(PORT_B))
137 return PORT_B;
138 else if (intel_dsi->ports & BIT(PORT_C))
139 return PORT_C;
140 }
141
142 return PORT_A;
143 }
144
mipi_exec_send_packet(struct intel_dsi * intel_dsi,const u8 * data)145 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
146 const u8 *data)
147 {
148 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
149 struct mipi_dsi_device *dsi_device;
150 u8 type, flags, seq_port;
151 u16 len;
152 enum port port;
153
154 drm_dbg_kms(&dev_priv->drm, "\n");
155
156 flags = *data++;
157 type = *data++;
158
159 len = *((u16 *) data);
160 data += 2;
161
162 seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
163
164 port = intel_dsi_seq_port_to_port(intel_dsi, seq_port);
165
166 if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port]))
167 goto out;
168
169 dsi_device = intel_dsi->dsi_hosts[port]->device;
170 if (!dsi_device) {
171 drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n",
172 port_name(port));
173 goto out;
174 }
175
176 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
177 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
178 else
179 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
180
181 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
182
183 switch (type) {
184 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
185 mipi_dsi_generic_write(dsi_device, NULL, 0);
186 break;
187 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
188 mipi_dsi_generic_write(dsi_device, data, 1);
189 break;
190 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
191 mipi_dsi_generic_write(dsi_device, data, 2);
192 break;
193 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
194 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
195 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
196 drm_dbg(&dev_priv->drm,
197 "Generic Read not yet implemented or used\n");
198 break;
199 case MIPI_DSI_GENERIC_LONG_WRITE:
200 mipi_dsi_generic_write(dsi_device, data, len);
201 break;
202 case MIPI_DSI_DCS_SHORT_WRITE:
203 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
204 break;
205 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
206 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
207 break;
208 case MIPI_DSI_DCS_READ:
209 drm_dbg(&dev_priv->drm,
210 "DCS Read not yet implemented or used\n");
211 break;
212 case MIPI_DSI_DCS_LONG_WRITE:
213 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
214 break;
215 }
216
217 if (INTEL_GEN(dev_priv) < 11)
218 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
219
220 out:
221 data += len;
222
223 return data;
224 }
225
mipi_exec_delay(struct intel_dsi * intel_dsi,const u8 * data)226 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
227 {
228 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
229 u32 delay = *((const u32 *) data);
230
231 drm_dbg_kms(&i915->drm, "\n");
232
233 usleep_range(delay, delay + 10);
234 data += 4;
235
236 return data;
237 }
238
vlv_exec_gpio(struct drm_i915_private * dev_priv,u8 gpio_source,u8 gpio_index,bool value)239 static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
240 u8 gpio_source, u8 gpio_index, bool value)
241 {
242 struct gpio_map *map;
243 u16 pconf0, padval;
244 u32 tmp;
245 u8 port;
246
247 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
248 drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n",
249 gpio_index);
250 return;
251 }
252
253 map = &vlv_gpio_table[gpio_index];
254
255 if (dev_priv->vbt.dsi.seq_version >= 3) {
256 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
257 port = IOSF_PORT_GPIO_NC;
258 } else {
259 if (gpio_source == 0) {
260 port = IOSF_PORT_GPIO_NC;
261 } else if (gpio_source == 1) {
262 drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n");
263 return;
264 } else {
265 drm_dbg_kms(&dev_priv->drm,
266 "unknown gpio source %u\n", gpio_source);
267 return;
268 }
269 }
270
271 pconf0 = VLV_GPIO_PCONF0(map->base_offset);
272 padval = VLV_GPIO_PAD_VAL(map->base_offset);
273
274 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
275 if (!map->init) {
276 /* FIXME: remove constant below */
277 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
278 map->init = true;
279 }
280
281 tmp = 0x4 | value;
282 vlv_iosf_sb_write(dev_priv, port, padval, tmp);
283 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
284 }
285
chv_exec_gpio(struct drm_i915_private * dev_priv,u8 gpio_source,u8 gpio_index,bool value)286 static void chv_exec_gpio(struct drm_i915_private *dev_priv,
287 u8 gpio_source, u8 gpio_index, bool value)
288 {
289 u16 cfg0, cfg1;
290 u16 family_num;
291 u8 port;
292
293 if (dev_priv->vbt.dsi.seq_version >= 3) {
294 if (gpio_index >= CHV_GPIO_IDX_START_SE) {
295 /* XXX: it's unclear whether 255->57 is part of SE. */
296 gpio_index -= CHV_GPIO_IDX_START_SE;
297 port = CHV_IOSF_PORT_GPIO_SE;
298 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
299 gpio_index -= CHV_GPIO_IDX_START_SW;
300 port = CHV_IOSF_PORT_GPIO_SW;
301 } else if (gpio_index >= CHV_GPIO_IDX_START_E) {
302 gpio_index -= CHV_GPIO_IDX_START_E;
303 port = CHV_IOSF_PORT_GPIO_E;
304 } else {
305 port = CHV_IOSF_PORT_GPIO_N;
306 }
307 } else {
308 /* XXX: The spec is unclear about CHV GPIO on seq v2 */
309 if (gpio_source != 0) {
310 drm_dbg_kms(&dev_priv->drm,
311 "unknown gpio source %u\n", gpio_source);
312 return;
313 }
314
315 if (gpio_index >= CHV_GPIO_IDX_START_E) {
316 drm_dbg_kms(&dev_priv->drm,
317 "invalid gpio index %u for GPIO N\n",
318 gpio_index);
319 return;
320 }
321
322 port = CHV_IOSF_PORT_GPIO_N;
323 }
324
325 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
326 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
327
328 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
329 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
330
331 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
332 vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
333 vlv_iosf_sb_write(dev_priv, port, cfg0,
334 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
335 CHV_GPIO_GPIOTXSTATE(value));
336 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
337 }
338
bxt_exec_gpio(struct drm_i915_private * dev_priv,u8 gpio_source,u8 gpio_index,bool value)339 static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
340 u8 gpio_source, u8 gpio_index, bool value)
341 {
342 /* XXX: this table is a quick ugly hack. */
343 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
344 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
345
346 if (!gpio_desc) {
347 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
348 NULL, gpio_index,
349 value ? GPIOD_OUT_LOW :
350 GPIOD_OUT_HIGH);
351
352 if (IS_ERR_OR_NULL(gpio_desc)) {
353 drm_err(&dev_priv->drm,
354 "GPIO index %u request failed (%ld)\n",
355 gpio_index, PTR_ERR(gpio_desc));
356 return;
357 }
358
359 bxt_gpio_table[gpio_index] = gpio_desc;
360 }
361
362 gpiod_set_value(gpio_desc, value);
363 }
364
icl_exec_gpio(struct drm_i915_private * dev_priv,u8 gpio_source,u8 gpio_index,bool value)365 static void icl_exec_gpio(struct drm_i915_private *dev_priv,
366 u8 gpio_source, u8 gpio_index, bool value)
367 {
368 drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
369 }
370
mipi_exec_gpio(struct intel_dsi * intel_dsi,const u8 * data)371 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
372 {
373 struct drm_device *dev = intel_dsi->base.base.dev;
374 struct drm_i915_private *dev_priv = to_i915(dev);
375 u8 gpio_source, gpio_index = 0, gpio_number;
376 bool value;
377
378 drm_dbg_kms(&dev_priv->drm, "\n");
379
380 if (dev_priv->vbt.dsi.seq_version >= 3)
381 gpio_index = *data++;
382
383 gpio_number = *data++;
384
385 /* gpio source in sequence v2 only */
386 if (dev_priv->vbt.dsi.seq_version == 2)
387 gpio_source = (*data >> 1) & 3;
388 else
389 gpio_source = 0;
390
391 /* pull up/down */
392 value = *data++ & 1;
393
394 if (INTEL_GEN(dev_priv) >= 11)
395 icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
396 else if (IS_VALLEYVIEW(dev_priv))
397 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
398 else if (IS_CHERRYVIEW(dev_priv))
399 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
400 else
401 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value);
402
403 return data;
404 }
405
406 #ifdef CONFIG_ACPI
i2c_adapter_lookup(struct acpi_resource * ares,void * data)407 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data)
408 {
409 struct i2c_adapter_lookup *lookup = data;
410 struct intel_dsi *intel_dsi = lookup->intel_dsi;
411 struct acpi_resource_i2c_serialbus *sb;
412 struct i2c_adapter *adapter;
413 acpi_handle adapter_handle;
414 acpi_status status;
415
416 if (!i2c_acpi_get_i2c_resource(ares, &sb))
417 return 1;
418
419 if (lookup->slave_addr != sb->slave_address)
420 return 1;
421
422 status = acpi_get_handle(lookup->dev_handle,
423 sb->resource_source.string_ptr,
424 &adapter_handle);
425 if (ACPI_FAILURE(status))
426 return 1;
427
428 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle);
429 if (adapter)
430 intel_dsi->i2c_bus_num = adapter->nr;
431
432 return 1;
433 }
434
i2c_acpi_find_adapter(struct intel_dsi * intel_dsi,const u16 slave_addr)435 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
436 const u16 slave_addr)
437 {
438 struct drm_device *drm_dev = intel_dsi->base.base.dev;
439 struct device *dev = &drm_dev->pdev->dev;
440 struct acpi_device *acpi_dev;
441 struct list_head resource_list;
442 struct i2c_adapter_lookup lookup;
443
444 acpi_dev = ACPI_COMPANION(dev);
445 if (acpi_dev) {
446 memset(&lookup, 0, sizeof(lookup));
447 lookup.slave_addr = slave_addr;
448 lookup.intel_dsi = intel_dsi;
449 lookup.dev_handle = acpi_device_handle(acpi_dev);
450
451 INIT_LIST_HEAD(&resource_list);
452 acpi_dev_get_resources(acpi_dev, &resource_list,
453 i2c_adapter_lookup,
454 &lookup);
455 acpi_dev_free_resource_list(&resource_list);
456 }
457 }
458 #else
i2c_acpi_find_adapter(struct intel_dsi * intel_dsi,const u16 slave_addr)459 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
460 const u16 slave_addr)
461 {
462 }
463 #endif
464
mipi_exec_i2c(struct intel_dsi * intel_dsi,const u8 * data)465 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
466 {
467 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
468 struct i2c_adapter *adapter;
469 struct i2c_msg msg;
470 int ret;
471 u8 vbt_i2c_bus_num = *(data + 2);
472 u16 slave_addr = *(u16 *)(data + 3);
473 u8 reg_offset = *(data + 5);
474 u8 payload_size = *(data + 6);
475 u8 *payload_data;
476
477 if (intel_dsi->i2c_bus_num < 0) {
478 intel_dsi->i2c_bus_num = vbt_i2c_bus_num;
479 i2c_acpi_find_adapter(intel_dsi, slave_addr);
480 }
481
482 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num);
483 if (!adapter) {
484 drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n");
485 goto err_bus;
486 }
487
488 payload_data = kzalloc(payload_size + 1, GFP_KERNEL);
489 if (!payload_data)
490 goto err_alloc;
491
492 payload_data[0] = reg_offset;
493 memcpy(&payload_data[1], (data + 7), payload_size);
494
495 msg.addr = slave_addr;
496 msg.flags = 0;
497 msg.len = payload_size + 1;
498 msg.buf = payload_data;
499
500 ret = i2c_transfer(adapter, &msg, 1);
501 if (ret < 0)
502 drm_err(&i915->drm,
503 "Failed to xfer payload of size (%u) to reg (%u)\n",
504 payload_size, reg_offset);
505
506 kfree(payload_data);
507 err_alloc:
508 i2c_put_adapter(adapter);
509 err_bus:
510 return data + payload_size + 7;
511 }
512
mipi_exec_spi(struct intel_dsi * intel_dsi,const u8 * data)513 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
514 {
515 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
516
517 drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n");
518
519 return data + *(data + 5) + 6;
520 }
521
mipi_exec_pmic(struct intel_dsi * intel_dsi,const u8 * data)522 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
523 {
524 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
525 #ifdef CONFIG_PMIC_OPREGION
526 u32 value, mask, reg_address;
527 u16 i2c_address;
528 int ret;
529
530 /* byte 0 aka PMIC Flag is reserved */
531 i2c_address = get_unaligned_le16(data + 1);
532 reg_address = get_unaligned_le32(data + 3);
533 value = get_unaligned_le32(data + 7);
534 mask = get_unaligned_le32(data + 11);
535
536 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address,
537 reg_address,
538 value, mask);
539 if (ret)
540 drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret);
541 #else
542 drm_err(&i915->drm,
543 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n");
544 #endif
545
546 return data + 15;
547 }
548
549 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
550 const u8 *data);
551 static const fn_mipi_elem_exec exec_elem[] = {
552 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
553 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
554 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
555 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
556 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
557 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
558 };
559
560 /*
561 * MIPI Sequence from VBT #53 parsing logic
562 * We have already separated each seqence during bios parsing
563 * Following is generic execution function for any sequence
564 */
565
566 static const char * const seq_name[] = {
567 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
568 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
569 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
570 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF",
571 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
572 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
573 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
574 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
575 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
576 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
577 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
578 };
579
sequence_name(enum mipi_seq seq_id)580 static const char *sequence_name(enum mipi_seq seq_id)
581 {
582 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
583 return seq_name[seq_id];
584 else
585 return "(unknown)";
586 }
587
intel_dsi_vbt_exec(struct intel_dsi * intel_dsi,enum mipi_seq seq_id)588 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
589 enum mipi_seq seq_id)
590 {
591 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
592 const u8 *data;
593 fn_mipi_elem_exec mipi_elem_exec;
594
595 if (drm_WARN_ON(&dev_priv->drm,
596 seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence)))
597 return;
598
599 data = dev_priv->vbt.dsi.sequence[seq_id];
600 if (!data)
601 return;
602
603 drm_WARN_ON(&dev_priv->drm, *data != seq_id);
604
605 drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n",
606 seq_id, sequence_name(seq_id));
607
608 /* Skip Sequence Byte. */
609 data++;
610
611 /* Skip Size of Sequence. */
612 if (dev_priv->vbt.dsi.seq_version >= 3)
613 data += 4;
614
615 while (1) {
616 u8 operation_byte = *data++;
617 u8 operation_size = 0;
618
619 if (operation_byte == MIPI_SEQ_ELEM_END)
620 break;
621
622 if (operation_byte < ARRAY_SIZE(exec_elem))
623 mipi_elem_exec = exec_elem[operation_byte];
624 else
625 mipi_elem_exec = NULL;
626
627 /* Size of Operation. */
628 if (dev_priv->vbt.dsi.seq_version >= 3)
629 operation_size = *data++;
630
631 if (mipi_elem_exec) {
632 const u8 *next = data + operation_size;
633
634 data = mipi_elem_exec(intel_dsi, data);
635
636 /* Consistency check if we have size. */
637 if (operation_size && data != next) {
638 drm_err(&dev_priv->drm,
639 "Inconsistent operation size\n");
640 return;
641 }
642 } else if (operation_size) {
643 /* We have size, skip. */
644 drm_dbg_kms(&dev_priv->drm,
645 "Unsupported MIPI operation byte %u\n",
646 operation_byte);
647 data += operation_size;
648 } else {
649 /* No size, can't skip without parsing. */
650 drm_err(&dev_priv->drm,
651 "Unsupported MIPI operation byte %u\n",
652 operation_byte);
653 return;
654 }
655 }
656 }
657
intel_dsi_vbt_exec_sequence(struct intel_dsi * intel_dsi,enum mipi_seq seq_id)658 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
659 enum mipi_seq seq_id)
660 {
661 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel)
662 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
663 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight)
664 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1);
665
666 intel_dsi_vbt_exec(intel_dsi, seq_id);
667
668 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel)
669 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
670 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight)
671 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0);
672 }
673
intel_dsi_msleep(struct intel_dsi * intel_dsi,int msec)674 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
675 {
676 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
677
678 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
679 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
680 return;
681
682 msleep(msec);
683 }
684
intel_dsi_log_params(struct intel_dsi * intel_dsi)685 void intel_dsi_log_params(struct intel_dsi *intel_dsi)
686 {
687 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
688
689 drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk);
690 drm_dbg_kms(&i915->drm, "Pixel overlap %d\n",
691 intel_dsi->pixel_overlap);
692 drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count);
693 drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
694 drm_dbg_kms(&i915->drm, "Video mode format %s\n",
695 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ?
696 "non-burst with sync pulse" :
697 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ?
698 "non-burst with sync events" :
699 intel_dsi->video_mode_format == VIDEO_MODE_BURST ?
700 "burst" : "<unknown>");
701 drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n",
702 intel_dsi->burst_mode_ratio);
703 drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val);
704 drm_dbg_kms(&i915->drm, "Eot %s\n",
705 enableddisabled(intel_dsi->eotp_pkt));
706 drm_dbg_kms(&i915->drm, "Clockstop %s\n",
707 enableddisabled(!intel_dsi->clock_stop));
708 drm_dbg_kms(&i915->drm, "Mode %s\n",
709 intel_dsi->operation_mode ? "command" : "video");
710 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
711 drm_dbg_kms(&i915->drm,
712 "Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
713 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
714 drm_dbg_kms(&i915->drm,
715 "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
716 else
717 drm_dbg_kms(&i915->drm, "Dual link: NONE\n");
718 drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format);
719 drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div);
720 drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n",
721 intel_dsi->lp_rx_timeout);
722 drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n",
723 intel_dsi->turn_arnd_val);
724 drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count);
725 drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n",
726 intel_dsi->hs_to_lp_count);
727 drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
728 drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
729 drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n",
730 intel_dsi->clk_lp_to_hs_count);
731 drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n",
732 intel_dsi->clk_hs_to_lp_count);
733 drm_dbg_kms(&i915->drm, "BTA %s\n",
734 enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
735 }
736
intel_dsi_vbt_init(struct intel_dsi * intel_dsi,u16 panel_id)737 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
738 {
739 struct drm_device *dev = intel_dsi->base.base.dev;
740 struct drm_i915_private *dev_priv = to_i915(dev);
741 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
742 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
743 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
744 u16 burst_mode_ratio;
745 enum port port;
746
747 drm_dbg_kms(&dev_priv->drm, "\n");
748
749 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
750 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
751 intel_dsi->lane_count = mipi_config->lane_cnt + 1;
752 intel_dsi->pixel_format =
753 pixel_format_from_register_bits(
754 mipi_config->videomode_color_format << 7);
755
756 intel_dsi->dual_link = mipi_config->dual_link;
757 intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
758 intel_dsi->operation_mode = mipi_config->is_cmd_mode;
759 intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
760 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
761 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
762 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
763 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
764 intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
765 intel_dsi->init_count = mipi_config->master_init_timer;
766 intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
767 intel_dsi->video_frmt_cfg_bits =
768 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
769 intel_dsi->bgr_enabled = mipi_config->rgb_flip;
770
771 /* Starting point, adjusted depending on dual link and burst mode */
772 intel_dsi->pclk = mode->clock;
773
774 /* In dual link mode each port needs half of pixel clock */
775 if (intel_dsi->dual_link) {
776 intel_dsi->pclk /= 2;
777
778 /* we can enable pixel_overlap if needed by panel. In this
779 * case we need to increase the pixelclock for extra pixels
780 */
781 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
782 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
783 }
784 }
785
786 /* Burst Mode Ratio
787 * Target ddr frequency from VBT / non burst ddr freq
788 * multiply by 100 to preserve remainder
789 */
790 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
791 if (mipi_config->target_burst_mode_freq) {
792 u32 bitrate = intel_dsi_bitrate(intel_dsi);
793
794 /*
795 * Sometimes the VBT contains a slightly lower clock,
796 * then the bitrate we have calculated, in this case
797 * just replace it with the calculated bitrate.
798 */
799 if (mipi_config->target_burst_mode_freq < bitrate &&
800 intel_fuzzy_clock_check(
801 mipi_config->target_burst_mode_freq,
802 bitrate))
803 mipi_config->target_burst_mode_freq = bitrate;
804
805 if (mipi_config->target_burst_mode_freq < bitrate) {
806 drm_err(&dev_priv->drm,
807 "Burst mode freq is less than computed\n");
808 return false;
809 }
810
811 burst_mode_ratio = DIV_ROUND_UP(
812 mipi_config->target_burst_mode_freq * 100,
813 bitrate);
814
815 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
816 } else {
817 drm_err(&dev_priv->drm,
818 "Burst mode target is not set\n");
819 return false;
820 }
821 } else
822 burst_mode_ratio = 100;
823
824 intel_dsi->burst_mode_ratio = burst_mode_ratio;
825
826 /* delays in VBT are in unit of 100us, so need to convert
827 * here in ms
828 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
829 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
830 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
831 intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
832 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
833 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
834
835 intel_dsi->i2c_bus_num = -1;
836
837 /* a regular driver would get the device in probe */
838 for_each_dsi_port(port, intel_dsi->ports) {
839 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
840 }
841
842 return true;
843 }
844
845 /*
846 * On some BYT/CHT devs some sequences are incomplete and we need to manually
847 * control some GPIOs. We need to add a GPIO lookup table before we get these.
848 * If the GOP did not initialize the panel (HDMI inserted) we may need to also
849 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM.
850 */
851 static struct gpiod_lookup_table pmic_panel_gpio_table = {
852 /* Intel GFX is consumer */
853 .dev_id = "0000:00:02.0",
854 .table = {
855 /* Panel EN/DISABLE */
856 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH),
857 { }
858 },
859 };
860
861 static struct gpiod_lookup_table soc_panel_gpio_table = {
862 .dev_id = "0000:00:02.0",
863 .table = {
864 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH),
865 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH),
866 { }
867 },
868 };
869
870 static const struct pinctrl_map soc_pwm_pinctrl_map[] = {
871 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00",
872 "pwm0_grp", "pwm"),
873 };
874
intel_dsi_vbt_gpio_init(struct intel_dsi * intel_dsi,bool panel_is_on)875 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)
876 {
877 struct drm_device *dev = intel_dsi->base.base.dev;
878 struct drm_i915_private *dev_priv = to_i915(dev);
879 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
880 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
881 bool want_backlight_gpio = false;
882 bool want_panel_gpio = false;
883 struct pinctrl *pinctrl;
884 int ret;
885
886 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
887 mipi_config->pwm_blc == PPS_BLC_PMIC) {
888 gpiod_add_lookup_table(&pmic_panel_gpio_table);
889 want_panel_gpio = true;
890 }
891
892 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
893 gpiod_add_lookup_table(&soc_panel_gpio_table);
894 want_panel_gpio = true;
895 want_backlight_gpio = true;
896
897 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */
898 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map,
899 ARRAY_SIZE(soc_pwm_pinctrl_map));
900 if (ret)
901 drm_err(&dev_priv->drm,
902 "Failed to register pwm0 pinmux mapping\n");
903
904 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0");
905 if (IS_ERR(pinctrl))
906 drm_err(&dev_priv->drm,
907 "Failed to set pinmux to PWM\n");
908 }
909
910 if (want_panel_gpio) {
911 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags);
912 if (IS_ERR(intel_dsi->gpio_panel)) {
913 drm_err(&dev_priv->drm,
914 "Failed to own gpio for panel control\n");
915 intel_dsi->gpio_panel = NULL;
916 }
917 }
918
919 if (want_backlight_gpio) {
920 intel_dsi->gpio_backlight =
921 gpiod_get(dev->dev, "backlight", flags);
922 if (IS_ERR(intel_dsi->gpio_backlight)) {
923 drm_err(&dev_priv->drm,
924 "Failed to own gpio for backlight control\n");
925 intel_dsi->gpio_backlight = NULL;
926 }
927 }
928 }
929
intel_dsi_vbt_gpio_cleanup(struct intel_dsi * intel_dsi)930 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi)
931 {
932 struct drm_device *dev = intel_dsi->base.base.dev;
933 struct drm_i915_private *dev_priv = to_i915(dev);
934 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
935
936 if (intel_dsi->gpio_panel) {
937 gpiod_put(intel_dsi->gpio_panel);
938 intel_dsi->gpio_panel = NULL;
939 }
940
941 if (intel_dsi->gpio_backlight) {
942 gpiod_put(intel_dsi->gpio_backlight);
943 intel_dsi->gpio_backlight = NULL;
944 }
945
946 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
947 mipi_config->pwm_blc == PPS_BLC_PMIC)
948 gpiod_remove_lookup_table(&pmic_panel_gpio_table);
949
950 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
951 pinctrl_unregister_mappings(soc_pwm_pinctrl_map);
952 gpiod_remove_lookup_table(&soc_panel_gpio_table);
953 }
954 }
955