1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <linux/pm_runtime.h>
25 #include <asm/iosf_mbi.h>
26
27 #include "i915_drv.h"
28 #include "i915_trace.h"
29 #include "i915_vgpu.h"
30 #include "intel_pm.h"
31
32 #define FORCEWAKE_ACK_TIMEOUT_MS 50
33 #define GT_FIFO_TIMEOUT_MS 10
34
35 #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
36
37 void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug * mmio_debug)38 intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
39 {
40 spin_lock_init(&mmio_debug->lock);
41 mmio_debug->unclaimed_mmio_check = 1;
42 }
43
mmio_debug_suspend(struct intel_uncore_mmio_debug * mmio_debug)44 static void mmio_debug_suspend(struct intel_uncore_mmio_debug *mmio_debug)
45 {
46 lockdep_assert_held(&mmio_debug->lock);
47
48 /* Save and disable mmio debugging for the user bypass */
49 if (!mmio_debug->suspend_count++) {
50 mmio_debug->saved_mmio_check = mmio_debug->unclaimed_mmio_check;
51 mmio_debug->unclaimed_mmio_check = 0;
52 }
53 }
54
mmio_debug_resume(struct intel_uncore_mmio_debug * mmio_debug)55 static void mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug)
56 {
57 lockdep_assert_held(&mmio_debug->lock);
58
59 if (!--mmio_debug->suspend_count)
60 mmio_debug->unclaimed_mmio_check = mmio_debug->saved_mmio_check;
61 }
62
63 static const char * const forcewake_domain_names[] = {
64 "render",
65 "blitter",
66 "media",
67 "vdbox0",
68 "vdbox1",
69 "vdbox2",
70 "vdbox3",
71 "vebox0",
72 "vebox1",
73 };
74
75 const char *
intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)76 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
77 {
78 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
79
80 if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
81 return forcewake_domain_names[id];
82
83 WARN_ON(id);
84
85 return "unknown";
86 }
87
88 #define fw_ack(d) readl((d)->reg_ack)
89 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
90 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
91
92 static inline void
fw_domain_reset(const struct intel_uncore_forcewake_domain * d)93 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
94 {
95 /*
96 * We don't really know if the powerwell for the forcewake domain we are
97 * trying to reset here does exist at this point (engines could be fused
98 * off in ICL+), so no waiting for acks
99 */
100 /* WaRsClearFWBitsAtReset:bdw,skl */
101 fw_clear(d, 0xffff);
102 }
103
104 static inline void
fw_domain_arm_timer(struct intel_uncore_forcewake_domain * d)105 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
106 {
107 GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask);
108 d->uncore->fw_domains_timer |= d->mask;
109 d->wake_count++;
110 hrtimer_start_range_ns(&d->timer,
111 NSEC_PER_MSEC,
112 NSEC_PER_MSEC,
113 HRTIMER_MODE_REL);
114 }
115
116 static inline int
__wait_for_ack(const struct intel_uncore_forcewake_domain * d,const u32 ack,const u32 value)117 __wait_for_ack(const struct intel_uncore_forcewake_domain *d,
118 const u32 ack,
119 const u32 value)
120 {
121 return wait_for_atomic((fw_ack(d) & ack) == value,
122 FORCEWAKE_ACK_TIMEOUT_MS);
123 }
124
125 static inline int
wait_ack_clear(const struct intel_uncore_forcewake_domain * d,const u32 ack)126 wait_ack_clear(const struct intel_uncore_forcewake_domain *d,
127 const u32 ack)
128 {
129 return __wait_for_ack(d, ack, 0);
130 }
131
132 static inline int
wait_ack_set(const struct intel_uncore_forcewake_domain * d,const u32 ack)133 wait_ack_set(const struct intel_uncore_forcewake_domain *d,
134 const u32 ack)
135 {
136 return __wait_for_ack(d, ack, ack);
137 }
138
139 static inline void
fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain * d)140 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
141 {
142 if (wait_ack_clear(d, FORCEWAKE_KERNEL)) {
143 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
144 intel_uncore_forcewake_domain_to_str(d->id));
145 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */
146 }
147 }
148
149 enum ack_type {
150 ACK_CLEAR = 0,
151 ACK_SET
152 };
153
154 static int
fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain * d,const enum ack_type type)155 fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
156 const enum ack_type type)
157 {
158 const u32 ack_bit = FORCEWAKE_KERNEL;
159 const u32 value = type == ACK_SET ? ack_bit : 0;
160 unsigned int pass;
161 bool ack_detected;
162
163 /*
164 * There is a possibility of driver's wake request colliding
165 * with hardware's own wake requests and that can cause
166 * hardware to not deliver the driver's ack message.
167 *
168 * Use a fallback bit toggle to kick the gpu state machine
169 * in the hope that the original ack will be delivered along with
170 * the fallback ack.
171 *
172 * This workaround is described in HSDES #1604254524 and it's known as:
173 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
174 * although the name is a bit misleading.
175 */
176
177 pass = 1;
178 do {
179 wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK);
180
181 fw_set(d, FORCEWAKE_KERNEL_FALLBACK);
182 /* Give gt some time to relax before the polling frenzy */
183 udelay(10 * pass);
184 wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK);
185
186 ack_detected = (fw_ack(d) & ack_bit) == value;
187
188 fw_clear(d, FORCEWAKE_KERNEL_FALLBACK);
189 } while (!ack_detected && pass++ < 10);
190
191 DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n",
192 intel_uncore_forcewake_domain_to_str(d->id),
193 type == ACK_SET ? "set" : "clear",
194 fw_ack(d),
195 pass);
196
197 return ack_detected ? 0 : -ETIMEDOUT;
198 }
199
200 static inline void
fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain * d)201 fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d)
202 {
203 if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL)))
204 return;
205
206 if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR))
207 fw_domain_wait_ack_clear(d);
208 }
209
210 static inline void
fw_domain_get(const struct intel_uncore_forcewake_domain * d)211 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
212 {
213 fw_set(d, FORCEWAKE_KERNEL);
214 }
215
216 static inline void
fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain * d)217 fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d)
218 {
219 if (wait_ack_set(d, FORCEWAKE_KERNEL)) {
220 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
221 intel_uncore_forcewake_domain_to_str(d->id));
222 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */
223 }
224 }
225
226 static inline void
fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain * d)227 fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d)
228 {
229 if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL)))
230 return;
231
232 if (fw_domain_wait_ack_with_fallback(d, ACK_SET))
233 fw_domain_wait_ack_set(d);
234 }
235
236 static inline void
fw_domain_put(const struct intel_uncore_forcewake_domain * d)237 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
238 {
239 fw_clear(d, FORCEWAKE_KERNEL);
240 }
241
242 static void
fw_domains_get(struct intel_uncore * uncore,enum forcewake_domains fw_domains)243 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
244 {
245 struct intel_uncore_forcewake_domain *d;
246 unsigned int tmp;
247
248 GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
249
250 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
251 fw_domain_wait_ack_clear(d);
252 fw_domain_get(d);
253 }
254
255 for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
256 fw_domain_wait_ack_set(d);
257
258 uncore->fw_domains_active |= fw_domains;
259 }
260
261 static void
fw_domains_get_with_fallback(struct intel_uncore * uncore,enum forcewake_domains fw_domains)262 fw_domains_get_with_fallback(struct intel_uncore *uncore,
263 enum forcewake_domains fw_domains)
264 {
265 struct intel_uncore_forcewake_domain *d;
266 unsigned int tmp;
267
268 GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
269
270 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
271 fw_domain_wait_ack_clear_fallback(d);
272 fw_domain_get(d);
273 }
274
275 for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
276 fw_domain_wait_ack_set_fallback(d);
277
278 uncore->fw_domains_active |= fw_domains;
279 }
280
281 static void
fw_domains_put(struct intel_uncore * uncore,enum forcewake_domains fw_domains)282 fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
283 {
284 struct intel_uncore_forcewake_domain *d;
285 unsigned int tmp;
286
287 GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
288
289 for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
290 fw_domain_put(d);
291
292 uncore->fw_domains_active &= ~fw_domains;
293 }
294
295 static void
fw_domains_reset(struct intel_uncore * uncore,enum forcewake_domains fw_domains)296 fw_domains_reset(struct intel_uncore *uncore,
297 enum forcewake_domains fw_domains)
298 {
299 struct intel_uncore_forcewake_domain *d;
300 unsigned int tmp;
301
302 if (!fw_domains)
303 return;
304
305 GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
306
307 for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
308 fw_domain_reset(d);
309 }
310
gt_thread_status(struct intel_uncore * uncore)311 static inline u32 gt_thread_status(struct intel_uncore *uncore)
312 {
313 u32 val;
314
315 val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
316 val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
317
318 return val;
319 }
320
__gen6_gt_wait_for_thread_c0(struct intel_uncore * uncore)321 static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore)
322 {
323 /*
324 * w/a for a sporadic read returning 0 by waiting for the GT
325 * thread to wake up.
326 */
327 drm_WARN_ONCE(&uncore->i915->drm,
328 wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000),
329 "GT thread status wait timed out\n");
330 }
331
fw_domains_get_with_thread_status(struct intel_uncore * uncore,enum forcewake_domains fw_domains)332 static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
333 enum forcewake_domains fw_domains)
334 {
335 fw_domains_get(uncore, fw_domains);
336
337 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
338 __gen6_gt_wait_for_thread_c0(uncore);
339 }
340
fifo_free_entries(struct intel_uncore * uncore)341 static inline u32 fifo_free_entries(struct intel_uncore *uncore)
342 {
343 u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
344
345 return count & GT_FIFO_FREE_ENTRIES_MASK;
346 }
347
__gen6_gt_wait_for_fifo(struct intel_uncore * uncore)348 static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore)
349 {
350 u32 n;
351
352 /* On VLV, FIFO will be shared by both SW and HW.
353 * So, we need to read the FREE_ENTRIES everytime */
354 if (IS_VALLEYVIEW(uncore->i915))
355 n = fifo_free_entries(uncore);
356 else
357 n = uncore->fifo_count;
358
359 if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
360 if (wait_for_atomic((n = fifo_free_entries(uncore)) >
361 GT_FIFO_NUM_RESERVED_ENTRIES,
362 GT_FIFO_TIMEOUT_MS)) {
363 drm_dbg(&uncore->i915->drm,
364 "GT_FIFO timeout, entries: %u\n", n);
365 return;
366 }
367 }
368
369 uncore->fifo_count = n - 1;
370 }
371
372 static enum hrtimer_restart
intel_uncore_fw_release_timer(struct hrtimer * timer)373 intel_uncore_fw_release_timer(struct hrtimer *timer)
374 {
375 struct intel_uncore_forcewake_domain *domain =
376 container_of(timer, struct intel_uncore_forcewake_domain, timer);
377 struct intel_uncore *uncore = domain->uncore;
378 unsigned long irqflags;
379
380 assert_rpm_device_not_suspended(uncore->rpm);
381
382 if (xchg(&domain->active, false))
383 return HRTIMER_RESTART;
384
385 spin_lock_irqsave(&uncore->lock, irqflags);
386
387 uncore->fw_domains_timer &= ~domain->mask;
388
389 GEM_BUG_ON(!domain->wake_count);
390 if (--domain->wake_count == 0)
391 uncore->funcs.force_wake_put(uncore, domain->mask);
392
393 spin_unlock_irqrestore(&uncore->lock, irqflags);
394
395 return HRTIMER_NORESTART;
396 }
397
398 /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */
399 static unsigned int
intel_uncore_forcewake_reset(struct intel_uncore * uncore)400 intel_uncore_forcewake_reset(struct intel_uncore *uncore)
401 {
402 unsigned long irqflags;
403 struct intel_uncore_forcewake_domain *domain;
404 int retry_count = 100;
405 enum forcewake_domains fw, active_domains;
406
407 iosf_mbi_assert_punit_acquired();
408
409 /* Hold uncore.lock across reset to prevent any register access
410 * with forcewake not set correctly. Wait until all pending
411 * timers are run before holding.
412 */
413 while (1) {
414 unsigned int tmp;
415
416 active_domains = 0;
417
418 for_each_fw_domain(domain, uncore, tmp) {
419 smp_store_mb(domain->active, false);
420 if (hrtimer_cancel(&domain->timer) == 0)
421 continue;
422
423 intel_uncore_fw_release_timer(&domain->timer);
424 }
425
426 spin_lock_irqsave(&uncore->lock, irqflags);
427
428 for_each_fw_domain(domain, uncore, tmp) {
429 if (hrtimer_active(&domain->timer))
430 active_domains |= domain->mask;
431 }
432
433 if (active_domains == 0)
434 break;
435
436 if (--retry_count == 0) {
437 drm_err(&uncore->i915->drm, "Timed out waiting for forcewake timers to finish\n");
438 break;
439 }
440
441 spin_unlock_irqrestore(&uncore->lock, irqflags);
442 cond_resched();
443 }
444
445 drm_WARN_ON(&uncore->i915->drm, active_domains);
446
447 fw = uncore->fw_domains_active;
448 if (fw)
449 uncore->funcs.force_wake_put(uncore, fw);
450
451 fw_domains_reset(uncore, uncore->fw_domains);
452 assert_forcewakes_inactive(uncore);
453
454 spin_unlock_irqrestore(&uncore->lock, irqflags);
455
456 return fw; /* track the lost user forcewake domains */
457 }
458
459 static bool
fpga_check_for_unclaimed_mmio(struct intel_uncore * uncore)460 fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
461 {
462 u32 dbg;
463
464 dbg = __raw_uncore_read32(uncore, FPGA_DBG);
465 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
466 return false;
467
468 __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
469
470 return true;
471 }
472
473 static bool
vlv_check_for_unclaimed_mmio(struct intel_uncore * uncore)474 vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
475 {
476 u32 cer;
477
478 cer = __raw_uncore_read32(uncore, CLAIM_ER);
479 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
480 return false;
481
482 __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
483
484 return true;
485 }
486
487 static bool
gen6_check_for_fifo_debug(struct intel_uncore * uncore)488 gen6_check_for_fifo_debug(struct intel_uncore *uncore)
489 {
490 u32 fifodbg;
491
492 fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
493
494 if (unlikely(fifodbg)) {
495 drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg);
496 __raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
497 }
498
499 return fifodbg;
500 }
501
502 static bool
check_for_unclaimed_mmio(struct intel_uncore * uncore)503 check_for_unclaimed_mmio(struct intel_uncore *uncore)
504 {
505 bool ret = false;
506
507 lockdep_assert_held(&uncore->debug->lock);
508
509 if (uncore->debug->suspend_count)
510 return false;
511
512 if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
513 ret |= fpga_check_for_unclaimed_mmio(uncore);
514
515 if (intel_uncore_has_dbg_unclaimed(uncore))
516 ret |= vlv_check_for_unclaimed_mmio(uncore);
517
518 if (intel_uncore_has_fifo(uncore))
519 ret |= gen6_check_for_fifo_debug(uncore);
520
521 return ret;
522 }
523
forcewake_early_sanitize(struct intel_uncore * uncore,unsigned int restore_forcewake)524 static void forcewake_early_sanitize(struct intel_uncore *uncore,
525 unsigned int restore_forcewake)
526 {
527 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
528
529 /* WaDisableShadowRegForCpd:chv */
530 if (IS_CHERRYVIEW(uncore->i915)) {
531 __raw_uncore_write32(uncore, GTFIFOCTL,
532 __raw_uncore_read32(uncore, GTFIFOCTL) |
533 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
534 GT_FIFO_CTL_RC6_POLICY_STALL);
535 }
536
537 iosf_mbi_punit_acquire();
538 intel_uncore_forcewake_reset(uncore);
539 if (restore_forcewake) {
540 spin_lock_irq(&uncore->lock);
541 uncore->funcs.force_wake_get(uncore, restore_forcewake);
542
543 if (intel_uncore_has_fifo(uncore))
544 uncore->fifo_count = fifo_free_entries(uncore);
545 spin_unlock_irq(&uncore->lock);
546 }
547 iosf_mbi_punit_release();
548 }
549
intel_uncore_suspend(struct intel_uncore * uncore)550 void intel_uncore_suspend(struct intel_uncore *uncore)
551 {
552 if (!intel_uncore_has_forcewake(uncore))
553 return;
554
555 iosf_mbi_punit_acquire();
556 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
557 &uncore->pmic_bus_access_nb);
558 uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore);
559 iosf_mbi_punit_release();
560 }
561
intel_uncore_resume_early(struct intel_uncore * uncore)562 void intel_uncore_resume_early(struct intel_uncore *uncore)
563 {
564 unsigned int restore_forcewake;
565
566 if (intel_uncore_unclaimed_mmio(uncore))
567 drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n");
568
569 if (!intel_uncore_has_forcewake(uncore))
570 return;
571
572 restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved);
573 forcewake_early_sanitize(uncore, restore_forcewake);
574
575 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
576 }
577
intel_uncore_runtime_resume(struct intel_uncore * uncore)578 void intel_uncore_runtime_resume(struct intel_uncore *uncore)
579 {
580 if (!intel_uncore_has_forcewake(uncore))
581 return;
582
583 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
584 }
585
__intel_uncore_forcewake_get(struct intel_uncore * uncore,enum forcewake_domains fw_domains)586 static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
587 enum forcewake_domains fw_domains)
588 {
589 struct intel_uncore_forcewake_domain *domain;
590 unsigned int tmp;
591
592 fw_domains &= uncore->fw_domains;
593
594 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
595 if (domain->wake_count++) {
596 fw_domains &= ~domain->mask;
597 domain->active = true;
598 }
599 }
600
601 if (fw_domains)
602 uncore->funcs.force_wake_get(uncore, fw_domains);
603 }
604
605 /**
606 * intel_uncore_forcewake_get - grab forcewake domain references
607 * @uncore: the intel_uncore structure
608 * @fw_domains: forcewake domains to get reference on
609 *
610 * This function can be used get GT's forcewake domain references.
611 * Normal register access will handle the forcewake domains automatically.
612 * However if some sequence requires the GT to not power down a particular
613 * forcewake domains this function should be called at the beginning of the
614 * sequence. And subsequently the reference should be dropped by symmetric
615 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
616 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
617 */
intel_uncore_forcewake_get(struct intel_uncore * uncore,enum forcewake_domains fw_domains)618 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
619 enum forcewake_domains fw_domains)
620 {
621 unsigned long irqflags;
622
623 if (!uncore->funcs.force_wake_get)
624 return;
625
626 assert_rpm_wakelock_held(uncore->rpm);
627
628 spin_lock_irqsave(&uncore->lock, irqflags);
629 __intel_uncore_forcewake_get(uncore, fw_domains);
630 spin_unlock_irqrestore(&uncore->lock, irqflags);
631 }
632
633 /**
634 * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
635 * @uncore: the intel_uncore structure
636 *
637 * This function is a wrapper around intel_uncore_forcewake_get() to acquire
638 * the GT powerwell and in the process disable our debugging for the
639 * duration of userspace's bypass.
640 */
intel_uncore_forcewake_user_get(struct intel_uncore * uncore)641 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
642 {
643 spin_lock_irq(&uncore->lock);
644 if (!uncore->user_forcewake_count++) {
645 intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
646 spin_lock(&uncore->debug->lock);
647 mmio_debug_suspend(uncore->debug);
648 spin_unlock(&uncore->debug->lock);
649 }
650 spin_unlock_irq(&uncore->lock);
651 }
652
653 /**
654 * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
655 * @uncore: the intel_uncore structure
656 *
657 * This function complements intel_uncore_forcewake_user_get() and releases
658 * the GT powerwell taken on behalf of the userspace bypass.
659 */
intel_uncore_forcewake_user_put(struct intel_uncore * uncore)660 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
661 {
662 spin_lock_irq(&uncore->lock);
663 if (!--uncore->user_forcewake_count) {
664 spin_lock(&uncore->debug->lock);
665 mmio_debug_resume(uncore->debug);
666
667 if (check_for_unclaimed_mmio(uncore))
668 drm_info(&uncore->i915->drm,
669 "Invalid mmio detected during user access\n");
670 spin_unlock(&uncore->debug->lock);
671
672 intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
673 }
674 spin_unlock_irq(&uncore->lock);
675 }
676
677 /**
678 * intel_uncore_forcewake_get__locked - grab forcewake domain references
679 * @uncore: the intel_uncore structure
680 * @fw_domains: forcewake domains to get reference on
681 *
682 * See intel_uncore_forcewake_get(). This variant places the onus
683 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
684 */
intel_uncore_forcewake_get__locked(struct intel_uncore * uncore,enum forcewake_domains fw_domains)685 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
686 enum forcewake_domains fw_domains)
687 {
688 lockdep_assert_held(&uncore->lock);
689
690 if (!uncore->funcs.force_wake_get)
691 return;
692
693 __intel_uncore_forcewake_get(uncore, fw_domains);
694 }
695
__intel_uncore_forcewake_put(struct intel_uncore * uncore,enum forcewake_domains fw_domains,bool delayed)696 static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
697 enum forcewake_domains fw_domains,
698 bool delayed)
699 {
700 struct intel_uncore_forcewake_domain *domain;
701 unsigned int tmp;
702
703 fw_domains &= uncore->fw_domains;
704
705 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
706 GEM_BUG_ON(!domain->wake_count);
707
708 if (--domain->wake_count) {
709 domain->active = true;
710 continue;
711 }
712
713 if (delayed &&
714 !(domain->uncore->fw_domains_timer & domain->mask))
715 fw_domain_arm_timer(domain);
716 else
717 uncore->funcs.force_wake_put(uncore, domain->mask);
718 }
719 }
720
721 /**
722 * intel_uncore_forcewake_put - release a forcewake domain reference
723 * @uncore: the intel_uncore structure
724 * @fw_domains: forcewake domains to put references
725 *
726 * This function drops the device-level forcewakes for specified
727 * domains obtained by intel_uncore_forcewake_get().
728 */
intel_uncore_forcewake_put(struct intel_uncore * uncore,enum forcewake_domains fw_domains)729 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
730 enum forcewake_domains fw_domains)
731 {
732 unsigned long irqflags;
733
734 if (!uncore->funcs.force_wake_put)
735 return;
736
737 spin_lock_irqsave(&uncore->lock, irqflags);
738 __intel_uncore_forcewake_put(uncore, fw_domains, false);
739 spin_unlock_irqrestore(&uncore->lock, irqflags);
740 }
741
intel_uncore_forcewake_put_delayed(struct intel_uncore * uncore,enum forcewake_domains fw_domains)742 void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
743 enum forcewake_domains fw_domains)
744 {
745 unsigned long irqflags;
746
747 if (!uncore->funcs.force_wake_put)
748 return;
749
750 spin_lock_irqsave(&uncore->lock, irqflags);
751 __intel_uncore_forcewake_put(uncore, fw_domains, true);
752 spin_unlock_irqrestore(&uncore->lock, irqflags);
753 }
754
755 /**
756 * intel_uncore_forcewake_flush - flush the delayed release
757 * @uncore: the intel_uncore structure
758 * @fw_domains: forcewake domains to flush
759 */
intel_uncore_forcewake_flush(struct intel_uncore * uncore,enum forcewake_domains fw_domains)760 void intel_uncore_forcewake_flush(struct intel_uncore *uncore,
761 enum forcewake_domains fw_domains)
762 {
763 struct intel_uncore_forcewake_domain *domain;
764 unsigned int tmp;
765
766 if (!uncore->funcs.force_wake_put)
767 return;
768
769 fw_domains &= uncore->fw_domains;
770 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
771 WRITE_ONCE(domain->active, false);
772 if (hrtimer_cancel(&domain->timer))
773 intel_uncore_fw_release_timer(&domain->timer);
774 }
775 }
776
777 /**
778 * intel_uncore_forcewake_put__locked - grab forcewake domain references
779 * @uncore: the intel_uncore structure
780 * @fw_domains: forcewake domains to get reference on
781 *
782 * See intel_uncore_forcewake_put(). This variant places the onus
783 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
784 */
intel_uncore_forcewake_put__locked(struct intel_uncore * uncore,enum forcewake_domains fw_domains)785 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
786 enum forcewake_domains fw_domains)
787 {
788 lockdep_assert_held(&uncore->lock);
789
790 if (!uncore->funcs.force_wake_put)
791 return;
792
793 __intel_uncore_forcewake_put(uncore, fw_domains, false);
794 }
795
assert_forcewakes_inactive(struct intel_uncore * uncore)796 void assert_forcewakes_inactive(struct intel_uncore *uncore)
797 {
798 if (!uncore->funcs.force_wake_get)
799 return;
800
801 drm_WARN(&uncore->i915->drm, uncore->fw_domains_active,
802 "Expected all fw_domains to be inactive, but %08x are still on\n",
803 uncore->fw_domains_active);
804 }
805
assert_forcewakes_active(struct intel_uncore * uncore,enum forcewake_domains fw_domains)806 void assert_forcewakes_active(struct intel_uncore *uncore,
807 enum forcewake_domains fw_domains)
808 {
809 struct intel_uncore_forcewake_domain *domain;
810 unsigned int tmp;
811
812 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
813 return;
814
815 if (!uncore->funcs.force_wake_get)
816 return;
817
818 spin_lock_irq(&uncore->lock);
819
820 assert_rpm_wakelock_held(uncore->rpm);
821
822 fw_domains &= uncore->fw_domains;
823 drm_WARN(&uncore->i915->drm, fw_domains & ~uncore->fw_domains_active,
824 "Expected %08x fw_domains to be active, but %08x are off\n",
825 fw_domains, fw_domains & ~uncore->fw_domains_active);
826
827 /*
828 * Check that the caller has an explicit wakeref and we don't mistake
829 * it for the auto wakeref.
830 */
831 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
832 unsigned int actual = READ_ONCE(domain->wake_count);
833 unsigned int expect = 1;
834
835 if (uncore->fw_domains_timer & domain->mask)
836 expect++; /* pending automatic release */
837
838 if (drm_WARN(&uncore->i915->drm, actual < expect,
839 "Expected domain %d to be held awake by caller, count=%d\n",
840 domain->id, actual))
841 break;
842 }
843
844 spin_unlock_irq(&uncore->lock);
845 }
846
847 /* We give fast paths for the really cool registers */
848 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
849
850 #define __gen6_reg_read_fw_domains(uncore, offset) \
851 ({ \
852 enum forcewake_domains __fwd; \
853 if (NEEDS_FORCE_WAKE(offset)) \
854 __fwd = FORCEWAKE_RENDER; \
855 else \
856 __fwd = 0; \
857 __fwd; \
858 })
859
fw_range_cmp(u32 offset,const struct intel_forcewake_range * entry)860 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
861 {
862 if (offset < entry->start)
863 return -1;
864 else if (offset > entry->end)
865 return 1;
866 else
867 return 0;
868 }
869
870 /* Copied and "macroized" from lib/bsearch.c */
871 #define BSEARCH(key, base, num, cmp) ({ \
872 unsigned int start__ = 0, end__ = (num); \
873 typeof(base) result__ = NULL; \
874 while (start__ < end__) { \
875 unsigned int mid__ = start__ + (end__ - start__) / 2; \
876 int ret__ = (cmp)((key), (base) + mid__); \
877 if (ret__ < 0) { \
878 end__ = mid__; \
879 } else if (ret__ > 0) { \
880 start__ = mid__ + 1; \
881 } else { \
882 result__ = (base) + mid__; \
883 break; \
884 } \
885 } \
886 result__; \
887 })
888
889 static enum forcewake_domains
find_fw_domain(struct intel_uncore * uncore,u32 offset)890 find_fw_domain(struct intel_uncore *uncore, u32 offset)
891 {
892 const struct intel_forcewake_range *entry;
893
894 entry = BSEARCH(offset,
895 uncore->fw_domains_table,
896 uncore->fw_domains_table_entries,
897 fw_range_cmp);
898
899 if (!entry)
900 return 0;
901
902 /*
903 * The list of FW domains depends on the SKU in gen11+ so we
904 * can't determine it statically. We use FORCEWAKE_ALL and
905 * translate it here to the list of available domains.
906 */
907 if (entry->domains == FORCEWAKE_ALL)
908 return uncore->fw_domains;
909
910 drm_WARN(&uncore->i915->drm, entry->domains & ~uncore->fw_domains,
911 "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
912 entry->domains & ~uncore->fw_domains, offset);
913
914 return entry->domains;
915 }
916
917 #define GEN_FW_RANGE(s, e, d) \
918 { .start = (s), .end = (e), .domains = (d) }
919
920 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
921 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
922 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
923 GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
924 GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
925 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
926 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
927 GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
928 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
929 };
930
931 #define __fwtable_reg_read_fw_domains(uncore, offset) \
932 ({ \
933 enum forcewake_domains __fwd = 0; \
934 if (NEEDS_FORCE_WAKE((offset))) \
935 __fwd = find_fw_domain(uncore, offset); \
936 __fwd; \
937 })
938
939 #define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
940 find_fw_domain(uncore, offset)
941
942 #define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \
943 find_fw_domain(uncore, offset)
944
945 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
946 static const i915_reg_t gen8_shadowed_regs[] = {
947 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
948 GEN6_RPNSWREQ, /* 0xA008 */
949 GEN6_RC_VIDEO_FREQ, /* 0xA00C */
950 RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */
951 RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */
952 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
953 /* TODO: Other registers are not yet used */
954 };
955
956 static const i915_reg_t gen11_shadowed_regs[] = {
957 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
958 GEN6_RPNSWREQ, /* 0xA008 */
959 GEN6_RC_VIDEO_FREQ, /* 0xA00C */
960 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
961 RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */
962 RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */
963 RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
964 RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */
965 RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */
966 RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
967 /* TODO: Other registers are not yet used */
968 };
969
970 static const i915_reg_t gen12_shadowed_regs[] = {
971 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
972 GEN6_RPNSWREQ, /* 0xA008 */
973 GEN6_RC_VIDEO_FREQ, /* 0xA00C */
974 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
975 RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */
976 RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */
977 RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
978 RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */
979 RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */
980 RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
981 /* TODO: Other registers are not yet used */
982 };
983
mmio_reg_cmp(u32 key,const i915_reg_t * reg)984 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
985 {
986 u32 offset = i915_mmio_reg_offset(*reg);
987
988 if (key < offset)
989 return -1;
990 else if (key > offset)
991 return 1;
992 else
993 return 0;
994 }
995
996 #define __is_genX_shadowed(x) \
997 static bool is_gen##x##_shadowed(u32 offset) \
998 { \
999 const i915_reg_t *regs = gen##x##_shadowed_regs; \
1000 return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \
1001 mmio_reg_cmp); \
1002 }
1003
1004 __is_genX_shadowed(8)
1005 __is_genX_shadowed(11)
1006 __is_genX_shadowed(12)
1007
1008 static enum forcewake_domains
gen6_reg_write_fw_domains(struct intel_uncore * uncore,i915_reg_t reg)1009 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
1010 {
1011 return FORCEWAKE_RENDER;
1012 }
1013
1014 #define __gen8_reg_write_fw_domains(uncore, offset) \
1015 ({ \
1016 enum forcewake_domains __fwd; \
1017 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
1018 __fwd = FORCEWAKE_RENDER; \
1019 else \
1020 __fwd = 0; \
1021 __fwd; \
1022 })
1023
1024 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1025 static const struct intel_forcewake_range __chv_fw_ranges[] = {
1026 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
1027 GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1028 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1029 GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1030 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1031 GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1032 GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
1033 GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1034 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1035 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1036 GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
1037 GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1038 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1039 GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
1040 GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
1041 GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
1042 };
1043
1044 #define __fwtable_reg_write_fw_domains(uncore, offset) \
1045 ({ \
1046 enum forcewake_domains __fwd = 0; \
1047 if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
1048 __fwd = find_fw_domain(uncore, offset); \
1049 __fwd; \
1050 })
1051
1052 #define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \
1053 ({ \
1054 enum forcewake_domains __fwd = 0; \
1055 const u32 __offset = (offset); \
1056 if (!is_gen11_shadowed(__offset)) \
1057 __fwd = find_fw_domain(uncore, __offset); \
1058 __fwd; \
1059 })
1060
1061 #define __gen12_fwtable_reg_write_fw_domains(uncore, offset) \
1062 ({ \
1063 enum forcewake_domains __fwd = 0; \
1064 const u32 __offset = (offset); \
1065 if (!is_gen12_shadowed(__offset)) \
1066 __fwd = find_fw_domain(uncore, __offset); \
1067 __fwd; \
1068 })
1069
1070 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1071 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
1072 GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
1073 GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1074 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1075 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
1076 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1077 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
1078 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1079 GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
1080 GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
1081 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1082 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
1083 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1084 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
1085 GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
1086 GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
1087 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1088 GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
1089 GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1090 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
1091 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1092 GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
1093 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1094 GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
1095 GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1096 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
1097 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1098 GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
1099 GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
1100 GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
1101 GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1102 GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
1103 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
1104 };
1105
1106 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1107 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
1108 GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */
1109 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1110 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
1111 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1112 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
1113 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1114 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
1115 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1116 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
1117 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1118 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
1119 GEN_FW_RANGE(0x8800, 0x8bff, 0),
1120 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1121 GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_BLITTER),
1122 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1123 GEN_FW_RANGE(0x9560, 0x95ff, 0),
1124 GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_BLITTER),
1125 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1126 GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_BLITTER),
1127 GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
1128 GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_BLITTER),
1129 GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
1130 GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_BLITTER),
1131 GEN_FW_RANGE(0x24000, 0x2407f, 0),
1132 GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_BLITTER),
1133 GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER),
1134 GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_BLITTER),
1135 GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER),
1136 GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_BLITTER),
1137 GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1138 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1139 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
1140 GEN_FW_RANGE(0x1c8000, 0x1cffff, FORCEWAKE_MEDIA_VEBOX0),
1141 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1142 GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0)
1143 };
1144
1145 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1146 static const struct intel_forcewake_range __gen12_fw_ranges[] = {
1147 GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
1148 GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1149 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1150 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
1151 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1152 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
1153 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1154 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
1155 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1156 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
1157 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1158 GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
1159 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1160 GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
1161 GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
1162 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
1163 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1164 GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
1165 GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1166 GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER),
1167 GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER),
1168 GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_BLITTER),
1169 GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER),
1170 GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_BLITTER),
1171 GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER),
1172 GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_BLITTER),
1173 GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1174 GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
1175 GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1176 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1177 GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
1178 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
1179 GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
1180 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1181 GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
1182 GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
1183 };
1184
1185 static void
ilk_dummy_write(struct intel_uncore * uncore)1186 ilk_dummy_write(struct intel_uncore *uncore)
1187 {
1188 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
1189 * the chip from rc6 before touching it for real. MI_MODE is masked,
1190 * hence harmless to write 0 into. */
1191 __raw_uncore_write32(uncore, MI_MODE, 0);
1192 }
1193
1194 static void
__unclaimed_reg_debug(struct intel_uncore * uncore,const i915_reg_t reg,const bool read,const bool before)1195 __unclaimed_reg_debug(struct intel_uncore *uncore,
1196 const i915_reg_t reg,
1197 const bool read,
1198 const bool before)
1199 {
1200 if (drm_WARN(&uncore->i915->drm,
1201 check_for_unclaimed_mmio(uncore) && !before,
1202 "Unclaimed %s register 0x%x\n",
1203 read ? "read from" : "write to",
1204 i915_mmio_reg_offset(reg)))
1205 /* Only report the first N failures */
1206 uncore->i915->params.mmio_debug--;
1207 }
1208
1209 static inline void
unclaimed_reg_debug(struct intel_uncore * uncore,const i915_reg_t reg,const bool read,const bool before)1210 unclaimed_reg_debug(struct intel_uncore *uncore,
1211 const i915_reg_t reg,
1212 const bool read,
1213 const bool before)
1214 {
1215 if (likely(!uncore->i915->params.mmio_debug))
1216 return;
1217
1218 /* interrupts are disabled and re-enabled around uncore->lock usage */
1219 lockdep_assert_held(&uncore->lock);
1220
1221 if (before)
1222 spin_lock(&uncore->debug->lock);
1223
1224 __unclaimed_reg_debug(uncore, reg, read, before);
1225
1226 if (!before)
1227 spin_unlock(&uncore->debug->lock);
1228 }
1229
1230 #define __vgpu_read(x) \
1231 static u##x \
1232 vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1233 u##x val = __raw_uncore_read##x(uncore, reg); \
1234 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1235 return val; \
1236 }
1237 __vgpu_read(8)
1238 __vgpu_read(16)
1239 __vgpu_read(32)
1240 __vgpu_read(64)
1241
1242 #define GEN2_READ_HEADER(x) \
1243 u##x val = 0; \
1244 assert_rpm_wakelock_held(uncore->rpm);
1245
1246 #define GEN2_READ_FOOTER \
1247 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1248 return val
1249
1250 #define __gen2_read(x) \
1251 static u##x \
1252 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1253 GEN2_READ_HEADER(x); \
1254 val = __raw_uncore_read##x(uncore, reg); \
1255 GEN2_READ_FOOTER; \
1256 }
1257
1258 #define __gen5_read(x) \
1259 static u##x \
1260 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1261 GEN2_READ_HEADER(x); \
1262 ilk_dummy_write(uncore); \
1263 val = __raw_uncore_read##x(uncore, reg); \
1264 GEN2_READ_FOOTER; \
1265 }
1266
1267 __gen5_read(8)
1268 __gen5_read(16)
1269 __gen5_read(32)
1270 __gen5_read(64)
1271 __gen2_read(8)
1272 __gen2_read(16)
1273 __gen2_read(32)
1274 __gen2_read(64)
1275
1276 #undef __gen5_read
1277 #undef __gen2_read
1278
1279 #undef GEN2_READ_FOOTER
1280 #undef GEN2_READ_HEADER
1281
1282 #define GEN6_READ_HEADER(x) \
1283 u32 offset = i915_mmio_reg_offset(reg); \
1284 unsigned long irqflags; \
1285 u##x val = 0; \
1286 assert_rpm_wakelock_held(uncore->rpm); \
1287 spin_lock_irqsave(&uncore->lock, irqflags); \
1288 unclaimed_reg_debug(uncore, reg, true, true)
1289
1290 #define GEN6_READ_FOOTER \
1291 unclaimed_reg_debug(uncore, reg, true, false); \
1292 spin_unlock_irqrestore(&uncore->lock, irqflags); \
1293 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1294 return val
1295
___force_wake_auto(struct intel_uncore * uncore,enum forcewake_domains fw_domains)1296 static noinline void ___force_wake_auto(struct intel_uncore *uncore,
1297 enum forcewake_domains fw_domains)
1298 {
1299 struct intel_uncore_forcewake_domain *domain;
1300 unsigned int tmp;
1301
1302 GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
1303
1304 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp)
1305 fw_domain_arm_timer(domain);
1306
1307 uncore->funcs.force_wake_get(uncore, fw_domains);
1308 }
1309
__force_wake_auto(struct intel_uncore * uncore,enum forcewake_domains fw_domains)1310 static inline void __force_wake_auto(struct intel_uncore *uncore,
1311 enum forcewake_domains fw_domains)
1312 {
1313 GEM_BUG_ON(!fw_domains);
1314
1315 /* Turn on all requested but inactive supported forcewake domains. */
1316 fw_domains &= uncore->fw_domains;
1317 fw_domains &= ~uncore->fw_domains_active;
1318
1319 if (fw_domains)
1320 ___force_wake_auto(uncore, fw_domains);
1321 }
1322
1323 #define __gen_read(func, x) \
1324 static u##x \
1325 func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1326 enum forcewake_domains fw_engine; \
1327 GEN6_READ_HEADER(x); \
1328 fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
1329 if (fw_engine) \
1330 __force_wake_auto(uncore, fw_engine); \
1331 val = __raw_uncore_read##x(uncore, reg); \
1332 GEN6_READ_FOOTER; \
1333 }
1334
1335 #define __gen_reg_read_funcs(func) \
1336 static enum forcewake_domains \
1337 func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
1338 return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
1339 } \
1340 \
1341 __gen_read(func, 8) \
1342 __gen_read(func, 16) \
1343 __gen_read(func, 32) \
1344 __gen_read(func, 64)
1345
1346 __gen_reg_read_funcs(gen12_fwtable);
1347 __gen_reg_read_funcs(gen11_fwtable);
1348 __gen_reg_read_funcs(fwtable);
1349 __gen_reg_read_funcs(gen6);
1350
1351 #undef __gen_reg_read_funcs
1352 #undef GEN6_READ_FOOTER
1353 #undef GEN6_READ_HEADER
1354
1355 #define GEN2_WRITE_HEADER \
1356 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1357 assert_rpm_wakelock_held(uncore->rpm); \
1358
1359 #define GEN2_WRITE_FOOTER
1360
1361 #define __gen2_write(x) \
1362 static void \
1363 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1364 GEN2_WRITE_HEADER; \
1365 __raw_uncore_write##x(uncore, reg, val); \
1366 GEN2_WRITE_FOOTER; \
1367 }
1368
1369 #define __gen5_write(x) \
1370 static void \
1371 gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1372 GEN2_WRITE_HEADER; \
1373 ilk_dummy_write(uncore); \
1374 __raw_uncore_write##x(uncore, reg, val); \
1375 GEN2_WRITE_FOOTER; \
1376 }
1377
1378 __gen5_write(8)
1379 __gen5_write(16)
1380 __gen5_write(32)
1381 __gen2_write(8)
1382 __gen2_write(16)
1383 __gen2_write(32)
1384
1385 #undef __gen5_write
1386 #undef __gen2_write
1387
1388 #undef GEN2_WRITE_FOOTER
1389 #undef GEN2_WRITE_HEADER
1390
1391 #define GEN6_WRITE_HEADER \
1392 u32 offset = i915_mmio_reg_offset(reg); \
1393 unsigned long irqflags; \
1394 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1395 assert_rpm_wakelock_held(uncore->rpm); \
1396 spin_lock_irqsave(&uncore->lock, irqflags); \
1397 unclaimed_reg_debug(uncore, reg, false, true)
1398
1399 #define GEN6_WRITE_FOOTER \
1400 unclaimed_reg_debug(uncore, reg, false, false); \
1401 spin_unlock_irqrestore(&uncore->lock, irqflags)
1402
1403 #define __gen6_write(x) \
1404 static void \
1405 gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1406 GEN6_WRITE_HEADER; \
1407 if (NEEDS_FORCE_WAKE(offset)) \
1408 __gen6_gt_wait_for_fifo(uncore); \
1409 __raw_uncore_write##x(uncore, reg, val); \
1410 GEN6_WRITE_FOOTER; \
1411 }
1412 __gen6_write(8)
1413 __gen6_write(16)
1414 __gen6_write(32)
1415
1416 #define __gen_write(func, x) \
1417 static void \
1418 func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1419 enum forcewake_domains fw_engine; \
1420 GEN6_WRITE_HEADER; \
1421 fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
1422 if (fw_engine) \
1423 __force_wake_auto(uncore, fw_engine); \
1424 __raw_uncore_write##x(uncore, reg, val); \
1425 GEN6_WRITE_FOOTER; \
1426 }
1427
1428 #define __gen_reg_write_funcs(func) \
1429 static enum forcewake_domains \
1430 func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
1431 return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
1432 } \
1433 \
1434 __gen_write(func, 8) \
1435 __gen_write(func, 16) \
1436 __gen_write(func, 32)
1437
1438 __gen_reg_write_funcs(gen12_fwtable);
1439 __gen_reg_write_funcs(gen11_fwtable);
1440 __gen_reg_write_funcs(fwtable);
1441 __gen_reg_write_funcs(gen8);
1442
1443 #undef __gen_reg_write_funcs
1444 #undef GEN6_WRITE_FOOTER
1445 #undef GEN6_WRITE_HEADER
1446
1447 #define __vgpu_write(x) \
1448 static void \
1449 vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1450 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1451 __raw_uncore_write##x(uncore, reg, val); \
1452 }
1453 __vgpu_write(8)
1454 __vgpu_write(16)
1455 __vgpu_write(32)
1456
1457 #define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
1458 do { \
1459 (uncore)->funcs.mmio_writeb = x##_write8; \
1460 (uncore)->funcs.mmio_writew = x##_write16; \
1461 (uncore)->funcs.mmio_writel = x##_write32; \
1462 } while (0)
1463
1464 #define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \
1465 do { \
1466 (uncore)->funcs.mmio_readb = x##_read8; \
1467 (uncore)->funcs.mmio_readw = x##_read16; \
1468 (uncore)->funcs.mmio_readl = x##_read32; \
1469 (uncore)->funcs.mmio_readq = x##_read64; \
1470 } while (0)
1471
1472 #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
1473 do { \
1474 ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \
1475 (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
1476 } while (0)
1477
1478 #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
1479 do { \
1480 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \
1481 (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
1482 } while (0)
1483
__fw_domain_init(struct intel_uncore * uncore,enum forcewake_domain_id domain_id,i915_reg_t reg_set,i915_reg_t reg_ack)1484 static int __fw_domain_init(struct intel_uncore *uncore,
1485 enum forcewake_domain_id domain_id,
1486 i915_reg_t reg_set,
1487 i915_reg_t reg_ack)
1488 {
1489 struct intel_uncore_forcewake_domain *d;
1490
1491 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
1492 GEM_BUG_ON(uncore->fw_domain[domain_id]);
1493
1494 if (i915_inject_probe_failure(uncore->i915))
1495 return -ENOMEM;
1496
1497 d = kzalloc(sizeof(*d), GFP_KERNEL);
1498 if (!d)
1499 return -ENOMEM;
1500
1501 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_set));
1502 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_ack));
1503
1504 d->uncore = uncore;
1505 d->wake_count = 0;
1506 d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
1507 d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
1508
1509 d->id = domain_id;
1510
1511 BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1512 BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1513 BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1514 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
1515 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
1516 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2));
1517 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3));
1518 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));
1519 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));
1520
1521 d->mask = BIT(domain_id);
1522
1523 hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1524 d->timer.function = intel_uncore_fw_release_timer;
1525
1526 uncore->fw_domains |= BIT(domain_id);
1527
1528 fw_domain_reset(d);
1529
1530 uncore->fw_domain[domain_id] = d;
1531
1532 return 0;
1533 }
1534
fw_domain_fini(struct intel_uncore * uncore,enum forcewake_domain_id domain_id)1535 static void fw_domain_fini(struct intel_uncore *uncore,
1536 enum forcewake_domain_id domain_id)
1537 {
1538 struct intel_uncore_forcewake_domain *d;
1539
1540 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
1541
1542 d = fetch_and_zero(&uncore->fw_domain[domain_id]);
1543 if (!d)
1544 return;
1545
1546 uncore->fw_domains &= ~BIT(domain_id);
1547 drm_WARN_ON(&uncore->i915->drm, d->wake_count);
1548 drm_WARN_ON(&uncore->i915->drm, hrtimer_cancel(&d->timer));
1549 kfree(d);
1550 }
1551
intel_uncore_fw_domains_fini(struct intel_uncore * uncore)1552 static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore)
1553 {
1554 struct intel_uncore_forcewake_domain *d;
1555 int tmp;
1556
1557 for_each_fw_domain(d, uncore, tmp)
1558 fw_domain_fini(uncore, d->id);
1559 }
1560
intel_uncore_fw_domains_init(struct intel_uncore * uncore)1561 static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
1562 {
1563 struct drm_i915_private *i915 = uncore->i915;
1564 int ret = 0;
1565
1566 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
1567
1568 #define fw_domain_init(uncore__, id__, set__, ack__) \
1569 (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__))))
1570
1571 if (INTEL_GEN(i915) >= 11) {
1572 /* we'll prune the domains of missing engines later */
1573 intel_engine_mask_t emask = INTEL_INFO(i915)->platform_engine_mask;
1574 int i;
1575
1576 uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
1577 uncore->funcs.force_wake_put = fw_domains_put;
1578 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1579 FORCEWAKE_RENDER_GEN9,
1580 FORCEWAKE_ACK_RENDER_GEN9);
1581 fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
1582 FORCEWAKE_BLITTER_GEN9,
1583 FORCEWAKE_ACK_BLITTER_GEN9);
1584
1585 for (i = 0; i < I915_MAX_VCS; i++) {
1586 if (!__HAS_ENGINE(emask, _VCS(i)))
1587 continue;
1588
1589 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
1590 FORCEWAKE_MEDIA_VDBOX_GEN11(i),
1591 FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
1592 }
1593 for (i = 0; i < I915_MAX_VECS; i++) {
1594 if (!__HAS_ENGINE(emask, _VECS(i)))
1595 continue;
1596
1597 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
1598 FORCEWAKE_MEDIA_VEBOX_GEN11(i),
1599 FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
1600 }
1601 } else if (IS_GEN_RANGE(i915, 9, 10)) {
1602 uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
1603 uncore->funcs.force_wake_put = fw_domains_put;
1604 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1605 FORCEWAKE_RENDER_GEN9,
1606 FORCEWAKE_ACK_RENDER_GEN9);
1607 fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
1608 FORCEWAKE_BLITTER_GEN9,
1609 FORCEWAKE_ACK_BLITTER_GEN9);
1610 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1611 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1612 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1613 uncore->funcs.force_wake_get = fw_domains_get;
1614 uncore->funcs.force_wake_put = fw_domains_put;
1615 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1616 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1617 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1618 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1619 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
1620 uncore->funcs.force_wake_get =
1621 fw_domains_get_with_thread_status;
1622 uncore->funcs.force_wake_put = fw_domains_put;
1623 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1624 FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1625 } else if (IS_IVYBRIDGE(i915)) {
1626 u32 ecobus;
1627
1628 /* IVB configs may use multi-threaded forcewake */
1629
1630 /* A small trick here - if the bios hasn't configured
1631 * MT forcewake, and if the device is in RC6, then
1632 * force_wake_mt_get will not wake the device and the
1633 * ECOBUS read will return zero. Which will be
1634 * (correctly) interpreted by the test below as MT
1635 * forcewake being disabled.
1636 */
1637 uncore->funcs.force_wake_get =
1638 fw_domains_get_with_thread_status;
1639 uncore->funcs.force_wake_put = fw_domains_put;
1640
1641 /* We need to init first for ECOBUS access and then
1642 * determine later if we want to reinit, in case of MT access is
1643 * not working. In this stage we don't know which flavour this
1644 * ivb is, so it is better to reset also the gen6 fw registers
1645 * before the ecobus check.
1646 */
1647
1648 __raw_uncore_write32(uncore, FORCEWAKE, 0);
1649 __raw_posting_read(uncore, ECOBUS);
1650
1651 ret = __fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1652 FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1653 if (ret)
1654 goto out;
1655
1656 spin_lock_irq(&uncore->lock);
1657 fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
1658 ecobus = __raw_uncore_read32(uncore, ECOBUS);
1659 fw_domains_put(uncore, FORCEWAKE_RENDER);
1660 spin_unlock_irq(&uncore->lock);
1661
1662 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1663 drm_info(&i915->drm, "No MT forcewake available on Ivybridge, this can result in issues\n");
1664 drm_info(&i915->drm, "when using vblank-synced partial screen updates.\n");
1665 fw_domain_fini(uncore, FW_DOMAIN_ID_RENDER);
1666 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1667 FORCEWAKE, FORCEWAKE_ACK);
1668 }
1669 } else if (IS_GEN(i915, 6)) {
1670 uncore->funcs.force_wake_get =
1671 fw_domains_get_with_thread_status;
1672 uncore->funcs.force_wake_put = fw_domains_put;
1673 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1674 FORCEWAKE, FORCEWAKE_ACK);
1675 }
1676
1677 #undef fw_domain_init
1678
1679 /* All future platforms are expected to require complex power gating */
1680 drm_WARN_ON(&i915->drm, !ret && uncore->fw_domains == 0);
1681
1682 out:
1683 if (ret)
1684 intel_uncore_fw_domains_fini(uncore);
1685
1686 return ret;
1687 }
1688
1689 #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \
1690 { \
1691 (uncore)->fw_domains_table = \
1692 (struct intel_forcewake_range *)(d); \
1693 (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \
1694 }
1695
i915_pmic_bus_access_notifier(struct notifier_block * nb,unsigned long action,void * data)1696 static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
1697 unsigned long action, void *data)
1698 {
1699 struct intel_uncore *uncore = container_of(nb,
1700 struct intel_uncore, pmic_bus_access_nb);
1701
1702 switch (action) {
1703 case MBI_PMIC_BUS_ACCESS_BEGIN:
1704 /*
1705 * forcewake all now to make sure that we don't need to do a
1706 * forcewake later which on systems where this notifier gets
1707 * called requires the punit to access to the shared pmic i2c
1708 * bus, which will be busy after this notification, leading to:
1709 * "render: timed out waiting for forcewake ack request."
1710 * errors.
1711 *
1712 * The notifier is unregistered during intel_runtime_suspend(),
1713 * so it's ok to access the HW here without holding a RPM
1714 * wake reference -> disable wakeref asserts for the time of
1715 * the access.
1716 */
1717 disable_rpm_wakeref_asserts(uncore->rpm);
1718 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
1719 enable_rpm_wakeref_asserts(uncore->rpm);
1720 break;
1721 case MBI_PMIC_BUS_ACCESS_END:
1722 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
1723 break;
1724 }
1725
1726 return NOTIFY_OK;
1727 }
1728
uncore_mmio_setup(struct intel_uncore * uncore)1729 static int uncore_mmio_setup(struct intel_uncore *uncore)
1730 {
1731 struct drm_i915_private *i915 = uncore->i915;
1732 struct pci_dev *pdev = i915->drm.pdev;
1733 int mmio_bar;
1734 int mmio_size;
1735
1736 mmio_bar = IS_GEN(i915, 2) ? 1 : 0;
1737 /*
1738 * Before gen4, the registers and the GTT are behind different BARs.
1739 * However, from gen4 onwards, the registers and the GTT are shared
1740 * in the same BAR, so we want to restrict this ioremap from
1741 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1742 * the register BAR remains the same size for all the earlier
1743 * generations up to Ironlake.
1744 */
1745 if (INTEL_GEN(i915) < 5)
1746 mmio_size = 512 * 1024;
1747 else
1748 mmio_size = 2 * 1024 * 1024;
1749 uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
1750 if (uncore->regs == NULL) {
1751 drm_err(&i915->drm, "failed to map registers\n");
1752 return -EIO;
1753 }
1754
1755 return 0;
1756 }
1757
uncore_mmio_cleanup(struct intel_uncore * uncore)1758 static void uncore_mmio_cleanup(struct intel_uncore *uncore)
1759 {
1760 struct pci_dev *pdev = uncore->i915->drm.pdev;
1761
1762 pci_iounmap(pdev, uncore->regs);
1763 }
1764
intel_uncore_init_early(struct intel_uncore * uncore,struct drm_i915_private * i915)1765 void intel_uncore_init_early(struct intel_uncore *uncore,
1766 struct drm_i915_private *i915)
1767 {
1768 spin_lock_init(&uncore->lock);
1769 uncore->i915 = i915;
1770 uncore->rpm = &i915->runtime_pm;
1771 uncore->debug = &i915->mmio_debug;
1772 }
1773
uncore_raw_init(struct intel_uncore * uncore)1774 static void uncore_raw_init(struct intel_uncore *uncore)
1775 {
1776 GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
1777
1778 if (intel_vgpu_active(uncore->i915)) {
1779 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu);
1780 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu);
1781 } else if (IS_GEN(uncore->i915, 5)) {
1782 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
1783 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
1784 } else {
1785 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2);
1786 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2);
1787 }
1788 }
1789
uncore_forcewake_init(struct intel_uncore * uncore)1790 static int uncore_forcewake_init(struct intel_uncore *uncore)
1791 {
1792 struct drm_i915_private *i915 = uncore->i915;
1793 int ret;
1794
1795 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
1796
1797 ret = intel_uncore_fw_domains_init(uncore);
1798 if (ret)
1799 return ret;
1800 forcewake_early_sanitize(uncore, 0);
1801
1802 if (IS_GEN_RANGE(i915, 6, 7)) {
1803 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
1804
1805 if (IS_VALLEYVIEW(i915)) {
1806 ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
1807 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1808 } else {
1809 ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
1810 }
1811 } else if (IS_GEN(i915, 8)) {
1812 if (IS_CHERRYVIEW(i915)) {
1813 ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
1814 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
1815 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1816 } else {
1817 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8);
1818 ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
1819 }
1820 } else if (IS_GEN_RANGE(i915, 9, 10)) {
1821 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
1822 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
1823 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1824 } else if (IS_GEN(i915, 11)) {
1825 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
1826 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable);
1827 ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
1828 } else {
1829 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
1830 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
1831 ASSIGN_READ_MMIO_VFUNCS(uncore, gen12_fwtable);
1832 }
1833
1834 uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier;
1835 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
1836
1837 return 0;
1838 }
1839
intel_uncore_init_mmio(struct intel_uncore * uncore)1840 int intel_uncore_init_mmio(struct intel_uncore *uncore)
1841 {
1842 struct drm_i915_private *i915 = uncore->i915;
1843 int ret;
1844
1845 ret = uncore_mmio_setup(uncore);
1846 if (ret)
1847 return ret;
1848
1849 if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
1850 uncore->flags |= UNCORE_HAS_FORCEWAKE;
1851
1852 if (!intel_uncore_has_forcewake(uncore)) {
1853 uncore_raw_init(uncore);
1854 } else {
1855 ret = uncore_forcewake_init(uncore);
1856 if (ret)
1857 goto out_mmio_cleanup;
1858 }
1859
1860 /* make sure fw funcs are set if and only if we have fw*/
1861 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_get);
1862 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_put);
1863 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);
1864 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);
1865
1866 if (HAS_FPGA_DBG_UNCLAIMED(i915))
1867 uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
1868
1869 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1870 uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
1871
1872 if (IS_GEN_RANGE(i915, 6, 7))
1873 uncore->flags |= UNCORE_HAS_FIFO;
1874
1875 /* clear out unclaimed reg detection bit */
1876 if (intel_uncore_unclaimed_mmio(uncore))
1877 drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n");
1878
1879 return 0;
1880
1881 out_mmio_cleanup:
1882 uncore_mmio_cleanup(uncore);
1883
1884 return ret;
1885 }
1886
1887 /*
1888 * We might have detected that some engines are fused off after we initialized
1889 * the forcewake domains. Prune them, to make sure they only reference existing
1890 * engines.
1891 */
intel_uncore_prune_engine_fw_domains(struct intel_uncore * uncore,struct intel_gt * gt)1892 void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
1893 struct intel_gt *gt)
1894 {
1895 enum forcewake_domains fw_domains = uncore->fw_domains;
1896 enum forcewake_domain_id domain_id;
1897 int i;
1898
1899 if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(uncore->i915) < 11)
1900 return;
1901
1902 for (i = 0; i < I915_MAX_VCS; i++) {
1903 domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
1904
1905 if (HAS_ENGINE(gt, _VCS(i)))
1906 continue;
1907
1908 if (fw_domains & BIT(domain_id))
1909 fw_domain_fini(uncore, domain_id);
1910 }
1911
1912 for (i = 0; i < I915_MAX_VECS; i++) {
1913 domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
1914
1915 if (HAS_ENGINE(gt, _VECS(i)))
1916 continue;
1917
1918 if (fw_domains & BIT(domain_id))
1919 fw_domain_fini(uncore, domain_id);
1920 }
1921 }
1922
intel_uncore_fini_mmio(struct intel_uncore * uncore)1923 void intel_uncore_fini_mmio(struct intel_uncore *uncore)
1924 {
1925 if (intel_uncore_has_forcewake(uncore)) {
1926 iosf_mbi_punit_acquire();
1927 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
1928 &uncore->pmic_bus_access_nb);
1929 intel_uncore_forcewake_reset(uncore);
1930 intel_uncore_fw_domains_fini(uncore);
1931 iosf_mbi_punit_release();
1932 }
1933
1934 uncore_mmio_cleanup(uncore);
1935 }
1936
1937 static const struct reg_whitelist {
1938 i915_reg_t offset_ldw;
1939 i915_reg_t offset_udw;
1940 u16 gen_mask;
1941 u8 size;
1942 } reg_read_whitelist[] = { {
1943 .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1944 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1945 .gen_mask = INTEL_GEN_MASK(4, 12),
1946 .size = 8
1947 } };
1948
i915_reg_read_ioctl(struct drm_device * dev,void * data,struct drm_file * file)1949 int i915_reg_read_ioctl(struct drm_device *dev,
1950 void *data, struct drm_file *file)
1951 {
1952 struct drm_i915_private *i915 = to_i915(dev);
1953 struct intel_uncore *uncore = &i915->uncore;
1954 struct drm_i915_reg_read *reg = data;
1955 struct reg_whitelist const *entry;
1956 intel_wakeref_t wakeref;
1957 unsigned int flags;
1958 int remain;
1959 int ret = 0;
1960
1961 entry = reg_read_whitelist;
1962 remain = ARRAY_SIZE(reg_read_whitelist);
1963 while (remain) {
1964 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
1965
1966 GEM_BUG_ON(!is_power_of_2(entry->size));
1967 GEM_BUG_ON(entry->size > 8);
1968 GEM_BUG_ON(entry_offset & (entry->size - 1));
1969
1970 if (INTEL_INFO(i915)->gen_mask & entry->gen_mask &&
1971 entry_offset == (reg->offset & -entry->size))
1972 break;
1973 entry++;
1974 remain--;
1975 }
1976
1977 if (!remain)
1978 return -EINVAL;
1979
1980 flags = reg->offset & (entry->size - 1);
1981
1982 with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
1983 if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
1984 reg->val = intel_uncore_read64_2x32(uncore,
1985 entry->offset_ldw,
1986 entry->offset_udw);
1987 else if (entry->size == 8 && flags == 0)
1988 reg->val = intel_uncore_read64(uncore,
1989 entry->offset_ldw);
1990 else if (entry->size == 4 && flags == 0)
1991 reg->val = intel_uncore_read(uncore, entry->offset_ldw);
1992 else if (entry->size == 2 && flags == 0)
1993 reg->val = intel_uncore_read16(uncore,
1994 entry->offset_ldw);
1995 else if (entry->size == 1 && flags == 0)
1996 reg->val = intel_uncore_read8(uncore,
1997 entry->offset_ldw);
1998 else
1999 ret = -EINVAL;
2000 }
2001
2002 return ret;
2003 }
2004
2005 /**
2006 * __intel_wait_for_register_fw - wait until register matches expected state
2007 * @uncore: the struct intel_uncore
2008 * @reg: the register to read
2009 * @mask: mask to apply to register value
2010 * @value: expected value
2011 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
2012 * @slow_timeout_ms: slow timeout in millisecond
2013 * @out_value: optional placeholder to hold registry value
2014 *
2015 * This routine waits until the target register @reg contains the expected
2016 * @value after applying the @mask, i.e. it waits until ::
2017 *
2018 * (I915_READ_FW(reg) & mask) == value
2019 *
2020 * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
2021 * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
2022 * must be not larger than 20,0000 microseconds.
2023 *
2024 * Note that this routine assumes the caller holds forcewake asserted, it is
2025 * not suitable for very long waits. See intel_wait_for_register() if you
2026 * wish to wait without holding forcewake for the duration (i.e. you expect
2027 * the wait to be slow).
2028 *
2029 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
2030 */
__intel_wait_for_register_fw(struct intel_uncore * uncore,i915_reg_t reg,u32 mask,u32 value,unsigned int fast_timeout_us,unsigned int slow_timeout_ms,u32 * out_value)2031 int __intel_wait_for_register_fw(struct intel_uncore *uncore,
2032 i915_reg_t reg,
2033 u32 mask,
2034 u32 value,
2035 unsigned int fast_timeout_us,
2036 unsigned int slow_timeout_ms,
2037 u32 *out_value)
2038 {
2039 u32 reg_value = 0;
2040 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
2041 int ret;
2042
2043 /* Catch any overuse of this function */
2044 might_sleep_if(slow_timeout_ms);
2045 GEM_BUG_ON(fast_timeout_us > 20000);
2046 GEM_BUG_ON(!fast_timeout_us && !slow_timeout_ms);
2047
2048 ret = -ETIMEDOUT;
2049 if (fast_timeout_us && fast_timeout_us <= 20000)
2050 ret = _wait_for_atomic(done, fast_timeout_us, 0);
2051 if (ret && slow_timeout_ms)
2052 ret = wait_for(done, slow_timeout_ms);
2053
2054 if (out_value)
2055 *out_value = reg_value;
2056
2057 return ret;
2058 #undef done
2059 }
2060
2061 /**
2062 * __intel_wait_for_register - wait until register matches expected state
2063 * @uncore: the struct intel_uncore
2064 * @reg: the register to read
2065 * @mask: mask to apply to register value
2066 * @value: expected value
2067 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
2068 * @slow_timeout_ms: slow timeout in millisecond
2069 * @out_value: optional placeholder to hold registry value
2070 *
2071 * This routine waits until the target register @reg contains the expected
2072 * @value after applying the @mask, i.e. it waits until ::
2073 *
2074 * (I915_READ(reg) & mask) == value
2075 *
2076 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
2077 *
2078 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
2079 */
__intel_wait_for_register(struct intel_uncore * uncore,i915_reg_t reg,u32 mask,u32 value,unsigned int fast_timeout_us,unsigned int slow_timeout_ms,u32 * out_value)2080 int __intel_wait_for_register(struct intel_uncore *uncore,
2081 i915_reg_t reg,
2082 u32 mask,
2083 u32 value,
2084 unsigned int fast_timeout_us,
2085 unsigned int slow_timeout_ms,
2086 u32 *out_value)
2087 {
2088 unsigned fw =
2089 intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
2090 u32 reg_value;
2091 int ret;
2092
2093 might_sleep_if(slow_timeout_ms);
2094
2095 spin_lock_irq(&uncore->lock);
2096 intel_uncore_forcewake_get__locked(uncore, fw);
2097
2098 ret = __intel_wait_for_register_fw(uncore,
2099 reg, mask, value,
2100 fast_timeout_us, 0, ®_value);
2101
2102 intel_uncore_forcewake_put__locked(uncore, fw);
2103 spin_unlock_irq(&uncore->lock);
2104
2105 if (ret && slow_timeout_ms)
2106 ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore,
2107 reg),
2108 (reg_value & mask) == value,
2109 slow_timeout_ms * 1000, 10, 1000);
2110
2111 /* just trace the final value */
2112 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2113
2114 if (out_value)
2115 *out_value = reg_value;
2116
2117 return ret;
2118 }
2119
intel_uncore_unclaimed_mmio(struct intel_uncore * uncore)2120 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
2121 {
2122 bool ret;
2123
2124 spin_lock_irq(&uncore->debug->lock);
2125 ret = check_for_unclaimed_mmio(uncore);
2126 spin_unlock_irq(&uncore->debug->lock);
2127
2128 return ret;
2129 }
2130
2131 bool
intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore * uncore)2132 intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
2133 {
2134 bool ret = false;
2135
2136 spin_lock_irq(&uncore->debug->lock);
2137
2138 if (unlikely(uncore->debug->unclaimed_mmio_check <= 0))
2139 goto out;
2140
2141 if (unlikely(check_for_unclaimed_mmio(uncore))) {
2142 if (!uncore->i915->params.mmio_debug) {
2143 drm_dbg(&uncore->i915->drm,
2144 "Unclaimed register detected, "
2145 "enabling oneshot unclaimed register reporting. "
2146 "Please use i915.mmio_debug=N for more information.\n");
2147 uncore->i915->params.mmio_debug++;
2148 }
2149 uncore->debug->unclaimed_mmio_check--;
2150 ret = true;
2151 }
2152
2153 out:
2154 spin_unlock_irq(&uncore->debug->lock);
2155
2156 return ret;
2157 }
2158
2159 /**
2160 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
2161 * a register
2162 * @uncore: pointer to struct intel_uncore
2163 * @reg: register in question
2164 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
2165 *
2166 * Returns a set of forcewake domains required to be taken with for example
2167 * intel_uncore_forcewake_get for the specified register to be accessible in the
2168 * specified mode (read, write or read/write) with raw mmio accessors.
2169 *
2170 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
2171 * callers to do FIFO management on their own or risk losing writes.
2172 */
2173 enum forcewake_domains
intel_uncore_forcewake_for_reg(struct intel_uncore * uncore,i915_reg_t reg,unsigned int op)2174 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
2175 i915_reg_t reg, unsigned int op)
2176 {
2177 enum forcewake_domains fw_domains = 0;
2178
2179 drm_WARN_ON(&uncore->i915->drm, !op);
2180
2181 if (!intel_uncore_has_forcewake(uncore))
2182 return 0;
2183
2184 if (op & FW_REG_READ)
2185 fw_domains = uncore->funcs.read_fw_domains(uncore, reg);
2186
2187 if (op & FW_REG_WRITE)
2188 fw_domains |= uncore->funcs.write_fw_domains(uncore, reg);
2189
2190 drm_WARN_ON(&uncore->i915->drm, fw_domains & ~uncore->fw_domains);
2191
2192 return fw_domains;
2193 }
2194
2195 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2196 #include "selftests/mock_uncore.c"
2197 #include "selftests/intel_uncore.c"
2198 #endif
2199