1 /******************************************************************************
2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3 * All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************/
18
19 #ifndef DRIVERS_B91_EXT_MISC_H_
20 #define DRIVERS_B91_EXT_MISC_H_
21
22 #include "nds_intrinsic.h"
23
24 #include "../analog.h"
25 #include "../clock.h"
26 #include "../dma.h"
27 #include "../flash.h"
28 #include "../gpio.h"
29 #include "../mdec.h"
30 #include "../plic.h"
31 #include "../pm.h"
32 #include "../stimer.h"
33 #include "../sys.h"
34 #include "../timer.h"
35 #include "../trng.h"
36 #include "../uart.h"
37 #include "compiler.h"
38 #include "types.h"
39
40 /* for debug */
41 #define DBG_SRAM_ADDR 0x00014
42
43 /*
44 * addr - only 0x00012 ~ 0x00021 can be used !!! */
45 #define write_dbg32(addr, value) write_sram32(addr, value)
46
47 #define write_log32(err_code) write_sram32(0x00014, err_code)
48
49 /******************************* stimer_start ******************************************************************/
50 #define SYSTICK_NUM_PER_US 16
51 #define reg_system_tick_irq reg_system_irq_level
52
53 typedef enum {
54 STIMER_IRQ_MASK = BIT(0),
55 STIMER_32K_CAL_IRQ_MASK = BIT(1),
56 } stimer_irq_mask_e;
57
58 typedef enum {
59 FLD_IRQ_SYSTEM_TIMER = BIT(0),
60 } system_timer_irq_mask_e;
61
62 typedef enum {
63 STIMER_IRQ_CLR = BIT(0),
64 STIMER_32K_CAL_IRQ_CLR = BIT(1),
65 } stimer_irq_clr_e;
66
67 /**
68 * @brief This function serves to enable system timer interrupt.
69 * @return none
70 */
systimer_irq_enable(void)71 static inline void systimer_irq_enable(void)
72 {
73 reg_irq_src0 |= BIT(IRQ1_SYSTIMER);
74 }
75
76 /**
77 * @brief This function serves to disable system timer interrupt.
78 * @return none
79 */
systimer_irq_disable(void)80 static inline void systimer_irq_disable(void)
81 {
82 reg_irq_src0 &= ~BIT(IRQ1_SYSTIMER);
83 }
84
systimer_set_irq_mask(void)85 static inline void systimer_set_irq_mask(void)
86 {
87 reg_system_irq_mask |= STIMER_IRQ_MASK;
88 }
89
systimer_clr_irq_mask(void)90 static inline void systimer_clr_irq_mask(void)
91 {
92 reg_system_irq_mask &= (~STIMER_IRQ_MASK);
93 }
94
systimer_get_irq_status(void)95 static inline unsigned char systimer_get_irq_status(void)
96 {
97 return reg_system_cal_irq & FLD_IRQ_SYSTEM_TIMER;
98 }
99
systimer_clr_irq_status(void)100 static inline void systimer_clr_irq_status(void)
101 {
102 reg_system_cal_irq = STIMER_IRQ_CLR;
103 }
104
systimer_set_irq_capture(unsigned int tick)105 static inline void systimer_set_irq_capture(unsigned int tick)
106 {
107 reg_system_irq_level = tick;
108 }
109
systimer_get_irq_capture(void)110 static inline unsigned int systimer_get_irq_capture(void)
111 {
112 return reg_system_irq_level;
113 }
114
tick1_exceed_tick2(unsigned int tick1,unsigned int tick2)115 static inline int tick1_exceed_tick2(unsigned int tick1, unsigned int tick2)
116 {
117 return (unsigned int)(tick1 - tick2) < BIT(30);
118 }
119 /******************************* stimer_end ********************************************************************/
120
121 /******************************* aes_start ******************************************************************/
122 extern unsigned int aes_data_buff[8];
123 /******************************* aes_end ********************************************************************/
124
125 /******************************* core_start ******************************************************************/
126 #define irq_disable core_interrupt_disable
127 #define irq_enable core_interrupt_enable
128 #define irq_restore(en) core_restore_interrupt(en)
129 /******************************* core_end ********************************************************************/
130
131 /******************************* analog_start ******************************************************************/
132 #define analog_write analog_write_reg8
133 #define analog_read analog_read_reg8
134
135 /******************************* analog_end ********************************************************************/
136
137 /******************************* clock_start ******************************************************************/
138 typedef enum {
139 SYSCLK_16M = 16,
140 SYSCLK_24M = 24,
141 SYSCLK_32M = 32,
142 SYSCLK_48M = 48,
143 SYSCLK_64M = 64,
144 } sys_clk_fre_t;
145
clock_get_system_clk(void)146 static inline unsigned char clock_get_system_clk(void)
147 {
148 return sys_clk.cclk;
149 }
150 /******************************* clock_end ********************************************************************/
151
152 /******************************* trng_start ******************************************************************/
153 #define rand trng_rand
154 #define random_generator_init trng_init
155
156 /**
157 * @brief This function performs to generate a series of random numbers
158 * @param[in] len - data length
159 * @param[out] data - data pointer
160 * @return none
161 **/
162 void generateRandomNum(int len, unsigned char *data);
163
164 /******************************* trng_end ********************************************************************/
165
166 /******************************* sys_start ******************************************************************/
167 #define sleep_us(x) delay_us(x)
168 #define sleep_ms(x) delay_ms(x)
169
170 /******************************* sys_end ********************************************************************/
171
172 /******************************* dma_start ***************************************************************/
173
174 /**
175 * @brief ACL RX Data buffer length = maxRxOct + 21, then 16 Byte align
176 * maxRxOct + 21 = 4(DMA_len) + 2(BLE header) + maxRxOct + 4(MIC) + 3(CRC) + 8(ExtraInfor)
177 RX buffer size must be be 16*n, due to MCU design
178 */
179 #define CAL_LL_ACL_RX_FIFO_SIZE(maxRxOct) ((((maxRxOct) + 21) + 15) / 16 * 16)
180
181 /**
182 * @brief ACL TX Data buffer length = maxTxOct + 10, then 16 Byte align
183 * maxTxOct + 10 = 4(DMA_len) + 2(BLE header) + maxTxOct + 4(MIC)
184 TX buffer size must be be 16*n, due to MCU design
185 */
186 #define CAL_LL_ACL_TX_FIFO_SIZE(maxTxOct) ((((maxTxOct) + 10) + 15) / 16 * 16)
187
188 /* HCI TX RX buffer len = uart_fifo+ dma 4byte */
189 #define HCI_FIFO_SIZE(n) ((((n) + 2 + 4) + 15) / 16 * 16)
190
191 /*
192 * @brief ISO RX Data buffer length = ISORxOct + 21, then 16 Byte align
193 * ISORxOct + 21 = 4(DMA_len) + 2(BLE header) + ISORxOct + 4(MIC) + 3(CRC) + 8(ExtraInfor)
194 * RX buffer size must be be 16*n, due to MCU design
195 */
196 #define CAL_LL_ISO_RX_FIFO_SIZE(n) ((((n) + 21) + 15) / 16 * 16)
197
198 /*
199 * @brief ISO TX Data buffer length = ISOTxOct + 10, then 16 Byte align
200 * ISORxOct + 10 = 4(DMA_len) + 2(BLE header) + ISOTxOct + 4(MIC)
201 * TX buffer size must be be 16*n, due to MCU design
202 */
203 #define CAL_LL_ISO_TX_FIFO_SIZE(n) ((((n) + 10) + 15) / 16 * 16)
204
205 /*
206 * DMA_LEN(4B)+Hdr(2B)+PLD(251B)+MIC(4B)+CRC(3B)+TLK_PKT_INFO(12B)
207 * **use 2B enough**
208 */
209 #define ISO_BIS_RX_PDU_SIZE_ALLIGN16(n) ((((n) + 25) + 15) / 16 * 16) // 4+2+4+2+4+3+12
210
211 // 12 = 4(struct bis_rx_pdu_tag *next) + 4(u32 payloadNum) + 4(u32 idealPldAnchorTick) in bis_rx_pdu_t
212 #define BIS_LL_RX_PDU_FIFO_SIZE(n) (CAL_LL_ISO_RX_FIFO_SIZE(n) + 12)
213
214 /******************************* dma_end ********************************************************************/
215
216 /******************************* plic_start ******************************************************************/
217 enum { // todo
218 FLD_IRQ_EXCEPTION_EN,
219 FLD_IRQ_SYSTIMER_EN,
220 FLD_IRQ_ALG_EN,
221 FLD_IRQ_TIMER1_EN,
222 FLD_IRQ_TIMER0_EN,
223 FLD_IRQ_DMA_EN,
224 FLD_IRQ_BMC_EN,
225 FLD_IRQ_USB_CTRL_EP_SETUP_EN,
226 FLD_IRQ_USB_CTRL_EP_DATA_EN,
227 FLD_IRQ_USB_CTRL_EP_STATUS_EN,
228 FLD_IRQ_USB_CTRL_EP_SETINF_EN,
229 FLD_IRQ_USB_ENDPOINT_EN,
230 FLD_IRQ_ZB_DM_EN,
231 FLD_IRQ_ZB_BLE_EN,
232 FLD_IRQ_ZB_BT_EN,
233 FLD_IRQ_ZB_RT_EN,
234 FLD_IRQ_PWM_EN,
235 FLD_IRQ_PKE_EN, // add
236 FLD_IRQ_UART1_EN,
237 FLD_IRQ_UART0_EN,
238 FLD_IRQ_DFIFO_EN,
239 FLD_IRQ_I2C_EN,
240 FLD_IRQ_SPI_APB_EN,
241 FLD_IRQ_USB_PWDN_EN,
242 FLD_IRQ_EN,
243 FLD_IRQ_GPIO2RISC0_EN,
244 FLD_IRQ_GPIO2RISC1_EN,
245 FLD_IRQ_SOFT_EN,
246
247 FLD_IRQ_NPE_BUS0_EN,
248 FLD_IRQ_NPE_BUS1_EN,
249 FLD_IRQ_NPE_BUS2_EN,
250 FLD_IRQ_NPE_BUS3_EN,
251 FLD_IRQ_NPE_BUS4_EN,
252
253 FLD_IRQ_USB_250US_EN,
254 FLD_IRQ_USB_RESET_EN,
255 FLD_IRQ_NPE_BUS7_EN,
256 FLD_IRQ_NPE_BUS8_EN,
257
258 FLD_IRQ_NPE_BUS13_EN = 42,
259 FLD_IRQ_NPE_BUS14_EN,
260 FLD_IRQ_NPE_BUS15_EN,
261
262 FLD_IRQ_NPE_BUS17_EN = 46,
263
264 FLD_IRQ_NPE_BUS21_EN = 50,
265 FLD_IRQ_NPE_BUS22_EN,
266 FLD_IRQ_NPE_BUS23_EN,
267 FLD_IRQ_NPE_BUS24_EN,
268 FLD_IRQ_NPE_BUS25_EN,
269 FLD_IRQ_NPE_BUS26_EN,
270 FLD_IRQ_NPE_BUS27_EN,
271 FLD_IRQ_NPE_BUS28_EN,
272 FLD_IRQ_NPE_BUS29_EN,
273 FLD_IRQ_NPE_BUS30_EN,
274 FLD_IRQ_NPE_BUS31_EN,
275
276 FLD_IRQ_NPE_COMB_EN,
277 FLD_IRQ_PM_TM_EN,
278 FLD_IRQ_EOC_EN,
279 };
280
281 /******************************* plic_end ********************************************************************/
282
283 /******************************* flash_start *****************************************************************/
284 /**
285 * @brief flash capacity definition
286 * Call flash_read_mid function to get the size of flash capacity.
287 * Example is as follows:
288 * unsigned char temp_buf[4];
289 * flash_read_mid(temp_buf);
290 * The value of temp_buf[2] reflects flash capacity.
291 */
292 typedef enum {
293 FLASH_CAPACITY_64K = 0x10,
294 FLASH_CAPACITY_128K = 0x11,
295 FLASH_CAPACITY_256K = 0x12,
296 FLASH_CAPACITY_512K = 0x13,
297 FLASH_CAPACITY_1M = 0x14,
298 FLASH_CAPACITY_2M = 0x15,
299 FLASH_CAPACITY_4M = 0x16,
300 FLASH_CAPACITY_8M = 0x17,
301 } Flash_CapacityDef;
302 void flash_set_capacity(Flash_CapacityDef flash_cap);
303 Flash_CapacityDef flash_get_capacity(void);
304
305 /******************************* flash_end *******************************************************************/
306
307 /******************************* usb_end *********************************************************************/
308 #define reg_usb_irq REG_ADDR8(0x100839)
309 /******************************* usb_end *********************************************************************/
310
311 /******************************* core_start ******************************************************************/
312 #define SUPPORT_PFT_ARCH 0
313 /******************************* core_end ********************************************************************/
314
315 /******************************* uart_start ******************************************************************/
316 _attribute_ram_code_ void uart_receive_dma_set(dma_chn_e chn, unsigned char *addr, unsigned int rev_size);
317
318 void uart0_init(unsigned int baudrate);
319 /******************************* uart_end ********************************************************************/
320
321 #endif /* DRIVERS_B91_EXT_MISC_H_ */
322