1 /*
2 * Copyright (C) 2017-2018 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 /* 500 gets us LDIB but doesn't change any other a4xx instructions */
28 #define GPU 500
29
30 #include "ir3_context.h"
31 #include "ir3_image.h"
32
33 /* SSBO data is available at this CB address, addressed like regular consts
34 * containing the following data in each vec4:
35 *
36 * [ base address, pitch, array_pitch, cpp ]
37 *
38 * These mirror the values uploaded to A4XX_SSBO_0 state. For A5XX, these are
39 * uploaded manually by the driver.
40 */
41 #define A4XX_SSBO_CB_BASE(i) (0x700 + ((i) << 2))
42
43 /*
44 * Handlers for instructions changed/added in a4xx:
45 */
46
47 /* Convert byte offset to address of appropriate width for GPU */
48 static struct ir3_instruction *
byte_offset_to_address(struct ir3_context * ctx,nir_src * ssbo,struct ir3_instruction * byte_offset)49 byte_offset_to_address(struct ir3_context *ctx,
50 nir_src *ssbo,
51 struct ir3_instruction *byte_offset)
52 {
53 struct ir3_block *b = ctx->block;
54
55 if (ctx->compiler->gen == 4) {
56 uint32_t index = nir_src_as_uint(*ssbo);
57 unsigned cb = A4XX_SSBO_CB_BASE(index);
58 byte_offset = ir3_ADD_U(b, create_uniform(b, cb), 0, byte_offset, 0);
59 }
60
61 if (fd_dev_64b(ctx->compiler->dev_id)) {
62 return ir3_collect(b, byte_offset, create_immed(b, 0));
63 } else {
64 return byte_offset;
65 }
66 }
67
68 /* src[] = { buffer_index, offset }. No const_index */
69 static void
emit_intrinsic_load_ssbo(struct ir3_context * ctx,nir_intrinsic_instr * intr,struct ir3_instruction ** dst)70 emit_intrinsic_load_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
71 struct ir3_instruction **dst)
72 {
73 struct ir3_block *b = ctx->block;
74 struct ir3_instruction *ldgb, *src0, *src1, *byte_offset, *offset;
75
76 struct ir3_instruction *ssbo = ir3_ssbo_to_ibo(ctx, intr->src[0]);
77
78 byte_offset = ir3_get_src(ctx, &intr->src[1])[0];
79 offset = ir3_get_src(ctx, &intr->src[2])[0];
80
81 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
82 src0 = byte_offset_to_address(ctx, &intr->src[0], byte_offset);
83 src1 = offset;
84
85 ldgb = ir3_LDGB(b, ssbo, 0, src0, 0, src1, 0);
86 ldgb->dsts[0]->wrmask = MASK(intr->num_components);
87 ldgb->cat6.iim_val = intr->num_components;
88 ldgb->cat6.d = 4;
89 ldgb->cat6.type = TYPE_U32;
90 ldgb->barrier_class = IR3_BARRIER_BUFFER_R;
91 ldgb->barrier_conflict = IR3_BARRIER_BUFFER_W;
92
93 ir3_split_dest(b, dst, ldgb, 0, intr->num_components);
94 }
95
96 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
97 static void
emit_intrinsic_store_ssbo(struct ir3_context * ctx,nir_intrinsic_instr * intr)98 emit_intrinsic_store_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
99 {
100 struct ir3_block *b = ctx->block;
101 struct ir3_instruction *stgb, *src0, *src1, *src2, *byte_offset, *offset;
102 unsigned wrmask = nir_intrinsic_write_mask(intr);
103 unsigned ncomp = ffs(~wrmask) - 1;
104
105 assert(wrmask == BITFIELD_MASK(intr->num_components));
106
107 struct ir3_instruction *ssbo = ir3_ssbo_to_ibo(ctx, intr->src[1]);
108
109 byte_offset = ir3_get_src(ctx, &intr->src[2])[0];
110 offset = ir3_get_src(ctx, &intr->src[3])[0];
111
112 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
113 * nir already *= 4:
114 */
115 src0 = ir3_create_collect(b, ir3_get_src(ctx, &intr->src[0]), ncomp);
116 src1 = offset;
117 src2 = byte_offset_to_address(ctx, &intr->src[1], byte_offset);
118
119 stgb = ir3_STGB(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
120 stgb->cat6.iim_val = ncomp;
121 stgb->cat6.d = 4;
122 stgb->cat6.type = TYPE_U32;
123 stgb->barrier_class = IR3_BARRIER_BUFFER_W;
124 stgb->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
125
126 array_insert(b, b->keeps, stgb);
127 }
128
129 /*
130 * SSBO atomic intrinsics
131 *
132 * All of the SSBO atomic memory operations read a value from memory,
133 * compute a new value using one of the operations below, write the new
134 * value to memory, and return the original value read.
135 *
136 * All operations take 3 sources except CompSwap that takes 4. These
137 * sources represent:
138 *
139 * 0: The SSBO buffer index.
140 * 1: The byte offset into the SSBO buffer of the variable that the atomic
141 * operation will operate on.
142 * 2: The data parameter to the atomic function (i.e. the value to add
143 * in ssbo_atomic_add, etc).
144 * 3: CompSwap: the second data parameter.
145 * Non-CompSwap: The dword offset into the SSBO buffer variable.
146 * 4: CompSwap: The dword offset into the SSBO buffer variable.
147 *
148 * We use custom ssbo_*_ir3 intrinsics generated by ir3_nir_lower_io_offsets()
149 * so we can have the dword offset generated in NIR.
150 */
151 static struct ir3_instruction *
emit_intrinsic_atomic_ssbo(struct ir3_context * ctx,nir_intrinsic_instr * intr)152 emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
153 {
154 struct ir3_block *b = ctx->block;
155 struct ir3_instruction *atomic;
156 type_t type = TYPE_U32;
157
158 struct ir3_instruction *ssbo = ir3_ssbo_to_ibo(ctx, intr->src[0]);
159
160 struct ir3_instruction *data = ir3_get_src(ctx, &intr->src[2])[0];
161 /* 64b byte offset */
162 struct ir3_instruction *byte_offset =
163 byte_offset_to_address(ctx, &intr->src[0], ir3_get_src(ctx, &intr->src[1])[0]);
164 /* dword offset for everything but comp_swap */
165 struct ir3_instruction *src3 = ir3_get_src(ctx, &intr->src[3])[0];
166
167 switch (intr->intrinsic) {
168 case nir_intrinsic_ssbo_atomic_add_ir3:
169 atomic = ir3_ATOMIC_S_ADD(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
170 break;
171 case nir_intrinsic_ssbo_atomic_imin_ir3:
172 atomic = ir3_ATOMIC_S_MIN(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
173 type = TYPE_S32;
174 break;
175 case nir_intrinsic_ssbo_atomic_umin_ir3:
176 atomic = ir3_ATOMIC_S_MIN(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
177 break;
178 case nir_intrinsic_ssbo_atomic_imax_ir3:
179 atomic = ir3_ATOMIC_S_MAX(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
180 type = TYPE_S32;
181 break;
182 case nir_intrinsic_ssbo_atomic_umax_ir3:
183 atomic = ir3_ATOMIC_S_MAX(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
184 break;
185 case nir_intrinsic_ssbo_atomic_and_ir3:
186 atomic = ir3_ATOMIC_S_AND(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
187 break;
188 case nir_intrinsic_ssbo_atomic_or_ir3:
189 atomic = ir3_ATOMIC_S_OR(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
190 break;
191 case nir_intrinsic_ssbo_atomic_xor_ir3:
192 atomic = ir3_ATOMIC_S_XOR(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
193 break;
194 case nir_intrinsic_ssbo_atomic_exchange_ir3:
195 atomic = ir3_ATOMIC_S_XCHG(b, ssbo, 0, data, 0, src3, 0, byte_offset, 0);
196 break;
197 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
198 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
199 data = ir3_collect(b, src3, data);
200 struct ir3_instruction *dword_offset = ir3_get_src(ctx, &intr->src[4])[0];
201 atomic = ir3_ATOMIC_S_CMPXCHG(b, ssbo, 0, data, 0, dword_offset, 0,
202 byte_offset, 0);
203 break;
204 default:
205 unreachable("boo");
206 }
207
208 atomic->cat6.iim_val = 1;
209 atomic->cat6.d = 4;
210 atomic->cat6.type = type;
211 atomic->barrier_class = IR3_BARRIER_BUFFER_W;
212 atomic->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
213
214 /* even if nothing consume the result, we can't DCE the instruction: */
215 array_insert(b, b->keeps, atomic);
216
217 return atomic;
218 }
219
220 static struct ir3_instruction *
get_image_offset(struct ir3_context * ctx,const nir_intrinsic_instr * instr,struct ir3_instruction * const * coords,bool byteoff)221 get_image_offset(struct ir3_context *ctx, const nir_intrinsic_instr *instr,
222 struct ir3_instruction *const *coords, bool byteoff)
223 {
224 struct ir3_block *b = ctx->block;
225 struct ir3_instruction *offset;
226 unsigned index = nir_src_as_uint(instr->src[0]);
227 unsigned ncoords = ir3_get_image_coords(instr, NULL);
228
229 /* to calculate the byte offset (yes, uggg) we need (up to) three
230 * const values to know the bytes per pixel, and y and z stride:
231 */
232 unsigned cb;
233 if (ctx->compiler->gen > 4) {
234 const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
235 assert(const_state->image_dims.mask & (1 << index));
236
237 cb = regid(const_state->offsets.image_dims, 0) +
238 const_state->image_dims.off[index];
239 } else {
240 index += ctx->s->info.num_ssbos;
241 cb = A4XX_SSBO_CB_BASE(index);
242 }
243
244 /* offset = coords.x * bytes_per_pixel: */
245 if (ctx->compiler->gen == 4)
246 offset = ir3_MUL_S24(b, coords[0], 0, create_uniform(b, cb + 3), 0);
247 else
248 offset = ir3_MUL_S24(b, coords[0], 0, create_uniform(b, cb + 0), 0);
249 if (ncoords > 1) {
250 /* offset += coords.y * y_pitch: */
251 offset =
252 ir3_MAD_S24(b, create_uniform(b, cb + 1), 0, coords[1], 0, offset, 0);
253 }
254 if (ncoords > 2) {
255 /* offset += coords.z * z_pitch: */
256 offset =
257 ir3_MAD_S24(b, create_uniform(b, cb + 2), 0, coords[2], 0, offset, 0);
258 }
259
260 /* a4xx: must add in the base address: */
261 if (ctx->compiler->gen == 4)
262 offset = ir3_ADD_U(b, offset, 0, create_uniform(b, cb + 0), 0);
263
264 if (!byteoff) {
265 /* Some cases, like atomics, seem to use dword offset instead
266 * of byte offsets.. blob just puts an extra shr.b in there
267 * in those cases:
268 */
269 offset = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
270 }
271
272 if (fd_dev_64b(ctx->compiler->dev_id))
273 return ir3_collect(b, offset, create_immed(b, 0));
274 else
275 return offset;
276 }
277
278 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
279 static void
emit_intrinsic_load_image(struct ir3_context * ctx,nir_intrinsic_instr * intr,struct ir3_instruction ** dst)280 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
281 struct ir3_instruction **dst)
282 {
283 struct ir3_block *b = ctx->block;
284 struct ir3_instruction *const *coords = ir3_get_src(ctx, &intr->src[1]);
285 struct ir3_instruction *ibo = ir3_image_to_ibo(ctx, intr->src[0]);
286 struct ir3_instruction *offset = get_image_offset(ctx, intr, coords, true);
287 unsigned ncoords = ir3_get_image_coords(intr, NULL);
288 unsigned ncomp =
289 ir3_get_num_components_for_image_format(nir_intrinsic_format(intr));
290
291 struct ir3_instruction *ldib;
292 /* At least A420 does not have LDIB. Use LDGB and perform conversion
293 * ourselves.
294 *
295 * TODO: Actually do the conversion. ES 3.1 only requires this for
296 * single-component 32-bit types anyways.
297 */
298 if (ctx->compiler->gen > 4) {
299 ldib = ir3_LDIB(
300 b, ibo, 0, offset, 0, ir3_create_collect(b, coords, ncoords), 0);
301 } else {
302 ldib = ir3_LDGB(
303 b, ibo, 0, offset, 0, ir3_create_collect(b, coords, ncoords), 0);
304 switch (nir_intrinsic_format(intr)) {
305 case PIPE_FORMAT_R32_UINT:
306 case PIPE_FORMAT_R32_SINT:
307 case PIPE_FORMAT_R32_FLOAT:
308 break;
309 default:
310 /* For some reason even more 32-bit components don't work. */
311 assert(0);
312 break;
313 }
314 }
315 ldib->dsts[0]->wrmask = MASK(intr->num_components);
316 ldib->cat6.iim_val = ncomp;
317 ldib->cat6.d = ncoords;
318 ldib->cat6.type = ir3_get_type_for_image_intrinsic(intr);
319 ldib->cat6.typed = true;
320 ldib->barrier_class = IR3_BARRIER_IMAGE_R;
321 ldib->barrier_conflict = IR3_BARRIER_IMAGE_W;
322
323 ir3_split_dest(b, dst, ldib, 0, intr->num_components);
324 }
325
326 /* src[] = { index, coord, sample_index, value }. const_index[] = {} */
327 static void
emit_intrinsic_store_image(struct ir3_context * ctx,nir_intrinsic_instr * intr)328 emit_intrinsic_store_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
329 {
330 struct ir3_block *b = ctx->block;
331 struct ir3_instruction *stib, *offset;
332 struct ir3_instruction *const *value = ir3_get_src(ctx, &intr->src[3]);
333 struct ir3_instruction *const *coords = ir3_get_src(ctx, &intr->src[1]);
334 struct ir3_instruction *ibo = ir3_image_to_ibo(ctx, intr->src[0]);
335 unsigned ncoords = ir3_get_image_coords(intr, NULL);
336 unsigned ncomp =
337 ir3_get_num_components_for_image_format(nir_intrinsic_format(intr));
338
339 /* src0 is value
340 * src1 is coords
341 * src2 is 64b byte offset
342 */
343
344 offset = get_image_offset(ctx, intr, coords, true);
345
346 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
347 * too and takes a dword offset.. not quite sure yet why blob uses
348 * one over the other in various cases.
349 */
350
351 stib = ir3_STIB(b, ibo, 0, ir3_create_collect(b, value, ncomp), 0,
352 ir3_create_collect(b, coords, ncoords), 0, offset, 0);
353 stib->cat6.iim_val = ncomp;
354 stib->cat6.d = ncoords;
355 stib->cat6.type = ir3_get_type_for_image_intrinsic(intr);
356 stib->cat6.typed = true;
357 stib->barrier_class = IR3_BARRIER_IMAGE_W;
358 stib->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
359
360 array_insert(b, b->keeps, stib);
361 }
362
363 /* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */
364 static struct ir3_instruction *
emit_intrinsic_atomic_image(struct ir3_context * ctx,nir_intrinsic_instr * intr)365 emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
366 {
367 struct ir3_block *b = ctx->block;
368 struct ir3_instruction *atomic, *src0, *src1, *src2;
369 struct ir3_instruction *const *coords = ir3_get_src(ctx, &intr->src[1]);
370 struct ir3_instruction *image = ir3_image_to_ibo(ctx, intr->src[0]);
371 unsigned ncoords = ir3_get_image_coords(intr, NULL);
372
373 /* src0 is value (or uvec2(value, compare))
374 * src1 is coords
375 * src2 is 64b byte offset
376 */
377 src0 = ir3_get_src(ctx, &intr->src[3])[0];
378 src1 = ir3_create_collect(b, coords, ncoords);
379 src2 = get_image_offset(ctx, intr, coords, ctx->compiler->gen == 4);
380
381 switch (intr->intrinsic) {
382 case nir_intrinsic_image_atomic_add:
383 atomic = ir3_ATOMIC_S_ADD(b, image, 0, src0, 0, src1, 0, src2, 0);
384 break;
385 case nir_intrinsic_image_atomic_imin:
386 case nir_intrinsic_image_atomic_umin:
387 atomic = ir3_ATOMIC_S_MIN(b, image, 0, src0, 0, src1, 0, src2, 0);
388 break;
389 case nir_intrinsic_image_atomic_imax:
390 case nir_intrinsic_image_atomic_umax:
391 atomic = ir3_ATOMIC_S_MAX(b, image, 0, src0, 0, src1, 0, src2, 0);
392 break;
393 case nir_intrinsic_image_atomic_and:
394 atomic = ir3_ATOMIC_S_AND(b, image, 0, src0, 0, src1, 0, src2, 0);
395 break;
396 case nir_intrinsic_image_atomic_or:
397 atomic = ir3_ATOMIC_S_OR(b, image, 0, src0, 0, src1, 0, src2, 0);
398 break;
399 case nir_intrinsic_image_atomic_xor:
400 atomic = ir3_ATOMIC_S_XOR(b, image, 0, src0, 0, src1, 0, src2, 0);
401 break;
402 case nir_intrinsic_image_atomic_exchange:
403 atomic = ir3_ATOMIC_S_XCHG(b, image, 0, src0, 0, src1, 0, src2, 0);
404 break;
405 case nir_intrinsic_image_atomic_comp_swap:
406 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
407 src0 = ir3_collect(b, ir3_get_src(ctx, &intr->src[4])[0], src0);
408 atomic = ir3_ATOMIC_S_CMPXCHG(b, image, 0, src0, 0, src1, 0, src2, 0);
409 break;
410 default:
411 unreachable("boo");
412 }
413
414 atomic->cat6.iim_val = 1;
415 atomic->cat6.d = ncoords;
416 atomic->cat6.type = ir3_get_type_for_image_intrinsic(intr);
417 atomic->cat6.typed = ctx->compiler->gen == 5;
418 atomic->barrier_class = IR3_BARRIER_IMAGE_W;
419 atomic->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
420
421 /* even if nothing consume the result, we can't DCE the instruction: */
422 array_insert(b, b->keeps, atomic);
423
424 return atomic;
425 }
426
427 static struct ir3_instruction *
emit_intrinsic_atomic_global(struct ir3_context * ctx,nir_intrinsic_instr * intr)428 emit_intrinsic_atomic_global(struct ir3_context *ctx, nir_intrinsic_instr *intr)
429 {
430 unreachable("Global atomic are unimplemented on A5xx");
431 }
432
433 const struct ir3_context_funcs ir3_a4xx_funcs = {
434 .emit_intrinsic_load_ssbo = emit_intrinsic_load_ssbo,
435 .emit_intrinsic_store_ssbo = emit_intrinsic_store_ssbo,
436 .emit_intrinsic_atomic_ssbo = emit_intrinsic_atomic_ssbo,
437 .emit_intrinsic_load_image = emit_intrinsic_load_image,
438 .emit_intrinsic_store_image = emit_intrinsic_store_image,
439 .emit_intrinsic_atomic_image = emit_intrinsic_atomic_image,
440 .emit_intrinsic_image_size = emit_intrinsic_image_size_tex,
441 .emit_intrinsic_load_global_ir3 = NULL,
442 .emit_intrinsic_store_global_ir3 = NULL,
443 .emit_intrinsic_atomic_global = emit_intrinsic_atomic_global,
444 };
445