1 /* 2 * Copyright (c) 2021 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef HPM_ENET_DRV_H 9 #define HPM_ENET_DRV_H 10 11 /*--------------------------------------------------------------------- 12 * Includes 13 *--------------------------------------------------------------------- 14 */ 15 #include "hpm_common.h" 16 #include "hpm_enet_regs.h" 17 #include "hpm_soc_feature.h" 18 #include "hpm_enet_soc_drv.h" 19 20 /** 21 * @brief Enet driver APIs 22 * @defgroup enet_interface Enet driver APIs 23 * @ingroup communication_interfaces 24 * @{ 25 */ 26 27 /*--------------------------------------------------------------------- 28 * Macro Constant Declarations 29 *--------------------------------------------------------------------- 30 */ 31 #define ENET_HEADER (14U) /**< 6-byte Dest addr, 6-byte Src addr, 2-byte type */ 32 #define ENET_EXTRA (2U) /**< Extra bytes in some cases */ 33 #define ENET_VLAN_TAG (4U) /**< optional 802.1q VLAN Tag */ 34 #define ENET_CRC (4U) /**< Ethernet CRC */ 35 #define ENET_MIN_PAYLOAD (46U) /**< Minimum Ethernet payload size */ 36 #define ENET_MAX_PAYLOAD (1500U) /**< Maximum Ethernet payload size */ 37 #define ENET_MAX_FRAME_SIZE (1524U) /**< ENET_HEADER + ENET_EXTRA + VLAN_TAG + MAX_ENET_PAYLOAD + ENET_CRC */ 38 #define ENET_JUMBO_FRAME_PAYLOAD (9000U) /**< Jumbo frame payload size */ 39 40 #define ENET_ERROR (0) /**< ENET error */ 41 #define ENET_SUCCESS (1) /**< ENET success */ 42 43 #define ENET_ADJ_FREQ_BASE_ADDEND (0x7fffffffUL) /**< PTP base adjustment addend */ 44 #define ENET_ONE_SEC_IN_NANOSEC (1000000000UL) /**< one second in nanoseconds */ 45 /*--------------------------------------------------------------------- 46 * Typedef Enum Declarations 47 *--------------------------------------------------------------------- 48 */ 49 /** @brief Programmable burst length selections */ 50 typedef enum { 51 enet_pbl_1 = 1, 52 enet_pbl_2 = 2, 53 enet_pbl_4 = 4, 54 enet_pbl_8 = 8, 55 enet_pbl_16 = 16, 56 enet_pbl_32 = 32 57 } enet_pbl_t; 58 59 /** @brief Checksum insertion control selections */ 60 typedef enum { 61 enet_cic_bypass = 0, 62 enet_cic_insert_ipv4_header, 63 enet_cic_insert_tcp_udp_icmp, 64 enet_cic_insert_tcp_upd_icmp, 65 } enet_insert_t; 66 67 /** @brief PHY opeartion selections */ 68 typedef enum { 69 enet_phy_op_read = 0, 70 enet_phy_op_write 71 } enet_phy_op_t; 72 73 74 /** @brief PHY status */ 75 typedef enum { 76 enet_phy_idle = 0, 77 enet_phy_busy 78 } enet_phy_status_t; 79 80 /** @brief CSR clock range and MDC clock selections */ 81 /** @note The suggested range of CSR clock is approximately 82 * between the frequency range 1.0MHz-2.5MHz. 83 * You can achieve higher frequency of the MDC clock than the frequency limit of 2.5MHz(specified in the IEEE Std 802.3) 84 * and program a clock divider of lower value. Program the value which is no less than enet_csr_60m_to_100m_mdc_csr_div_4 85 * only if the interfacing chips support faster MDC clocks. 86 */ 87 typedef enum { 88 enet_csr_60m_to_100m_mdc_csr_div_42 = 0, /**< CSR clock range: 60-100MHz <==> MDC clock: CSR clock / 42 */ 89 enet_csr_100m_to_150m_mdc_csr_div_62, /**< CSR clock range: 100-150MHz <==> MDC clock: CSR clock / 62 */ 90 enet_csr_20m_to_35m_mdc_csr_div_16, /**< CSR clock range: 20-35MHz <==> MDC clock: CSR clock / 16 */ 91 enet_csr_35m_to_60m_mdc_csr_div_26, /**< CSR clock range: 35-60MHz <==> MDC clock: CSR clock / 26 */ 92 enet_csr_150m_to_250m_mdc_csr_div_102, /**< CSR clock range: 150-250MHz <==> MDC clock: CSR clock / 102 */ 93 enet_csr_250m_to_300m_mdc_csr_div_124, /**< CSR clock range: 250-300MHz <==> MDC clock: CSR clock / 124 */ 94 95 enet_csr_60m_to_100m_mdc_csr_div_4 = 8, /**< CSR clock / 4 */ 96 enet_csr_60m_to_100m_mdc_csr_div_6, /**< CSR clock / 6 */ 97 enet_csr_60m_to_100m_mdc_csr_div_8, /**< CSR clock / 8 */ 98 enet_csr_60m_to_100m_mdc_csr_div_10, /**< CSR clock / 10 */ 99 enet_csr_60m_to_100m_mdc_csr_div_12, /**< CSR clock / 12 */ 100 enet_csr_60m_to_100m_mdc_csr_div_14, /**< CSR clock / 14 */ 101 enet_csr_60m_to_100m_mdc_csr_div_16, /**< CSR clock / 16 */ 102 enet_csr_60m_to_100m_mdc_csr_div_18 /**< CSR clock / 18 */ 103 } enet_csr_clk_range_t; 104 105 /** @brief enet interface selections */ 106 typedef enum { 107 enet_inf_rmii = 4, 108 enet_inf_rgmii = 1 109 } enet_inf_type_t; 110 111 /** @brief enet timestamp update methods */ 112 typedef enum { 113 enet_ptp_time_coarse_update = 0, 114 enet_ptp_time_fine_update 115 } enet_ptp_time_update_method_t; 116 117 /** @brief PTP versions */ 118 typedef enum { 119 enet_ptp_v1 = 0, 120 enet_ptp_v2 121 } enet_ptp_version_t; 122 123 /** @brief PTP frame types */ 124 typedef enum { 125 enet_ptp_frame_ipv4 = 0, 126 enet_ptp_frame_ipv6, 127 enet_ptp_frame_ethernet 128 } enet_ptp_frame_type_t; 129 130 /** @brief PTP message type for snapshots */ 131 typedef enum { 132 enet_ts_ss_ptp_msg_0 = 0, /* SYNC, Follow_Up, Delay_Req, Delay_Resp */ 133 enet_ts_ss_ptp_msg_1 = 1, /* SYNC */ 134 enet_ts_ss_ptp_msg_2 = 3, /* Delay_Req */ 135 enet_ts_ss_ptp_msg_3 = 4, /* SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp, Pdelay_Resp_Follow_Up */ 136 enet_ts_ss_ptp_msg_4 = 5, /* SYNC, Pdelay_Req, Pdelay_Resp */ 137 enet_ts_ss_ptp_msg_5 = 7, /* Delay_Req, Pdelay_Req, Pdelay_Resp */ 138 enet_ts_ss_ptp_msg_6 = 8, /* SYNC, Delay_Req */ 139 enet_ts_ss_ptp_msg_7 = 12 /* Pdelay_Req, Pdelay_Resp */ 140 } enet_ts_ss_ptp_msg_t; 141 142 typedef enum { 143 enet_ptp_count_res_high = 0, /* ptp sub-second count resolution at 0.465 ns */ 144 enet_ptp_count_res_low /* ptp su-second count resolution at 1 ns */ 145 } enet_ptp_count_res_t; 146 147 /*--------------------------------------------------------------------- 148 * Typedef Struct Declarations 149 *--------------------------------------------------------------------- 150 */ 151 /** @brief enet buffer config struct */ 152 typedef struct { 153 uint32_t buffer; 154 uint32_t count; 155 uint16_t size; 156 } enet_buff_config_t; 157 158 159 /** @brief enet mac config struct */ 160 typedef struct { 161 uint32_t mac_addr_high[ENET_SOC_ADDR_MAX_COUNT]; 162 uint32_t mac_addr_low[ENET_SOC_ADDR_MAX_COUNT]; 163 uint8_t valid_max_count; 164 } enet_mac_config_t; 165 166 /** @brief transmission descriptor struct */ 167 typedef struct { 168 union { 169 uint32_t tdes0; 170 struct { 171 uint32_t db: 1; /**< * Deferred Bit*/ 172 uint32_t uf: 1; /**< * Underflow Error */ 173 uint32_t ed: 1; /**< * Excessive Deferral */ 174 uint32_t cc: 4; /**< * Collision Count */ 175 uint32_t vf: 1; /**< * VLAN Frame */ 176 uint32_t ec: 1; /**< * Excessive Collision */ 177 uint32_t lc: 1; /**< * Late Collision */ 178 uint32_t nc: 1; /**< * No Carrier */ 179 uint32_t loc: 1; /**< * Loss of Carrier */ 180 uint32_t ipe: 1; /**< * IP Payload Error */ 181 uint32_t ff: 1; /**< * Frame Flushed */ 182 uint32_t jt: 1; /**< * Jabber Timeout */ 183 uint32_t es: 1; /**< * Error Summary */ 184 uint32_t ihe: 1; /**< * IP Header Error */ 185 uint32_t ttss: 1; /**< * Transmit Timestamp Status */ 186 uint32_t vlic: 2; /**< * VLAN Insertion Control */ 187 uint32_t tch: 1; /**< * Second Address Chained */ 188 uint32_t ter: 1; /**< * Transmit End of Ring */ 189 uint32_t cic: 2; /**< * Checksum Insertion Control */ 190 uint32_t crcr: 1; /**< * CRC Replacement Control */ 191 uint32_t ttse: 1; /**< * Transmit Timestamp Enable */ 192 uint32_t dp: 1; /**< * Disable Pad */ 193 uint32_t dc: 1; /**< * Disable CRC */ 194 uint32_t fs: 1; /**< * First Segment */ 195 uint32_t ls: 1; /**< * Last Segment */ 196 uint32_t ic: 1; /**< * Interrupt on Completion */ 197 uint32_t own: 1; /**< * Own Bit */ 198 } tdes0_bm; 199 }; 200 201 union { 202 uint32_t tdes1; 203 struct { 204 uint32_t tbs1 : 13; /**< Transmit Buffer 1 Size */ 205 uint32_t reserved: 3; /**< Reserved */ 206 uint32_t tbs2 : 13; /**< Transmit Buffer 2 Size */ 207 uint32_t saic : 3; /**< SA Inertion Control */ 208 } tdes1_bm; 209 }; 210 211 union { 212 uint32_t tdes2; 213 struct { 214 uint32_t buffer1; /**< Buffer 1 Address */ 215 } tdes2_bm; 216 }; 217 218 union { 219 uint32_t tdes3; 220 union { 221 uint32_t buffer2; /**< Buffer 2 Address */ 222 uint32_t next_desc; /**< Next Descriptor Address */ 223 } tdes3_bm; 224 }; 225 226 #if ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MAX_LEN 227 struct { 228 uint32_t reserved; 229 } tdes4_bm; 230 231 struct { 232 uint32_t reserved; 233 } tdes5_bm; 234 235 struct { 236 uint32_t ttsl; /**< Transmit Frame Timestamp Low */ 237 } tdes6_bm; 238 239 struct { 240 uint32_t ttsh; /**< Transmit Frame Timestamp High */ 241 } tdes7_bm; 242 #endif 243 } enet_tx_desc_t; 244 245 246 /** @brief reception descriptor struct */ 247 typedef struct { 248 union { 249 uint32_t rdes0; 250 251 struct { 252 uint32_t ex_sta_rx_addr : 1; /**< Extended Status Available or Rx MAC Address*/ 253 uint32_t ce : 1; /**< CRC Error */ 254 uint32_t dbe : 1; /**< Dribble Bit Error */ 255 uint32_t re : 1; /**< Receive Error */ 256 uint32_t rwt : 1; /**< Receive Watchdog Timeout */ 257 uint32_t ft : 1; /**< Frame Type */ 258 uint32_t lc : 1; /**< Late Collision */ 259 uint32_t ts_ip_gf : 1; /**< Timestamp Available, IP Checksum Error or Giant Frame*/ 260 uint32_t ls : 1; /**< Last Descriptor */ 261 uint32_t fs : 1; /**< First Descriptor */ 262 uint32_t vlan : 1; /**< VLAN Tag */ 263 uint32_t oe : 1; /**< Overflow Error */ 264 uint32_t le : 1; /**< Length Error */ 265 uint32_t saf : 1; /**< Source Address Filter Fail */ 266 uint32_t dse : 1; /**< Descriptor Error */ 267 uint32_t es : 1; /**< Error Summary */ 268 uint32_t fl : 14; /**< Frame Length */ 269 uint32_t afm : 1; /**< Destination Address Filter Fail */ 270 uint32_t own : 1; /**< Own Bit */ 271 } rdes0_bm; 272 }; 273 274 union { 275 uint32_t rdes1; 276 struct { 277 uint32_t rbs1 : 13; /**< Receive Buffer 1 Size */ 278 uint32_t reserved0: 1; /**< Reserved */ 279 uint32_t rch : 1; /**< Second Address Chained */ 280 uint32_t rer : 1; /**< Receive End of Ring */ 281 uint32_t rbs2 : 13; /**< Receive Buffer 2 Size */ 282 uint32_t reserved1: 2; /**< Reserved */ 283 uint32_t dic : 1; /**< Disable Interrupt on Completion */ 284 } rdes1_bm; 285 }; 286 287 union { 288 uint32_t rdes2; 289 struct { 290 uint32_t buffer1; /**< Buffer 1 Address */ 291 } rdes2_bm; 292 }; 293 294 union { 295 uint32_t rdes3; 296 union { 297 uint32_t buffer2; /**< Buffer 2 Address */ 298 uint32_t next_desc; /**< Next Descriptor Address */ 299 } rdes3_bm; 300 }; 301 302 #if ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MAX_LEN 303 union { 304 uint32_t rdes4; 305 struct { 306 uint32_t ip_payload_type : 3; /**< IP Payload Type */ 307 uint32_t ip_header_err : 1; /**< IP Header Error */ 308 uint32_t ip_payload_err : 1; /**< IP Payload Error */ 309 uint32_t ip_chksum_bypassed : 1; /**< IP Checksum Bypassed */ 310 uint32_t ipv4_pkt_received : 1; /**< IPv4 Packet Received */ 311 uint32_t ipv6_pkt_received : 1; /**< IPv6 Packet Received */ 312 uint32_t msg_type : 4; /**< Message Type */ 313 uint32_t ptp_frame_type : 1; /**< PTP Frame Type */ 314 uint32_t ptp_version : 1; /**< PTP Version */ 315 uint32_t ts_dp : 1; /**< Timestamp Dropped */ 316 uint32_t reserved0 : 1; /**< Reserved */ 317 uint32_t av_pkt_recv : 1; /**< AV Packet Received */ 318 uint32_t av_tagged_pkt_recv : 1; /**< AV Tagged Packet Received */ 319 uint32_t vlan_tag_pri_value : 3; /**< VLAN Tag Priority Value */ 320 uint32_t reserved1 : 3; /**< Reserved */ 321 uint32_t l3_fm : 1; /**< Layer 3 Filter Matched */ 322 uint32_t l4_fm : 1; /**< Layer 4 Filter Matched */ 323 uint32_t l3_l4_fnl : 2; /**< Layer 3 and Layer 4 Filter Number Matched */ 324 uint32_t reserved2 : 4; /**< Reserved */ 325 } rdes4_bm; 326 }; 327 328 struct { 329 uint32_t reserved; 330 } rdes5_bm; 331 332 struct { 333 uint32_t rtsl; /**< Receive Frame Timestamp Low */ 334 } rdes6_bm; 335 336 struct { 337 uint32_t rtsh; /**< Receive Frame Timestamp High */ 338 } rdes7_bm; 339 #endif 340 } enet_rx_desc_t; 341 342 /** @brief enet frame struct */ 343 typedef struct{ 344 uint32_t length; 345 uint32_t buffer; 346 enet_rx_desc_t *rx_desc; 347 } enet_frame_t; 348 349 /** @brief enet reception frame info struct */ 350 typedef struct { 351 enet_rx_desc_t *fs_rx_desc; 352 enet_rx_desc_t *ls_rx_desc; 353 uint32_t seg_count; 354 } enet_rx_frame_info_t; 355 356 /** @brief enet description struct */ 357 typedef struct { 358 enet_tx_desc_t *tx_desc_list_head; 359 enet_rx_desc_t *rx_desc_list_head; 360 enet_tx_desc_t *tx_desc_list_cur; 361 enet_rx_desc_t *rx_desc_list_cur; 362 enet_buff_config_t tx_buff_cfg; 363 enet_buff_config_t rx_buff_cfg; 364 enet_rx_frame_info_t rx_frame_info; 365 } enet_desc_t; 366 367 /** @brief PTP timestamp struct */ 368 typedef struct { 369 uint32_t sec; 370 uint32_t nsec; 371 uint8_t sign; 372 } enet_ptp_time_t; 373 374 /* PTP config strcut */ 375 typedef struct { 376 uint8_t ssinc; 377 uint8_t sub_sec_count_res; 378 uint8_t update_method; 379 uint32_t addend; 380 } enet_ptp_config_t; 381 382 /* 383 * @brief Bit definition of TDES1 384 */ 385 #define ENET_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /**< Transmit Buffer2 Size */ 386 #define ENET_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /**< Transmit Buffer1 Size */ 387 388 #if defined __cplusplus 389 extern "C" { 390 #endif /* __cplusplus */ 391 /*--------------------------------------------------------------------- 392 * Exported Functions 393 *--------------------------------------------------------------------- 394 */ 395 /** 396 * @brief Initialize controller 397 * 398 * @param[in] ptr An Ethernet peripheral base address 399 * @param[in] inf_type the specified interface 400 * @param[in] desc A pointer to descriptor config 401 * @param[in] config A pointer to mac config 402 * @param[in] intr A mask of all required interrupts 403 */ 404 int enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *config, uint32_t intr); 405 406 /** 407 * @brief Read phy 408 * 409 * @param[in] ptr An Ethernet peripheral base address 410 * @param[in] phy_addr the specified address of phy 411 * @param[in] addr the specified address of register 412 * @retval A value corresponding to the specifeid register address 413 */ 414 uint16_t enet_read_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr); 415 416 /** 417 * @brief Write phy 418 * 419 * @param[in] ptr An Ethernet peripheral base address 420 * @param[in] phy_addr a specified address of phy 421 * @param[in] addr a specified address of the register 422 * @param[in] data a specified data to be written 423 */ 424 void enet_write_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data); 425 426 /** 427 * @brief Check if there is a received frame 428 * 429 * @param[out] parent_rx_desc_list_cur a parrent pointer to the current reception descritpion list 430 * @param[in] rx_frame_info A pointer to the information of the reception frames 431 * @retval A result of reception frame. 432 * 1 means that a reception of frame is successful. 433 * 0 means that a reception of frame is unsuccessful. 434 */ 435 uint32_t enet_check_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info); 436 437 /** 438 * @brief get a received frame 439 * 440 * @param[out] parent_rx_desc_list_cur A parrent pointer to the current reception descritpion list 441 * @param[in] rx_frame_info A pointer to the information of the reception frames 442 * @retval A struct of the current reception frame 443 */ 444 enet_frame_t enet_get_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info); 445 446 /** 447 * @brief get a received frame from interrupt 448 * 449 * @param[out] parent_rx_desc_list_cur the parrent pointer to the current reception descritpion list 450 * @param[in] rx_frame_info A pointer to the information of the reception frames 451 * @param[in] rx_desc_count A total count of the reception descriptors 452 * @retval A struct of the current reception frame 453 */ 454 enet_frame_t enet_get_received_frame_interrupt(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info, uint32_t rx_desc_count); 455 456 /** 457 * @brief prepare for the transmission descriptors 458 * 459 * @param[in] ptr An Ethernet peripheral base address 460 * @param[out] parent_tx_desc_list_cur a pointer to the information of the reception frames 461 * @param[in] frame_length the length of the transmission 462 * @param[in] tx_buff_size the size of the transmission buffer 463 * @retval a result of the transmission preparation. 464 * 1 means that the preparation is successful. 465 * 0 means that the prepartion is unsuccessful. 466 */ 467 uint32_t enet_prepare_transmission_descriptors(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, uint16_t frame_length, uint16_t tx_buff_size); 468 469 /** 470 * @brief Initialize DMA transmission descriptors in chain mode 471 * 472 * @param[in] ptr An Ethernet peripheral base address 473 * @param[in] desc A pointer to transmission descriptors 474 */ 475 void enet_dma_tx_desc_chain_init(ENET_Type *ptr, enet_desc_t *desc); 476 477 /** 478 * @brief Initialize DMA reception descriptors in chain mode 479 * 480 * @param[in] ptr An Ethernet peripheral base address 481 * @param[in] desc A pointer to reception descriptors 482 */ 483 void enet_dma_rx_desc_chain_init(ENET_Type *ptr, enet_desc_t *desc); 484 485 /** 486 * @brief Flush DMA 487 * 488 * @param[in] ptr An Ethernet peripheral base address 489 */ 490 void enet_dma_flush(ENET_Type *ptr); 491 492 /** 493 * @brief Initialize a PTP timer 494 * 495 * @param[in] ptr An Ethernet peripheral base address 496 * @param[in] config A pointer to an enet_ptp_config struct instance 497 */ 498 void enet_init_ptp(ENET_Type *ptr, enet_ptp_config_t *config); 499 500 /** 501 * @brief Set a timestamp to the PTP timer 502 * 503 * @param[in] ptr An Ethernet peripheral base address 504 * @param[in] timestamp A pointer to a timestamp structure instance 505 */ 506 void enet_set_ptp_timestamp(ENET_Type *ptr, enet_ptp_time_t *timestamp); 507 508 /** 509 * @brief Get a timestamp from the PTP timer 510 * 511 * @param[in] ptr An Ethernet peripheral base address 512 * @param[out] timestamp A pointer to a timestamp structure instance 513 */ 514 void enet_get_ptp_timestamp(ENET_Type *ptr, enet_ptp_time_t *timestamp); 515 516 /** 517 * @brief Update a timestamp to the PTP timer 518 * 519 * @param[in] ptr An Ethernet peripheral base address 520 * @param[in] timeoffset A pointer to a timestamp structure instance 521 */ 522 void enet_update_ptp_timeoffset(ENET_Type *ptr, enet_ptp_time_t *timeoffset); 523 524 /** 525 * @brief Adjust the count frequency of the PTP timer 526 * 527 * @param[in] ptr An Ethernet peripheral base address 528 * @param[in] adj An adjustment value for the count frequency of the PTP timer 529 */ 530 void enet_adjust_ptp_time_freq(ENET_Type *ptr, int32_t adj); 531 532 /** 533 * @brief Set the PTP version 534 * 535 * @param[in] ptr An Ethernet peripheral base address 536 * @param[in] ptp_ver An enum value indicating the PTP protocol 537 */ 538 void enet_set_ptp_version(ENET_Type *ptr, enet_ptp_version_t ptp_ver); 539 540 /** 541 * @brief Enable the specified ptp frame type for MAC process 542 * 543 * @param[in] ptr An Ethernet peripheral base address 544 * @param[in] ptp_frame_type An enum value indicating the transport protocol of PTP frames 545 * @param[in] enable A value to enable or disable the transport protocol of PTP frames which is specified by ptp_frame_type parameter 546 * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success 547 */ 548 hpm_stat_t enet_enable_ptp_frame_type(ENET_Type *ptr, enet_ptp_frame_type_t ptp_frame_type, bool enable); 549 550 /** 551 * @brief Set the ptp message type for snapshots 552 * 553 * @param[in] ptr An Ethernet peripheral base address 554 * @param[in] ts_ss_ptp_msg An enum value indicating the specified ptp message type for snapshots 555 */ 556 void enet_set_snapshot_ptp_message_type(ENET_Type *ptr, enet_ts_ss_ptp_msg_t ts_ss_ptp_msg); 557 558 #if defined __cplusplus 559 } 560 #endif /* __cplusplus */ 561 562 /** @} */ 563 #endif /* HPM_ENET_DRV_H */ 564