1 /* 2 * drivers/spi/spi-sunxi.h 3 * 4 * Copyright (C) 2012 - 2016 Reuuimlla Limited 5 * Pan Nan <pannan@reuuimllatech.com> 6 * 7 * SUNXI SPI Register Definition 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * 2013.5.7 Mintow <duanmintao@allwinnertech.com> 15 * Adapt to support sun8i/sun9i of Allwinner. 16 */ 17 18 #include <linux/regulator/consumer.h> 19 20 #ifndef _SUNXI_SPI_H_ 21 #define _SUNXI_SPI_H_ 22 23 #define HEXADECIMAL (0x10) 24 #define REG_END (0x0f) 25 #define SAMPLE_NUMBER (0x80) 26 #define REG_INTERVAL (0x04) 27 #define REG_CL (0x0c) 28 29 #define SPI_MODULE_NUM (4) 30 #define SPI_FIFO_DEPTH (128) 31 #define MAX_FIFU 64 32 #define BULK_DATA_BOUNDARY 64 /* can modify to adapt the application */ 33 #define SPI_MAX_FREQUENCY 100000000 /* spi controller just support 100Mhz */ 34 #define SPI_HIGH_FREQUENCY 60000000 /* sample mode threshold frequency */ 35 #define SPI_LOW_FREQUENCY 24000000 /* sample mode threshold frequency */ 36 37 /* SPI Registers offsets from peripheral base address */ 38 #define SPI_VER_REG (0x00) /* version number register */ 39 #define SPI_GC_REG (0x04) /* global control register */ 40 #define SPI_TC_REG (0x08) /* transfer control register */ 41 #define SPI_INT_CTL_REG (0x10) /* interrupt control register */ 42 #define SPI_INT_STA_REG (0x14) /* interrupt status register */ 43 #define SPI_FIFO_CTL_REG (0x18) /* fifo control register */ 44 #define SPI_FIFO_STA_REG (0x1C) /* fifo status register */ 45 #define SPI_WAIT_CNT_REG (0x20) /* wait clock counter register */ 46 #define SPI_CLK_CTL_REG (0x24) /* clock rate control register */ 47 #define SPI_SAMPLE_DELAY_REG (0x28) /* sample delay control register */ 48 #define SPI_BURST_CNT_REG (0x30) /* burst counter register */ 49 #define SPI_TRANSMIT_CNT_REG (0x34) /* transmit counter register */ 50 #define SPI_BCC_REG (0x38) /* burst control counter register */ 51 #define SPI_DMA_CTL_REG (0x88) /* DMA control register, only for 1639 */ 52 #define SPI_TXDATA_REG (0x200) /* tx data register */ 53 #define SPI_RXDATA_REG (0x300) /* rx data register */ 54 #define SPI_DBI_CR_REG (0x100) /* DBI control register */ 55 #define SPI_DBI_CR_REG1 (0x104) /* DBI control register */ 56 #define SPI_DBI_CR_REG2 (0x108) /* DBI control register */ 57 #define SPI_DBI_TIMER_REG (0x10C) /* DBI timer register */ 58 #define SPI_DBI_VIDEO_SIZE (0x110) /* DBI VIDEO SIZE register */ 59 #define SPI_DBI_INT_REG (0x120) /* DBI interrupter status register */ 60 61 /* SPI Global Control Register Bit Fields & Masks,default value:0x0000_0080 */ 62 #define SPI_GC_EN (0x1 << 0) /* SPI module enable control 1:enable; 0:disable; default:0 */ 63 #define SPI_GC_MODE (0x1 << 1) /* SPI function mode select 1:master; 0:slave; default:0 */ 64 #define SPI_GC_TP_EN (0x1 << 7) /* SPI transmit stop enable 1:stop transmit data when RXFIFO is full; 0:ignore RXFIFO status; default:1 */ 65 #define SPI_GC_SRST (0x1 << 31) /* soft reset, write 1 will clear SPI control, auto clear to 0 */ 66 #define SPI_GC_DBI_MODE_SEL (0x1 << 3) /* SPI interface mode select 1:dbi; 0:spi; default:0 */ 67 #define SPI_GC_DBI_EN (0x1 << 4) /* SPI DBI mode enable 1:enable; 0:disable; default:0 */ 68 69 /* SPI Transfer Control Register Bit Fields & Masks,default value:0x0000_0087 */ 70 #define SPI_TC_PHA (0x1 << 0) /* SPI Clock/Data phase control,0: phase0,1: phase1;default:1 */ 71 #define SPI_TC_POL (0x1 << 1) /* SPI Clock polarity control,0:low level idle,1:high level idle;default:1 */ 72 #define SPI_TC_SPOL (0x1 << 2) /* SPI Chip select signal polarity control,default: 1,low effective like this:~~|_____~~ */ 73 #define SPI_TC_SSCTL (0x1 << 3) /* SPI chip select control,default 0:SPI_SSx remains asserted between SPI bursts,1:negate SPI_SSx between SPI bursts */ 74 #define SPI_TC_SS_MASK (0x3 << 4) /* SPI chip select:00-SPI_SS0;01-SPI_SS1;10-SPI_SS2;11-SPI_SS3*/ 75 #define SPI_TC_SS_OWNER (0x1 << 6) /* SS output mode select default is 0:automatic output SS;1:manual output SS */ 76 #define SPI_TC_SS_LEVEL (0x1 << 7) /* defautl is 1:set SS to high;0:set SS to low */ 77 #define SPI_TC_DHB (0x1 << 8) /* Discard Hash Burst,default 0:receiving all spi burst in BC period 1:discard unused,fectch WTC bursts */ 78 #define SPI_TC_DDB (0x1 << 9) /* Dummy burst Type,default 0: dummy spi burst is zero;1:dummy spi burst is one */ 79 #define SPI_TC_RPSM (0x1 << 10) /* select mode for high speed write,0:normal write mode,1:rapids write mode,default 0 */ 80 #define SPI_TC_SDM (0x1 << 13) /* master sample data mode, 1: normal sample mode;0:delay sample mode. */ 81 #define SPI_TC_SDC (0x1 << 11) /* master sample data control, 1: delay--high speed operation;0:no delay. */ 82 #define SPI_TC_SDC1 (0x1 << 15) /* master sample data control, 1: delay--high speed operation;0:no delay. */ 83 #define SPI_TC_FBS (0x1 << 12) /* LSB/MSB transfer first select 0:MSB,1:LSB,default 0:MSB first */ 84 #define SPI_TC_XCH (0x1 << 31) /* Exchange burst default 0:idle,1:start exchange;when BC is zero,this bit cleared by SPI controller*/ 85 #define SPI_TC_SS_BIT_POS (4) 86 87 /* SPI Interrupt Control Register Bit Fields & Masks,default value:0x0000_0000 */ 88 #define SPI_INTEN_RX_RDY (0x1 << 0) /* rxFIFO Ready Interrupt Enable,---used for immediately received,0:disable;1:enable */ 89 #define SPI_INTEN_RX_EMP (0x1 << 1) /* rxFIFO Empty Interrupt Enable ---used for IRQ received */ 90 #define SPI_INTEN_RX_FULL (0x1 << 2) /* rxFIFO Full Interrupt Enable ---seldom used */ 91 #define SPI_INTEN_TX_ERQ (0x1 << 4) /* txFIFO Empty Request Interrupt Enable ---seldom used */ 92 #define SPI_INTEN_TX_EMP (0x1 << 5) /* txFIFO Empty Interrupt Enable ---used for IRQ tx */ 93 #define SPI_INTEN_TX_FULL (0x1 << 6) /* txFIFO Full Interrupt Enable ---seldom used */ 94 #define SPI_INTEN_RX_OVF (0x1 << 8) /* rxFIFO Overflow Interrupt Enable ---used for error detect */ 95 #define SPI_INTEN_RX_UDR (0x1 << 9) /* rxFIFO Underrun Interrupt Enable ---used for error detect */ 96 #define SPI_INTEN_TX_OVF (0x1 << 10) /* txFIFO Overflow Interrupt Enable ---used for error detect */ 97 #define SPI_INTEN_TX_UDR (0x1 << 11) /* txFIFO Underrun Interrupt Enable ---not happened */ 98 #define SPI_INTEN_TC (0x1 << 12) /* Transfer Completed Interrupt Enable ---used */ 99 #define SPI_INTEN_SSI (0x1 << 13) /* SSI interrupt Enable,chip select from valid state to invalid state,for slave used only */ 100 #define SPI_INTEN_ERR (SPI_INTEN_TX_OVF|SPI_INTEN_RX_UDR|SPI_INTEN_RX_OVF) /* NO txFIFO underrun */ 101 #define SPI_INTEN_MASK (0x77|(0x3f<<8)) 102 103 /* SPI Interrupt Status Register Bit Fields & Masks,default value:0x0000_0022 */ 104 #define SPI_INT_STA_RX_RDY (0x1 << 0) /* rxFIFO ready, 0:RX_WL < RX_TRIG_LEVEL,1:RX_WL >= RX_TRIG_LEVEL */ 105 #define SPI_INT_STA_RX_EMP (0x1 << 1) /* rxFIFO empty, this bit is set when rxFIFO is empty */ 106 #define SPI_INT_STA_RX_FULL (0x1 << 2) /* rxFIFO full, this bit is set when rxFIFO is full */ 107 #define SPI_INT_STA_TX_RDY (0x1 << 4) /* txFIFO ready, 0:TX_WL > TX_TRIG_LEVEL,1:TX_WL <= TX_TRIG_LEVEL */ 108 #define SPI_INT_STA_TX_EMP (0x1 << 5) /* txFIFO empty, this bit is set when txFIFO is empty */ 109 #define SPI_INT_STA_TX_FULL (0x1 << 6) /* txFIFO full, this bit is set when txFIFO is full */ 110 #define SPI_INT_STA_RX_OVF (0x1 << 8) /* rxFIFO overflow, when set rxFIFO has overflowed */ 111 #define SPI_INT_STA_RX_UDR (0x1 << 9) /* rxFIFO underrun, when set rxFIFO has underrun */ 112 #define SPI_INT_STA_TX_OVF (0x1 << 10) /* txFIFO overflow, when set txFIFO has overflowed */ 113 #define SPI_INT_STA_TX_UDR (0x1 << 11) /* fxFIFO underrun, when set txFIFO has underrun */ 114 #define SPI_INT_STA_TC (0x1 << 12) /* Transfer Completed */ 115 #define SPI_INT_STA_SSI (0x1 << 13) /* SS invalid interrupt, when set SS has changed from valid to invalid */ 116 #define SPI_INT_STA_ERR (SPI_INT_STA_TX_OVF|SPI_INT_STA_RX_UDR|SPI_INT_STA_RX_OVF) /* NO txFIFO underrun */ 117 #define SPI_INT_STA_MASK (0x77|(0x3f<<8)) 118 119 /* SPI FIFO Control Register Bit Fields & Masks,default value:0x0040_0001 */ 120 #define SPI_FIFO_CTL_RX_LEVEL (0xFF << 0) /* rxFIFO reday request trigger level,default 0x1 */ 121 #define SPI_FIFO_CTL_RX_DRQEN (0x1 << 8) /* rxFIFO DMA request enable,1:enable,0:disable */ 122 #define SPI_FIFO_CTL_RX_TESTEN (0x1 << 14) /* rxFIFO test mode enable,1:enable,0:disable */ 123 #define SPI_FIFO_CTL_RX_RST (0x1 << 15) /* rxFIFO reset, write 1, auto clear to 0 */ 124 #define SPI_FIFO_CTL_TX_LEVEL (0xFF << 16) /* txFIFO empty request trigger level,default 0x40 */ 125 #define SPI_FIFO_CTL_TX_DRQEN (0x1 << 24) /* txFIFO DMA request enable,1:enable,0:disable */ 126 #define SPI_FIFO_CTL_TX_TESTEN (0x1 << 30) /* txFIFO test mode enable,1:enable,0:disable */ 127 #define SPI_FIFO_CTL_TX_RST (0x1 << 31) /* txFIFO reset, write 1, auto clear to 0 */ 128 #define SPI_FIFO_CTL_DRQEN_MASK (SPI_FIFO_CTL_TX_DRQEN|SPI_FIFO_CTL_RX_DRQEN) 129 130 /* SPI FIFO Status Register Bit Fields & Masks,default value:0x0000_0000 */ 131 #define SPI_FIFO_STA_RX_CNT (0xFF << 0) /* rxFIFO counter,how many bytes in rxFIFO */ 132 #define SPI_FIFO_STA_RB_CNT (0x7 << 12) /* rxFIFO read buffer counter,how many bytes in rxFIFO read buffer */ 133 #define SPI_FIFO_STA_RB_WR (0x1 << 15) /* rxFIFO read buffer write enable */ 134 #define SPI_FIFO_STA_TX_CNT (0xFF << 16) /* txFIFO counter,how many bytes in txFIFO */ 135 #define SPI_FIFO_STA_TB_CNT (0x7 << 28) /* txFIFO write buffer counter,how many bytes in txFIFO write buffer */ 136 #define SPI_FIFO_STA_TB_WR (0x1 << 31) /* txFIFO write buffer write enable */ 137 #define SPI_RXCNT_BIT_POS (0) 138 #define SPI_TXCNT_BIT_POS (16) 139 140 /* SPI Wait Clock Register Bit Fields & Masks,default value:0x0000_0000 */ 141 #define SPI_WAIT_WCC_MASK (0xFFFF << 0) /* used only in master mode: Wait Between Transactions */ 142 #define SPI_WAIT_SWC_MASK (0xF << 16) /* used only in master mode: Wait before start dual data transfer in dual SPI mode */ 143 144 /* SPI Sample Delay Control Register Bit Fields & Masks,default value:0x0000_2000 */ 145 #define SPI_SAMP_MODE_EN (1 << 2) /* Sample Timong Mode Select */ 146 #define SPI_SAMP_DL_SW_EN (1 << 7) /* Sample Delay Software Enable */ 147 #define DELAY_NORMAL_SAMPLE (0x100) 148 #define DELAY_0_5_CYCLE_SAMPLE (0x000) 149 #define DELAY_1_CYCLE_SAMPLE (0x010) 150 #define DELAY_1_5_CYCLE_SAMPLE (0x110) 151 #define DELAY_2_CYCLE_SAMPLE (0x101) 152 #define DELAY_2_5_CYCLE_SAMPLE (0x001) 153 #define DELAY_3_CYCLE_SAMPLE (0x011) 154 #define DELAY_SDM_POS (8) 155 #define DELAY_SDC_POS (4) 156 #define DELAY_SDC1_POS (0) 157 #define SAMP_MODE_DL_DEFAULT (0xaaaaffff) 158 159 /* SPI Clock Control Register Bit Fields & Masks,default:0x0000_0002 */ 160 #define SPI_CLK_CTL_CDR2 (0xFF << 0) /* Clock Divide Rate 2,master mode only : SPI_CLK = AHB_CLK/(2*(n+1)) */ 161 #define SPI_CLK_CTL_CDR1 (0xF << 8) /* Clock Divide Rate 1,master mode only : SPI_CLK = AHB_CLK/2^n */ 162 #define SPI_CLK_CTL_DRS (0x1 << 12) /* Divide rate select,default,0:rate 1;1:rate 2 */ 163 #define SPI_CLK_SCOPE (SPI_CLK_CTL_CDR2+1) 164 165 /* SPI Master Burst Counter Register Bit Fields & Masks,default:0x0000_0000 */ 166 /* master mode: when SMC = 1,BC specifies total burst number, Max length is 16Mbytes */ 167 #define SPI_BC_CNT_MASK (0xFFFFFF << 0) /* Total Burst Counter, tx length + rx length ,SMC=1 */ 168 169 /* SPI Master Transmit Counter reigster default:0x0000_0000 */ 170 #define SPI_TC_CNT_MASK (0xFFFFFF << 0) /* Write Transmit Counter, tx length, NOT rx length!!! */ 171 172 /* SPI Master Burst Control Counter reigster Bit Fields & Masks,default:0x0000_0000 */ 173 #define SPI_BCC_STC_MASK (0xFFFFFF << 0) /* master single mode transmit counter */ 174 #define SPI_BCC_DBC_MASK (0xF << 24) /* master dummy burst counter */ 175 #define SPI_BCC_DUAL_MODE (0x1 << 28) /* master dual mode RX enable */ 176 #define SPI_BCC_QUAD_MODE (0x1 << 29) /* master quad mode RX enable */ 177 178 #define DBI_CR_READ (0x1 << 31) 179 #define DBI_CR_LSB_FIRST (0x1 << 19) 180 #define DBI_CR_TRANSMIT_MODE (0x1 << 15) 181 #define DBI_CR_FORMAT (12) 182 #define DBI_CR_FORMAT_MASK (0x7 << DBI_CR_FORMAT) 183 #define DBI_CR_INTERFACE (8) 184 #define DBI_CR_INTERFACE_MASK (0x7 << DBI_CR_INTERFACE) 185 #define DBI_CR1_DCX_DATA (0x1 << 22) 186 #define DBI_CR1_CLK_AUTO (0x1 << 24) 187 #define DBI_CR2_SDI_PIN (0x1 << 6) 188 #define DBI_CR2_DCX_PIN (0x1 << 5) 189 #define DBI_CR2_TE_ENABLE (0x1 << 0) 190 #define DBI_CR2_DMA_ENABLE (0x1 << 15) 191 #define DBI_INT_STA_MASK (0x7f|(0x7f<<8)) 192 #define DBI_INT_TE_INT (0x1 << 10) /* te enable*/ 193 #define DBI_INT_TIMER_INT (0x1 << 12) /* timer enable*/ 194 #define DBI_INT_STA_FRAME (0x1 << 9) /* fram Transfer Completed */ 195 #define DBI_INT_FIFO_EMPTY (0x1 << 14) 196 #define DBI_FRAM_DONE_INT_EN (0x1 << 1) /* fram Transfer Completed En*/ 197 #define DBI_FIFO_EMPTY_INT_EN (0x1 << 6) /* fram Transfer Completed En*/ 198 #define DBI_TE_INT_EN (0x1 << 2) /* TE interrupt*/ 199 #define DBI_TIMER_INT_EN (0x1 << 4) /* timer interrupt*/ 200 201 #define SPI_PHA_ACTIVE_ (0x01) 202 #define SPI_POL_ACTIVE_ (0x02) 203 204 #define SPI_MODE_0_ACTIVE_ (0|0) 205 #define SPI_MODE_1_ACTIVE_ (0|SPI_PHA_ACTIVE_) 206 #define SPI_MODE_2_ACTIVE_ (SPI_POL_ACTIVE_|0) 207 #define SPI_MODE_3_ACTIVE_ (SPI_POL_ACTIVE_|SPI_PHA_ACTIVE_) 208 #define SPI_CS_HIGH_ACTIVE_ (0x04) 209 #define SPI_LSB_FIRST_ACTIVE_ (0x08) 210 #define SPI_DUMMY_ONE_ACTIVE_ (0x10) 211 #define SPI_RECEIVE_ALL_ACTIVE_ (0x20) 212 213 #define SPI_DBI_COMMAND_READ_ (0x10) 214 #define SPI_DBI_LSB_FIRST_ (0x20) 215 #define SPI_DBI_TRANSMIT_VIDEO_ (0x40) 216 #define SPI_DBI_DCX_DATA_ (0x80) 217 218 /* About SUNXI */ 219 #define SUNXI_SPI_DEV_NAME "spi" 220 221 /* About DMA */ 222 #ifdef CONFIG_ARCH_SUN9IW1P1 223 #define SPI_DMA_WAIT_MODE 0xA5 224 #define SPI_DMA_SHAKE_MODE 0xEA 225 #define spi_set_dma_mode(base) writel(SPI_DMA_SHAKE_MODE, base + SPI_DMA_CTL_REG) 226 #else 227 #define spi_set_dma_mode(base) 228 #endif 229 230 struct sunxi_spi_platform_data { 231 int cs_bitmap; /* cs0-0x1,cs1-0x2,cs0&cs1-0x3 */ 232 int cs_num; /* number of cs */ 233 int sclk_freq_def; /* clk frequence*/ 234 char regulator_id[16]; 235 struct regulator *regulator; 236 }; 237 238 /* spi device controller state, alloc */ 239 struct sunxi_spi_config { 240 int bits_per_word; /* 8bit */ 241 int max_speed_hz; /* 80MHz */ 242 int mode; /* pha,pol,LSB,etc.. */ 243 }; 244 245 /* spi device data, used in dual spi mode */ 246 struct sunxi_dual_mode_dev_data { 247 int dual_mode; /* dual SPI mode, 0-single mode, 1-dual mode */ 248 int single_cnt; /* single mode transmit counter */ 249 int dummy_cnt; /* dummy counter should be sent before receive in dual mode */ 250 }; 251 252 enum { 253 DEBUG_INIT = 1U << 0, 254 DEBUG_SUSPEND = 1U << 1, 255 DEBUG_DATA = 1U << 2, 256 DEBUG_INFO = 1U << 3, 257 DEBUG_INFO1 = 1U << 4, 258 DEBUG_INFO2 = 1U << 5, 259 DEBUG_INFO3 = 1U << 6, 260 DEBUG_INFO4 = 1U << 7, 261 }; 262 263 enum dbi_out_seq { 264 DBI_OUT_RGB = 0, 265 DBI_OUT_RBG = 1, 266 DBI_OUT_GRB = 2, 267 DBI_OUT_GBR = 3, 268 DBI_OUT_BRG = 4, 269 DBI_OUT_BGR = 5, 270 }; 271 272 enum dbi_src_seq { 273 DBI_SRC_RGB = 0, 274 DBI_SRC_RBG = 1, 275 DBI_SRC_GRB = 2, 276 DBI_SRC_GBR = 3, 277 DBI_SRC_BRG = 4, 278 DBI_SRC_BGR = 5, 279 /* following definition only for rgb565 280 * to change the RGB order in two byte(16 bit). 281 * format:R(5bit)--G_1(3bit)--G_0(3bit)--B(5bit) 282 * G_0 mean the low 3 bit of G component 283 * G_1 mean the high 3 bit of G component 284 * */ 285 DBI_SRC_GRBG_0 = 6, 286 DBI_SRC_GRBG_1 = 7, 287 DBI_SRC_GBRG_0 = 8, 288 DBI_SRC_GBRG_1 = 9, 289 }; 290 291 enum dbi_te_en { 292 DBI_TE_DISABLE = 0, 293 DBI_TE_RISING_EDGE = 1, 294 DBI_TE_FALLING_EDGE = 2, 295 }; 296 297 struct spi_dbi_config { 298 enum dbi_src_seq dbi_src_sequence; 299 enum dbi_out_seq dbi_out_sequence; 300 char dbi_rgb_bit_order; 301 char dbi_rgb32_alpha_pos; 302 char dbi_rgb16_pixel_endian; 303 char dbi_format; /*DBI OUT format*/ 304 char dbi_interface; 305 u16 dbi_mode; 306 char dbi_clk_out_mode; 307 u16 dbi_video_v; 308 u16 dbi_video_h; 309 enum dbi_te_en dbi_te_en; 310 unsigned char dbi_fps; 311 void (*dbi_vsync_handle)(unsigned long data); 312 char dbi_read_bytes; 313 }; 314 315 extern int spi_get_dbi_config(const struct spi_device *spi, struct spi_dbi_config *dbi_config); 316 extern int spi_set_dbi_config(struct spi_device *spi, const struct spi_dbi_config *dbi_config); 317 318 #define DBI_RGB111 (0x0) 319 #define DBI_RGB444 (0x1) 320 #define DBI_RGB565 (0x2) 321 #define DBI_RGB666 (0x3) 322 #define DBI_RGB888 (0x4) 323 324 #define L3I1 (0x0) 325 #define L3I2 (0x1) 326 #define L4I1 (0x2) 327 #define L4I2 (0x3) 328 #define D2LI (0x4) 329 330 #define SPI_DBI_READ (0x10) 331 #define SPI_DBI_LSB_FIRST (0x20) 332 #define SPI_DBI_TRANSMIT_VIDEO (0x40) 333 #define SPI_DBI_DCX_DATA (0x80) 334 335 #define SPI_DBI_CLK_AUTO_GATING (0x0) /*default*/ 336 #define SPI_DBI_CLK_ALWAYS_ON (0x1) 337 338 #define DBI_READ(dbi_mode) (dbi_mode |= (SPI_DBI_READ)) 339 #define DBI_WRITE(dbi_mode) (dbi_mode &= ~(SPI_DBI_READ)) 340 #define DBI_LSB_FIRST(dbi_mode) (dbi_mode |= SPI_DBI_LSB_FIRST) 341 #define DBI_MSB_FIRST(dbi_mode) (dbi_mode &= ~SPI_DBI_LSB_FIRST) 342 #define DBI_TR_VIDEO(dbi_mode) (dbi_mode |= SPI_DBI_TRANSMIT_VIDEO) 343 #define DBI_TR_COMMAND(dbi_mode) (dbi_mode &= ~(SPI_DBI_TRANSMIT_VIDEO)) 344 #define DBI_DCX_DATA(dbi_mode) (dbi_mode |= SPI_DBI_DCX_DATA) 345 #define DBI_DCX_COMMAND(dbi_mode) (dbi_mode &= ~(SPI_DBI_DCX_DATA)) 346 347 #endif 348