1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19 #include "mipi_rx_hal.h"
20 #include "hi_osal.h"
21 #include "type.h"
22 #include "hi_mipi.h"
23 #include "mipi_rx_reg.h"
24
25 #ifdef __cplusplus
26 #if __cplusplus
27 extern "C" {
28 #endif
29 #endif /* End of #ifdef __cplusplus */
30
31 static unsigned long g_mipi_rx_core_reset_addr;
32
33 typedef struct {
34 unsigned int phy_rg_en_2121;
35 unsigned int phy_rg_clk0_en;
36 unsigned int phy_rg_clk1_en;
37 unsigned int phy_rg_lp0_mode_en;
38 unsigned int phy_rg_lp1_mode_en;
39 } phy_mode_link_t;
40
41 typedef enum {
42 MIPI_ESC_D0 = 0x1 << 0,
43 MIPI_ESC_D1 = 0x1 << 1,
44 MIPI_ESC_D2 = 0x1 << 2,
45 MIPI_ESC_D3 = 0x1 << 3,
46 MIPI_ESC_CLK0 = 0x1 << 4,
47 MIPI_ESC_CLK1 = 0x1 << 5,
48
49 MIPI_TIMEOUT_D0 = 0x1 << 8,
50 MIPI_TIMEOUT_D1 = 0x1 << 9,
51 MIPI_TIMEOUT_D2 = 0x1 << 10,
52 MIPI_TIMEOUT_D3 = 0x1 << 11,
53 MIPI_TIMEOUT_CLK0 = 0x1 << 12,
54 MIPI_TIMEOUT_CLK1 = 0x1 << 13,
55 } phy_err_int_state;
56
57 typedef enum {
58 MIPI_VC0_PKT_DATA_CRC = 0x1 << 0, /* VC0'S data CRC error */
59 MIPI_VC1_PKT_DATA_CRC = 0x1 << 1,
60 MIPI_VC2_PKT_DATA_CRC = 0x1 << 2,
61 MIPI_VC3_PKT_DATA_CRC = 0x1 << 3,
62
63 MIPI_PKT_HEADER_ERR = 0x1 << 16, /* Header has two error at least ,and ECC error correction is invalid */
64 } mipi_pkt_int_state;
65
66 typedef enum {
67 MIPI_VC0_PKT_INVALID_DT = 0x1 << 0, /* do not support VC0'S data type */
68 MIPI_VC1_PKT_INVALID_DT = 0x1 << 1, /* do not support VC1'S data type */
69 MIPI_VC2_PKT_INVALID_DT = 0x1 << 2, /* do not support VC2'S data type */
70 MIPI_VC3_PKT_INVALID_DT = 0x1 << 3, /* do not support VC3'S data type */
71
72 MIPI_VC0_PKT_HEADER_ECC = 0x1 << 16, /* VC0'S header has errors,and ECC error correction is ok */
73 MIPI_VC1_PKT_HEADER_ECC = 0x1 << 17,
74 MIPI_VC2_PKT_HEADER_ECC = 0x1 << 18,
75 MIPI_VC3_PKT_HEADER_ECC = 0x1 << 19,
76 } mipi_pkt2_int_state;
77
78 typedef enum {
79 MIPI_VC0_NO_MATCH = 0x1 << 0, /* VC0,frame's start and frame's end do not match */
80 MIPI_VC1_NO_MATCH = 0x1 << 1, /* VC1,frame's start and frame's end do not match */
81 MIPI_VC2_NO_MATCH = 0x1 << 2, /* VC2,frame's start and frame's end do not match */
82 MIPI_VC3_NO_MATCH = 0x1 << 3, /* VC3,frame's start and frame's end do not match */
83
84 MIPI_VC0_ORDER_ERR = 0x1 << 8, /* VC0'S frame order error */
85 MIPI_VC1_ORDER_ERR = 0x1 << 9, /* VC1'S frame order error */
86 MIPI_VC2_ORDER_ERR = 0x1 << 10, /* VC2'S frame order error */
87 MIPI_VC3_ORDER_ERR = 0x1 << 11, /* VC3'S frame order error */
88
89 MIPI_VC0_FRAME_CRC = 0x1 << 16, /* in the last frame, VC0'S data has a CRC ERROR at least */
90 MIPI_VC1_FRAME_CRC = 0x1 << 17, /* in the last frame, VC1'S data has a CRC ERROR at least */
91 MIPI_VC2_FRAME_CRC = 0x1 << 18, /* in the last frame, VC2'S data has a CRC ERROR at least */
92 MIPI_VC3_FRAME_CRC = 0x1 << 19, /* in the last frame, VC3'S data has a CRC ERROR at least */
93 } mipi_frame_int_state;
94
95 typedef enum {
96 CMD_FIFO_WRITE_ERR = 0x1 << 0, /* MIPI_CTRL write command FIFO error */
97 DATA_FIFO_WRITE_ERR = 0x1 << 1,
98 CMD_FIFO_READ_ERR = 0x1 << 16,
99 DATA_FIFO_READ_ERR = 0x1 << 17,
100 } mipi_ctrl_int_state;
101
102 typedef enum {
103 LINK0_WRITE_ERR = 0x1 << 16,
104 LINK0_READ_ERR = 0x1 << 20,
105 LVDS_STAT_ERR = 0x1 << 24,
106 LVDS_POP_ERR = 0x1 << 25,
107 CMD_WR_ERR = 0x1 << 26,
108 CMD_RD_ERR = 0x1 << 27,
109 } lvds_int_state;
110
111 typedef enum {
112 ALIGN_FIFO_FULL_ERR = 0x1 << 0,
113 ALIGN_LANE0_ERR = 0x1 << 1,
114 ALIGN_LANE1_ERR = 0x1 << 2,
115 ALIGN_LANE2_ERR = 0x1 << 3,
116 ALIGN_LANE3_ERR = 0x1 << 4,
117 } align_int_state;
118
119 /* macro definition */
120 #define MIPI_RX_REGS_ADDR 0x113A0000
121 #define MIPI_RX_REGS_SIZE 0x10000
122
123 #define SNS_CRG_ADDR 0x120100F0
124 #define MIPI_RX_CRG_ADDR 0x120100F8
125
126 #define MIPI_RX_WORK_MODE_ADDR 0x12030018
127
128 #define MIPI_RX_IRQ 89
129
130 static unsigned int g_reg_map_flag = 0;
131
132 #define is_valid_id(id) ((id) != -1)
133
134 #define SKEW_LINK 0x0
135 #define MIPI_FSMO_VALUE 0x000d1d0c
136
137 /* global variables definition */
138 mipi_rx_regs_type_t *g_mipi_rx_regs_va = NULL;
139
140 unsigned int g_mipi_rx_irq_num = MIPI_RX_IRQ;
141
142 static const phy_mode_link_t g_phy_mode[][MIPI_RX_MAX_PHY_NUM] = {
143 {{ 0, 1, 1, 1, 1 }},
144 {{ 1, 1, 1, 1, 1 }},
145 };
146
147 phy_err_int_cnt_t g_phy_err_int_cnt[MIPI_RX_MAX_PHY_NUM];
148 mipi_err_int_cnt_t g_mipi_err_int_cnt[MIPI_RX_MAX_DEV_NUM];
149 lvds_err_int_cnt_t g_lvds_err_int_cnt[MIPI_RX_MAX_DEV_NUM];
150 align_err_int_cnt_t g_align_err_int_cnt[MIPI_RX_MAX_DEV_NUM];
151
mipi_rx_hal_get_phy_err_int_cnt(unsigned int phy_id)152 phy_err_int_cnt_t *mipi_rx_hal_get_phy_err_int_cnt(unsigned int phy_id)
153 {
154 return &g_phy_err_int_cnt[phy_id];
155 }
156
mipi_rx_hal_get_mipi_err_int(unsigned int phy_id)157 mipi_err_int_cnt_t *mipi_rx_hal_get_mipi_err_int(unsigned int phy_id)
158 {
159 return &g_mipi_err_int_cnt[phy_id];
160 }
161
mipi_rx_hal_get_lvds_err_int_cnt(unsigned int phy_id)162 lvds_err_int_cnt_t *mipi_rx_hal_get_lvds_err_int_cnt(unsigned int phy_id)
163 {
164 return &g_lvds_err_int_cnt[phy_id];
165 }
166
mipi_rx_hal_get_align_err_int_cnt(unsigned int phy_id)167 align_err_int_cnt_t *mipi_rx_hal_get_align_err_int_cnt(unsigned int phy_id)
168 {
169 return &g_align_err_int_cnt[phy_id];
170 }
171
172 /* function definition */
set_bit(unsigned long value,unsigned long offset,unsigned long addr)173 static void set_bit(unsigned long value, unsigned long offset,
174 unsigned long addr)
175 {
176 unsigned long t, mask;
177
178 mask = 1 << offset;
179 t = osal_readl((const volatile void *)addr);
180 t &= ~mask;
181 t |= (value << offset) & mask;
182 osal_writel(t, (volatile void *)addr);
183 }
184
write_reg32(unsigned long addr,unsigned int value,unsigned int mask)185 static void write_reg32(unsigned long addr, unsigned int value, unsigned int mask)
186 {
187 unsigned int t;
188
189 t = osal_readl((void *)addr);
190 t &= ~mask;
191 t |= value & mask;
192
193 osal_writel(t, (void *)addr);
194 }
195
get_mipi_rx_phy_regs(unsigned int phy_id)196 static mipi_rx_phy_cfg_t *get_mipi_rx_phy_regs(unsigned int phy_id)
197 {
198 return &g_mipi_rx_regs_va->mipi_rx_phy_cfg[phy_id];
199 }
200
get_mipi_rx_sys_regs(void)201 static mipi_rx_sys_regs_t *get_mipi_rx_sys_regs(void)
202 {
203 return &g_mipi_rx_regs_va->mipi_rx_sys_regs;
204 }
205
get_mipi_ctrl_regs(combo_dev_t devno)206 static mipi_ctrl_regs_t *get_mipi_ctrl_regs(combo_dev_t devno)
207 {
208 return &g_mipi_rx_regs_va->mipi_rx_ctrl_regs[devno].mipi_ctrl_regs;
209 }
210
get_lvds_ctrl_regs(combo_dev_t devno)211 static lvds_ctrl_regs_t *get_lvds_ctrl_regs(combo_dev_t devno)
212 {
213 return &g_mipi_rx_regs_va->mipi_rx_ctrl_regs[devno].lvds_ctrl_regs;
214 }
215
mipi_rx_set_cil_int_mask(unsigned int phy_id,unsigned int mask)216 void mipi_rx_set_cil_int_mask(unsigned int phy_id, unsigned int mask)
217 {
218 U_MIPI_INT_MSK mipi_int_msk;
219 volatile mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
220 volatile mipi_rx_sys_regs_t *mipi_rx_sys_regs = get_mipi_rx_sys_regs();
221
222 mipi_int_msk.u32 = mipi_rx_sys_regs->MIPI_INT_MSK.u32;
223
224 if (phy_id == 0) {
225 mipi_int_msk.bits.int_phycil0_mask = 0x0;
226 }
227
228 mipi_rx_sys_regs->MIPI_INT_MSK.u32 = mipi_int_msk.u32;
229
230 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
231 mipi_rx_phy_cfg->MIPI_CIL_INT_MSK_LINK.u32 = mask;
232 }
233
mipi_rx_set_phy_skew_link(unsigned int phy_id,unsigned int value)234 static void mipi_rx_set_phy_skew_link(unsigned int phy_id, unsigned int value)
235 {
236 volatile U_PHY_SKEW_LINK phy_skew_link;
237 volatile mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
238
239 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
240 phy_skew_link.u32 = value;
241 mipi_rx_phy_cfg->PHY_SKEW_LINK.u32 = phy_skew_link.u32;
242 }
243
mipi_rx_set_phy_fsmo_link(unsigned int phy_id,unsigned int value)244 void mipi_rx_set_phy_fsmo_link(unsigned int phy_id, unsigned int value)
245 {
246 volatile mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
247
248 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
249 mipi_rx_phy_cfg->CIL_FSM0_LINK.u32 = value;
250 }
251
mipi_rx_set_phy_rg_2121_en(unsigned int phy_id,int enable)252 void mipi_rx_set_phy_rg_2121_en(unsigned int phy_id, int enable)
253 {
254 volatile U_PHY_MODE_LINK phy_mode_link;
255 mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
256
257 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
258 phy_mode_link.u32 = mipi_rx_phy_cfg->PHY_MODE_LINK.u32;
259 phy_mode_link.bits.phy0_rg_en_2l2l = enable;
260 mipi_rx_phy_cfg->PHY_MODE_LINK.u32 = phy_mode_link.u32;
261 }
262
mipi_rx_set_phy_rg_clk0_en(unsigned int phy_id,int enable)263 void mipi_rx_set_phy_rg_clk0_en(unsigned int phy_id, int enable)
264 {
265 volatile U_PHY_MODE_LINK phy_mode_link;
266 mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
267
268 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
269 phy_mode_link.u32 = mipi_rx_phy_cfg->PHY_MODE_LINK.u32;
270 phy_mode_link.bits.phy0_rg_faclk0_en = enable;
271 mipi_rx_phy_cfg->PHY_MODE_LINK.u32 = phy_mode_link.u32;
272 }
273
mipi_rx_set_phy_rg_clk1_en(unsigned int phy_id,int enable)274 void mipi_rx_set_phy_rg_clk1_en(unsigned int phy_id, int enable)
275 {
276 volatile U_PHY_MODE_LINK phy_mode_link;
277 mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
278
279 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
280 phy_mode_link.u32 = mipi_rx_phy_cfg->PHY_MODE_LINK.u32;
281 phy_mode_link.bits.phy0_rg_faclk1_en = enable;
282 mipi_rx_phy_cfg->PHY_MODE_LINK.u32 = phy_mode_link.u32;
283 }
284
mipi_rx_set_phy_rg_lp0_mode_en(unsigned int phy_id,int enable)285 void mipi_rx_set_phy_rg_lp0_mode_en(unsigned int phy_id, int enable)
286 {
287 volatile U_PHY_MODE_LINK phy_mode_link;
288 mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
289
290 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
291 phy_mode_link.u32 = mipi_rx_phy_cfg->PHY_MODE_LINK.u32;
292 phy_mode_link.bits.phy0_rg_en_lp0 = enable;
293 mipi_rx_phy_cfg->PHY_MODE_LINK.u32 = phy_mode_link.u32;
294 }
295
mipi_rx_set_phy_rg_lp1_mode_en(unsigned int phy_id,int enable)296 void mipi_rx_set_phy_rg_lp1_mode_en(unsigned int phy_id, int enable)
297 {
298 volatile U_PHY_MODE_LINK phy_mode_link;
299 mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
300
301 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
302 phy_mode_link.u32 = mipi_rx_phy_cfg->PHY_MODE_LINK.u32;
303 phy_mode_link.bits.phy0_rg_en_lp1 = enable;
304 mipi_rx_phy_cfg->PHY_MODE_LINK.u32 = phy_mode_link.u32;
305 }
306
mipi_rx_drv_set_work_mode(combo_dev_t devno,input_mode_t input_mode)307 void mipi_rx_drv_set_work_mode(combo_dev_t devno, input_mode_t input_mode)
308 {
309 unsigned long mipi_rx_work_mode_addr;
310
311 mipi_rx_work_mode_addr = (unsigned long)osal_ioremap(MIPI_RX_WORK_MODE_ADDR, (unsigned long)0x4);
312 if (mipi_rx_work_mode_addr == 0) {
313 HI_ERR("mipi_rx work mode reg ioremap failed!\n");
314 return;
315 }
316
317 if (input_mode == INPUT_MODE_MIPI) {
318 write_reg32(mipi_rx_work_mode_addr, 0x0 << (2 * devno), 0x1 << (2 * devno)); /* 2 bit, [1:0] */
319 } else if ((input_mode == INPUT_MODE_SUBLVDS) ||
320 (input_mode == INPUT_MODE_LVDS) || (input_mode == INPUT_MODE_HISPI)) {
321 write_reg32(mipi_rx_work_mode_addr, 0x1 << (2 * devno), 0x1 << (2 * devno)); /* 2 bit, [1:0] */
322 } else {
323 }
324
325 osal_iounmap((void *)mipi_rx_work_mode_addr, (unsigned long)0x4);
326 }
327
mipi_rx_drv_set_mipi_image_rect(combo_dev_t devno,img_rect_t * p_img_rect)328 void mipi_rx_drv_set_mipi_image_rect(combo_dev_t devno, img_rect_t *p_img_rect)
329 {
330 U_MIPI_CROP_START_CHN0 crop_start_chn0;
331 U_MIPI_CROP_START_CHN1 crop_start_chn1;
332 U_MIPI_CROP_START_CHN2 crop_start_chn2;
333 U_MIPI_CROP_START_CHN3 crop_start_chn3;
334 U_MIPI_IMGSIZE mipi_imgsize;
335
336 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
337
338 crop_start_chn0.u32 = mipi_ctrl_regs->MIPI_CROP_START_CHN0.u32;
339 crop_start_chn1.u32 = mipi_ctrl_regs->MIPI_CROP_START_CHN1.u32;
340 crop_start_chn2.u32 = mipi_ctrl_regs->MIPI_CROP_START_CHN2.u32;
341 crop_start_chn3.u32 = mipi_ctrl_regs->MIPI_CROP_START_CHN3.u32;
342 mipi_imgsize.u32 = mipi_ctrl_regs->MIPI_IMGSIZE.u32;
343
344 mipi_imgsize.bits.mipi_imgwidth = p_img_rect->width - 1;
345 mipi_imgsize.bits.mipi_imgheight = p_img_rect->height - 1;
346
347 crop_start_chn0.bits.mipi_start_x_chn0 = p_img_rect->x;
348 crop_start_chn0.bits.mipi_start_y_chn0 = p_img_rect->y;
349
350 crop_start_chn1.bits.mipi_start_x_chn1 = p_img_rect->x;
351 crop_start_chn1.bits.mipi_start_y_chn1 = p_img_rect->y;
352
353 crop_start_chn2.bits.mipi_start_x_chn2 = p_img_rect->x;
354 crop_start_chn2.bits.mipi_start_y_chn2 = p_img_rect->y;
355
356 crop_start_chn3.bits.mipi_start_x_chn3 = p_img_rect->x;
357 crop_start_chn3.bits.mipi_start_y_chn3 = p_img_rect->y;
358
359 mipi_ctrl_regs->MIPI_CROP_START_CHN0.u32 = crop_start_chn0.u32;
360 mipi_ctrl_regs->MIPI_CROP_START_CHN1.u32 = crop_start_chn1.u32;
361 mipi_ctrl_regs->MIPI_CROP_START_CHN2.u32 = crop_start_chn2.u32;
362 mipi_ctrl_regs->MIPI_CROP_START_CHN3.u32 = crop_start_chn3.u32;
363 mipi_ctrl_regs->MIPI_IMGSIZE.u32 = mipi_imgsize.u32;
364 }
365
mipi_rx_drv_set_mipi_crop_en(combo_dev_t devno,int enable)366 void mipi_rx_drv_set_mipi_crop_en(combo_dev_t devno, int enable)
367 {
368 U_MIPI_CTRL_MODE_PIXEL mipi_ctrl_mode_pixel;
369 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
370
371 mipi_ctrl_mode_pixel.u32 = mipi_ctrl_regs->MIPI_CTRL_MODE_PIXEL.u32;
372 mipi_ctrl_mode_pixel.bits.crop_en = enable;
373 mipi_ctrl_regs->MIPI_CTRL_MODE_PIXEL.u32 = mipi_ctrl_mode_pixel.u32;
374 }
375
mipi_rx_drv_get_data_type(data_type_t input_data_type)376 short mipi_rx_drv_get_data_type(data_type_t input_data_type)
377 {
378 if (input_data_type == DATA_TYPE_RAW_8BIT) {
379 return 0x2a;
380 } else if (input_data_type == DATA_TYPE_RAW_10BIT) {
381 return 0x2b;
382 } else if (input_data_type == DATA_TYPE_RAW_12BIT) {
383 return 0x2c;
384 } else if (input_data_type == DATA_TYPE_RAW_14BIT) {
385 return 0x2d;
386 } else if (input_data_type == DATA_TYPE_RAW_16BIT) {
387 return 0x2e;
388 } else if (input_data_type == DATA_TYPE_YUV420_8BIT_NORMAL) {
389 return 0x18;
390 } else if (input_data_type == DATA_TYPE_YUV420_8BIT_LEGACY) {
391 return 0x1a;
392 } else if (input_data_type == DATA_TYPE_YUV422_8BIT) {
393 return 0x1e;
394 } else if (input_data_type == DATA_TYPE_YUV422_PACKED) {
395 return 0x1e;
396 } else {
397 return 0x0;
398 }
399 }
400
mipi_rx_drv_get_data_bit_width(data_type_t input_data_type)401 short mipi_rx_drv_get_data_bit_width(data_type_t input_data_type)
402 {
403 if (input_data_type == DATA_TYPE_RAW_8BIT) {
404 return 0x0;
405 } else if (input_data_type == DATA_TYPE_RAW_10BIT) {
406 return 0x1;
407 } else if (input_data_type == DATA_TYPE_RAW_12BIT) {
408 return 0x2;
409 } else if (input_data_type == DATA_TYPE_RAW_14BIT) {
410 return 0x3;
411 } else if (input_data_type == DATA_TYPE_RAW_16BIT) {
412 return 0x4;
413 } else if (input_data_type == DATA_TYPE_YUV420_8BIT_NORMAL) {
414 return 0x0;
415 } else if (input_data_type == DATA_TYPE_YUV420_8BIT_LEGACY) {
416 return 0x0;
417 } else if (input_data_type == DATA_TYPE_YUV422_8BIT) {
418 return 0x0;
419 } else if (input_data_type == DATA_TYPE_YUV422_PACKED) {
420 return 0x4;
421 } else {
422 return 0x0;
423 }
424 }
425
426 /* magic num mean bit width, convert to register condfig */
mipi_rx_drv_get_ext_data_bit_width(unsigned int ext_data_bit_width)427 short mipi_rx_drv_get_ext_data_bit_width(unsigned int ext_data_bit_width)
428 {
429 if (ext_data_bit_width == 8) { /* 8:magic bit width */
430 return 0x0;
431 } else if (ext_data_bit_width == 10) { /* 10:magic bit width */
432 return 0x1;
433 } else if (ext_data_bit_width == 12) { /* 12:magic bit width */
434 return 0x2;
435 } else if (ext_data_bit_width == 14) { /* 14:magic bit width */
436 return 0x3;
437 } else if (ext_data_bit_width == 16) { /* 16:magic bit width */
438 return 0x4;
439 } else {
440 return 0x0;
441 }
442 }
443
mipi_rx_drv_set_di_dt(combo_dev_t devno,data_type_t input_data_type)444 void mipi_rx_drv_set_di_dt(combo_dev_t devno, data_type_t input_data_type)
445 {
446 U_MIPI_DI_1 mipi_di_1;
447 U_MIPI_DI_2 mipi_di_2;
448 unsigned int temp_data_type;
449 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
450
451 temp_data_type = mipi_rx_drv_get_data_type(input_data_type);
452
453 mipi_di_1.u32 = mipi_ctrl_regs->MIPI_DI_1.u32;
454 mipi_di_1.bits.di0_dt = temp_data_type;
455 mipi_di_1.bits.di1_dt = temp_data_type;
456 mipi_di_1.bits.di2_dt = temp_data_type;
457 mipi_di_1.bits.di3_dt = temp_data_type;
458 mipi_ctrl_regs->MIPI_DI_1.u32 = mipi_di_1.u32;
459
460 mipi_di_2.u32 = mipi_ctrl_regs->MIPI_DI_2.u32;
461 mipi_di_2.bits.di4_dt = temp_data_type;
462 mipi_di_2.bits.di5_dt = temp_data_type;
463 mipi_di_2.bits.di6_dt = temp_data_type;
464 mipi_di_2.bits.di7_dt = temp_data_type;
465 mipi_ctrl_regs->MIPI_DI_2.u32 = mipi_di_2.u32;
466 }
467
mipi_rx_drv_set_mode_pixel(combo_dev_t devno,data_type_t input_data_type)468 static void mipi_rx_drv_set_mode_pixel(combo_dev_t devno, data_type_t input_data_type)
469 {
470 U_MIPI_CTRL_MODE_PIXEL mipi_ctrl_mode_pixel;
471 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
472
473 mipi_ctrl_mode_pixel.u32 = mipi_ctrl_regs->MIPI_CTRL_MODE_PIXEL.u32;
474
475 if (input_data_type == DATA_TYPE_YUV420_8BIT_NORMAL) {
476 mipi_ctrl_mode_pixel.bits.mipi_yuv420_even_detect = 1;
477 mipi_ctrl_mode_pixel.bits.mipi_yuv_420_nolegacy_en = 1;
478 mipi_ctrl_mode_pixel.bits.mipi_yuv_420_legacy_en = 0;
479 mipi_ctrl_mode_pixel.bits.mipi_yuv_422_en = 0;
480 } else if (input_data_type == DATA_TYPE_YUV420_8BIT_LEGACY) {
481 mipi_ctrl_mode_pixel.bits.mipi_yuv_420_nolegacy_en = 0;
482 mipi_ctrl_mode_pixel.bits.mipi_yuv_420_legacy_en = 1;
483 mipi_ctrl_mode_pixel.bits.mipi_yuv_422_en = 0;
484 } else if (input_data_type == DATA_TYPE_YUV422_8BIT) {
485 mipi_ctrl_mode_pixel.bits.mipi_yuv_420_nolegacy_en = 0;
486 mipi_ctrl_mode_pixel.bits.mipi_yuv_420_legacy_en = 0;
487 mipi_ctrl_mode_pixel.bits.mipi_yuv_422_en = 1;
488 } else {
489 mipi_ctrl_mode_pixel.bits.mipi_yuv_420_nolegacy_en = 0;
490 mipi_ctrl_mode_pixel.bits.mipi_yuv_420_legacy_en = 0;
491 mipi_ctrl_mode_pixel.bits.mipi_yuv_422_en = 0;
492 }
493
494 mipi_ctrl_regs->MIPI_CTRL_MODE_PIXEL.u32 = mipi_ctrl_mode_pixel.u32;
495 }
496
mipi_rx_drv_set_user_def(combo_dev_t devno,data_type_t input_data_type)497 static void mipi_rx_drv_set_user_def(combo_dev_t devno, data_type_t input_data_type)
498 {
499 unsigned char bit_width;
500 unsigned int temp_data_type;
501 U_MIPI_USERDEF_DT user_def_dt;
502 U_MIPI_USER_DEF user_def;
503 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
504
505 if (input_data_type == DATA_TYPE_YUV420_8BIT_NORMAL) {
506 bit_width = 0;
507 temp_data_type = 0x18;
508 } else if (input_data_type == DATA_TYPE_YUV420_8BIT_LEGACY) {
509 bit_width = 0;
510 temp_data_type = 0x1a;
511 } else if (input_data_type == DATA_TYPE_YUV422_8BIT) {
512 bit_width = 0; /* 0 -- 8bit */
513 temp_data_type = 0x1e;
514 } else if (input_data_type == DATA_TYPE_YUV422_PACKED) {
515 bit_width = 4; /* 4 -- 16bit */
516 temp_data_type = 0x1e;
517 } else {
518 return;
519 }
520
521 user_def_dt.u32 = mipi_ctrl_regs->MIPI_USERDEF_DT.u32;
522 user_def.u32 = mipi_ctrl_regs->MIPI_USER_DEF.u32;
523
524 user_def_dt.bits.user_def0_dt = bit_width;
525 user_def_dt.bits.user_def1_dt = bit_width;
526 user_def_dt.bits.user_def2_dt = bit_width;
527 user_def_dt.bits.user_def3_dt = bit_width;
528
529 user_def.bits.user_def0 = temp_data_type;
530 user_def.bits.user_def1 = temp_data_type;
531 user_def.bits.user_def2 = temp_data_type;
532 user_def.bits.user_def3 = temp_data_type;
533
534 mipi_ctrl_regs->MIPI_USERDEF_DT.u32 = user_def_dt.u32;
535 mipi_ctrl_regs->MIPI_USER_DEF.u32 = user_def.u32;
536
537 return;
538 }
539
mipi_rx_drv_ctrl_mode_hs(combo_dev_t devno,data_type_t input_data_type)540 static void mipi_rx_drv_ctrl_mode_hs(combo_dev_t devno, data_type_t input_data_type)
541 {
542 unsigned char user_def_en;
543 U_MIPI_CTRL_MODE_HS mipi_ctrl_mode_hs;
544 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
545
546 if ((input_data_type == DATA_TYPE_YUV420_8BIT_NORMAL) ||
547 (input_data_type == DATA_TYPE_YUV420_8BIT_LEGACY) ||
548 (input_data_type == DATA_TYPE_YUV422_8BIT) ||
549 (input_data_type == DATA_TYPE_YUV422_PACKED)) {
550 user_def_en = 1;
551 } else {
552 user_def_en = 0;
553 }
554
555 mipi_ctrl_mode_hs.u32 = mipi_ctrl_regs->MIPI_CTRL_MODE_HS.u32;
556
557 mipi_ctrl_mode_hs.bits.user_def_en = user_def_en;
558
559 mipi_ctrl_regs->MIPI_CTRL_MODE_HS.u32 = mipi_ctrl_mode_hs.u32;
560 }
561
mipi_rx_drv_set_mipi_user_dt(combo_dev_t devno,int index,short data_type,short bit_width)562 void mipi_rx_drv_set_mipi_user_dt(combo_dev_t devno, int index, short data_type, short bit_width)
563 {
564 U_MIPI_USERDEF_DT user_def_dt;
565 U_MIPI_USER_DEF user_def;
566 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
567
568 if (mipi_ctrl_regs != NULL) {
569 user_def_dt.u32 = mipi_ctrl_regs->MIPI_USERDEF_DT.u32;
570 user_def.u32 = mipi_ctrl_regs->MIPI_USER_DEF.u32;
571
572 if (index == 0) {
573 user_def_dt.bits.user_def0_dt = bit_width;
574 user_def.bits.user_def0 = data_type;
575 } else if (index == 1) {
576 user_def_dt.bits.user_def1_dt = bit_width;
577 user_def.bits.user_def1 = data_type;
578 } else if (index == 2) {
579 user_def_dt.bits.user_def2_dt = bit_width;
580 user_def.bits.user_def2 = data_type;
581 } else if (index == 3) {
582 user_def_dt.bits.user_def3_dt = bit_width;
583 user_def.bits.user_def3 = data_type;
584 }
585
586 mipi_ctrl_regs->MIPI_USERDEF_DT.u32 = user_def_dt.u32;
587 mipi_ctrl_regs->MIPI_USER_DEF.u32 = user_def.u32;
588 }
589 }
590
mipi_rx_drv_set_mipi_yuv_dt(combo_dev_t devno,data_type_t input_data_type)591 void mipi_rx_drv_set_mipi_yuv_dt(combo_dev_t devno, data_type_t input_data_type)
592 {
593 mipi_rx_drv_ctrl_mode_hs(devno, input_data_type);
594
595 mipi_rx_drv_set_user_def(devno, input_data_type);
596
597 mipi_rx_drv_set_mode_pixel(devno, input_data_type);
598 }
599
mipi_rx_drv_set_mipi_wdr_user_dt(combo_dev_t devno,data_type_t input_data_type,const short data_type[WDR_VC_NUM])600 void mipi_rx_drv_set_mipi_wdr_user_dt(combo_dev_t devno, data_type_t input_data_type, const short data_type[WDR_VC_NUM])
601 {
602 U_MIPI_USERDEF_DT user_def_dt;
603 U_MIPI_USER_DEF user_def;
604 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
605
606 user_def_dt.u32 = mipi_ctrl_regs->MIPI_USERDEF_DT.u32;
607 user_def.u32 = mipi_ctrl_regs->MIPI_USER_DEF.u32;
608
609 user_def_dt.bits.user_def0_dt = input_data_type;
610 user_def_dt.bits.user_def1_dt = input_data_type;
611
612 user_def.bits.user_def0 = data_type[0];
613 user_def.bits.user_def1 = data_type[1];
614
615 mipi_ctrl_regs->MIPI_USERDEF_DT.u32 = user_def_dt.u32;
616 mipi_ctrl_regs->MIPI_USER_DEF.u32 = user_def.u32;
617 }
618
mipi_rx_drv_set_mipi_dol_id(combo_dev_t devno,data_type_t input_data_type,short dol_id[])619 void mipi_rx_drv_set_mipi_dol_id(combo_dev_t devno, data_type_t input_data_type, short dol_id[])
620 {
621 U_MIPI_DOL_ID_CODE0 dol_id0;
622 U_MIPI_DOL_ID_CODE1 dol_id1;
623 U_MIPI_DOL_ID_CODE2 dol_id2;
624 short lef, sef1, sef2;
625 short nxt_lef, nxt_sef1, nxt_sef2;
626 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
627
628 hi_mipi_rx_unused(input_data_type);
629 hi_mipi_rx_unused(dol_id);
630 dol_id0.u32 = mipi_ctrl_regs->MIPI_DOL_ID_CODE0.u32;
631 dol_id1.u32 = mipi_ctrl_regs->MIPI_DOL_ID_CODE1.u32;
632 dol_id2.u32 = mipi_ctrl_regs->MIPI_DOL_ID_CODE2.u32;
633
634 lef = 0x241;
635 sef1 = 0x242;
636 sef2 = 0x244;
637
638 nxt_lef = lef + (1 << 4); /* 4:The LEF frame ID code of the N+1 frame is larger than the LEF frame
639 * ID code of the Nth frame(1 << 4)
640 */
641 nxt_sef1 = sef1 + (1 << 4); /* 4:The SEF1 frame ID code of the N+1 frame is larger than the LEF frame
642 * ID code of the Nth frame(1 << 4)
643 */
644 nxt_sef2 = sef2 + (1 << 4); /* 4:The SEF2 frame ID code of the N+1 frame is larger than the LEF frame
645 * ID code of the Nth frame(1 << 4)
646 */
647
648 dol_id0.bits.id_code_reg0 = lef;
649 dol_id0.bits.id_code_reg1 = sef1;
650 dol_id1.bits.id_code_reg2 = sef2;
651
652 dol_id1.bits.id_code_reg3 = nxt_lef;
653 dol_id2.bits.id_code_reg4 = nxt_sef1;
654 dol_id2.bits.id_code_reg5 = nxt_sef2;
655
656 mipi_ctrl_regs->MIPI_DOL_ID_CODE0.u32 = dol_id0.u32;
657 mipi_ctrl_regs->MIPI_DOL_ID_CODE1.u32 = dol_id1.u32;
658 mipi_ctrl_regs->MIPI_DOL_ID_CODE2.u32 = dol_id2.u32;
659 }
660
mipi_rx_drv_set_mipi_wdr_mode(combo_dev_t devno,mipi_wdr_mode_t wdr_mode)661 void mipi_rx_drv_set_mipi_wdr_mode(combo_dev_t devno, mipi_wdr_mode_t wdr_mode)
662 {
663 U_MIPI_CTRL_MODE_HS mode_hs;
664 U_MIPI_CTRL_MODE_PIXEL mode_pixel;
665 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
666
667 mode_hs.u32 = mipi_ctrl_regs->MIPI_CTRL_MODE_HS.u32;
668 mode_pixel.u32 = mipi_ctrl_regs->MIPI_CTRL_MODE_PIXEL.u32;
669
670 if (wdr_mode == HI_MIPI_WDR_MODE_NONE) {
671 mode_pixel.bits.mipi_dol_mode = 0;
672 }
673
674 if (wdr_mode == HI_MIPI_WDR_MODE_VC) {
675 mode_pixel.bits.mipi_dol_mode = 0;
676 } else if (wdr_mode == HI_MIPI_WDR_MODE_DT) {
677 mode_hs.bits.user_def_en = 1;
678 } else if (wdr_mode == HI_MIPI_WDR_MODE_DOL) {
679 mode_pixel.bits.mipi_dol_mode = 1;
680 }
681
682 mipi_ctrl_regs->MIPI_CTRL_MODE_HS.u32 = mode_hs.u32;
683 mipi_ctrl_regs->MIPI_CTRL_MODE_PIXEL.u32 = mode_pixel.u32;
684 }
685
mipi_rx_drv_enable_user_define_dt(combo_dev_t devno,int enable)686 void mipi_rx_drv_enable_user_define_dt(combo_dev_t devno, int enable)
687 {
688 U_MIPI_CTRL_MODE_HS mode_hs;
689 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
690
691 if (mipi_ctrl_regs != NULL) {
692 mode_hs.u32 = mipi_ctrl_regs->MIPI_CTRL_MODE_HS.u32;
693 mode_hs.bits.user_def_en = enable;
694
695 mipi_ctrl_regs->MIPI_CTRL_MODE_HS.u32 = mode_hs.u32;
696 }
697 }
698
mipi_rx_drv_set_ext_data_type(ext_data_type_t * data_type,data_type_t input_data_type)699 void mipi_rx_drv_set_ext_data_type(ext_data_type_t* data_type, data_type_t input_data_type)
700 {
701 unsigned int i;
702 combo_dev_t devno;
703 short input_dt;
704 short bit_width;
705 short ext_bit_width;
706
707 devno = data_type->devno;
708 input_dt = mipi_rx_drv_get_data_type(input_data_type);
709 bit_width = mipi_rx_drv_get_data_bit_width(input_data_type);
710
711 mipi_rx_drv_set_mipi_user_dt(devno, 0, input_dt, bit_width);
712
713 for (i = 0; i < data_type->num; i++) {
714 ext_bit_width = mipi_rx_drv_get_ext_data_bit_width(data_type->ext_data_bit_width[i]);
715 mipi_rx_drv_set_mipi_user_dt(devno, i + 1, data_type->ext_data_type[i], ext_bit_width);
716 }
717
718 mipi_rx_drv_enable_user_define_dt(devno, 1);
719 }
720
mipi_rx_drv_get_phy_data(int phy_id,int lane_id)721 unsigned int mipi_rx_drv_get_phy_data(int phy_id, int lane_id)
722 {
723 volatile U_PHY_DATA_LINK phy_data_link;
724 mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
725 unsigned int lane_data = 0x0;
726
727 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
728 phy_data_link.u32 = mipi_rx_phy_cfg->PHY_DATA_LINK.u32;
729
730 if (lane_id == 0) { /* 0 -- lane_id 0 */
731 lane_data = phy_data_link.bits.phy_data0_mipi;
732 } else if (lane_id == 1) { /* 1 -- lane_id 1 */
733 lane_data = phy_data_link.bits.phy_data1_mipi;
734 } else if (lane_id == 2) { /* 2 -- lane_id 2 */
735 lane_data = phy_data_link.bits.phy_data2_mipi;
736 } else if (lane_id == 3) { /* 3 -- lane_id 3 */
737 lane_data = phy_data_link.bits.phy_data3_mipi;
738 }
739
740 return lane_data;
741 }
742
mipi_rx_drv_get_phy_mipi_link_data(int phy_id,int lane_id)743 unsigned int mipi_rx_drv_get_phy_mipi_link_data(int phy_id, int lane_id)
744 {
745 volatile U_PHY_DATA_MIPI_LINK phy_data_mipi_link;
746 mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
747 unsigned int lane_data = 0x0;
748
749 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
750 phy_data_mipi_link.u32 = mipi_rx_phy_cfg->PHY_DATA_MIPI_LINK.u32;
751
752 if (lane_id == 0) { /* 0 -- lane_id 0 */
753 lane_data = phy_data_mipi_link.bits.phy_data0_mipi_hs;
754 } else if (lane_id == 1) { /* 1 -- lane_id 1 */
755 lane_data = phy_data_mipi_link.bits.phy_data1_mipi_hs;
756 } else if (lane_id == 2) { /* 2 -- lane_id 2 */
757 lane_data = phy_data_mipi_link.bits.phy_data2_mipi_hs;
758 } else if (lane_id == 3) { /* 3 -- lane_id 3 */
759 lane_data = phy_data_mipi_link.bits.phy_data3_mipi_hs;
760 }
761
762 return lane_data;
763 }
764
765
mipi_rx_drv_get_phy_lvds_link_data(int phy_id,int lane_id)766 unsigned int mipi_rx_drv_get_phy_lvds_link_data(int phy_id, int lane_id)
767 {
768 volatile U_PHY_DATA_LVDS_LINK phy_data_lvds_link;
769 mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
770 unsigned int lane_data = 0x0;
771
772 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
773 phy_data_lvds_link.u32 = mipi_rx_phy_cfg->PHY_DATA_LVDS_LINK.u32;
774
775 if (lane_id == 0) { /* 0 -- lane_id 0 */
776 lane_data = phy_data_lvds_link.bits.phy_data0_lvds_hs;
777 } else if (lane_id == 1) { /* 1 -- lane_id 1 */
778 lane_data = phy_data_lvds_link.bits.phy_data1_lvds_hs;
779 } else if (lane_id == 2) { /* 2 -- lane_id 2 */
780 lane_data = phy_data_lvds_link.bits.phy_data2_lvds_hs;
781 } else if (lane_id == 3) { /* 3 -- lane_id 3 */
782 lane_data = phy_data_lvds_link.bits.phy_data3_lvds_hs;
783 }
784
785 return lane_data;
786 }
787
mipi_rx_drv_set_data_rate(combo_dev_t devno,mipi_data_rate_t data_rate)788 void mipi_rx_drv_set_data_rate(combo_dev_t devno, mipi_data_rate_t data_rate)
789 {
790 U_MIPI_CTRL_MODE_PIXEL mipi_ctrl_mode_pixel;
791 unsigned int mipi_double_pix_en = 0;
792 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
793
794 if (data_rate == MIPI_DATA_RATE_X1) {
795 mipi_double_pix_en = 0;
796 } else if (data_rate == MIPI_DATA_RATE_X2) {
797 mipi_double_pix_en = 1;
798 } else {
799 HI_ERR("unsupported data_rate:%d devno %d\n", data_rate, devno);
800 return;
801 }
802
803 mipi_ctrl_mode_pixel.u32 = mipi_ctrl_regs->MIPI_CTRL_MODE_PIXEL.u32;
804 mipi_ctrl_mode_pixel.bits.mipi_double_pix_en = mipi_double_pix_en;
805 mipi_ctrl_mode_pixel.bits.sync_clear_en = 0x1;
806 mipi_ctrl_regs->MIPI_CTRL_MODE_PIXEL.u32 = mipi_ctrl_mode_pixel.u32;
807 }
808
mipi_rx_set_lane_id(combo_dev_t devno,int lane_idx,short lane_id,unsigned int lane_bitmap,lane_divide_mode_t mode)809 void mipi_rx_set_lane_id(combo_dev_t devno, int lane_idx, short lane_id,
810 unsigned int lane_bitmap, lane_divide_mode_t mode)
811 {
812 U_LANE_ID0_CHN lane_id0_ch0;
813
814 volatile lvds_ctrl_regs_t *lvds_ctrl_regs = get_lvds_ctrl_regs(devno);
815
816 lane_id0_ch0.u32 = lvds_ctrl_regs->LANE_ID0_CHN0.u32;
817
818 switch (lane_id) {
819 case 0: /* 0 -- lane_id 0 */
820 lane_id0_ch0.bits.lane0_id = lane_idx;
821 break;
822
823 case 1: /* 1 -- lane_id 1 */
824 lane_id0_ch0.bits.lane1_id = lane_idx;
825 break;
826
827 case 2: /* 2 -- lane_id 2 */
828 lane_id0_ch0.bits.lane2_id = lane_idx;
829 break;
830
831 case 3: /* 3 -- lane_id 3 */
832 lane_id0_ch0.bits.lane3_id = lane_idx;
833 break;
834
835 default:
836 break;
837 }
838
839 if (lane_bitmap == 0xa && mode == 1 && devno == 1) {
840 lane_id0_ch0.u32 = 0x3210;
841 }
842
843 lvds_ctrl_regs->LANE_ID0_CHN0.u32 = lane_id0_ch0.u32;
844 }
845
mipi_rx_drv_set_link_lane_id(combo_dev_t devno,input_mode_t input_mode,const short * p_lane_id,unsigned int lane_bitmap,lane_divide_mode_t mode)846 void mipi_rx_drv_set_link_lane_id(combo_dev_t devno, input_mode_t input_mode, const short *p_lane_id,
847 unsigned int lane_bitmap, lane_divide_mode_t mode)
848 {
849 int i;
850 int lane_num;
851
852 if (input_mode == INPUT_MODE_MIPI) {
853 lane_num = MIPI_LANE_NUM;
854 } else {
855 lane_num = LVDS_LANE_NUM;
856 }
857
858 for (i = 0; i < lane_num; i++) {
859 if (is_valid_id(p_lane_id[i])) {
860 mipi_rx_set_lane_id(devno, i, p_lane_id[i], lane_bitmap, mode);
861 }
862 }
863 }
864
mipi_rx_drv_set_mem_cken(combo_dev_t devno,int enable)865 void mipi_rx_drv_set_mem_cken(combo_dev_t devno, int enable)
866 {
867 U_CHN0_MEM_CTRL chn0_mem_ctrl;
868 U_CHN1_MEM_CTRL chn1_mem_ctrl;
869 mipi_rx_sys_regs_t *mipi_rx_sys_regs = NULL;
870
871 mipi_rx_sys_regs = get_mipi_rx_sys_regs();
872
873 switch (devno) {
874 case 0: /* 0 -- mipi dev 0 */
875 chn0_mem_ctrl.u32 = mipi_rx_sys_regs->CHN0_MEM_CTRL.u32;
876 chn0_mem_ctrl.bits.chn0_mem_ck_gt = enable;
877 mipi_rx_sys_regs->CHN0_MEM_CTRL.u32 = chn0_mem_ctrl.u32;
878 break;
879 case 1: /* 1 -- mipi dev 1 */
880 chn1_mem_ctrl.u32 = mipi_rx_sys_regs->CHN1_MEM_CTRL.u32;
881 chn1_mem_ctrl.bits.chn1_mem_ck_gt = enable;
882 mipi_rx_sys_regs->CHN1_MEM_CTRL.u32 = chn1_mem_ctrl.u32;
883 break;
884 default:
885 break;
886 }
887 }
888
mipi_rx_drv_set_clr_cken(combo_dev_t devno,int enable)889 void mipi_rx_drv_set_clr_cken(combo_dev_t devno, int enable)
890 {
891 U_CHN0_CLR_EN chn0_clr_en;
892 U_CHN1_CLR_EN chn1_clr_en;
893 mipi_rx_sys_regs_t *mipi_rx_sys_regs = NULL;
894
895 mipi_rx_sys_regs = get_mipi_rx_sys_regs();
896
897 switch (devno) {
898 case 0: /* 0 -- mipi dev 0 */
899 chn0_clr_en.u32 = mipi_rx_sys_regs->CHN0_CLR_EN.u32;
900 chn0_clr_en.bits.chn0_clr_en_lvds = enable;
901 chn0_clr_en.bits.chn0_clr_en_align = enable;
902 mipi_rx_sys_regs->CHN0_CLR_EN.u32 = chn0_clr_en.u32;
903 break;
904 case 1: /* 1 -- mipi dev 1 */
905 chn1_clr_en.u32 = mipi_rx_sys_regs->CHN1_CLR_EN.u32;
906 chn1_clr_en.bits.chn1_clr_en_lvds = enable;
907 chn1_clr_en.bits.chn1_clr_en_align = enable;
908 mipi_rx_sys_regs->CHN1_CLR_EN.u32 = chn1_clr_en.u32;
909 break;
910
911 default:
912 break;
913 }
914 }
915
mipi_rx_drv_set_lane_num(combo_dev_t devno,unsigned int lane_num)916 void mipi_rx_drv_set_lane_num(combo_dev_t devno, unsigned int lane_num)
917 {
918 U_MIPI_LANES_NUM mipi_lanes_num;
919 mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
920
921 mipi_lanes_num.u32 = mipi_ctrl_regs->MIPI_LANES_NUM.u32;
922 mipi_lanes_num.bits.lane_num = lane_num - 1;
923 mipi_ctrl_regs->MIPI_LANES_NUM.u32 = mipi_lanes_num.u32;
924 }
925
mipi_rx_drv_set_phy_en_link(unsigned int phy_id,unsigned int lane_bitmap)926 void mipi_rx_drv_set_phy_en_link(unsigned int phy_id, unsigned int lane_bitmap)
927 {
928 U_PHY_EN_LINK phy_en_link;
929 mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
930
931 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
932 phy_en_link.u32 = mipi_rx_phy_cfg->PHY_EN_LINK.u32;
933
934 if (lane_bitmap & 0x5) {
935 phy_en_link.bits.phy_da_d0_valid = lane_bitmap & 0x1; /* 0 -- lane0 */
936 phy_en_link.bits.phy_da_d2_valid = (lane_bitmap & 0x4) >> 2; /* 2 -- lane2 */
937 phy_en_link.bits.phy_d0_term_en = lane_bitmap & 0x1;
938 phy_en_link.bits.phy_d2_term_en = (lane_bitmap & 0x4) >> 2; /* 2 -- lane2 */
939 phy_en_link.bits.phy_clk0_term_en = 1;
940 }
941
942 if (lane_bitmap & 0xa) {
943 phy_en_link.bits.phy_da_d1_valid = (lane_bitmap & 0x2) >> 1; /* 1 -- lane1 */
944 phy_en_link.bits.phy_da_d3_valid = (lane_bitmap & 0x8) >> 3; /* 3 -- lane3 */
945 phy_en_link.bits.phy_d1_term_en = (lane_bitmap & 0x2) >> 1; /* 1 -- lane1 */
946 phy_en_link.bits.phy_d3_term_en = (lane_bitmap & 0x8) >> 3; /* 3 -- lane3 */
947 phy_en_link.bits.phy_clk1_term_en = 1;
948 }
949
950 mipi_rx_phy_cfg->PHY_EN_LINK.u32 = phy_en_link.u32;
951 }
952
mipi_rx_drv_set_phy_mode(unsigned int phy_id,input_mode_t input_mode,unsigned int lane_bitmap)953 void mipi_rx_drv_set_phy_mode(unsigned int phy_id, input_mode_t input_mode, unsigned int lane_bitmap)
954 {
955 U_PHY_MODE_LINK phy_mode_link;
956 mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
957 int cmos_en = 0;
958
959 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
960 phy_mode_link.u32 = mipi_rx_phy_cfg->PHY_MODE_LINK.u32;
961
962 if (input_mode == INPUT_MODE_CMOS ||
963 input_mode == INPUT_MODE_BT1120 ||
964 input_mode == INPUT_MODE_BYPASS) {
965 cmos_en = 1;
966 }
967
968 phy_mode_link.bits.phy0_rg_en_d = phy_mode_link.bits.phy0_rg_en_d | (lane_bitmap & 0xf);
969 phy_mode_link.bits.phy0_rg_en_cmos = cmos_en;
970 phy_mode_link.bits.phy0_rg_en_clk0 = 1;
971 phy_mode_link.bits.phy0_rg_mipi_mode0 = 1;
972
973 if (lane_bitmap & 0xa) {
974 phy_mode_link.bits.phy0_rg_en_clk1 = 1;
975 phy_mode_link.bits.phy0_rg_mipi_mode1 = 1;
976 }
977
978 mipi_rx_phy_cfg->PHY_MODE_LINK.u32 = phy_mode_link.u32;
979 }
980
mipi_rx_drv_set_cmos_en(unsigned int phy_id,int enable)981 void mipi_rx_drv_set_cmos_en(unsigned int phy_id, int enable)
982 {
983 volatile U_PHY_MODE_LINK phy_mode_link;
984 mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
985
986 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
987 phy_mode_link.u32 = mipi_rx_phy_cfg->PHY_MODE_LINK.u32;
988 phy_mode_link.bits.phy0_rg_en_cmos = enable;
989 mipi_rx_phy_cfg->PHY_MODE_LINK.u32 = phy_mode_link.u32;
990 }
991
mipi_rx_drv_set_phy_en(unsigned int lane_bitmap)992 void mipi_rx_drv_set_phy_en(unsigned int lane_bitmap)
993 {
994 U_PHY_EN phy_en;
995 mipi_rx_sys_regs_t *mipi_rx_sys_regs = NULL;
996
997 mipi_rx_sys_regs = get_mipi_rx_sys_regs();
998 phy_en.u32 = mipi_rx_sys_regs->PHY_EN.u32;
999
1000 if (lane_bitmap & 0xf) {
1001 phy_en.bits.phy0_en = 1;
1002 }
1003
1004 mipi_rx_sys_regs->PHY_EN.u32 = phy_en.u32;
1005 }
1006
mipi_rx_drv_set_lane_en(unsigned int lane_bitmap)1007 void mipi_rx_drv_set_lane_en(unsigned int lane_bitmap)
1008 {
1009 U_LANE_EN lane_en;
1010 mipi_rx_sys_regs_t *mipi_rx_sys_regs = NULL;
1011
1012 mipi_rx_sys_regs = get_mipi_rx_sys_regs();
1013 lane_en.u32 = mipi_rx_sys_regs->LANE_EN.u32;
1014 lane_en.u32 = lane_en.u32 | (lane_bitmap & 0xf);
1015 mipi_rx_sys_regs->LANE_EN.u32 = lane_en.u32;
1016 }
1017
mipi_rx_drv_set_phy_cil_en(unsigned int lane_bitmap,int enable)1018 void mipi_rx_drv_set_phy_cil_en(unsigned int lane_bitmap, int enable)
1019 {
1020 U_PHY_CIL_CTRL phy_cil_ctrl;
1021 mipi_rx_sys_regs_t *mipi_rx_sys_regs = NULL;
1022
1023 mipi_rx_sys_regs = get_mipi_rx_sys_regs();
1024 phy_cil_ctrl.u32 = mipi_rx_sys_regs->PHY_CIL_CTRL.u32;
1025
1026 if (lane_bitmap & 0xf) {
1027 phy_cil_ctrl.bits.phycil0_cken = enable;
1028 }
1029
1030 mipi_rx_sys_regs->PHY_CIL_CTRL.u32 = phy_cil_ctrl.u32;
1031 }
1032
mipi_rx_drv_set_phy_cfg_mode(input_mode_t input_mode,unsigned int lane_bitmap)1033 void mipi_rx_drv_set_phy_cfg_mode(input_mode_t input_mode, unsigned int lane_bitmap)
1034 {
1035 U_PHYCFG_MODE phycfg_mode;
1036 mipi_rx_sys_regs_t *mipi_rx_sys_regs = NULL;
1037 unsigned int cfg_mode;
1038 unsigned int cfg_mode_sel;
1039
1040 mipi_rx_sys_regs = get_mipi_rx_sys_regs();
1041 phycfg_mode.u32 = mipi_rx_sys_regs->PHYCFG_MODE.u32;
1042
1043 if (input_mode == INPUT_MODE_MIPI) {
1044 cfg_mode = 0;
1045 cfg_mode_sel = 0;
1046 } else if (input_mode == INPUT_MODE_SUBLVDS ||
1047 input_mode == INPUT_MODE_LVDS ||
1048 input_mode == INPUT_MODE_HISPI) {
1049 cfg_mode = 1;
1050 cfg_mode_sel = 0; /* RAW */
1051 } else {
1052 cfg_mode = 2; /* 2 -- PHY cfg is controlled by register value */
1053 cfg_mode_sel = 1; /* CMOS */
1054 }
1055
1056 if (lane_bitmap & 0xf) {
1057 phycfg_mode.bits.phycil0_0_cfg_mode = cfg_mode;
1058 phycfg_mode.bits.phycil0_1_cfg_mode = cfg_mode;
1059 phycfg_mode.bits.phycil0_cfg_mode_sel = cfg_mode_sel;
1060 } else if (lane_bitmap & 0x5) {
1061 phycfg_mode.bits.phycil0_0_cfg_mode = cfg_mode;
1062 phycfg_mode.bits.phycil0_cfg_mode_sel = cfg_mode_sel;
1063 } else if (lane_bitmap & 0xa) {
1064 phycfg_mode.bits.phycil0_1_cfg_mode = cfg_mode;
1065 phycfg_mode.bits.phycil0_cfg_mode_sel = cfg_mode_sel;
1066 }
1067
1068 mipi_rx_sys_regs->PHYCFG_MODE.u32 = phycfg_mode.u32;
1069 }
1070
mipi_rx_drv_set_phy_cfg_en(unsigned int lane_bitmap,int enable)1071 void mipi_rx_drv_set_phy_cfg_en(unsigned int lane_bitmap, int enable)
1072 {
1073 U_PHYCFG_EN phycfg_en;
1074 mipi_rx_sys_regs_t *mipi_rx_sys_regs = NULL;
1075
1076 mipi_rx_sys_regs = get_mipi_rx_sys_regs();
1077 phycfg_en.u32 = mipi_rx_sys_regs->PHYCFG_EN.u32;
1078
1079 if (lane_bitmap & 0xf) {
1080 phycfg_en.bits.phycil0_cfg_en = enable;
1081 }
1082
1083 mipi_rx_sys_regs->PHYCFG_EN.u32 = phycfg_en.u32;
1084 }
1085
mipi_rx_drv_set_phy_config(input_mode_t input_mode,unsigned int lane_bitmap)1086 void mipi_rx_drv_set_phy_config(input_mode_t input_mode, unsigned int lane_bitmap)
1087 {
1088 unsigned int i;
1089 unsigned int mask;
1090 unsigned int phy_lane_bitmap;
1091
1092 for (i = 0; i < MIPI_RX_MAX_PHY_NUM; i++) {
1093 mask = 0xf << (4 * i); /* 4 -- 4bit */
1094 if (lane_bitmap & mask) {
1095 phy_lane_bitmap = (lane_bitmap & mask) >> (4 * i); /* 4 -- 4bit */
1096 mipi_rx_drv_set_phy_en_link(i, phy_lane_bitmap);
1097 mipi_rx_drv_set_phy_mode(i, input_mode, phy_lane_bitmap);
1098 }
1099 }
1100
1101 mipi_rx_drv_set_phy_en(lane_bitmap);
1102 mipi_rx_drv_set_lane_en(lane_bitmap);
1103 mipi_rx_drv_set_phy_cil_en(lane_bitmap, 1);
1104 mipi_rx_drv_set_phy_cfg_mode(input_mode, lane_bitmap);
1105 mipi_rx_drv_set_phy_cfg_en(lane_bitmap, 1);
1106 }
1107
mipi_rx_drv_set_phy_cmv(unsigned int phy_id,phy_cmv_mode_t cmv_mode,unsigned int lane_bitmap)1108 static void mipi_rx_drv_set_phy_cmv(unsigned int phy_id, phy_cmv_mode_t cmv_mode, unsigned int lane_bitmap)
1109 {
1110 int mipi_cmv_mode = 0;
1111 U_PHY_MODE_LINK phy_mode_link;
1112 mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
1113
1114 if (cmv_mode == PHY_CMV_GE1200MV) {
1115 mipi_cmv_mode = 0;
1116 } else if (cmv_mode == PHY_CMV_LT1200MV) {
1117 mipi_cmv_mode = 1;
1118 }
1119
1120 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
1121 phy_mode_link.u32 = mipi_rx_phy_cfg->PHY_MODE_LINK.u32;
1122
1123 if (lane_bitmap & 0xa) {
1124 phy_mode_link.bits.phy0_rg_mipi_mode1 = mipi_cmv_mode;
1125 }
1126
1127 if (lane_bitmap & 0x5) {
1128 phy_mode_link.bits.phy0_rg_mipi_mode0 = mipi_cmv_mode;
1129 }
1130
1131 mipi_rx_phy_cfg->PHY_MODE_LINK.u32 = phy_mode_link.u32;
1132 }
1133
1134
mipi_rx_drv_set_phy_cmvmode(input_mode_t input_mode,phy_cmv_mode_t cmv_mode,unsigned int lane_bitmap)1135 void mipi_rx_drv_set_phy_cmvmode(input_mode_t input_mode, phy_cmv_mode_t cmv_mode, unsigned int lane_bitmap)
1136 {
1137 unsigned int i;
1138 unsigned int mask;
1139 unsigned int phy_lane_bitmap;
1140
1141 for (i = 0; i < MIPI_RX_MAX_PHY_NUM; i++) {
1142 mask = 0xf << (4 * i); /* 4 -- 4bit */
1143 if (lane_bitmap & mask) {
1144 phy_lane_bitmap = (lane_bitmap & mask) >> (4 * i); /* 4 -- 4bit */
1145 mipi_rx_drv_set_phy_cmv(i, cmv_mode, phy_lane_bitmap);
1146 }
1147 }
1148
1149 mipi_rx_drv_set_phy_cfg_mode(input_mode, lane_bitmap);
1150 mipi_rx_drv_set_phy_cfg_en(lane_bitmap, 1);
1151 }
1152
mipi_rx_drv_set_lvds_image_rect(combo_dev_t devno,img_rect_t * p_img_rect,short total_lane_num)1153 void mipi_rx_drv_set_lvds_image_rect(combo_dev_t devno, img_rect_t *p_img_rect, short total_lane_num)
1154 {
1155 volatile lvds_ctrl_regs_t *ctrl_reg = NULL;
1156 U_LVDS_IMGSIZE lvds_img_size;
1157 U_LVDS_CROP_START0 crop_start0;
1158 U_LVDS_CROP_START1 crop_start1;
1159 U_LVDS_CROP_START2 crop_start2;
1160 U_LVDS_CROP_START3 crop_start3;
1161 unsigned int width_per_lane, x_per_lane;
1162
1163 ctrl_reg = get_lvds_ctrl_regs(devno);
1164
1165 if (total_lane_num == 0) {
1166 return;
1167 }
1168
1169 width_per_lane = (p_img_rect->width / total_lane_num);
1170 x_per_lane = (p_img_rect->x / total_lane_num);
1171
1172 lvds_img_size.u32 = ctrl_reg->LVDS_IMGSIZE.u32;
1173 crop_start0.u32 = ctrl_reg->LVDS_CROP_START0.u32;
1174 crop_start1.u32 = ctrl_reg->LVDS_CROP_START1.u32;
1175 crop_start2.u32 = ctrl_reg->LVDS_CROP_START2.u32;
1176 crop_start3.u32 = ctrl_reg->LVDS_CROP_START3.u32;
1177
1178 lvds_img_size.bits.lvds_imgwidth_lane = width_per_lane - 1;
1179 lvds_img_size.bits.lvds_imgheight = p_img_rect->height - 1;
1180
1181 crop_start0.bits.lvds_start_x0_lane = x_per_lane;
1182 crop_start0.bits.lvds_start_y0 = p_img_rect->y;
1183
1184 crop_start1.bits.lvds_start_x1_lane = x_per_lane;
1185 crop_start1.bits.lvds_start_y1 = p_img_rect->y;
1186
1187 crop_start2.bits.lvds_start_x2_lane = x_per_lane;
1188 crop_start2.bits.lvds_start_y2 = p_img_rect->y;
1189
1190 crop_start3.bits.lvds_start_x3_lane = x_per_lane;
1191 crop_start3.bits.lvds_start_y3 = p_img_rect->y;
1192
1193 ctrl_reg->LVDS_IMGSIZE.u32 = lvds_img_size.u32;
1194 ctrl_reg->LVDS_CROP_START0.u32 = crop_start0.u32;
1195 ctrl_reg->LVDS_CROP_START1.u32 = crop_start1.u32;
1196 ctrl_reg->LVDS_CROP_START2.u32 = crop_start2.u32;
1197 ctrl_reg->LVDS_CROP_START3.u32 = crop_start3.u32;
1198 }
1199
mipi_rx_drv_set_lvds_crop_en(combo_dev_t devno,int enable)1200 void mipi_rx_drv_set_lvds_crop_en(combo_dev_t devno, int enable)
1201 {
1202 volatile lvds_ctrl_regs_t *ctrl_reg = NULL;
1203 U_LVDS_CTRL lvds_ctrl;
1204
1205 ctrl_reg = get_lvds_ctrl_regs(devno);
1206 if (ctrl_reg == NULL) {
1207 return;
1208 }
1209
1210 lvds_ctrl.u32 = ctrl_reg->LVDS_CTRL.u32;
1211 lvds_ctrl.bits.lvds_crop_en = enable;
1212 ctrl_reg->LVDS_CTRL.u32 = lvds_ctrl.u32;
1213 }
1214
mipi_rx_hal_set_lvds_wdr_en(combo_dev_t devno,wdr_mode_t wdr_mode)1215 static int mipi_rx_hal_set_lvds_wdr_en(combo_dev_t devno, wdr_mode_t wdr_mode)
1216 {
1217 int ret = HI_SUCCESS;
1218 U_LVDS_WDR lvds_wdr;
1219 volatile lvds_ctrl_regs_t *ctrl_reg = NULL;
1220
1221 ctrl_reg = get_lvds_ctrl_regs(devno);
1222 lvds_wdr.u32 = ctrl_reg->LVDS_WDR.u32;
1223
1224 if (wdr_mode == HI_WDR_MODE_NONE) {
1225 lvds_wdr.bits.lvds_wdr_en = 0;
1226 lvds_wdr.bits.lvds_wdr_num = 0;
1227 } else {
1228 lvds_wdr.bits.lvds_wdr_en = 1;
1229
1230 switch (wdr_mode) {
1231 case HI_WDR_MODE_2F:
1232 case HI_WDR_MODE_DOL_2F:
1233 lvds_wdr.bits.lvds_wdr_num = 1; /* 1 -- 2_wdr */
1234 break;
1235
1236 case HI_WDR_MODE_3F:
1237 case HI_WDR_MODE_DOL_3F:
1238 lvds_wdr.bits.lvds_wdr_num = 2; /* 2 -- 3_wdr */
1239 break;
1240
1241 case HI_WDR_MODE_4F:
1242 case HI_WDR_MODE_DOL_4F:
1243 lvds_wdr.bits.lvds_wdr_num = 3; /* 3 -- 4_wdr */
1244 break;
1245
1246 default:
1247 ret = HI_FAILURE;
1248 HI_ERR("not support WDR_MODE: %d\n", wdr_mode);
1249 break;
1250 }
1251 }
1252
1253 ctrl_reg->LVDS_WDR.u32 = lvds_wdr.u32;
1254
1255 return ret;
1256 }
1257
mipi_rx_hal_set_lvds_sof_wdr(combo_dev_t devno,wdr_mode_t wdr_mode,const lvds_vsync_attr_t * vsync_attr)1258 static int mipi_rx_hal_set_lvds_sof_wdr(combo_dev_t devno, wdr_mode_t wdr_mode,
1259 const lvds_vsync_attr_t *vsync_attr)
1260 {
1261 U_LVDS_WDR lvds_wdr;
1262 volatile lvds_ctrl_regs_t *ctrl_reg = NULL;
1263
1264 hi_mipi_rx_unused(wdr_mode);
1265 ctrl_reg = get_lvds_ctrl_regs(devno);
1266 lvds_wdr.u32 = ctrl_reg->LVDS_WDR.u32;
1267
1268 if (vsync_attr->sync_type == LVDS_VSYNC_NORMAL) {
1269 /* SOF-EOF WDR, long exposure frame and short exposure frame has independent sync code */
1270 lvds_wdr.bits.lvds_wdr_mode = 0x0;
1271 } else if (vsync_attr->sync_type == LVDS_VSYNC_SHARE) {
1272 /* SOF-EOF WDR, long exposure frame and short exposure frame share the SOF and EOF */
1273 lvds_wdr.bits.lvds_wdr_mode = 0x2;
1274 } else {
1275 HI_ERR("not support vsync type: %d\n", vsync_attr->sync_type);
1276 return HI_FAILURE;
1277 }
1278
1279 ctrl_reg->LVDS_WDR.u32 = lvds_wdr.u32;
1280
1281 return HI_SUCCESS;
1282 }
1283
mipi_rx_hal_set_lvds_dol_wdr(combo_dev_t devno,wdr_mode_t wdr_mode,const lvds_vsync_attr_t * vsync_attr,const lvds_fid_attr_t * fid_attr)1284 static int mipi_rx_hal_set_lvds_dol_wdr(combo_dev_t devno, wdr_mode_t wdr_mode,
1285 const lvds_vsync_attr_t *vsync_attr, const lvds_fid_attr_t *fid_attr)
1286 {
1287 U_LVDS_WDR lvds_wdr;
1288 volatile lvds_ctrl_regs_t *ctrl_reg = NULL;
1289
1290 hi_mipi_rx_unused(wdr_mode);
1291 ctrl_reg = get_lvds_ctrl_regs(devno);
1292 lvds_wdr.u32 = ctrl_reg->LVDS_WDR.u32;
1293
1294 /* Sony DOL WDR */
1295 if (vsync_attr->sync_type == LVDS_VSYNC_NORMAL) {
1296 /*
1297 * SAV-EAV WDR, 4 sync code, fid embedded in 4th sync code
1298 * long exposure fame and short exposure frame has independent sync code
1299 */
1300 if (fid_attr->fid_type == LVDS_FID_IN_SAV) {
1301 lvds_wdr.bits.lvds_wdr_mode = 0x4;
1302 } else if (fid_attr->fid_type == LVDS_FID_IN_DATA) {
1303 /*
1304 * SAV-EAV WDR, 5 sync code(Line Information), fid in the fist DATA,
1305 * fid in data, line information
1306 */
1307 if (fid_attr->output_fil) {
1308 /* Frame Information Line is included in the image data */
1309 lvds_wdr.bits.lvds_wdr_mode = 0xd;
1310 } else {
1311 /* Frame Information Line is not included in the image data */
1312 lvds_wdr.bits.lvds_wdr_mode = 0x6;
1313 }
1314 } else {
1315 HI_ERR("not support fid type: %d\n", fid_attr->fid_type);
1316 return HI_FAILURE;
1317 }
1318 } else if (vsync_attr->sync_type == LVDS_VSYNC_HCONNECT) {
1319 /*
1320 * SAV-EAV H-Connection DOL, long exposure frame and short exposure frame
1321 * share the same SAV EAV, the H-Blank is assigned by the dol_hblank1 and dol_hblank2
1322 */
1323 if (fid_attr->fid_type == LVDS_FID_NONE) {
1324 lvds_wdr.bits.lvds_wdr_mode = 0x5;
1325 } else {
1326 HI_ERR("not support fid type: %d\n", fid_attr->fid_type);
1327 return HI_FAILURE;
1328 }
1329 } else {
1330 HI_ERR("not support vsync type: %d\n", vsync_attr->sync_type);
1331 return HI_FAILURE;
1332 }
1333
1334 ctrl_reg->LVDS_WDR.u32 = lvds_wdr.u32;
1335 return HI_SUCCESS;
1336 }
1337
mipi_rx_hal_set_lvds_wdr_type(combo_dev_t devno,wdr_mode_t wdr_mode,const lvds_vsync_attr_t * vsync_attr,const lvds_fid_attr_t * fid_attr)1338 static int mipi_rx_hal_set_lvds_wdr_type(combo_dev_t devno, wdr_mode_t wdr_mode,
1339 const lvds_vsync_attr_t *vsync_attr, const lvds_fid_attr_t *fid_attr)
1340 {
1341 int ret = HI_SUCCESS;
1342
1343 if (wdr_mode >= HI_WDR_MODE_2F && wdr_mode <= HI_WDR_MODE_4F) {
1344 ret = mipi_rx_hal_set_lvds_sof_wdr(devno, wdr_mode, vsync_attr);
1345 } else if (wdr_mode >= HI_WDR_MODE_DOL_2F && wdr_mode <= HI_WDR_MODE_DOL_4F) {
1346 ret = mipi_rx_hal_set_lvds_dol_wdr(devno, wdr_mode, vsync_attr, fid_attr);
1347 } else {
1348 }
1349
1350 return ret;
1351 }
1352
mipi_rx_hal_set_scd_hblk(combo_dev_t devno,wdr_mode_t wdr_mode,const lvds_vsync_attr_t * vsync_attr)1353 static void mipi_rx_hal_set_scd_hblk(combo_dev_t devno, wdr_mode_t wdr_mode,
1354 const lvds_vsync_attr_t *vsync_attr)
1355 {
1356 U_LVDS_DOLSCD_HBLK scd_hblk;
1357 volatile lvds_ctrl_regs_t *ctrl_reg = NULL;
1358
1359 ctrl_reg = get_lvds_ctrl_regs(devno);
1360 scd_hblk.u32 = ctrl_reg->LVDS_DOLSCD_HBLK.u32;
1361
1362 if ((wdr_mode >= HI_WDR_MODE_DOL_2F && wdr_mode <= HI_WDR_MODE_DOL_4F) &&
1363 (vsync_attr->sync_type == LVDS_VSYNC_HCONNECT)) {
1364 scd_hblk.bits.dol_hblank1 = vsync_attr->hblank1;
1365 scd_hblk.bits.dol_hblank2 = vsync_attr->hblank2;
1366 }
1367
1368 ctrl_reg->LVDS_DOLSCD_HBLK.u32 = scd_hblk.u32;
1369 }
1370
mipi_rx_drv_set_lvds_wdr_mode(combo_dev_t devno,wdr_mode_t wdr_mode,lvds_vsync_attr_t * vsync_attr,lvds_fid_attr_t * fid_attr)1371 int mipi_rx_drv_set_lvds_wdr_mode(combo_dev_t devno, wdr_mode_t wdr_mode,
1372 lvds_vsync_attr_t *vsync_attr, lvds_fid_attr_t *fid_attr)
1373 {
1374 int ret;
1375
1376 if (wdr_mode == HI_WDR_MODE_BUTT) {
1377 HI_ERR("not support WDR_MODE: %d\n", wdr_mode);
1378 return HI_FAILURE;
1379 }
1380
1381 ret = mipi_rx_hal_set_lvds_wdr_en(devno, wdr_mode);
1382 if (ret != HI_SUCCESS) {
1383 return ret;
1384 }
1385
1386 if (wdr_mode != HI_WDR_MODE_NONE) {
1387 ret = mipi_rx_hal_set_lvds_wdr_type(devno, wdr_mode, vsync_attr, fid_attr);
1388 if (ret != HI_SUCCESS) {
1389 return ret;
1390 }
1391
1392 mipi_rx_hal_set_scd_hblk(devno, wdr_mode, vsync_attr);
1393 }
1394
1395 return ret;
1396 }
1397
mipi_rx_drv_set_lvds_ctrl_mode(combo_dev_t devno,lvds_sync_mode_t sync_mode,data_type_t input_data_type,lvds_bit_endian_t data_endian,lvds_bit_endian_t sync_code_endian)1398 void mipi_rx_drv_set_lvds_ctrl_mode(combo_dev_t devno, lvds_sync_mode_t sync_mode,
1399 data_type_t input_data_type,
1400 lvds_bit_endian_t data_endian,
1401 lvds_bit_endian_t sync_code_endian)
1402 {
1403 volatile lvds_ctrl_regs_t *ctrl_reg = NULL;
1404 U_LVDS_CTRL lvds_ctrl;
1405 unsigned short raw_type;
1406
1407 ctrl_reg = get_lvds_ctrl_regs(devno);
1408
1409 lvds_ctrl.u32 = ctrl_reg->LVDS_CTRL.u32;
1410
1411 switch (input_data_type) {
1412 case DATA_TYPE_RAW_8BIT:
1413 raw_type = 0x1;
1414 break;
1415
1416 case DATA_TYPE_RAW_10BIT:
1417 raw_type = 0x2;
1418 break;
1419
1420 case DATA_TYPE_RAW_12BIT:
1421 raw_type = 0x3;
1422 break;
1423
1424 case DATA_TYPE_RAW_14BIT:
1425 raw_type = 0x4;
1426 break;
1427
1428 case DATA_TYPE_RAW_16BIT:
1429 raw_type = 0x5;
1430 break;
1431
1432 default:
1433 return;
1434 }
1435
1436 lvds_ctrl.bits.lvds_sync_mode = sync_mode;
1437 lvds_ctrl.bits.lvds_raw_type = raw_type;
1438 lvds_ctrl.bits.lvds_pix_big_endian = data_endian;
1439 lvds_ctrl.bits.lvds_code_big_endian = sync_code_endian;
1440
1441 ctrl_reg->LVDS_CTRL.u32 = lvds_ctrl.u32;
1442 }
1443
mipi_rx_drv_set_lvds_data_rate(combo_dev_t devno,mipi_data_rate_t data_rate)1444 void mipi_rx_drv_set_lvds_data_rate(combo_dev_t devno, mipi_data_rate_t data_rate)
1445 {
1446 U_LVDS_OUTPUT_PIX_NUM lvds_output_pixel_num;
1447 unsigned int lvds_double_pix_en = 0;
1448 volatile lvds_ctrl_regs_t *lvds_ctrl_regs = get_lvds_ctrl_regs(devno);
1449
1450 if (data_rate == MIPI_DATA_RATE_X1) {
1451 lvds_double_pix_en = 0;
1452 } else if (data_rate == MIPI_DATA_RATE_X2) {
1453 lvds_double_pix_en = 0x1;
1454 } else {
1455 HI_ERR("unsupported data_rate:%d devno %d\n", data_rate, devno);
1456 return;
1457 }
1458
1459 lvds_output_pixel_num.u32 = lvds_ctrl_regs->LVDS_OUTPUT_PIX_NUM.u32;
1460 lvds_output_pixel_num.bits.lvds_double_pix_en = lvds_double_pix_en;
1461 lvds_ctrl_regs->LVDS_OUTPUT_PIX_NUM.u32 = lvds_output_pixel_num.u32;
1462 }
1463
mipi_rx_drv_set_dol_line_information(combo_dev_t devno,wdr_mode_t wdr_mode)1464 void mipi_rx_drv_set_dol_line_information(combo_dev_t devno, wdr_mode_t wdr_mode)
1465 {
1466 volatile lvds_ctrl_regs_t *ctrl_reg = NULL;
1467
1468 ctrl_reg = get_lvds_ctrl_regs(devno);
1469
1470 if (wdr_mode >= HI_WDR_MODE_DOL_2F) {
1471 ctrl_reg->LVDS_LI_WORD0.bits.li_word0_0 = 0x0201;
1472 ctrl_reg->LVDS_LI_WORD0.bits.li_word0_1 = 0x0211;
1473 ctrl_reg->LVDS_LI_WORD1.bits.li_word1_0 = 0x0202;
1474 ctrl_reg->LVDS_LI_WORD1.bits.li_word1_1 = 0x0212;
1475 }
1476
1477 if (wdr_mode >= HI_WDR_MODE_DOL_3F) {
1478 ctrl_reg->LVDS_LI_WORD2.bits.li_word2_0 = 0x0204;
1479 ctrl_reg->LVDS_LI_WORD2.bits.li_word2_1 = 0x0214;
1480 }
1481
1482 if (wdr_mode >= HI_WDR_MODE_DOL_4F) {
1483 ctrl_reg->LVDS_LI_WORD3.bits.li_word3_0 = 0x0208;
1484 ctrl_reg->LVDS_LI_WORD3.bits.li_word3_1 = 0x0218;
1485 }
1486 }
1487
set_lvds_lane_sof(combo_dev_t devno,int n_frame,int i,const unsigned short sync_code[][WDR_VC_NUM][SYNC_CODE_NUM])1488 static void set_lvds_lane_sof(combo_dev_t devno, int n_frame, int i,
1489 const unsigned short sync_code[][WDR_VC_NUM][SYNC_CODE_NUM])
1490 {
1491 volatile lvds_ctrl_regs_t *ctrl_reg = NULL;
1492 volatile lvds_sync_code_cfg_t *p_sync_code = NULL;
1493
1494 ctrl_reg = get_lvds_ctrl_regs(devno);
1495
1496 if (n_frame == TRUE) {
1497 p_sync_code = &ctrl_reg->lvds_this_frame_sync_code[i];
1498 } else {
1499 p_sync_code = &ctrl_reg->lvds_next_frame_sync_code[i];
1500 }
1501
1502 {
1503 U_LVDS_LANE_SOF_01 lvds_sof_01;
1504 lvds_sof_01.u32 = p_sync_code->LVDS_LANE_SOF_01.u32;
1505 lvds_sof_01.bits.lane_sof_0 = sync_code[i][0][0]; /* 0 -- frame0 sof */
1506 lvds_sof_01.bits.lane_sof_1 = sync_code[i][1][0]; /* 1 -- frame1 sof */
1507 p_sync_code->LVDS_LANE_SOF_01.u32 = lvds_sof_01.u32;
1508 }
1509 {
1510 U_LVDS_LANE_SOF_23 lvds_sof_23;
1511 lvds_sof_23.u32 = p_sync_code->LVDS_LANE_SOF_23.u32;
1512 lvds_sof_23.bits.lane_sof_2 = sync_code[i][2][0]; /* 2 -- frame2 sof */
1513 lvds_sof_23.bits.lane_sof_3 = sync_code[i][3][0]; /* 3 -- frame3 sof */
1514 p_sync_code->LVDS_LANE_SOF_23.u32 = lvds_sof_23.u32;
1515 }
1516 }
1517
set_lvds_lane_eof(combo_dev_t devno,int n_frame,int i,const unsigned short sync_code[][WDR_VC_NUM][SYNC_CODE_NUM])1518 static void set_lvds_lane_eof(combo_dev_t devno, int n_frame, int i,
1519 const unsigned short sync_code[][WDR_VC_NUM][SYNC_CODE_NUM])
1520 {
1521 volatile lvds_ctrl_regs_t *ctrl_reg = NULL;
1522 volatile lvds_sync_code_cfg_t *p_sync_code = NULL;
1523
1524 ctrl_reg = get_lvds_ctrl_regs(devno);
1525
1526 if (n_frame == TRUE) {
1527 p_sync_code = &ctrl_reg->lvds_this_frame_sync_code[i];
1528 } else {
1529 p_sync_code = &ctrl_reg->lvds_next_frame_sync_code[i];
1530 }
1531
1532 {
1533 U_LVDS_LANE_EOF_01 lvds_eof_01;
1534 lvds_eof_01.u32 = p_sync_code->LVDS_LANE_EOF_01.u32;
1535 lvds_eof_01.bits.lane_eof_0 = sync_code[i][0][1]; /* 0 -- frame0 eof */
1536 lvds_eof_01.bits.lane_eof_1 = sync_code[i][1][1]; /* 1 -- frame1 eof */
1537 p_sync_code->LVDS_LANE_EOF_01.u32 = lvds_eof_01.u32;
1538 }
1539 {
1540 U_LVDS_LANE_EOF_23 lvds_eof_23;
1541 lvds_eof_23.u32 = p_sync_code->LVDS_LANE_EOF_23.u32;
1542 lvds_eof_23.bits.lane_eof_2 = sync_code[i][2][1]; /* 2 -- frame2 eof */
1543 lvds_eof_23.bits.lane_eof_3 = sync_code[i][3][1]; /* 3 -- frame3 eof */
1544 p_sync_code->LVDS_LANE_EOF_23.u32 = lvds_eof_23.u32;
1545 }
1546 }
1547
set_lvds_lane_sol(combo_dev_t devno,int n_frame,int i,const unsigned short sync_code[][WDR_VC_NUM][SYNC_CODE_NUM])1548 static void set_lvds_lane_sol(combo_dev_t devno, int n_frame, int i,
1549 const unsigned short sync_code[][WDR_VC_NUM][SYNC_CODE_NUM])
1550 {
1551 volatile lvds_ctrl_regs_t *ctrl_reg = NULL;
1552 volatile lvds_sync_code_cfg_t *p_sync_code = NULL;
1553
1554 ctrl_reg = get_lvds_ctrl_regs(devno);
1555
1556 if (n_frame == TRUE) {
1557 p_sync_code = &ctrl_reg->lvds_this_frame_sync_code[i];
1558 } else {
1559 p_sync_code = &ctrl_reg->lvds_next_frame_sync_code[i];
1560 }
1561
1562 {
1563 U_LVDS_LANE_SOL_01 lvds_sol_01;
1564 lvds_sol_01.u32 = p_sync_code->LVDS_LANE_SOL_01.u32;
1565 lvds_sol_01.bits.lane_sol_0 = sync_code[i][0][2]; /* [0][2] -- frame0 sol bit */
1566 lvds_sol_01.bits.lane_sol_1 = sync_code[i][1][2]; /* [1][2] -- frame1 sol bit */
1567 p_sync_code->LVDS_LANE_SOL_01.u32 = lvds_sol_01.u32;
1568 }
1569 {
1570 U_LVDS_LANE_SOL_23 lvds_sol_23;
1571 lvds_sol_23.u32 = p_sync_code->LVDS_LANE_SOL_23.u32;
1572 lvds_sol_23.bits.lane_sol_2 = sync_code[i][2][2]; /* [2][2] -- frame2 sol bit */
1573 lvds_sol_23.bits.lane_sol_3 = sync_code[i][3][2]; /* [3][2] -- frame3 sol bit */
1574 p_sync_code->LVDS_LANE_SOL_23.u32 = lvds_sol_23.u32;
1575 }
1576 }
1577
set_lvds_lane_eol(combo_dev_t devno,int n_frame,int i,const unsigned short sync_code[][WDR_VC_NUM][SYNC_CODE_NUM])1578 static void set_lvds_lane_eol(combo_dev_t devno, int n_frame, int i,
1579 const unsigned short sync_code[][WDR_VC_NUM][SYNC_CODE_NUM])
1580 {
1581 volatile lvds_ctrl_regs_t *ctrl_reg = NULL;
1582 volatile lvds_sync_code_cfg_t *p_sync_code = NULL;
1583
1584 ctrl_reg = get_lvds_ctrl_regs(devno);
1585
1586 if (n_frame == TRUE) {
1587 p_sync_code = &ctrl_reg->lvds_this_frame_sync_code[i];
1588 } else {
1589 p_sync_code = &ctrl_reg->lvds_next_frame_sync_code[i];
1590 }
1591
1592 {
1593 U_LVDS_LANE_EOL_01 lvds_eol_01;
1594 lvds_eol_01.u32 = p_sync_code->LVDS_LANE_EOL_01.u32;
1595 lvds_eol_01.bits.lane_eol_0 = sync_code[i][0][3]; /* [0][3] -- frame0 sol */
1596 lvds_eol_01.bits.lane_eol_1 = sync_code[i][1][3]; /* [1][3] -- frame1 sol */
1597 p_sync_code->LVDS_LANE_EOL_01.u32 = lvds_eol_01.u32;
1598 }
1599 {
1600 U_LVDS_LANE_EOL_23 lvds_eol_23;
1601 lvds_eol_23.u32 = p_sync_code->LVDS_LANE_EOL_23.u32;
1602 lvds_eol_23.bits.lane_eol_2 = sync_code[i][2][3]; /* [2][3] -- frame2 sol */
1603 lvds_eol_23.bits.lane_eol_3 = sync_code[i][3][3]; /* [3][3] -- frame3 sol */
1604 p_sync_code->LVDS_LANE_EOL_23.u32 = lvds_eol_23.u32;
1605 }
1606 }
1607
set_lvds_sync_code(combo_dev_t devno,int n_frame,unsigned int lane_cnt,const short lane_id[LVDS_LANE_NUM],unsigned short sync_code[][WDR_VC_NUM][SYNC_CODE_NUM])1608 void set_lvds_sync_code(combo_dev_t devno, int n_frame, unsigned int lane_cnt,
1609 const short lane_id[LVDS_LANE_NUM], unsigned short sync_code[][WDR_VC_NUM][SYNC_CODE_NUM])
1610 {
1611 int i;
1612
1613 hi_mipi_rx_unused(lane_cnt);
1614 for (i = 0; i < LVDS_LANE_NUM; i++) {
1615 if (lane_id[i] == -1) {
1616 continue;
1617 }
1618
1619 set_lvds_lane_sof(devno, n_frame, i, sync_code);
1620
1621 set_lvds_lane_eof(devno, n_frame, i, sync_code);
1622
1623 set_lvds_lane_sol(devno, n_frame, i, sync_code);
1624
1625 set_lvds_lane_eol(devno, n_frame, i, sync_code);
1626 }
1627 }
1628
mipi_rx_drv_set_lvds_sync_code(combo_dev_t devno,unsigned int lane_cnt,const short lane_id[LVDS_LANE_NUM],unsigned short sync_code[][WDR_VC_NUM][SYNC_CODE_NUM])1629 void mipi_rx_drv_set_lvds_sync_code(combo_dev_t devno, unsigned int lane_cnt, const short lane_id[LVDS_LANE_NUM],
1630 unsigned short sync_code[][WDR_VC_NUM][SYNC_CODE_NUM])
1631 {
1632 set_lvds_sync_code(devno, TRUE, lane_cnt, lane_id, sync_code);
1633 }
1634
mipi_rx_drv_set_lvds_nxt_sync_code(combo_dev_t devno,unsigned int lane_cnt,const short lane_id[LVDS_LANE_NUM],unsigned short sync_code[][WDR_VC_NUM][SYNC_CODE_NUM])1635 void mipi_rx_drv_set_lvds_nxt_sync_code(combo_dev_t devno, unsigned int lane_cnt, const short lane_id[LVDS_LANE_NUM],
1636 unsigned short sync_code[][WDR_VC_NUM][SYNC_CODE_NUM])
1637 {
1638 set_lvds_sync_code(devno, FALSE, lane_cnt, lane_id, sync_code);
1639 }
1640
mipi_rx_drv_set_phy_sync_dct(unsigned int phy_id,int raw_type,lvds_bit_endian_t code_endian,unsigned int phy_lane_bitmap)1641 void mipi_rx_drv_set_phy_sync_dct(unsigned int phy_id, int raw_type,
1642 lvds_bit_endian_t code_endian, unsigned int phy_lane_bitmap)
1643 {
1644 U_PHY_SYNC_DCT_LINK phy_sync_dct_link;
1645 mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
1646
1647 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
1648 phy_sync_dct_link.u32 = mipi_rx_phy_cfg->PHY_SYNC_DCT_LINK.u32;
1649
1650 if (phy_lane_bitmap & 0x5) {
1651 phy_sync_dct_link.bits.cil_raw_type0 = raw_type;
1652 phy_sync_dct_link.bits.cil_code_big_endian0 = code_endian;
1653 }
1654
1655 if (phy_lane_bitmap & 0xa) {
1656 phy_sync_dct_link.bits.cil_raw_type1 = raw_type;
1657 phy_sync_dct_link.bits.cil_code_big_endian1 = code_endian;
1658 }
1659
1660 mipi_rx_phy_cfg->PHY_SYNC_DCT_LINK.u32 = phy_sync_dct_link.u32;
1661 }
1662
get_sensor_lane_index(short lane,const short lane_id[LVDS_LANE_NUM])1663 short get_sensor_lane_index(short lane, const short lane_id[LVDS_LANE_NUM])
1664 {
1665 int i;
1666
1667 for (i = 0; i < LVDS_LANE_NUM; i++) {
1668 if (lane_id[i] == lane) {
1669 break;
1670 }
1671 }
1672
1673 return i;
1674 }
1675
mipi_rx_drv_set_lvds_phy_sync_code(unsigned int phy_id,const short lane_id[LVDS_LANE_NUM],unsigned short n_sync_code[][WDR_VC_NUM][SYNC_CODE_NUM],unsigned short nxt_sync_code[][WDR_VC_NUM][SYNC_CODE_NUM],unsigned int phy_lane_bitmap)1676 void mipi_rx_drv_set_lvds_phy_sync_code(unsigned int phy_id,
1677 const short lane_id[LVDS_LANE_NUM],
1678 unsigned short n_sync_code[][WDR_VC_NUM][SYNC_CODE_NUM],
1679 unsigned short nxt_sync_code[][WDR_VC_NUM][SYNC_CODE_NUM],
1680 unsigned int phy_lane_bitmap)
1681 {
1682 U_PHY_SYNC_SOF0_LINK phy_sync_sof0_link;
1683 U_PHY_SYNC_SOF1_LINK phy_sync_sof1_link;
1684 U_PHY_SYNC_SOF2_LINK phy_sync_sof2_link;
1685 U_PHY_SYNC_SOF3_LINK phy_sync_sof3_link;
1686 mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
1687 short sensor_lane_idx;
1688 short lane;
1689
1690 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
1691 phy_sync_sof0_link.u32 = mipi_rx_phy_cfg->PHY_SYNC_SOF0_LINK.u32;
1692 phy_sync_sof1_link.u32 = mipi_rx_phy_cfg->PHY_SYNC_SOF1_LINK.u32;
1693 phy_sync_sof2_link.u32 = mipi_rx_phy_cfg->PHY_SYNC_SOF2_LINK.u32;
1694 phy_sync_sof3_link.u32 = mipi_rx_phy_cfg->PHY_SYNC_SOF3_LINK.u32;
1695
1696 if (phy_lane_bitmap & 0x1) {
1697 lane = 0 + 4 * phy_id; /* 4 -- 1 phy have 4 lane */
1698 sensor_lane_idx = get_sensor_lane_index(lane, lane_id);
1699 phy_sync_sof0_link.bits.cil_sof0_word4_0 = n_sync_code[sensor_lane_idx][0][0];
1700 phy_sync_sof0_link.bits.cil_sof1_word4_0 = nxt_sync_code[sensor_lane_idx][0][0];
1701 }
1702
1703 if (phy_lane_bitmap & 0x2) {
1704 lane = 1 + 4 * phy_id; /* 4 -- 1 phy have 4 lane */
1705 sensor_lane_idx = get_sensor_lane_index(lane, lane_id);
1706 phy_sync_sof1_link.bits.cil_sof0_word4_1 = n_sync_code[sensor_lane_idx][0][0];
1707 phy_sync_sof1_link.bits.cil_sof1_word4_1 = nxt_sync_code[sensor_lane_idx][0][0];
1708 }
1709
1710 if (phy_lane_bitmap & 0x4) {
1711 lane = 2 + 4 * phy_id; /* 4 -- 1 phy have 4 lane, 2 -- lane_id 2 */
1712 sensor_lane_idx = get_sensor_lane_index(lane, lane_id);
1713 phy_sync_sof2_link.bits.cil_sof0_word4_2 = n_sync_code[sensor_lane_idx][0][0];
1714 phy_sync_sof2_link.bits.cil_sof1_word4_2 = nxt_sync_code[sensor_lane_idx][0][0];
1715 }
1716
1717 if (phy_lane_bitmap & 0x8) {
1718 lane = 3 + 4 * phy_id; /* 4 -- 1 phy have 4 lane, 3 -- lane_id 3 */
1719 sensor_lane_idx = get_sensor_lane_index(lane, lane_id);
1720 phy_sync_sof3_link.bits.cil_sof0_word4_3 = n_sync_code[sensor_lane_idx][0][0];
1721 phy_sync_sof3_link.bits.cil_sof1_word4_3 = nxt_sync_code[sensor_lane_idx][0][0];
1722 }
1723
1724 mipi_rx_phy_cfg->PHY_SYNC_SOF0_LINK.u32 = phy_sync_sof0_link.u32;
1725 mipi_rx_phy_cfg->PHY_SYNC_SOF1_LINK.u32 = phy_sync_sof1_link.u32;
1726 mipi_rx_phy_cfg->PHY_SYNC_SOF2_LINK.u32 = phy_sync_sof2_link.u32;
1727 mipi_rx_phy_cfg->PHY_SYNC_SOF3_LINK.u32 = phy_sync_sof3_link.u32;
1728 }
1729
mipi_rx_drv_set_phy_sync_config(lvds_dev_attr_t * p_attr,unsigned int lane_bitmap,unsigned short nxt_sync_code[][WDR_VC_NUM][SYNC_CODE_NUM])1730 void mipi_rx_drv_set_phy_sync_config(lvds_dev_attr_t *p_attr, unsigned int lane_bitmap,
1731 unsigned short nxt_sync_code[][WDR_VC_NUM][SYNC_CODE_NUM])
1732 {
1733 int raw_type;
1734 unsigned int i;
1735 unsigned int mask;
1736 unsigned int phy_lane_bitmap;
1737
1738 switch (p_attr->input_data_type) {
1739 case DATA_TYPE_RAW_8BIT:
1740 raw_type = 0x1;
1741 break;
1742
1743 case DATA_TYPE_RAW_10BIT:
1744 raw_type = 0x2;
1745 break;
1746
1747 case DATA_TYPE_RAW_12BIT:
1748 raw_type = 0x3;
1749 break;
1750
1751 case DATA_TYPE_RAW_14BIT:
1752 raw_type = 0x4;
1753 break;
1754
1755 case DATA_TYPE_RAW_16BIT:
1756 raw_type = 0x5;
1757 break;
1758
1759 default:
1760 return;
1761 }
1762
1763 for (i = 0; i < MIPI_RX_MAX_PHY_NUM; i++) {
1764 mask = 0xf << (4 * i); /* 4 -- 4bit */
1765 if (lane_bitmap & mask) {
1766 phy_lane_bitmap = (lane_bitmap & mask) >> (4 * i); /* 4 -- 4bit */
1767 mipi_rx_drv_set_phy_sync_dct(i, raw_type, p_attr->sync_code_endian, phy_lane_bitmap);
1768 mipi_rx_drv_set_lvds_phy_sync_code(i, p_attr->lane_id, p_attr->sync_code, nxt_sync_code, phy_lane_bitmap);
1769 }
1770 }
1771 }
1772
mipi_rx_drv_is_lane_valid(combo_dev_t devno,short lane_id,lane_divide_mode_t mode)1773 int mipi_rx_drv_is_lane_valid(combo_dev_t devno, short lane_id, lane_divide_mode_t mode)
1774 {
1775 int lane_valid = 0;
1776
1777 switch (mode) {
1778 case LANE_DIVIDE_MODE_0:
1779 if (devno == 0) {
1780 if (lane_id >= 0 && lane_id <= 3) { /* 3 -- lane_id max value */
1781 lane_valid = 1;
1782 }
1783 }
1784 break;
1785
1786 case LANE_DIVIDE_MODE_1:
1787 if ((devno == 0) || (devno == 1)) {
1788 if (lane_id >= 0 && lane_id <= 3) { /* 3 -- lane_id max value */
1789 lane_valid = 1;
1790 }
1791 }
1792 break;
1793
1794 default:
1795 break;
1796 }
1797
1798 return lane_valid;
1799 }
1800
1801 static void mipi_rx_drv_hw_init(void);
mipi_rx_drv_set_hs_mode(lane_divide_mode_t mode)1802 void mipi_rx_drv_set_hs_mode(lane_divide_mode_t mode)
1803 {
1804 U_HS_MODE_SELECT hs_mode_sel;
1805 mipi_rx_sys_regs_t *mipi_rx_sys_regs = NULL;
1806 int i;
1807
1808 mipi_rx_drv_hw_init();
1809
1810 for (i = 0; i < MIPI_RX_MAX_PHY_NUM; i++) {
1811 mipi_rx_set_phy_rg_2121_en(i, g_phy_mode[mode][i].phy_rg_en_2121);
1812 mipi_rx_set_phy_rg_clk0_en(i, g_phy_mode[mode][i].phy_rg_clk0_en);
1813 mipi_rx_set_phy_rg_clk1_en(i, g_phy_mode[mode][i].phy_rg_clk1_en);
1814 mipi_rx_set_phy_rg_lp0_mode_en(i, g_phy_mode[mode][i].phy_rg_lp0_mode_en);
1815 mipi_rx_set_phy_rg_lp1_mode_en(i, g_phy_mode[mode][i].phy_rg_lp1_mode_en);
1816 }
1817
1818 mipi_rx_sys_regs = get_mipi_rx_sys_regs();
1819 hs_mode_sel.u32 = mipi_rx_sys_regs->HS_MODE_SELECT.u32;
1820 hs_mode_sel.bits.hs_mode = mode;
1821 mipi_rx_sys_regs->HS_MODE_SELECT.u32 = hs_mode_sel.u32;
1822 }
1823
mipi_rx_drv_set_mipi_int_mask(combo_dev_t devno)1824 void mipi_rx_drv_set_mipi_int_mask(combo_dev_t devno)
1825 {
1826 U_MIPI_INT_MSK mipi_int_msk;
1827 volatile mipi_rx_sys_regs_t *mipi_rx_sys_regs = get_mipi_rx_sys_regs();
1828
1829 mipi_int_msk.u32 = mipi_rx_sys_regs->MIPI_INT_MSK.u32;
1830
1831 if (devno == 0) {
1832 mipi_int_msk.bits.int_chn0_mask = 0x1;
1833 } else if (devno == 1) {
1834 mipi_int_msk.bits.int_chn1_mask = 0x1;
1835 }
1836
1837 mipi_rx_sys_regs->MIPI_INT_MSK.u32 = mipi_int_msk.u32;
1838 }
1839
mipi_rx_drv_set_lvds_ctrl_int_mask(combo_dev_t devno,unsigned int mask)1840 void mipi_rx_drv_set_lvds_ctrl_int_mask(combo_dev_t devno, unsigned int mask)
1841 {
1842 volatile lvds_ctrl_regs_t *lvds_ctrl_regs = get_lvds_ctrl_regs(devno);
1843
1844 lvds_ctrl_regs->LVDS_CTRL_INT_MSK.u32 = mask;
1845 }
1846
mipi_rx_drv_set_mipi_ctrl_int_mask(combo_dev_t devno,unsigned int mask)1847 void mipi_rx_drv_set_mipi_ctrl_int_mask(combo_dev_t devno, unsigned int mask)
1848 {
1849 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
1850
1851 mipi_ctrl_regs->MIPI_CTRL_INT_MSK.u32 = mask;
1852 }
1853
mipi_rx_drv_set_mipi_pkt1_int_mask(combo_dev_t devno,unsigned int mask)1854 void mipi_rx_drv_set_mipi_pkt1_int_mask(combo_dev_t devno, unsigned int mask)
1855 {
1856 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
1857
1858 mipi_ctrl_regs->MIPI_PKT_INTR_MSK.u32 = mask;
1859 }
1860
mipi_rx_drv_set_mipi_pkt2_int_mask(combo_dev_t devno,unsigned int mask)1861 void mipi_rx_drv_set_mipi_pkt2_int_mask(combo_dev_t devno, unsigned int mask)
1862 {
1863 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
1864
1865 mipi_ctrl_regs->MIPI_PKT_INTR2_MSK.u32 = mask;
1866 }
1867
mipi_rx_drv_set_mipi_frame_int_mask(combo_dev_t devno,unsigned int mask)1868 void mipi_rx_drv_set_mipi_frame_int_mask(combo_dev_t devno, unsigned int mask)
1869 {
1870 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
1871
1872 mipi_ctrl_regs->MIPI_FRAME_INTR_MSK.u32 = mask;
1873 }
1874
mipi_rx_drv_set_align_int_mask(combo_dev_t devno,unsigned int mask)1875 void mipi_rx_drv_set_align_int_mask(combo_dev_t devno, unsigned int mask)
1876 {
1877 volatile lvds_ctrl_regs_t *lvds_ctrl_regs = get_lvds_ctrl_regs(devno);
1878
1879 lvds_ctrl_regs->ALIGN0_INT_MSK.u32 = mask;
1880 lvds_ctrl_regs->CHN_INT_MASK.u32 = 0xf;
1881 }
1882
mipi_rx_enable_disable_clock(combo_dev_t combo_dev,int enable)1883 void mipi_rx_enable_disable_clock(combo_dev_t combo_dev, int enable)
1884 {
1885 unsigned long mipi_rx_clock_addr;
1886
1887 mipi_rx_clock_addr = (unsigned long)osal_ioremap(MIPI_RX_CRG_ADDR, (unsigned long)0x4);
1888 if (mipi_rx_clock_addr == 0) {
1889 HI_ERR("mipi_rx clock ioremap failed!\n");
1890 return;
1891 }
1892 set_bit(enable, 1 + combo_dev, mipi_rx_clock_addr);
1893 osal_iounmap((void *)mipi_rx_clock_addr, (unsigned long)0x4);
1894 }
1895
mipi_rx_drv_enable_clock(combo_dev_t combo_dev)1896 void mipi_rx_drv_enable_clock(combo_dev_t combo_dev)
1897 {
1898 mipi_rx_enable_disable_clock(combo_dev, 1);
1899 }
1900
mipi_rx_drv_disable_clock(combo_dev_t combo_dev)1901 void mipi_rx_drv_disable_clock(combo_dev_t combo_dev)
1902 {
1903 mipi_rx_enable_disable_clock(combo_dev, 0);
1904 }
1905
sensor_enable_disable_clock(sns_clk_source_t sns_clk_source,int enable)1906 void sensor_enable_disable_clock(sns_clk_source_t sns_clk_source, int enable)
1907 {
1908 unsigned long sensor_clock_addr;
1909 unsigned offset;
1910
1911 if (sns_clk_source == 0) {
1912 offset = 0; /* 0 -- sensor0_cken is bit[0] */
1913 } else if (sns_clk_source == 1) {
1914 offset = 6; /* 6 -- sensor1_cken is bit[6] */
1915 } else {
1916 HI_ERR("invalid sensor clock source!\n");
1917 return;
1918 }
1919
1920 sensor_clock_addr = (unsigned long)osal_ioremap(SNS_CRG_ADDR, (unsigned long)0x4);
1921 if (sensor_clock_addr == 0) {
1922 HI_ERR("sensor clock ioremap failed!\n");
1923 return;
1924 }
1925 set_bit(enable, offset, sensor_clock_addr);
1926 osal_iounmap((void *)sensor_clock_addr, (unsigned long)0x4);
1927 }
1928
sensor_drv_enable_clock(sns_clk_source_t sns_clk_source)1929 void sensor_drv_enable_clock(sns_clk_source_t sns_clk_source)
1930 {
1931 sensor_enable_disable_clock(sns_clk_source, 1);
1932 }
1933
sensor_drv_disable_clock(sns_clk_source_t sns_clk_source)1934 void sensor_drv_disable_clock(sns_clk_source_t sns_clk_source)
1935 {
1936 sensor_enable_disable_clock(sns_clk_source, 0);
1937 }
1938
mipi_rx_core_reset_unreset(combo_dev_t combo_dev,int reset)1939 void mipi_rx_core_reset_unreset(combo_dev_t combo_dev, int reset)
1940 {
1941 set_bit(reset, (combo_dev + 4), g_mipi_rx_core_reset_addr); /* 4 -- mipi_pix0_core_srst_req bit[4] */
1942 }
1943
mipi_rx_drv_core_reset(combo_dev_t combo_dev)1944 void mipi_rx_drv_core_reset(combo_dev_t combo_dev)
1945 {
1946 mipi_rx_core_reset_unreset(combo_dev, 1);
1947 }
1948
mipi_rx_drv_core_unreset(combo_dev_t combo_dev)1949 void mipi_rx_drv_core_unreset(combo_dev_t combo_dev)
1950 {
1951 mipi_rx_core_reset_unreset(combo_dev, 0);
1952 }
1953
sensor_reset_unreset(sns_rst_source_t sns_reset_source,int reset)1954 void sensor_reset_unreset(sns_rst_source_t sns_reset_source, int reset)
1955 {
1956 unsigned long sensor_reset_addr;
1957 unsigned offset;
1958
1959 if (sns_reset_source == 0) {
1960 offset = 1; /* 1 -- sensor0_srst_req is bit[1] */
1961 } else if (sns_reset_source == 1) {
1962 offset = 7; /* 7 -- sensor1_srst_req is bit[7] */
1963 } else {
1964 HI_ERR("invalid sensor reset source!\n");
1965 return;
1966 }
1967
1968 sensor_reset_addr = (unsigned long)osal_ioremap(SNS_CRG_ADDR, (unsigned long)0x4);
1969 if (sensor_reset_addr == 0) {
1970 HI_ERR("sensor reset ioremap failed!\n");
1971 return;
1972 }
1973 set_bit(reset, offset, sensor_reset_addr);
1974 osal_iounmap((void *)sensor_reset_addr, (unsigned long)0x4);
1975 }
1976
sensor_drv_reset(sns_rst_source_t sns_reset_source)1977 void sensor_drv_reset(sns_rst_source_t sns_reset_source)
1978 {
1979 sensor_reset_unreset(sns_reset_source, 1);
1980 }
1981
sensor_drv_unreset(sns_rst_source_t sns_reset_source)1982 void sensor_drv_unreset(sns_rst_source_t sns_reset_source)
1983 {
1984 sensor_reset_unreset(sns_reset_source, 0);
1985 }
1986
mipi_rx_drv_get_mipi_imgsize_statis(combo_dev_t devno,short vc,img_size_t * p_size)1987 void mipi_rx_drv_get_mipi_imgsize_statis(combo_dev_t devno, short vc, img_size_t *p_size)
1988 {
1989 U_MIPI_IMGSIZE0_STATIS mipi_imgsize0_statis;
1990 U_MIPI_IMGSIZE1_STATIS mipi_imgsize1_statis;
1991 U_MIPI_IMGSIZE2_STATIS mipi_imgsize2_statis;
1992 U_MIPI_IMGSIZE3_STATIS mipi_imgsize3_statis;
1993
1994 volatile mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
1995
1996 if (vc == 0) { /* 0 -- vc0 */
1997 mipi_imgsize0_statis.u32 = mipi_ctrl_regs->MIPI_IMGSIZE0_STATIS.u32;
1998 p_size->width = mipi_imgsize0_statis.bits.imgwidth_statis_vc0;
1999 p_size->height = mipi_imgsize0_statis.bits.imgheight_statis_vc0;
2000 } else if (vc == 1) { /* 1 -- vc1 */
2001 mipi_imgsize1_statis.u32 = mipi_ctrl_regs->MIPI_IMGSIZE1_STATIS.u32;
2002 p_size->width = mipi_imgsize1_statis.bits.imgwidth_statis_vc1;
2003 p_size->height = mipi_imgsize1_statis.bits.imgheight_statis_vc1;
2004 } else if (vc == 2) { /* 2 -- vc2 */
2005 mipi_imgsize2_statis.u32 = mipi_ctrl_regs->MIPI_IMGSIZE2_STATIS.u32;
2006 p_size->width = mipi_imgsize2_statis.bits.imgwidth_statis_vc2;
2007 p_size->height = mipi_imgsize2_statis.bits.imgheight_statis_vc2;
2008 } else if (vc == 3) { /* 3 -- vc3 */
2009 mipi_imgsize3_statis.u32 = mipi_ctrl_regs->MIPI_IMGSIZE3_STATIS.u32;
2010 p_size->width = mipi_imgsize3_statis.bits.imgwidth_statis_vc3;
2011 p_size->height = mipi_imgsize3_statis.bits.imgheight_statis_vc3;
2012 } else {
2013 p_size->width = 0;
2014 p_size->height = 0;
2015 }
2016 }
2017
mipi_rx_drv_get_lvds_imgsize_statis(combo_dev_t devno,short vc,img_size_t * p_size)2018 void mipi_rx_drv_get_lvds_imgsize_statis(combo_dev_t devno, short vc, img_size_t *p_size)
2019 {
2020 U_LVDS_IMGSIZE0_STATIS lvds_img_size0_statis;
2021 U_LVDS_IMGSIZE1_STATIS lvds_img_size1_statis;
2022
2023 volatile lvds_ctrl_regs_t *lvds_ctrl_regs = get_lvds_ctrl_regs(devno);
2024
2025 if (vc == 0) {
2026 lvds_img_size0_statis.u32 = lvds_ctrl_regs->LVDS_IMGSIZE0_STATIS.u32;
2027 p_size->width = lvds_img_size0_statis.bits.lvds_imgwidth0;
2028 p_size->height = lvds_img_size0_statis.bits.lvds_imgheight0;
2029 } else if (vc == 1) {
2030 lvds_img_size1_statis.u32 = lvds_ctrl_regs->LVDS_IMGSIZE1_STATIS.u32;
2031 p_size->width = lvds_img_size1_statis.bits.lvds_imgwidth1;
2032 p_size->height = lvds_img_size1_statis.bits.lvds_imgheight1;
2033 }
2034 }
2035
mipi_rx_drv_get_lvds_lane_imgsize_statis(combo_dev_t devno,short lane,img_size_t * p_size)2036 void mipi_rx_drv_get_lvds_lane_imgsize_statis(combo_dev_t devno, short lane, img_size_t *p_size)
2037 {
2038 U_LVDS_LANE_IMGSIZE_STATIS lvds_lane_img_size_statis;
2039
2040 volatile lvds_ctrl_regs_t *lvds_ctrl_regs = get_lvds_ctrl_regs(devno);
2041
2042 lvds_lane_img_size_statis.u32 = lvds_ctrl_regs->LVDS_LANE_IMGSIZE_STATIS[lane].u32;
2043 p_size->width = lvds_lane_img_size_statis.bits.lane_imgwidth + 1;
2044 p_size->height = lvds_lane_img_size_statis.bits.lane_imgheight;
2045 }
2046
mipi_rx_phy_cil_int_statis(int phy_id)2047 static void mipi_rx_phy_cil_int_statis(int phy_id)
2048 {
2049 unsigned int phy_int_status;
2050
2051 mipi_rx_phy_cfg_t *mipi_rx_phy_cfg = NULL;
2052
2053 mipi_rx_phy_cfg = get_mipi_rx_phy_regs(phy_id);
2054 phy_int_status = mipi_rx_phy_cfg->MIPI_CIL_INT_LINK.u32;
2055
2056 if (phy_int_status) {
2057 mipi_rx_phy_cfg->MIPI_CIL_INT_RAW_LINK.u32 = 0xffffffff;
2058
2059 if (phy_int_status & MIPI_ESC_CLK1) {
2060 g_phy_err_int_cnt[phy_id].clk1_fsm_escape_err_cnt++;
2061 }
2062
2063 if (phy_int_status & MIPI_ESC_CLK0) {
2064 g_phy_err_int_cnt[phy_id].clk0_fsm_escape_err_cnt++;
2065 }
2066
2067 if (phy_int_status & MIPI_ESC_D0) {
2068 g_phy_err_int_cnt[phy_id].d0_fsm_escape_err_cnt++;
2069 }
2070
2071 if (phy_int_status & MIPI_ESC_D1) {
2072 g_phy_err_int_cnt[phy_id].d1_fsm_escape_err_cnt++;
2073 }
2074
2075 if (phy_int_status & MIPI_ESC_D2) {
2076 g_phy_err_int_cnt[phy_id].d2_fsm_escape_err_cnt++;
2077 }
2078
2079 if (phy_int_status & MIPI_ESC_D3) {
2080 g_phy_err_int_cnt[phy_id].d3_fsm_escape_err_cnt++;
2081 }
2082
2083 if (phy_int_status & MIPI_TIMEOUT_CLK1) {
2084 g_phy_err_int_cnt[phy_id].clk1_fsm_timeout_err_cnt++;
2085 }
2086
2087 if (phy_int_status & MIPI_TIMEOUT_CLK0) {
2088 g_phy_err_int_cnt[phy_id].clk0_fsm_timeout_err_cnt++;
2089 }
2090
2091 if (phy_int_status & MIPI_TIMEOUT_D0) {
2092 g_phy_err_int_cnt[phy_id].d0_fsm_timeout_err_cnt++;
2093 }
2094
2095 if (phy_int_status & MIPI_TIMEOUT_D1) {
2096 g_phy_err_int_cnt[phy_id].d1_fsm_timeout_err_cnt++;
2097 }
2098
2099 if (phy_int_status & MIPI_TIMEOUT_D2) {
2100 g_phy_err_int_cnt[phy_id].d2_fsm_timeout_err_cnt++;
2101 }
2102
2103 if (phy_int_status & MIPI_TIMEOUT_D3) {
2104 g_phy_err_int_cnt[phy_id].d3_fsm_timeout_err_cnt++;
2105 }
2106 }
2107 }
2108
mipi_rx_pkt_int1_statics(combo_dev_t devno)2109 static void mipi_rx_pkt_int1_statics(combo_dev_t devno)
2110 {
2111 unsigned int pkt_int1;
2112 mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
2113
2114 pkt_int1 = mipi_ctrl_regs->MIPI_PKT_INTR_ST.u32;
2115 if (pkt_int1) {
2116 if (pkt_int1 & MIPI_PKT_HEADER_ERR) {
2117 g_mipi_err_int_cnt[devno].err_ecc_double_cnt++;
2118 }
2119
2120 if (pkt_int1 & MIPI_VC0_PKT_DATA_CRC) {
2121 g_mipi_err_int_cnt[devno].vc0_err_crc_cnt++;
2122 }
2123
2124 if (pkt_int1 & MIPI_VC1_PKT_DATA_CRC) {
2125 g_mipi_err_int_cnt[devno].vc1_err_crc_cnt++;
2126 }
2127
2128 if (pkt_int1 & MIPI_VC2_PKT_DATA_CRC) {
2129 g_mipi_err_int_cnt[devno].vc2_err_crc_cnt++;
2130 }
2131
2132 if (pkt_int1 & MIPI_VC3_PKT_DATA_CRC) {
2133 g_mipi_err_int_cnt[devno].vc3_err_crc_cnt++;
2134 }
2135 }
2136 }
2137
mipi_rx_pkt_int2_statics(combo_dev_t devno)2138 static void mipi_rx_pkt_int2_statics(combo_dev_t devno)
2139 {
2140 unsigned int pkt_int2;
2141 mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
2142
2143 pkt_int2 = mipi_ctrl_regs->MIPI_PKT_INTR2_ST.u32;
2144 if (pkt_int2) {
2145 if (pkt_int2 & MIPI_VC0_PKT_INVALID_DT) {
2146 g_mipi_err_int_cnt[devno].err_id_vc0_cnt++;
2147 }
2148
2149 if (pkt_int2 & MIPI_VC1_PKT_INVALID_DT) {
2150 g_mipi_err_int_cnt[devno].err_id_vc1_cnt++;
2151 }
2152
2153 if (pkt_int2 & MIPI_VC2_PKT_INVALID_DT) {
2154 g_mipi_err_int_cnt[devno].err_id_vc2_cnt++;
2155 }
2156
2157 if (pkt_int2 & MIPI_VC3_PKT_INVALID_DT) {
2158 g_mipi_err_int_cnt[devno].err_id_vc3_cnt++;
2159 }
2160
2161 if (pkt_int2 & MIPI_VC0_PKT_HEADER_ECC) {
2162 g_mipi_err_int_cnt[devno].vc0_err_ecc_corrected_cnt++;
2163 }
2164
2165 if (pkt_int2 & MIPI_VC1_PKT_HEADER_ECC) {
2166 g_mipi_err_int_cnt[devno].vc1_err_ecc_corrected_cnt++;
2167 }
2168
2169 if (pkt_int2 & MIPI_VC2_PKT_HEADER_ECC) {
2170 g_mipi_err_int_cnt[devno].vc2_err_ecc_corrected_cnt++;
2171 }
2172
2173 if (pkt_int2 & MIPI_VC3_PKT_HEADER_ECC) {
2174 g_mipi_err_int_cnt[devno].vc3_err_ecc_corrected_cnt++;
2175 }
2176 }
2177 }
2178
mipi_rx_frame_intr_statics(combo_dev_t devno)2179 static void mipi_rx_frame_intr_statics(combo_dev_t devno)
2180 {
2181 unsigned int frame_int;
2182 mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
2183
2184 frame_int = mipi_ctrl_regs->MIPI_FRAME_INTR_ST.u32;
2185 if (frame_int) {
2186 if (frame_int & MIPI_VC0_FRAME_CRC) {
2187 g_mipi_err_int_cnt[devno].err_frame_data_vc0_cnt++;
2188 }
2189
2190 if (frame_int & MIPI_VC1_FRAME_CRC) {
2191 g_mipi_err_int_cnt[devno].err_frame_data_vc1_cnt++;
2192 }
2193
2194 if (frame_int & MIPI_VC2_FRAME_CRC) {
2195 g_mipi_err_int_cnt[devno].err_frame_data_vc2_cnt++;
2196 }
2197
2198 if (frame_int & MIPI_VC3_FRAME_CRC) {
2199 g_mipi_err_int_cnt[devno].err_frame_data_vc3_cnt++;
2200 }
2201
2202 if (frame_int & MIPI_VC0_ORDER_ERR) {
2203 g_mipi_err_int_cnt[devno].err_f_seq_vc0_cnt++;
2204 }
2205
2206 if (frame_int & MIPI_VC1_ORDER_ERR) {
2207 g_mipi_err_int_cnt[devno].err_f_seq_vc1_cnt++;
2208 }
2209
2210 if (frame_int & MIPI_VC2_ORDER_ERR) {
2211 g_mipi_err_int_cnt[devno].err_f_seq_vc2_cnt++;
2212 }
2213
2214 if (frame_int & MIPI_VC3_ORDER_ERR) {
2215 g_mipi_err_int_cnt[devno].err_f_seq_vc3_cnt++;
2216 }
2217
2218 if (frame_int & MIPI_VC0_NO_MATCH) {
2219 g_mipi_err_int_cnt[devno].err_f_bndry_match_vc0_cnt++;
2220 }
2221
2222 if (frame_int & MIPI_VC1_NO_MATCH) {
2223 g_mipi_err_int_cnt[devno].err_f_bndry_match_vc1_cnt++;
2224 }
2225
2226 if (frame_int & MIPI_VC2_NO_MATCH) {
2227 g_mipi_err_int_cnt[devno].err_f_bndry_match_vc2_cnt++;
2228 }
2229
2230 if (frame_int & MIPI_VC3_NO_MATCH) {
2231 g_mipi_err_int_cnt[devno].err_f_bndry_match_vc3_cnt++;
2232 }
2233 }
2234 }
2235
mipi_rx_main_int_statics(combo_dev_t devno)2236 static void mipi_rx_main_int_statics(combo_dev_t devno)
2237 {
2238 unsigned int line_int;
2239 unsigned int mipi_main_int;
2240 unsigned int mipi_ctrl_int;
2241 mipi_ctrl_regs_t *mipi_ctrl_regs = get_mipi_ctrl_regs(devno);
2242
2243 mipi_ctrl_int = mipi_ctrl_regs->MIPI_CTRL_INT.u32;
2244
2245 /* Need read mipi_main_int and line_int, to clear MIPI_MAIN_INT_ST and MIPI_LINE_INTR_ST interrupt. */
2246 mipi_main_int = mipi_ctrl_regs->MIPI_MAIN_INT_ST.u32;
2247 line_int = mipi_ctrl_regs->MIPI_LINE_INTR_ST.u32;
2248
2249 if (mipi_main_int) {
2250 mipi_ctrl_regs->MIPI_MAIN_INT_ST.u32 = 0xffffffff;
2251 }
2252
2253 if (line_int) {
2254 mipi_ctrl_regs->MIPI_LINE_INTR_ST.u32 = 0xffffffff;
2255 }
2256
2257 if (mipi_ctrl_int) {
2258 mipi_ctrl_regs->MIPI_CTRL_INT_RAW.u32 = 0xffffffff;
2259 }
2260
2261 if (mipi_ctrl_int) {
2262 if (mipi_ctrl_int & CMD_FIFO_READ_ERR) {
2263 g_mipi_err_int_cnt[devno].cmd_fifo_rderr_cnt++;
2264 }
2265
2266 if (mipi_ctrl_int & DATA_FIFO_READ_ERR) {
2267 g_mipi_err_int_cnt[devno].data_fifo_rderr_cnt++;
2268 }
2269
2270 if (mipi_ctrl_int & CMD_FIFO_WRITE_ERR) {
2271 g_mipi_err_int_cnt[devno].cmd_fifo_wrerr_cnt++;
2272 }
2273
2274 if (mipi_ctrl_int & DATA_FIFO_WRITE_ERR) {
2275 g_mipi_err_int_cnt[devno].data_fifo_wrerr_cnt++;
2276 }
2277 }
2278 }
2279
mipi_int_statics(combo_dev_t devno)2280 static void mipi_int_statics(combo_dev_t devno)
2281 {
2282 mipi_rx_main_int_statics(devno);
2283
2284 mipi_rx_pkt_int1_statics(devno);
2285
2286 mipi_rx_pkt_int2_statics(devno);
2287
2288 mipi_rx_frame_intr_statics(devno);
2289 }
2290
lvds_int_statics(combo_dev_t devno)2291 static void lvds_int_statics(combo_dev_t devno)
2292 {
2293 unsigned int lvds_ctrl_int;
2294 volatile lvds_ctrl_regs_t *lvds_ctrl_regs = get_lvds_ctrl_regs(devno);
2295
2296 lvds_ctrl_int = lvds_ctrl_regs->LVDS_CTRL_INT.u32;
2297
2298 if (lvds_ctrl_int) {
2299 lvds_ctrl_regs->LVDS_CTRL_INT_RAW.u32 = 0xffffffff;
2300 }
2301
2302 if (lvds_ctrl_int & CMD_RD_ERR) {
2303 g_lvds_err_int_cnt[devno].cmd_rd_err_cnt++;
2304 }
2305
2306 if (lvds_ctrl_int & CMD_WR_ERR) {
2307 g_lvds_err_int_cnt[devno].cmd_wr_err_cnt++;
2308 }
2309
2310 if (lvds_ctrl_int & LVDS_POP_ERR) {
2311 g_lvds_err_int_cnt[devno].pop_err_cnt++;
2312 }
2313
2314 if (lvds_ctrl_int & LVDS_STAT_ERR) {
2315 g_lvds_err_int_cnt[devno].lvds_state_err_cnt++;
2316 }
2317
2318 if (lvds_ctrl_int & LINK0_READ_ERR) {
2319 g_lvds_err_int_cnt[devno].link0_rd_err_cnt++;
2320 }
2321
2322 if (lvds_ctrl_int & LINK0_WRITE_ERR) {
2323 g_lvds_err_int_cnt[devno].link0_wr_err_cnt++;
2324 }
2325 }
2326
align_int_statis(combo_dev_t devno)2327 static void align_int_statis(combo_dev_t devno)
2328 {
2329 unsigned int align_int;
2330 volatile lvds_ctrl_regs_t *lvds_ctrl_regs = get_lvds_ctrl_regs(devno);
2331
2332 align_int = lvds_ctrl_regs->ALIGN0_INT.u32;
2333
2334 if (align_int) {
2335 lvds_ctrl_regs->ALIGN0_INT_RAW.u32 = 0xffffffff;
2336 }
2337
2338 if (align_int & ALIGN_FIFO_FULL_ERR) {
2339 g_align_err_int_cnt[devno].fifo_full_err_cnt++;
2340 }
2341
2342 if (align_int & ALIGN_LANE0_ERR) {
2343 g_align_err_int_cnt[devno].lane0_align_err_cnt++;
2344 }
2345
2346 if (align_int & ALIGN_LANE1_ERR) {
2347 g_align_err_int_cnt[devno].lane1_align_err_cnt++;
2348 }
2349
2350 if (align_int & ALIGN_LANE2_ERR) {
2351 g_align_err_int_cnt[devno].lane2_align_err_cnt++;
2352 }
2353
2354 if (align_int & ALIGN_LANE3_ERR) {
2355 g_align_err_int_cnt[devno].lane3_align_err_cnt++;
2356 }
2357 }
2358
mipi_rx_interrupt_route(int irq,void * dev_id)2359 static int mipi_rx_interrupt_route(int irq, void *dev_id)
2360 {
2361 volatile mipi_rx_sys_regs_t *mipi_rx_sys_regs = get_mipi_rx_sys_regs();
2362 volatile lvds_ctrl_regs_t *lvds_ctrl_regs = NULL;
2363 int i;
2364
2365 hi_mipi_rx_unused(irq);
2366 hi_mipi_rx_unused(dev_id);
2367 for (i = 0; i < MIPI_RX_MAX_PHY_NUM; i++) {
2368 mipi_rx_phy_cil_int_statis(i);
2369 }
2370
2371 for (i = 0; i < MIPI_RX_MAX_DEV_NUM; i++) {
2372 lvds_ctrl_regs = get_lvds_ctrl_regs(i);
2373 if (lvds_ctrl_regs->CHN_INT_RAW.u32) {
2374 mipi_rx_drv_core_reset(i);
2375 mipi_rx_drv_core_unreset(i);
2376 } else {
2377 continue;
2378 }
2379
2380 mipi_int_statics(i);
2381 lvds_int_statics(i);
2382 align_int_statis(i);
2383 lvds_ctrl_regs->CHN_INT_RAW.u32 = 0xf;
2384 }
2385
2386 mipi_rx_sys_regs->MIPI_INT_RAW.u32 = 0xff;
2387
2388 return OSAL_IRQ_HANDLED;
2389 }
2390
mipi_rx_drv_reg_init(void)2391 static int mipi_rx_drv_reg_init(void)
2392 {
2393 if (g_mipi_rx_regs_va == NULL) {
2394 g_mipi_rx_regs_va = (mipi_rx_regs_type_t *)osal_ioremap(MIPI_RX_REGS_ADDR, (unsigned int)MIPI_RX_REGS_SIZE);
2395 if (g_mipi_rx_regs_va == NULL) {
2396 HI_ERR("remap mipi_rx reg addr fail\n");
2397 return -1;
2398 }
2399 g_reg_map_flag = 1;
2400 }
2401
2402 return 0;
2403 }
2404
mipi_rx_drv_reg_exit(void)2405 static void mipi_rx_drv_reg_exit(void)
2406 {
2407 if (g_reg_map_flag == 1) {
2408 if (g_mipi_rx_regs_va != NULL) {
2409 osal_iounmap((void *)g_mipi_rx_regs_va, (unsigned long)0x4);
2410 g_mipi_rx_regs_va = NULL;
2411 }
2412 g_reg_map_flag = 0;
2413 }
2414 }
2415
mipi_rx_register_irq(void)2416 static int mipi_rx_register_irq(void)
2417 {
2418 int ret;
2419
2420 ret = osal_request_irq(g_mipi_rx_irq_num, mipi_rx_interrupt_route, NULL, "MIPI_RX", mipi_rx_interrupt_route);
2421 if (ret < 0) {
2422 HI_ERR("mipi_rx: failed to register irq.\n");
2423 return -1;
2424 }
2425
2426 return 0;
2427 }
2428
mipi_rx_unregister_irq(void)2429 static void mipi_rx_unregister_irq(void)
2430 {
2431 osal_free_irq(g_mipi_rx_irq_num, mipi_rx_interrupt_route);
2432 }
2433
mipi_rx_drv_hw_init(void)2434 static void mipi_rx_drv_hw_init(void)
2435 {
2436 unsigned long mipi_rx_crg_addr;
2437 int i;
2438
2439 mipi_rx_crg_addr = (unsigned long)osal_ioremap(MIPI_RX_CRG_ADDR, (unsigned long)0x4);
2440
2441 write_reg32(mipi_rx_crg_addr, 1 << 0, 0x1 << 0); /* 0 -- cil_cken bit[0] */
2442 write_reg32(mipi_rx_crg_addr, 1 << 3, 0x1 << 3); /* 3 -- mipi_bus_cken bit[3] */
2443 write_reg32(mipi_rx_crg_addr, 1 << 6, 0x1 << 6); /* 6 -- mipi_bus_srst_req bit[6] */
2444 osal_udelay(10); /* 10 -- udelay 10ns */
2445 write_reg32(mipi_rx_crg_addr, 0, 0x1 << 6); /* 6 -- mipi_bus_srst_req bit[6] */
2446
2447 osal_iounmap((void *)mipi_rx_crg_addr, (unsigned long)0x4);
2448
2449 for (i = 0; i < MIPI_RX_MAX_PHY_NUM; ++i) {
2450 mipi_rx_set_cil_int_mask(i, MIPI_CIL_INT_MASK);
2451 mipi_rx_set_phy_skew_link(i, SKEW_LINK);
2452 mipi_rx_set_phy_fsmo_link(i, MIPI_FSMO_VALUE);
2453 }
2454 }
2455
mipi_rx_drv_hw_exit(void)2456 static void mipi_rx_drv_hw_exit(void)
2457 {
2458 unsigned long mipi_rx_crg_addr;
2459
2460 mipi_rx_crg_addr = (unsigned long)osal_ioremap(MIPI_RX_CRG_ADDR, (unsigned long)0x4);
2461
2462 write_reg32(mipi_rx_crg_addr, 1 << 6, 0x1 << 6); /* 6 -- mipi_bus_srst_req bit[6] */
2463 write_reg32(mipi_rx_crg_addr, 0, 0x1 << 0); /* 0 -- cil_cken bit[0] */
2464 write_reg32(mipi_rx_crg_addr, 0, 0x1 << 3); /* 3 -- mipi_bus_cken bit[3] */
2465
2466 osal_iounmap((void *)mipi_rx_crg_addr, (unsigned long)0x4);
2467 }
2468
mipi_rx_drv_init(void)2469 int mipi_rx_drv_init(void)
2470 {
2471 int ret;
2472
2473 ret = mipi_rx_drv_reg_init();
2474 if (ret < 0) {
2475 HI_ERR("mipi_rx_drv_reg_init fail!\n");
2476 goto fail0;
2477 }
2478
2479 ret = mipi_rx_register_irq();
2480 if (ret < 0) {
2481 HI_ERR("mipi_rx_register_irq fail!\n");
2482 goto fail1;
2483 }
2484
2485 g_mipi_rx_core_reset_addr = (unsigned long)(uintptr_t)osal_ioremap(MIPI_RX_CRG_ADDR, (unsigned long)0x4);
2486 if (g_mipi_rx_core_reset_addr == 0) {
2487 HI_ERR("mipi_rx reset ioremap failed!\n");
2488 goto fail2;
2489 }
2490
2491 mipi_rx_drv_hw_init();
2492
2493 return HI_SUCCESS;
2494
2495 fail2:
2496 mipi_rx_unregister_irq();
2497 fail1:
2498 mipi_rx_drv_reg_exit();
2499 fail0:
2500 return HI_FAILURE;
2501 }
2502
mipi_rx_drv_exit(void)2503 void mipi_rx_drv_exit(void)
2504 {
2505 mipi_rx_unregister_irq();
2506 mipi_rx_drv_reg_exit();
2507 mipi_rx_drv_hw_exit();
2508 osal_iounmap((void *)(uintptr_t)g_mipi_rx_core_reset_addr, (unsigned long)0x4);
2509 }
2510
2511 #ifdef __cplusplus
2512 #if __cplusplus
2513 }
2514
2515 #endif
2516 #endif /* End of #ifdef __cplusplus */
2517