1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19 #include "hi_mipi.h"
20 #include "hi_osal.h"
21 #include "type.h"
22 #include "mipi_rx_hal.h"
23 #include "securec.h"
24
25 #ifdef __cplusplus
26 #if __cplusplus
27 extern "C" {
28 #endif
29 #endif /* End of #ifdef __cplusplus */
30
31 /* macro definition */
32 #define MIPI_RX_DEV_NAME "hi_mipi"
33 #define MIPI_RX_PROC_NAME "mipi_rx"
34
35 #define HIMEDIA_DYNAMIC_MINOR 255
36
37 #define COMBO_DEV_MAX_NUM 2
38 #define COMBO_MAX_LANE_NUM 4
39
40 #define COMBO_MIN_WIDTH 32
41 #define COMBO_MIN_HEIGHT 32
42
43 #define MIPI_HEIGHT_ALIGN 2
44 #define MIPI_WIDTH_ALIGN 2
45
46 #define ENABLE_INT_MASK
47
48 /* global variables definition */
49 typedef struct {
50 lane_divide_mode_t lane_divide_mode;
51 unsigned char hs_mode_cfged;
52 combo_dev_attr_t combo_dev_attr[COMBO_DEV_MAX_NUM];
53 unsigned char dev_valid[COMBO_DEV_MAX_NUM];
54 unsigned char dev_cfged[COMBO_DEV_MAX_NUM];
55 unsigned int lane_bitmap[COMBO_DEV_MAX_NUM];
56 } mipi_dev_ctx_t;
57
58 static osal_dev_t *g_mipirx_dev = NULL;
59 static osal_mutex_t g_mipirx_mutex;
60 static mipi_dev_ctx_t g_mipirx_dev_ctx;
61 static osal_spinlock_t g_mipirx_ctx_lock;
62
63 /* function definition */
mipi_is_hs_mode_cfged(void)64 unsigned char mipi_is_hs_mode_cfged(void)
65 {
66 unsigned char hs_mode_cfged;
67
68 osal_spin_lock(&g_mipirx_ctx_lock);
69 hs_mode_cfged = g_mipirx_dev_ctx.hs_mode_cfged;
70 osal_spin_unlock(&g_mipirx_ctx_lock);
71
72 return hs_mode_cfged;
73 }
74
mipi_is_dev_valid(combo_dev_t devno)75 static unsigned char mipi_is_dev_valid(combo_dev_t devno)
76 {
77 unsigned char dev_valid;
78
79 osal_spin_lock(&g_mipirx_ctx_lock);
80 dev_valid = g_mipirx_dev_ctx.dev_valid[devno];
81 osal_spin_unlock(&g_mipirx_ctx_lock);
82
83 return dev_valid;
84 }
85
mipi_is_dev_cfged(combo_dev_t devno)86 static unsigned char mipi_is_dev_cfged(combo_dev_t devno)
87 {
88 unsigned char dev_cfged;
89
90 osal_spin_lock(&g_mipirx_ctx_lock);
91 dev_cfged = g_mipirx_dev_ctx.dev_cfged[devno];
92 osal_spin_unlock(&g_mipirx_ctx_lock);
93
94 return dev_cfged;
95 }
96
check_lane(combo_dev_t devno,int lane_num,lane_divide_mode_t cur_lane_divide_mode,int * lane_sum,const short p_lane_id[])97 static int check_lane(combo_dev_t devno,
98 int lane_num,
99 lane_divide_mode_t cur_lane_divide_mode,
100 int *lane_sum,
101 const short p_lane_id[])
102 {
103 int i;
104 int j;
105 int all_lane_id_invalid_flag = 1;
106 for (i = 0; i < lane_num; i++) {
107 int temp_id = p_lane_id[i];
108 int lane_valid;
109
110 if (temp_id < -1 || temp_id >= COMBO_MAX_LANE_NUM) {
111 HI_ERR("lane_id[%d] is invalid value %d.\n", i, temp_id);
112 return HI_FAILURE;
113 }
114
115 if (temp_id == -1) {
116 continue;
117 }
118 *lane_sum = *lane_sum + 1;
119 all_lane_id_invalid_flag = 0;
120
121 for (j = i + 1; j < lane_num; j++) {
122 if (temp_id == p_lane_id[j]) {
123 HI_ERR("lane_id[%d] can't be same value %d as lane_id[%d]\n", i, temp_id, j);
124 return HI_FAILURE;
125 }
126 }
127
128 lane_valid = mipi_rx_drv_is_lane_valid(devno, temp_id, cur_lane_divide_mode);
129 if (!lane_valid) {
130 HI_ERR("lane_id[%d] %d is invalid in hs_mode %d\n", i, temp_id, cur_lane_divide_mode);
131 return HI_FAILURE;
132 }
133 }
134 if (all_lane_id_invalid_flag) {
135 HI_ERR("all lane_id is invalid!\n");
136 return HI_FAILURE;
137 }
138 return HI_SUCCESS;
139 }
check_lane_id(combo_dev_t devno,input_mode_t input_mode,const short p_lane_id[])140 static int check_lane_id(combo_dev_t devno, input_mode_t input_mode, const short p_lane_id[])
141 {
142 int lane_num;
143 int lane_sum = 0;
144 int mode1_lane_num = 2;
145 lane_divide_mode_t cur_lane_divide_mode;
146
147 if (input_mode == INPUT_MODE_MIPI) {
148 lane_num = MIPI_LANE_NUM;
149 } else if (input_mode == INPUT_MODE_LVDS) {
150 lane_num = LVDS_LANE_NUM;
151 } else {
152 return HI_SUCCESS;
153 }
154
155 osal_spin_lock(&g_mipirx_ctx_lock);
156 cur_lane_divide_mode = g_mipirx_dev_ctx.lane_divide_mode;
157 osal_spin_unlock(&g_mipirx_ctx_lock);
158 if (check_lane(devno, lane_num, cur_lane_divide_mode, &lane_sum, p_lane_id) == HI_FAILURE) {
159 HI_ERR("lane_id is invalid!\n");
160 return HI_FAILURE;
161 }
162 if ((cur_lane_divide_mode == LANE_DIVIDE_MODE_1) && (lane_sum > mode1_lane_num)) {
163 HI_ERR("When divide mode is LANE_DIVIDE_MODE_1, valid lane number cannot be greater than 2 !\n");
164 return HI_FAILURE;
165 }
166 return HI_SUCCESS;
167 }
168
mipi_get_lane_bitmap(input_mode_t input_mode,const short * p_lane_id,unsigned int * p_total_lane_num)169 static unsigned int mipi_get_lane_bitmap(input_mode_t input_mode, const short *p_lane_id,
170 unsigned int *p_total_lane_num)
171 {
172 unsigned int lane_bitmap = 0;
173 int lane_num;
174 int total_lane_num;
175 int i;
176
177 if (input_mode == INPUT_MODE_MIPI) {
178 lane_num = MIPI_LANE_NUM;
179 } else {
180 lane_num = LVDS_LANE_NUM;
181 }
182
183 total_lane_num = 0;
184
185 for (i = 0; i < lane_num; i++) {
186 short tmp_lane_id;
187 tmp_lane_id = p_lane_id[i];
188
189 if (tmp_lane_id != -1) {
190 lane_bitmap = lane_bitmap | (1 << (unsigned short)(tmp_lane_id));
191 total_lane_num++;
192 }
193 }
194
195 *p_total_lane_num = total_lane_num;
196
197 return lane_bitmap;
198 }
199
mipi_check_comb_dev_attr(combo_dev_attr_t * p_attr)200 static int mipi_check_comb_dev_attr(combo_dev_attr_t *p_attr)
201 {
202 if (p_attr->devno >= COMBO_DEV_MAX_NUM) {
203 HI_ERR("invalid combo_dev number(%d).\n", p_attr->devno);
204 return HI_FAILURE;
205 }
206
207 if (p_attr->input_mode < INPUT_MODE_MIPI || p_attr->input_mode >= INPUT_MODE_BUTT) {
208 HI_ERR("invalid input_mode(%d).\n", p_attr->input_mode);
209 return HI_FAILURE;
210 }
211
212 if (p_attr->data_rate != MIPI_DATA_RATE_X1) {
213 HI_ERR("invalid data_rate(%d).\n", p_attr->data_rate);
214 return HI_FAILURE;
215 }
216
217 if (p_attr->img_rect.x < 0 || p_attr->img_rect.y < 0) {
218 HI_ERR("crop x and y (%d, %d) must be great than 0\n", p_attr->img_rect.x, p_attr->img_rect.y);
219 return HI_FAILURE;
220 }
221
222 if (p_attr->img_rect.width < COMBO_MIN_WIDTH || p_attr->img_rect.height < COMBO_MIN_HEIGHT) {
223 HI_ERR("invalid img_size(%d, %d), can't be smaller than (%d, %d)\n",
224 p_attr->img_rect.width, p_attr->img_rect.height, COMBO_MIN_WIDTH, COMBO_MIN_HEIGHT);
225 return HI_FAILURE;
226 }
227
228 /* width and height align 2 */
229 if ((p_attr->img_rect.width & (MIPI_WIDTH_ALIGN - 1)) != 0) {
230 HI_ERR("img_width should be %d bytes align which is %d!\n",
231 MIPI_WIDTH_ALIGN, p_attr->img_rect.width);
232 return HI_FAILURE;
233 }
234
235 if ((p_attr->img_rect.height & (MIPI_HEIGHT_ALIGN - 1)) != 0) {
236 HI_ERR("img_height should be %d bytes align which is %d!\n",
237 MIPI_WIDTH_ALIGN, p_attr->img_rect.height);
238 return HI_FAILURE;
239 }
240
241 return HI_SUCCESS;
242 }
243
check_lvds_wdr_mode(lvds_dev_attr_t * p_attr)244 static int check_lvds_wdr_mode(lvds_dev_attr_t *p_attr)
245 {
246 int ret = HI_SUCCESS;
247
248 switch (p_attr->wdr_mode) {
249 case HI_WDR_MODE_2F:
250 case HI_WDR_MODE_3F:
251 case HI_WDR_MODE_4F: {
252 if (p_attr->vsync_attr.sync_type != LVDS_VSYNC_NORMAL &&
253 p_attr->vsync_attr.sync_type != LVDS_VSYNC_SHARE) {
254 HI_ERR("invalid sync_type, must be LVDS_VSYNC_NORMAL or LVDS_VSYNC_SHARE\n");
255 ret = HI_FAILURE;
256 }
257 break;
258 }
259
260 case HI_WDR_MODE_DOL_2F:
261 case HI_WDR_MODE_DOL_3F:
262 case HI_WDR_MODE_DOL_4F: {
263 if (p_attr->vsync_attr.sync_type == LVDS_VSYNC_NORMAL) {
264 if (p_attr->fid_attr.fid_type != LVDS_FID_IN_SAV &&
265 p_attr->fid_attr.fid_type != LVDS_FID_IN_DATA) {
266 HI_ERR("invalid fid_type, must be LVDS_FID_IN_SAV or LVDS_FID_IN_DATA\n");
267 ret = HI_FAILURE;
268 }
269 } else if (p_attr->vsync_attr.sync_type == LVDS_VSYNC_HCONNECT) {
270 if (p_attr->fid_attr.fid_type != LVDS_FID_NONE &&
271 p_attr->fid_attr.fid_type != LVDS_FID_IN_DATA) {
272 HI_ERR("invalid fid_type, must be LVDS_FID_NONE or LVDS_FID_IN_DATA\n");
273 ret = HI_FAILURE;
274 }
275 } else {
276 HI_ERR("invalid sync_type, must be LVDS_VSYNC_NORMAL or LVDS_VSYNC_HCONNECT\n");
277 ret = HI_FAILURE;
278 }
279 break;
280 }
281
282 default:
283 break;
284 }
285
286 return ret;
287 }
288
check_lvds_dev_attr(combo_dev_t devno,lvds_dev_attr_t * p_attr)289 static int check_lvds_dev_attr(combo_dev_t devno, lvds_dev_attr_t *p_attr)
290 {
291 int ret;
292
293 if ((p_attr->input_data_type < DATA_TYPE_RAW_8BIT) ||
294 (p_attr->input_data_type > DATA_TYPE_RAW_16BIT)) {
295 HI_ERR("invalid data_type, must be in [%d, %d]\n", DATA_TYPE_RAW_8BIT, DATA_TYPE_RAW_16BIT);
296 return HI_FAILURE;
297 }
298
299 if ((p_attr->wdr_mode < HI_WDR_MODE_NONE) || (p_attr->wdr_mode >= HI_WDR_MODE_BUTT)) {
300 HI_ERR("invalid wdr_mode, must be in [%d, %d)\n", HI_WDR_MODE_NONE, HI_WDR_MODE_BUTT);
301 return HI_FAILURE;
302 }
303
304 if ((p_attr->sync_mode < LVDS_SYNC_MODE_SOF) || (p_attr->sync_mode >= LVDS_SYNC_MODE_BUTT)) {
305 HI_ERR("invalid sync_mode, must be in [%d, %d)\n", LVDS_SYNC_MODE_SOF, LVDS_SYNC_MODE_BUTT);
306 return HI_FAILURE;
307 }
308
309 if (p_attr->vsync_attr.sync_type < LVDS_VSYNC_NORMAL ||
310 p_attr->vsync_attr.sync_type >= LVDS_VSYNC_BUTT) {
311 HI_ERR("invalid vsync_code, must be in [%d, %d)\n", LVDS_VSYNC_NORMAL, LVDS_VSYNC_BUTT);
312 return HI_FAILURE;
313 }
314
315 if (p_attr->fid_attr.fid_type < LVDS_FID_NONE || p_attr->fid_attr.fid_type >= LVDS_FID_BUTT) {
316 HI_ERR("invalid fid_type, must be in [%d, %d)\n", LVDS_FID_NONE, LVDS_FID_BUTT);
317 return HI_FAILURE;
318 }
319
320 if (p_attr->fid_attr.output_fil != TRUE && p_attr->fid_attr.output_fil != FALSE) {
321 HI_ERR("invalid output_fil, must be HI_TURE or FALSE\n");
322 return HI_FAILURE;
323 }
324
325 if ((p_attr->data_endian < LVDS_ENDIAN_LITTLE) || (p_attr->data_endian >= LVDS_ENDIAN_BUTT)) {
326 HI_ERR("invalid lvds_bit_endian, must be in [%d, %d)\n", LVDS_ENDIAN_LITTLE, LVDS_ENDIAN_BUTT);
327 return HI_FAILURE;
328 }
329
330 if ((p_attr->sync_code_endian < LVDS_ENDIAN_LITTLE) ||
331 (p_attr->sync_code_endian >= LVDS_ENDIAN_BUTT)) {
332 HI_ERR("invalid lvds_bit_endian, must be in [%d, %d)\n", LVDS_ENDIAN_LITTLE, LVDS_ENDIAN_BUTT);
333 return HI_FAILURE;
334 }
335
336 ret = check_lvds_wdr_mode(p_attr);
337 if (ret != HI_SUCCESS) {
338 HI_ERR("check_lvds_wdr_mode failed!\n");
339 return HI_FAILURE;
340 }
341
342 ret = check_lane_id(devno, INPUT_MODE_LVDS, p_attr->lane_id);
343 if (ret != HI_SUCCESS) {
344 HI_ERR("check_lane_id failed!\n");
345 return HI_FAILURE;
346 }
347
348 return HI_SUCCESS;
349 }
350
mipi_set_lvds_sync_codes(combo_dev_t devno,lvds_dev_attr_t * p_attr,unsigned int total_lane_num,unsigned int lane_bitmap)351 static void mipi_set_lvds_sync_codes(combo_dev_t devno, lvds_dev_attr_t *p_attr,
352 unsigned int total_lane_num, unsigned int lane_bitmap)
353 {
354 int i;
355 int j;
356 int k;
357 unsigned short (*p_nxt_sync_code)[WDR_VC_NUM][SYNC_CODE_NUM] = NULL;
358 int alloc_flag = FALSE;
359
360 if (p_attr->wdr_mode >= HI_WDR_MODE_DOL_2F && p_attr->wdr_mode <= HI_WDR_MODE_DOL_4F) {
361 /* Sony DOL Mode */
362 p_nxt_sync_code = osal_vmalloc(sizeof(unsigned short) * total_lane_num * WDR_VC_NUM * SYNC_CODE_NUM);
363 if (p_nxt_sync_code == NULL) {
364 HI_ERR("alloc memory for nxt_sync_code failed\n");
365 return;
366 }
367
368 alloc_flag = TRUE;
369
370 /*
371 * SONY DOL N frame and N+1 Frame has the different sync_code
372 * N+1 Frame FSET is 1, FSET is the 10th bit
373 */
374 for (i = 0; i < LVDS_LANE_NUM; i++) {
375 for (j = 0; j < WDR_VC_NUM; j++) {
376 for (k = 0; k < SYNC_CODE_NUM; k++) {
377 if (p_attr->input_data_type == DATA_TYPE_RAW_10BIT) {
378 p_nxt_sync_code[i][j][k] = p_attr->sync_code[i][j][k] + (1 << 8); /* 8 --N+1 Frame sync */
379 } else {
380 p_nxt_sync_code[i][j][k] = p_attr->sync_code[i][j][k] + (1 << 10); /* 10 --N+1 Frame sync */
381 }
382 }
383 }
384 }
385
386 /* Set Dony DOL Line Information */
387 if (p_attr->fid_attr.fid_type == LVDS_FID_IN_DATA) {
388 mipi_rx_drv_set_dol_line_information(devno, p_attr->wdr_mode);
389 }
390 } else {
391 p_nxt_sync_code = p_attr->sync_code;
392 }
393
394 /* LVDS_CTRL Sync code */
395 mipi_rx_drv_set_lvds_sync_code(devno, total_lane_num, p_attr->lane_id, p_attr->sync_code);
396 mipi_rx_drv_set_lvds_nxt_sync_code(devno, total_lane_num, p_attr->lane_id, p_nxt_sync_code);
397
398 /* PHY Sync code detect setting */
399 mipi_rx_drv_set_phy_sync_config(p_attr, lane_bitmap, p_nxt_sync_code);
400
401 if (alloc_flag == TRUE) {
402 osal_vfree(p_nxt_sync_code);
403 }
404 }
405
mipi_set_lvds_int_mask(combo_dev_t devno)406 static void mipi_set_lvds_int_mask(combo_dev_t devno)
407 {
408 (void)memset_s(mipi_rx_hal_get_lvds_err_int_cnt(devno), sizeof(lvds_err_int_cnt_t), 0, sizeof(lvds_err_int_cnt_t));
409 (void)memset_s(mipi_rx_hal_get_align_err_int_cnt(devno), sizeof(align_err_int_cnt_t), 0,
410 sizeof(align_err_int_cnt_t));
411
412 #ifdef ENABLE_INT_MASK
413 mipi_rx_drv_set_mipi_int_mask(devno);
414 mipi_rx_drv_set_lvds_ctrl_int_mask(devno, LVDS_CTRL_INT_MASK);
415 mipi_rx_drv_set_align_int_mask(devno, ALIGN0_INT_MASK);
416 #endif
417 }
418
mipi_set_lvds_phy_sync_cfg(combo_dev_t devno,lvds_dev_attr_t * p_lvds_attr,unsigned int lane_bitmap,unsigned int lane_num)419 static void mipi_set_lvds_phy_sync_cfg(combo_dev_t devno,
420 lvds_dev_attr_t *p_lvds_attr, unsigned int lane_bitmap, unsigned int lane_num)
421 {
422 /* phy lane config */
423 mipi_rx_drv_set_link_lane_id(devno, INPUT_MODE_LVDS, p_lvds_attr->lane_id, lane_bitmap,
424 g_mipirx_dev_ctx.lane_divide_mode);
425 mipi_rx_drv_set_mem_cken(devno, TRUE);
426 mipi_rx_drv_set_clr_cken(devno, TRUE);
427
428 mipi_rx_drv_set_phy_config(INPUT_MODE_LVDS, lane_bitmap);
429
430 /* sync codes */
431 mipi_set_lvds_sync_codes(devno, p_lvds_attr, lane_num, lane_bitmap);
432
433 mipi_rx_set_phy_rg_lp0_mode_en(devno, 0);
434 mipi_rx_set_phy_rg_lp1_mode_en(devno, 0);
435 }
436
mipi_set_lvds_dev_attr(combo_dev_attr_t * p_combo_dev_attr)437 static int mipi_set_lvds_dev_attr(combo_dev_attr_t *p_combo_dev_attr)
438 {
439 combo_dev_t devno;
440 lvds_dev_attr_t *p_lvds_attr;
441 int ret;
442 unsigned int lane_bitmap;
443 unsigned int lane_num;
444
445 devno = p_combo_dev_attr->devno;
446 p_lvds_attr = &p_combo_dev_attr->lvds_attr;
447
448 if (mipi_is_hs_mode_cfged() != TRUE) {
449 HI_ERR("mipi must set hs mode before set lvds attr!\n");
450 return HI_FAILURE;
451 }
452
453 if (!mipi_is_dev_valid(devno)) {
454 HI_ERR("invalid combo dev num after set hs mode!\n");
455 return HI_FAILURE;
456 }
457
458 ret = check_lvds_dev_attr(devno, p_lvds_attr);
459 if (ret != HI_SUCCESS) {
460 HI_ERR("check_lvds_dev_attr failed!\n");
461 return HI_FAILURE;
462 }
463
464 lane_bitmap = mipi_get_lane_bitmap(INPUT_MODE_LVDS, p_lvds_attr->lane_id, &lane_num);
465
466 /* work mode */
467 mipi_rx_drv_set_work_mode(devno, INPUT_MODE_LVDS);
468
469 /* image crop */
470 mipi_rx_drv_set_lvds_image_rect(devno, &p_combo_dev_attr->img_rect, lane_num);
471 mipi_rx_drv_set_lvds_crop_en(devno, TRUE);
472
473 /* data type & mode */
474 ret = mipi_rx_drv_set_lvds_wdr_mode(devno, p_lvds_attr->wdr_mode, &p_lvds_attr->vsync_attr, &p_lvds_attr->fid_attr);
475 if (ret < 0) {
476 HI_ERR("set lvds wdr mode failed!\n");
477 return HI_FAILURE;
478 }
479
480 mipi_rx_drv_set_lvds_ctrl_mode(devno, p_lvds_attr->sync_mode, p_lvds_attr->input_data_type,
481 p_lvds_attr->data_endian, p_lvds_attr->sync_code_endian);
482
483 /* data rate */
484 mipi_rx_drv_set_lvds_data_rate(devno, p_combo_dev_attr->data_rate);
485
486 mipi_set_lvds_phy_sync_cfg(devno, p_lvds_attr, lane_bitmap, lane_num);
487
488 mipi_set_lvds_int_mask(devno);
489
490 return HI_SUCCESS;
491 }
492
check_mipi_dev_attr(combo_dev_t devno,mipi_dev_attr_t * p_attr)493 static int check_mipi_dev_attr(combo_dev_t devno, mipi_dev_attr_t *p_attr)
494 {
495 int ret;
496 int i;
497
498 if ((p_attr->input_data_type < DATA_TYPE_RAW_8BIT) || (p_attr->input_data_type >= DATA_TYPE_BUTT)) {
499 HI_ERR("invalid input_data_type, must be in [%d, %d)\n", DATA_TYPE_RAW_8BIT, DATA_TYPE_BUTT);
500 return HI_FAILURE;
501 }
502
503 if ((p_attr->wdr_mode < HI_MIPI_WDR_MODE_NONE) || (p_attr->wdr_mode >= HI_MIPI_WDR_MODE_BUTT)) {
504 HI_ERR("invalid wdr_mode, must be in [%d, %d)\n", HI_MIPI_WDR_MODE_NONE, HI_MIPI_WDR_MODE_BUTT);
505 return HI_FAILURE;
506 }
507
508 if ((p_attr->wdr_mode != HI_MIPI_WDR_MODE_NONE) &&
509 (p_attr->input_data_type >= DATA_TYPE_YUV420_8BIT_NORMAL)) {
510 HI_ERR("It do not support wdr mode when input_data_type is yuv format!\n");
511 return HI_FAILURE;
512 }
513
514 if (p_attr->wdr_mode == HI_MIPI_WDR_MODE_DT) {
515 for (i = 0; i < WDR_VC_NUM; i++) {
516 /* data_type must be the CSI-2 reserve Type [0x38, 0x3f] */
517 if (p_attr->data_type[i] < 0x38 || p_attr->data_type[i] > 0x3f) {
518 HI_ERR("invalid data_type[%d]: %d, must be in [0x38, 0x3f]\n", i, p_attr->data_type[i]);
519 return HI_FAILURE;
520 }
521 }
522 }
523
524 ret = check_lane_id(devno, INPUT_MODE_MIPI, p_attr->lane_id);
525 if (ret < 0) {
526 HI_ERR("check_lane_id failed!\n");
527 return HI_FAILURE;
528 }
529
530 return HI_SUCCESS;
531 }
532
mipi_set_dt_and_mode(combo_dev_t devno,mipi_dev_attr_t * p_attr)533 static void mipi_set_dt_and_mode(combo_dev_t devno, mipi_dev_attr_t *p_attr)
534 {
535 data_type_t input_data_type;
536
537 input_data_type = p_attr->input_data_type;
538
539 mipi_rx_drv_set_di_dt(devno, input_data_type);
540 mipi_rx_drv_set_mipi_yuv_dt(devno, input_data_type);
541
542 if (p_attr->wdr_mode == HI_MIPI_WDR_MODE_DT) {
543 mipi_rx_drv_set_mipi_wdr_user_dt(devno, input_data_type, p_attr->data_type);
544 } else if (p_attr->wdr_mode == HI_MIPI_WDR_MODE_DOL) {
545 mipi_rx_drv_set_mipi_dol_id(devno, input_data_type, NULL);
546 }
547
548 mipi_rx_drv_set_mipi_wdr_mode(devno, p_attr->wdr_mode);
549 }
550
mipi_set_int_mask(combo_dev_t devno)551 static void mipi_set_int_mask(combo_dev_t devno)
552 {
553 /* interrupt mask */
554 (void)memset_s(mipi_rx_hal_get_mipi_err_int(devno), sizeof(mipi_err_int_cnt_t), 0, sizeof(mipi_err_int_cnt_t));
555 (void)memset_s(mipi_rx_hal_get_align_err_int_cnt(devno), sizeof(align_err_int_cnt_t), 0,
556 sizeof(align_err_int_cnt_t));
557
558 #ifdef ENABLE_INT_MASK
559 mipi_rx_drv_set_mipi_int_mask(devno);
560 mipi_rx_drv_set_mipi_ctrl_int_mask(devno, MIPI_CTRL_INT_MASK); /* 0x12f8 */
561 mipi_rx_drv_set_mipi_pkt1_int_mask(devno, MIPI_PKT_INT1_MASK); /* 0x1064 */
562 mipi_rx_drv_set_mipi_pkt2_int_mask(devno, MIPI_PKT_INT2_MASK); /* 0x1074 */
563 mipi_rx_drv_set_mipi_frame_int_mask(devno, MIPI_FRAME_INT_MASK); /* 0x1084 */
564 mipi_rx_drv_set_align_int_mask(devno, ALIGN0_INT_MASK); /* 0x18f8 */
565 #endif
566 }
567
mipi_set_phy_cfg(combo_dev_attr_t * p_combo_dev_attr)568 static void mipi_set_phy_cfg(combo_dev_attr_t *p_combo_dev_attr)
569 {
570 combo_dev_t devno;
571 unsigned int lane_bitmap;
572 unsigned int lane_num;
573 mipi_dev_attr_t *p_mipi_attr;
574
575 devno = p_combo_dev_attr->devno;
576 p_mipi_attr = &p_combo_dev_attr->mipi_attr;
577
578 lane_bitmap = mipi_get_lane_bitmap(INPUT_MODE_MIPI, p_mipi_attr->lane_id, &lane_num);
579 mipi_rx_drv_set_link_lane_id(devno, INPUT_MODE_MIPI, p_mipi_attr->lane_id,
580 lane_bitmap, g_mipirx_dev_ctx.lane_divide_mode);
581
582 if (g_mipirx_dev_ctx.lane_divide_mode == 0) {
583 mipi_rx_drv_set_lane_num(devno, lane_num);
584 } else {
585 mipi_rx_drv_set_lane_num(devno, lane_num);
586
587 if (devno == 1) {
588 if (lane_bitmap == 0x3) {
589 lane_bitmap = 0xa;
590 } else if (lane_bitmap == 0x1) {
591 lane_bitmap = 0x2;
592 } else if (lane_bitmap == 0x2) {
593 lane_bitmap = 0x8;
594 } else {
595 lane_bitmap = 0xa;
596 }
597 }
598 }
599
600 g_mipirx_dev_ctx.lane_bitmap[devno] = lane_bitmap;
601 mipi_rx_drv_set_phy_config(INPUT_MODE_MIPI, lane_bitmap);
602 }
603
mipi_set_mipi_dev_attr(combo_dev_attr_t * p_combo_dev_attr)604 static int mipi_set_mipi_dev_attr(combo_dev_attr_t *p_combo_dev_attr)
605 {
606 combo_dev_t devno;
607 mipi_dev_attr_t *p_mipi_attr;
608 int ret;
609
610 devno = p_combo_dev_attr->devno;
611 p_mipi_attr = &p_combo_dev_attr->mipi_attr;
612
613 if (mipi_is_hs_mode_cfged() != TRUE) {
614 HI_ERR("mipi must set hs mode before set mipi attr!\n");
615 return HI_FAILURE;
616 }
617
618 if (!mipi_is_dev_valid(devno)) {
619 HI_ERR("invalid combo dev num after set hs mode!\n");
620 return HI_FAILURE;
621 }
622
623 ret = check_mipi_dev_attr(devno, p_mipi_attr);
624 if (ret < 0) {
625 HI_ERR("check_mipi_dev_attr failed!\n");
626 return HI_FAILURE;
627 }
628
629 /* work mode */
630 mipi_rx_drv_set_work_mode(devno, INPUT_MODE_MIPI);
631
632 /* image crop */
633 mipi_rx_drv_set_mipi_image_rect(devno, &p_combo_dev_attr->img_rect);
634 mipi_rx_drv_set_mipi_crop_en(devno, TRUE);
635
636 /* data type & mode */
637 mipi_set_dt_and_mode(devno, p_mipi_attr);
638
639 /* data rate */
640 mipi_rx_drv_set_data_rate(devno, p_combo_dev_attr->data_rate);
641
642 /* phy lane config */
643 mipi_set_phy_cfg(p_combo_dev_attr);
644
645 mipi_rx_drv_set_mem_cken(devno, TRUE);
646
647 mipi_set_int_mask(devno);
648
649 return HI_SUCCESS;
650 }
651
mipi_set_cmos_dev_attr(combo_dev_attr_t * p_combo_dev_attr)652 static int mipi_set_cmos_dev_attr(combo_dev_attr_t *p_combo_dev_attr)
653 {
654 combo_dev_t devno;
655 unsigned int lane_bitmap = 0xf;
656 unsigned int phy_id = 0;
657
658 devno = p_combo_dev_attr->devno;
659
660 if ((devno > CMOS_MAX_DEV_NUM) || (devno == 0)) {
661 HI_ERR("invalid cmos devno(%d)!\n", devno);
662 return HI_FAILURE;
663 }
664
665 if (devno == 1) {
666 phy_id = 0;
667 lane_bitmap = 0xf;
668 }
669
670 if (p_combo_dev_attr->input_mode != INPUT_MODE_BT656) {
671 if (devno == 1) {
672 mipi_rx_drv_set_cmos_en(phy_id, 1);
673 }
674 mipi_rx_drv_set_phy_en(lane_bitmap);
675 mipi_rx_drv_set_phy_cfg_en(lane_bitmap, 1);
676 mipi_rx_drv_set_lane_en(lane_bitmap);
677 mipi_rx_drv_set_phy_cil_en(lane_bitmap, 1);
678 mipi_rx_drv_set_phy_cfg_mode(INPUT_MODE_CMOS, lane_bitmap); /* BT1120 may not need 698~700 */
679
680 mipi_rx_set_phy_rg_lp0_mode_en(phy_id, 0);
681 mipi_rx_set_phy_rg_lp1_mode_en(phy_id, 0);
682 }
683
684 return HI_SUCCESS;
685 }
686
687
mipi_set_combo_dev_attr(combo_dev_attr_t * p_attr)688 static int mipi_set_combo_dev_attr(combo_dev_attr_t *p_attr)
689 {
690 int ret;
691
692 ret = mipi_check_comb_dev_attr(p_attr);
693 if (ret < 0) {
694 HI_ERR("mipi check combo_dev attr failed!\n");
695 return HI_FAILURE;
696 }
697
698 if (osal_mutex_lock_interruptible(&g_mipirx_mutex)) {
699 return -ERESTARTSYS;
700 }
701
702 switch (p_attr->input_mode) {
703 case INPUT_MODE_LVDS:
704 case INPUT_MODE_SUBLVDS:
705 case INPUT_MODE_HISPI: {
706 ret = mipi_set_lvds_dev_attr(p_attr);
707 if (ret < 0) {
708 HI_ERR("mipi set lvds attr failed!\n");
709 ret = HI_FAILURE;
710 }
711 break;
712 }
713
714 case INPUT_MODE_MIPI: {
715 ret = mipi_set_mipi_dev_attr(p_attr);
716 if (ret < 0) {
717 HI_ERR("mipi set mipi attr failed!\n");
718 ret = HI_FAILURE;
719 }
720 break;
721 }
722
723 case INPUT_MODE_CMOS:
724 case INPUT_MODE_BT601:
725 case INPUT_MODE_BT656:
726 case INPUT_MODE_BT1120: {
727 ret = mipi_set_cmos_dev_attr(p_attr);
728 if (ret < 0) {
729 HI_ERR("mipi set cmos attr failed!\n");
730 ret = HI_FAILURE;
731 }
732 break;
733 }
734
735 default: {
736 HI_ERR("invalid input mode\n");
737 ret = HI_FAILURE;
738 break;
739 }
740 }
741
742 osal_mutex_unlock(&g_mipirx_mutex);
743
744 return ret;
745 }
746
mipi_set_ext_data_type(ext_data_type_t * data_type)747 int mipi_set_ext_data_type(ext_data_type_t* data_type)
748 {
749 unsigned int i;
750 combo_dev_t devno;
751 input_mode_t input_mode;
752 data_type_t input_data_type;
753
754 devno = data_type->devno;
755
756 if (devno >= COMBO_DEV_MAX_NUM) {
757 HI_ERR("invalid mipi dev number(%d).\n", devno);
758 return HI_FAILURE;
759 }
760
761 if (osal_mutex_lock_interruptible(&g_mipirx_mutex)) {
762 return -ERESTARTSYS;
763 }
764
765 if (!mipi_is_dev_cfged(devno)) {
766 osal_mutex_unlock(&g_mipirx_mutex);
767 HI_ERR("MIPI device %d has not beed configured\n", devno);
768 return HI_FAILURE;
769 }
770
771 osal_spin_lock(&g_mipirx_ctx_lock);
772 input_mode = g_mipirx_dev_ctx.combo_dev_attr[devno].input_mode;
773 input_data_type = g_mipirx_dev_ctx.combo_dev_attr[devno].mipi_attr.input_data_type;
774 osal_spin_unlock(&g_mipirx_ctx_lock);
775
776 if (input_mode != INPUT_MODE_MIPI) {
777 osal_mutex_unlock(&g_mipirx_mutex);
778 HI_ERR("devno: %d, input mode: %d, not support set data type\n", devno, input_mode);
779 return HI_FAILURE;
780 }
781
782 if (data_type->num > MAX_EXT_DATA_TYPE_NUM) {
783 osal_mutex_unlock(&g_mipirx_mutex);
784 HI_ERR("invalid ext data type num(%d)\n", data_type->num);
785 return HI_FAILURE;
786 }
787
788 for (i = 0; i < data_type->num; i++) {
789 if (data_type->ext_data_bit_width[i] < MIPI_RX_MIN_EXT_DATA_TYPE_BIT_WIDTH ||
790 data_type->ext_data_bit_width[i] > MIPI_RX_MAX_EXT_DATA_TYPE_BIT_WIDTH) {
791 osal_mutex_unlock(&g_mipirx_mutex);
792 HI_ERR("invalid ext data bit width(%d)\n", data_type->ext_data_bit_width[i]);
793 return HI_FAILURE;
794 }
795
796 if (data_type->ext_data_bit_width[i] % 2 != 0) { /* 2:even check */
797 HI_ERR("invalid ext data bit width(%d),must be even value\n", data_type->ext_data_bit_width[i]);
798 osal_mutex_unlock(&g_mipirx_mutex);
799 return HI_FAILURE;
800 }
801 }
802
803 mipi_rx_drv_set_ext_data_type(data_type, input_data_type);
804
805 osal_mutex_unlock(&g_mipirx_mutex);
806
807 return HI_SUCCESS;
808 }
809
mipi_set_phy_cmvmode(combo_dev_t devno,phy_cmv_mode_t cmv_mode)810 static int mipi_set_phy_cmvmode(combo_dev_t devno, phy_cmv_mode_t cmv_mode)
811 {
812 input_mode_t input_mode;
813 unsigned int lane_bit_map;
814
815 if (devno >= COMBO_DEV_MAX_NUM) {
816 HI_ERR("invalid mipi dev number(%d).\n", devno);
817 return HI_FAILURE;
818 }
819
820 if ((cmv_mode < PHY_CMV_GE1200MV) || (cmv_mode >= PHY_CMV_BUTT)) {
821 HI_ERR("invalid common mode voltage mode: %d, must be int [%d, %d)\n",
822 cmv_mode, PHY_CMV_GE1200MV, PHY_CMV_BUTT);
823 return HI_FAILURE;
824 }
825
826 if (osal_mutex_lock_interruptible(&g_mipirx_mutex)) {
827 return -ERESTARTSYS;
828 }
829
830 if (!mipi_is_dev_cfged(devno)) {
831 osal_mutex_unlock(&g_mipirx_mutex);
832 HI_ERR("MIPI device %d has not beed configured\n", devno);
833 return HI_FAILURE;
834 }
835
836 osal_spin_lock(&g_mipirx_ctx_lock);
837 input_mode = g_mipirx_dev_ctx.combo_dev_attr[devno].input_mode;
838 lane_bit_map = g_mipirx_dev_ctx.lane_bitmap[devno];
839 osal_spin_unlock(&g_mipirx_ctx_lock);
840
841 if (input_mode != INPUT_MODE_MIPI &&
842 input_mode != INPUT_MODE_SUBLVDS &&
843 input_mode != INPUT_MODE_LVDS &&
844 input_mode != INPUT_MODE_HISPI) {
845 osal_mutex_unlock(&g_mipirx_mutex);
846 HI_ERR("devno: %d, input mode: %d, not support set common voltage mode\n", devno, input_mode);
847 return HI_FAILURE;
848 }
849
850 mipi_rx_drv_set_phy_cmvmode(input_mode, cmv_mode, lane_bit_map);
851
852 osal_mutex_unlock(&g_mipirx_mutex);
853
854 return HI_SUCCESS;
855 }
856
mipi_reset_sensor(sns_rst_source_t sns_reset_source)857 static int mipi_reset_sensor(sns_rst_source_t sns_reset_source)
858 {
859 if (sns_reset_source >= SNS_MAX_RST_SOURCE_NUM) {
860 HI_ERR("invalid sns_reset_source(%d).\n", sns_reset_source);
861 return HI_FAILURE;
862 }
863
864 sensor_drv_reset(sns_reset_source);
865
866 return HI_SUCCESS;
867 }
868
mipi_unreset_sensor(sns_rst_source_t sns_reset_source)869 static int mipi_unreset_sensor(sns_rst_source_t sns_reset_source)
870 {
871 if (sns_reset_source >= SNS_MAX_RST_SOURCE_NUM) {
872 HI_ERR("invalid sns_reset_source(%d).\n", sns_reset_source);
873 return HI_FAILURE;
874 }
875
876 sensor_drv_unreset(sns_reset_source);
877
878 return HI_SUCCESS;
879 }
880
mipi_reset_mipi_rx(combo_dev_t combo_dev)881 static int mipi_reset_mipi_rx(combo_dev_t combo_dev)
882 {
883 if (combo_dev >= MIPI_RX_MAX_DEV_NUM) {
884 HI_ERR("invalid combo_dev num(%d).\n", combo_dev);
885 return HI_FAILURE;
886 }
887
888 mipi_rx_drv_core_reset(combo_dev);
889
890 return HI_SUCCESS;
891 }
892
mipi_unreset_mipi_rx(combo_dev_t combo_dev)893 static int mipi_unreset_mipi_rx(combo_dev_t combo_dev)
894 {
895 if (combo_dev >= MIPI_RX_MAX_DEV_NUM) {
896 HI_ERR("invalid combo_dev num(%d).\n", combo_dev);
897 return HI_FAILURE;
898 }
899
900 mipi_rx_drv_core_unreset(combo_dev);
901
902 return HI_SUCCESS;
903 }
904
mipi_set_dev_valid(lane_divide_mode_t mode)905 static void mipi_set_dev_valid(lane_divide_mode_t mode)
906 {
907 switch (mode) {
908 case LANE_DIVIDE_MODE_0:
909 g_mipirx_dev_ctx.dev_valid[0] = 1;
910 break;
911 case LANE_DIVIDE_MODE_1:
912 g_mipirx_dev_ctx.dev_valid[0] = 1;
913 g_mipirx_dev_ctx.dev_valid[1] = 1;
914 break;
915 default:
916 break;
917 }
918 }
919
mipi_set_hs_mode(lane_divide_mode_t lane_divide_mode)920 static int mipi_set_hs_mode(lane_divide_mode_t lane_divide_mode)
921 {
922 if ((lane_divide_mode < LANE_DIVIDE_MODE_0) ||
923 (lane_divide_mode >= LANE_DIVIDE_MODE_BUTT)) {
924 HI_ERR("invalid lane_divide_mode(%d), must be in [%d, %d)\n",
925 lane_divide_mode, LANE_DIVIDE_MODE_0, LANE_DIVIDE_MODE_BUTT);
926 return HI_FAILURE;
927 }
928
929 mipi_rx_drv_set_hs_mode(lane_divide_mode);
930
931 osal_spin_lock(&g_mipirx_ctx_lock);
932 g_mipirx_dev_ctx.lane_divide_mode = lane_divide_mode;
933 g_mipirx_dev_ctx.hs_mode_cfged = TRUE;
934 (void)memset_s(g_mipirx_dev_ctx.dev_valid,
935 sizeof(g_mipirx_dev_ctx.dev_valid),
936 0,
937 sizeof(g_mipirx_dev_ctx.dev_valid));
938 mipi_set_dev_valid(lane_divide_mode);
939 osal_spin_unlock(&g_mipirx_ctx_lock);
940
941 return HI_SUCCESS;
942 }
943
mipi_enable_mipi_rx_clock(combo_dev_t combo_dev)944 static int mipi_enable_mipi_rx_clock(combo_dev_t combo_dev)
945 {
946 if (combo_dev >= MIPI_RX_MAX_DEV_NUM) {
947 HI_ERR("invalid combo_dev num(%d).\n", combo_dev);
948 return HI_FAILURE;
949 }
950
951 mipi_rx_drv_enable_clock(combo_dev);
952
953 return HI_SUCCESS;
954 }
955
mipi_disable_mipi_rx_clock(combo_dev_t combo_dev)956 static int mipi_disable_mipi_rx_clock(combo_dev_t combo_dev)
957 {
958 if (combo_dev >= MIPI_RX_MAX_DEV_NUM) {
959 HI_ERR("invalid combo_dev num(%d).\n", combo_dev);
960 return HI_FAILURE;
961 }
962
963 mipi_rx_drv_disable_clock(combo_dev);
964
965 return HI_SUCCESS;
966 }
967
mipi_enable_sensor_clock(sns_clk_source_t sns_clk_source)968 static int mipi_enable_sensor_clock(sns_clk_source_t sns_clk_source)
969 {
970 if (sns_clk_source >= SNS_MAX_CLK_SOURCE_NUM) {
971 HI_ERR("invalid sns_clk_source(%d).\n", sns_clk_source);
972 return HI_FAILURE;
973 }
974
975 sensor_drv_enable_clock(sns_clk_source);
976
977 return HI_SUCCESS;
978 }
979
mipi_disable_sensor_clock(sns_clk_source_t sns_clk_source)980 static int mipi_disable_sensor_clock(sns_clk_source_t sns_clk_source)
981 {
982 if (sns_clk_source >= SNS_MAX_CLK_SOURCE_NUM) {
983 HI_ERR("invalid sns_clk_source(%d).\n", sns_clk_source);
984 return HI_FAILURE;
985 }
986
987 sensor_drv_disable_clock(sns_clk_source);
988
989 return HI_SUCCESS;
990 }
991
mipi_rx_ioctl(unsigned int cmd,unsigned long arg,void * private_data)992 static long mipi_rx_ioctl(unsigned int cmd, unsigned long arg, void *private_data)
993 {
994 unsigned long *argp = (unsigned long *)(uintptr_t)arg;
995 int ret;
996 errno_t err;
997
998 if (argp == NULL) {
999 HI_ERR("NULL pointer \r\n");
1000 return HI_FAILURE;
1001 }
1002
1003 hi_mipi_rx_unused(private_data);
1004 switch (cmd) {
1005 case HI_MIPI_SET_DEV_ATTR: {
1006 combo_dev_attr_t *pstcombo_dev_attr = NULL;
1007 combo_dev_t devno;
1008
1009 pstcombo_dev_attr = (combo_dev_attr_t *)argp;
1010
1011 ret = mipi_set_combo_dev_attr(pstcombo_dev_attr);
1012 if (ret < 0) {
1013 HI_ERR("mipi set combo_dev attr failed!\n");
1014 ret = HI_FAILURE;
1015 } else {
1016 devno = pstcombo_dev_attr->devno;
1017 osal_spin_lock(&g_mipirx_ctx_lock);
1018 g_mipirx_dev_ctx.dev_cfged[devno] = TRUE;
1019 err = memcpy_s(&g_mipirx_dev_ctx.combo_dev_attr[devno],
1020 sizeof(combo_dev_attr_t),
1021 pstcombo_dev_attr,
1022 sizeof(combo_dev_attr_t));
1023 if (err != EOK) {
1024 g_mipirx_dev_ctx.dev_cfged[devno] = FALSE;
1025 ret = HI_FAILURE;
1026 }
1027 osal_spin_unlock(&g_mipirx_ctx_lock);
1028 }
1029 break;
1030 }
1031
1032 case HI_MIPI_SET_PHY_CMVMODE: {
1033 phy_cmv_t *p_phy_cmv;
1034
1035 p_phy_cmv = (phy_cmv_t *)argp;
1036
1037 ret = mipi_set_phy_cmvmode(p_phy_cmv->devno, p_phy_cmv->cmv_mode);
1038 if (ret < 0) {
1039 HI_ERR("mipi set phy cmv mode failed!\n");
1040 ret = HI_FAILURE;
1041 }
1042 break;
1043 }
1044
1045 case HI_MIPI_RESET_SENSOR: {
1046 sns_rst_source_t sns_reset_source;
1047
1048 err = memcpy_s(&sns_reset_source, sizeof(sns_rst_source_t), argp, sizeof(sns_rst_source_t));
1049 if (err != EOK) {
1050 ret = HI_FAILURE;
1051 } else {
1052 ret = mipi_reset_sensor(sns_reset_source);
1053 if (ret < 0) {
1054 HI_ERR("mipi reset sensor failed!\n");
1055 ret = HI_FAILURE;
1056 }
1057 }
1058 break;
1059 }
1060
1061 case HI_MIPI_UNRESET_SENSOR: {
1062 sns_rst_source_t sns_reset_source;
1063
1064 err = memcpy_s(&sns_reset_source, sizeof(sns_rst_source_t), argp, sizeof(sns_rst_source_t));
1065 if (err != EOK) {
1066 ret = HI_FAILURE;
1067 } else {
1068 ret = mipi_unreset_sensor(sns_reset_source);
1069 if (ret < 0) {
1070 HI_ERR("mipi unreset sensor failed!\n");
1071 ret = HI_FAILURE;
1072 }
1073 }
1074 break;
1075 }
1076
1077 case HI_MIPI_RESET_MIPI: {
1078 combo_dev_t combo_dev;
1079
1080 err = memcpy_s(&combo_dev, sizeof(combo_dev_t), argp, sizeof(combo_dev_t));
1081 if (err != EOK) {
1082 ret = HI_FAILURE;
1083 } else {
1084 ret = mipi_reset_mipi_rx(combo_dev);
1085 if (ret < 0) {
1086 HI_ERR("mipi reset mipi_rx failed!\n");
1087 ret = HI_FAILURE;
1088 }
1089 }
1090 break;
1091 }
1092
1093 case HI_MIPI_UNRESET_MIPI: {
1094 combo_dev_t combo_dev;
1095
1096 err = memcpy_s(&combo_dev, sizeof(combo_dev_t), argp, sizeof(combo_dev_t));
1097 if (err != EOK) {
1098 ret = HI_FAILURE;
1099 } else {
1100 ret = mipi_unreset_mipi_rx(combo_dev);
1101 if (ret < 0) {
1102 HI_ERR("mipi unreset mipi_rx failed!\n");
1103 ret = HI_FAILURE;
1104 }
1105 }
1106 break;
1107 }
1108
1109 case HI_MIPI_RESET_SLVS: {
1110 HI_ERR("Do not support SLVS, please use mipi/lvds mode.\n");
1111 ret = HI_FAILURE;
1112 break;
1113 }
1114
1115 case HI_MIPI_UNRESET_SLVS: {
1116 HI_ERR("Do not support SLVS, please use mipi/lvds mode.\n");
1117 ret = HI_FAILURE;
1118 break;
1119 }
1120
1121 case HI_MIPI_SET_HS_MODE: {
1122 lane_divide_mode_t lane_divide_mode;
1123
1124 err = memcpy_s(&lane_divide_mode, sizeof(lane_divide_mode_t), argp, sizeof(lane_divide_mode_t));
1125 if (err != EOK) {
1126 ret = HI_FAILURE;
1127 } else {
1128 ret = mipi_set_hs_mode(lane_divide_mode);
1129 if (ret < 0) {
1130 HI_ERR("mipi set hs mode failed!\n");
1131 ret = HI_FAILURE;
1132 }
1133 }
1134 break;
1135 }
1136
1137 case HI_MIPI_ENABLE_MIPI_CLOCK: {
1138 combo_dev_t combo_dev;
1139
1140 err = memcpy_s(&combo_dev, sizeof(combo_dev_t), argp, sizeof(combo_dev_t));
1141 if (err != EOK) {
1142 ret = HI_FAILURE;
1143 } else {
1144 ret = mipi_enable_mipi_rx_clock(combo_dev);
1145 if (ret < 0) {
1146 HI_ERR("mipi enable mipi_rx clock failed!\n");
1147 ret = HI_FAILURE;
1148 }
1149 }
1150 break;
1151 }
1152
1153 case HI_MIPI_DISABLE_MIPI_CLOCK: {
1154 combo_dev_t combo_dev;
1155
1156 err = memcpy_s(&combo_dev, sizeof(combo_dev_t), argp, sizeof(combo_dev_t));
1157 if (err != EOK) {
1158 ret = HI_FAILURE;
1159 } else {
1160 ret = mipi_disable_mipi_rx_clock(combo_dev);
1161 if (ret < 0) {
1162 HI_ERR("mipi disable mipi_rx clock failed!\n");
1163 ret = HI_FAILURE;
1164 }
1165 }
1166 break;
1167 }
1168
1169 case HI_MIPI_ENABLE_SLVS_CLOCK: {
1170 HI_ERR("Do not support SLVS, please use mipi/lvds mode.\n");
1171 ret = HI_FAILURE;
1172 break;
1173 }
1174
1175 case HI_MIPI_DISABLE_SLVS_CLOCK: {
1176 HI_ERR("Do not support SLVS, please use mipi/lvds mode.\n");
1177 ret = HI_FAILURE;
1178 break;
1179 }
1180
1181 case HI_MIPI_ENABLE_SENSOR_CLOCK: {
1182 sns_clk_source_t sns_clk_source;
1183
1184 err = memcpy_s(&sns_clk_source, sizeof(sns_clk_source_t), argp, sizeof(sns_clk_source_t));
1185 if (err != EOK) {
1186 ret = HI_FAILURE;
1187 } else {
1188 ret = mipi_enable_sensor_clock(sns_clk_source);
1189 if (ret < 0) {
1190 HI_ERR("mipi enable sensor clock failed!\n");
1191 ret = HI_FAILURE;
1192 }
1193 }
1194 break;
1195 }
1196
1197 case HI_MIPI_DISABLE_SENSOR_CLOCK: {
1198 sns_clk_source_t sns_clk_source;
1199
1200 err = memcpy_s(&sns_clk_source, sizeof(sns_clk_source_t), argp, sizeof(sns_clk_source_t));
1201 if (err != EOK) {
1202 ret = HI_FAILURE;
1203 } else {
1204 ret = mipi_disable_sensor_clock(sns_clk_source);
1205 if (ret < 0) {
1206 HI_ERR("mipi disable sensor clock failed!\n");
1207 ret = HI_FAILURE;
1208 }
1209 }
1210 break;
1211 }
1212
1213 case HI_MIPI_SET_EXT_DATA_TYPE: {
1214 ext_data_type_t* data_type;
1215
1216 data_type = (ext_data_type_t*)argp;
1217
1218 ret = mipi_set_ext_data_type(data_type);
1219 break;
1220 }
1221
1222 default: {
1223 HI_ERR("invalid himipi ioctl cmd\n");
1224 ret = HI_FAILURE;
1225 break;
1226 }
1227 }
1228
1229 return ret;
1230 }
1231
1232 #ifdef CONFIG_COMPAT
mipi_rx_compat_ioctl(unsigned int cmd,unsigned long arg,void * private_data)1233 static long mipi_rx_compat_ioctl(unsigned int cmd, unsigned long arg, void *private_data)
1234 {
1235 return mipi_rx_ioctl(cmd, arg, private_data);
1236 }
1237 #endif
1238
1239 #ifdef CONFIG_HI_PROC_SHOW_SUPPORT
mipi_get_intput_mode_name(input_mode_t input_mode)1240 static const char *mipi_get_intput_mode_name(input_mode_t input_mode)
1241 {
1242 switch (input_mode) {
1243 case INPUT_MODE_SUBLVDS:
1244 case INPUT_MODE_LVDS:
1245 case INPUT_MODE_HISPI:
1246 return "LVDS";
1247
1248 case INPUT_MODE_MIPI:
1249 return "MIPI";
1250
1251 case INPUT_MODE_CMOS:
1252 case INPUT_MODE_BT1120:
1253 case INPUT_MODE_BT656:
1254 case INPUT_MODE_BYPASS:
1255 return "CMOS";
1256
1257 default:
1258 break;
1259 }
1260
1261 return "N/A";
1262 }
1263
mipi_get_raw_data_type_name(data_type_t type)1264 static const char *mipi_get_raw_data_type_name(data_type_t type)
1265 {
1266 switch (type) {
1267 case DATA_TYPE_RAW_8BIT:
1268 return "RAW8";
1269
1270 case DATA_TYPE_RAW_10BIT:
1271 return "RAW10";
1272
1273 case DATA_TYPE_RAW_12BIT:
1274 return "RAW12";
1275
1276 case DATA_TYPE_RAW_14BIT:
1277 return "RAW14";
1278
1279 case DATA_TYPE_RAW_16BIT:
1280 return "RAW16";
1281
1282 case DATA_TYPE_YUV420_8BIT_NORMAL:
1283 return "yuv420_8bit_normal";
1284
1285 case DATA_TYPE_YUV420_8BIT_LEGACY:
1286 return "yuv420_8bit_legacy";
1287
1288 case DATA_TYPE_YUV422_8BIT:
1289 return "yuv422_8bit";
1290
1291 case DATA_TYPE_YUV422_PACKED:
1292 return "yuv422_packed";
1293
1294 default:
1295 break;
1296 }
1297
1298 return "N/A";
1299 }
1300
mipi_get_data_rate_name(mipi_data_rate_t data_rate)1301 static const char *mipi_get_data_rate_name(mipi_data_rate_t data_rate)
1302 {
1303 switch (data_rate) {
1304 case MIPI_DATA_RATE_X1:
1305 return "X1";
1306
1307 case MIPI_DATA_RATE_X2:
1308 return "X2";
1309
1310 default:
1311 break;
1312 }
1313
1314 return "N/A";
1315 }
mipi_print_mipi_wdr_mode(mipi_wdr_mode_t wdr_mode)1316 static const char *mipi_print_mipi_wdr_mode(mipi_wdr_mode_t wdr_mode)
1317 {
1318 switch (wdr_mode) {
1319 case HI_MIPI_WDR_MODE_NONE:
1320 return "None";
1321
1322 case HI_MIPI_WDR_MODE_VC:
1323 return "VC";
1324
1325 case HI_MIPI_WDR_MODE_DT:
1326 return "DT";
1327
1328 case HI_MIPI_WDR_MODE_DOL:
1329 return "DOL";
1330
1331 default:
1332 break;
1333 }
1334
1335 return "N/A";
1336 }
1337
mipi_print_lvds_wdr_mode(wdr_mode_t wdr_mode)1338 static const char *mipi_print_lvds_wdr_mode(wdr_mode_t wdr_mode)
1339 {
1340 switch (wdr_mode) {
1341 case HI_WDR_MODE_NONE:
1342 return "None";
1343
1344 case HI_WDR_MODE_2F:
1345 return "2F";
1346
1347 case HI_WDR_MODE_3F:
1348 return "3F";
1349
1350 case HI_WDR_MODE_4F:
1351 return "4F";
1352
1353 case HI_WDR_MODE_DOL_2F:
1354 return "DOL_2F";
1355
1356 case HI_WDR_MODE_DOL_3F:
1357 return "DOL_3F";
1358
1359 case HI_WDR_MODE_DOL_4F:
1360 return "DOL_4F";
1361
1362 default:
1363 break;
1364 }
1365
1366 return "N/A";
1367 }
1368
mipi_print_lane_divide_mode(lane_divide_mode_t mode)1369 static const char *mipi_print_lane_divide_mode(lane_divide_mode_t mode)
1370 {
1371 if (mode == LANE_DIVIDE_MODE_0) {
1372 return "4";
1373 } else {
1374 return "2+2";
1375 }
1376 }
1377
proc_show_mipi_device(osal_proc_entry_t * s)1378 static void proc_show_mipi_device(osal_proc_entry_t *s)
1379 {
1380 const char *wdr_mode = NULL;
1381 combo_dev_t devno;
1382 input_mode_t input_mode;
1383 data_type_t data_type;
1384
1385 osal_seq_printf(s,
1386 "\n-----MIPI DEV ATTR-----------------------------------------------"
1387 "------------------------------------------------------\n");
1388
1389 osal_seq_printf(s,
1390 "%8s" "%10s" "%10s" "%20s" "%10s" "%8s" "%8s" "%8s" "%8s" "\n",
1391 "Devno", "WorkMode", "DataRate", "DataType", "WDRMode", "ImgX", "ImgY", "ImgW", "ImgH");
1392
1393 for (devno = 0; devno < MIPI_RX_MAX_DEV_NUM; devno++) {
1394 combo_dev_attr_t *pdev_attr = &g_mipirx_dev_ctx.combo_dev_attr[devno];
1395 input_mode = pdev_attr->input_mode;
1396
1397 if (!mipi_is_dev_cfged(devno)) {
1398 continue;
1399 }
1400
1401 if (input_mode == INPUT_MODE_MIPI) {
1402 data_type = pdev_attr->mipi_attr.input_data_type;
1403 wdr_mode = mipi_print_mipi_wdr_mode(pdev_attr->mipi_attr.wdr_mode);
1404 } else {
1405 data_type = pdev_attr->lvds_attr.input_data_type;
1406 wdr_mode = mipi_print_lvds_wdr_mode(pdev_attr->lvds_attr.wdr_mode);
1407 }
1408
1409 osal_seq_printf(s, "%8d" "%10s" "%10s" "%20s" "%10s" "%8d" "%8d" "%8d" "%8d" "\n",
1410 devno,
1411 mipi_get_intput_mode_name(input_mode),
1412 mipi_get_data_rate_name(pdev_attr->data_rate),
1413 mipi_get_raw_data_type_name(data_type),
1414 wdr_mode,
1415 pdev_attr->img_rect.x,
1416 pdev_attr->img_rect.y,
1417 pdev_attr->img_rect.width,
1418 pdev_attr->img_rect.height);
1419 }
1420 }
1421
proc_show_mipi_lane(osal_proc_entry_t * s)1422 static void proc_show_mipi_lane(osal_proc_entry_t *s)
1423 {
1424 combo_dev_t devno;
1425 input_mode_t input_mode;
1426
1427 osal_seq_printf(s,
1428 "\n-----MIPI LANE INFO----------------------------------------------"
1429 "-------------------------------------------------------\n");
1430
1431 osal_seq_printf(s, "%8s" "%24s" "\n", "Devno", "LaneID");
1432
1433 for (devno = 0; devno < MIPI_RX_MAX_DEV_NUM; devno++) {
1434 combo_dev_attr_t *pdev_attr = &g_mipirx_dev_ctx.combo_dev_attr[devno];
1435
1436 input_mode = pdev_attr->input_mode;
1437
1438 if (!mipi_is_dev_cfged(devno)) {
1439 continue;
1440 }
1441
1442 if (input_mode == INPUT_MODE_MIPI) {
1443 osal_seq_printf(s, "%8d" "%10d,%3d,%3d,%3d" "\n",
1444 devno,
1445 pdev_attr->mipi_attr.lane_id[0], /* 0 -- lane_id 0 */
1446 pdev_attr->mipi_attr.lane_id[1], /* 1 -- lane_id 1 */
1447 pdev_attr->mipi_attr.lane_id[2], /* 2 -- lane_id 2 */
1448 pdev_attr->mipi_attr.lane_id[3]); /* 3 -- lane_id 3 */
1449 } else if (input_mode == INPUT_MODE_LVDS ||
1450 input_mode == INPUT_MODE_SUBLVDS ||
1451 input_mode == INPUT_MODE_HISPI) {
1452 osal_seq_printf(s, "%8d" "%10d,%3d,%3d,%3d" "\n",
1453 devno,
1454 pdev_attr->lvds_attr.lane_id[0],
1455 pdev_attr->lvds_attr.lane_id[1],
1456 pdev_attr->lvds_attr.lane_id[2], /* 2 -- lane_id 2 */
1457 pdev_attr->lvds_attr.lane_id[3]); /* 3 -- lane_id 3 */
1458 }
1459 }
1460 }
1461
proc_show_mipi_phy_data(osal_proc_entry_t * s)1462 static void proc_show_mipi_phy_data(osal_proc_entry_t *s)
1463 {
1464 int i;
1465
1466 osal_seq_printf(s, "\n-----MIPI PHY DATA INFO------------------------------------------------------\n");
1467 osal_seq_printf(s, "%8s" "%15s" "%19s" "%24s" "%22s" "\n",
1468 "PhyId", "LaneId", "PhyData", "MipiData", "LvdsData");
1469
1470 for (i = 0; i < MIPI_RX_MAX_PHY_NUM; i++) {
1471 osal_seq_printf(s,
1472 "%8d%8d,%2d,%2d,%2d, 0x%02x,0x%02x,0x%02x,0x%02x 0x%02x,0x%02x,0x%02x,0x%02x"
1473 " 0x%02x,0x%02x,0x%02x,0x%02x\n",
1474 i,
1475 4 * i, /* 4 * i + 0 -- phy_id lane_id 0 */
1476 4 * i + 1, /* 4 * i + 1 -- phy_id lane_id 1 */
1477 4 * i + 2, /* 4 * i + 2 -- phy_id lane_id 2 */
1478 4 * i + 3, /* 4 * i + 3 -- phy_id lane_id 3 */
1479 mipi_rx_drv_get_phy_data(i, 0), /* 0 -- lane_id 0 */
1480 mipi_rx_drv_get_phy_data(i, 1), /* 1 -- lane_id 1 */
1481 mipi_rx_drv_get_phy_data(i, 2), /* 2 -- lane_id 2 */
1482 mipi_rx_drv_get_phy_data(i, 3), /* 3 -- lane_id 3 */
1483 mipi_rx_drv_get_phy_mipi_link_data(i, 0), /* 0 -- lane_id 0 */
1484 mipi_rx_drv_get_phy_mipi_link_data(i, 1), /* 1 -- lane_id 1 */
1485 mipi_rx_drv_get_phy_mipi_link_data(i, 2), /* 2 -- lane_id 2 */
1486 mipi_rx_drv_get_phy_mipi_link_data(i, 3), /* 3 -- lane_id 3 */
1487 mipi_rx_drv_get_phy_lvds_link_data(i, 0), /* 0 -- lane_id 0 */
1488 mipi_rx_drv_get_phy_lvds_link_data(i, 1), /* 1 -- lane_id 1 */
1489 mipi_rx_drv_get_phy_lvds_link_data(i, 2), /* 2 -- lane_id 2 */
1490 mipi_rx_drv_get_phy_lvds_link_data(i, 3)); /* 3 -- lane_id 3 */
1491 }
1492 }
1493
1494
proc_show_mipi_detect_info(osal_proc_entry_t * s,combo_dev_t devno_array[],int mipi_cnt)1495 static void proc_show_mipi_detect_info(osal_proc_entry_t *s, combo_dev_t devno_array[], int mipi_cnt)
1496 {
1497 img_size_t image_size;
1498 short vc_num;
1499 int devno_idx;
1500
1501 osal_seq_printf(s, "\n-----MIPI DETECT INFO----------------------------------------------------\n");
1502 osal_seq_printf(s, "%6s%3s%8s%8s\n", "Devno", "VC", "width", "height");
1503
1504 for (devno_idx = 0; devno_idx < mipi_cnt; devno_idx++) {
1505 for (vc_num = 0; vc_num < WDR_VC_NUM; vc_num++) {
1506 mipi_rx_drv_get_mipi_imgsize_statis(devno_array[devno_idx], vc_num, &image_size);
1507 osal_seq_printf(s, "%6d%3d%8u%8u\n",
1508 devno_array[devno_idx], vc_num, image_size.width, image_size.height);
1509 }
1510 }
1511 }
1512
proc_show_lvds_detect_info(osal_proc_entry_t * s,combo_dev_t devno_array[],int mipi_cnt)1513 static void proc_show_lvds_detect_info(osal_proc_entry_t *s, combo_dev_t devno_array[], int mipi_cnt)
1514 {
1515 img_size_t image_size;
1516 short vc_num;
1517 int devno_idx;
1518
1519 osal_seq_printf(s, "\n-----LVDS DETECT INFO----------------------------------------------------\n");
1520 osal_seq_printf(s, "%6s%3s%8s%8s\n", "Devno", "VC", "width", "height");
1521
1522 for (devno_idx = 0; devno_idx < mipi_cnt; devno_idx++) {
1523 for (vc_num = 0; vc_num < WDR_VC_NUM; vc_num++) {
1524 mipi_rx_drv_get_lvds_imgsize_statis(devno_array[devno_idx], vc_num, &image_size);
1525 osal_seq_printf(s, "%6d%3d%8d%8d\n",
1526 devno_array[devno_idx], vc_num, image_size.width, image_size.height);
1527 }
1528 }
1529 }
1530
proc_show_lvds_lane_detect_info(osal_proc_entry_t * s,combo_dev_t devno_array[],int mipi_cnt)1531 static void proc_show_lvds_lane_detect_info(osal_proc_entry_t *s, combo_dev_t devno_array[], int mipi_cnt)
1532 {
1533 img_size_t image_size;
1534 short lane;
1535 int devno_idx;
1536 combo_dev_attr_t *pstcombo_dev_attr = NULL;
1537
1538 osal_seq_printf(s, "\n-----LVDS LANE DETECT INFO----------------------------------------------------\n");
1539 osal_seq_printf(s, "%6s%6s%8s%8s\n", "Devno", "Lane", "width", "height");
1540
1541 for (devno_idx = 0; devno_idx < mipi_cnt; devno_idx++) {
1542 pstcombo_dev_attr = &g_mipirx_dev_ctx.combo_dev_attr[devno_array[devno_idx]];
1543
1544 for (lane = 0; lane < LVDS_LANE_NUM; lane++) {
1545 if (pstcombo_dev_attr->lvds_attr.lane_id[lane] != -1) {
1546 mipi_rx_drv_get_lvds_lane_imgsize_statis(devno_array[devno_idx], lane, &image_size);
1547 osal_seq_printf(s, "%6d%6d%8d%8d\n",
1548 devno_array[devno_idx], pstcombo_dev_attr->lvds_attr.lane_id[lane],
1549 image_size.width, image_size.height);
1550 }
1551 }
1552 }
1553 }
1554
proc_show_mipi_hs_mode(osal_proc_entry_t * s)1555 static void proc_show_mipi_hs_mode(osal_proc_entry_t *s)
1556 {
1557 lane_divide_mode_t lane_divide_mode;
1558
1559 osal_spin_lock(&g_mipirx_ctx_lock);
1560 lane_divide_mode = g_mipirx_dev_ctx.lane_divide_mode;
1561 osal_spin_unlock(&g_mipirx_ctx_lock);
1562
1563 osal_seq_printf(s,
1564 "\n-----MIPI LANE DIVIDE MODE---------------------------------------"
1565 "------------------------------------------------------\n");
1566 osal_seq_printf(s, "%6s" "%20s" "\n", "MODE", "LANE DIVIDE");
1567 osal_seq_printf(s, "%6d" "%20s" "\n", lane_divide_mode, mipi_print_lane_divide_mode(lane_divide_mode));
1568 }
1569
proc_show_phy_cil_int_err_cnt(osal_proc_entry_t * s)1570 static void proc_show_phy_cil_int_err_cnt(osal_proc_entry_t *s)
1571 {
1572 int phy_id;
1573
1574 osal_seq_printf(s, "\n-----PHY CIL ERR INT INFO---------------------------------------------\n");
1575 osal_seq_printf(s, "%8s%11s%10s%12s%12s%12s%12s%9s%8s%10s%10s%10s%10s\n",
1576 "PhyId", "Clk2TmOut", "ClkTmOut", "Lane0TmOut", "Lane1TmOut", "Lane2TmOut", "Lane3TmOut",
1577 "Clk2Esc", "ClkEsc", "Lane0Esc", "Lane1Esc", "Lane2Esc", "Lane3Esc");
1578
1579 for (phy_id = 0; phy_id < MIPI_RX_MAX_PHY_NUM; phy_id++) {
1580 osal_seq_printf(s, "%8d%11d%10d%12d%12d%12d%12d%9d%8d%10d%10d%10d%10d\n",
1581 phy_id,
1582 mipi_rx_hal_get_phy_err_int_cnt(phy_id)->clk1_fsm_timeout_err_cnt,
1583 mipi_rx_hal_get_phy_err_int_cnt(phy_id)->clk0_fsm_timeout_err_cnt,
1584 mipi_rx_hal_get_phy_err_int_cnt(phy_id)->d0_fsm_timeout_err_cnt,
1585 mipi_rx_hal_get_phy_err_int_cnt(phy_id)->d1_fsm_timeout_err_cnt,
1586 mipi_rx_hal_get_phy_err_int_cnt(phy_id)->d2_fsm_timeout_err_cnt,
1587 mipi_rx_hal_get_phy_err_int_cnt(phy_id)->d3_fsm_timeout_err_cnt,
1588 mipi_rx_hal_get_phy_err_int_cnt(phy_id)->clk1_fsm_escape_err_cnt,
1589 mipi_rx_hal_get_phy_err_int_cnt(phy_id)->clk0_fsm_escape_err_cnt,
1590 mipi_rx_hal_get_phy_err_int_cnt(phy_id)->d0_fsm_escape_err_cnt,
1591 mipi_rx_hal_get_phy_err_int_cnt(phy_id)->d1_fsm_escape_err_cnt,
1592 mipi_rx_hal_get_phy_err_int_cnt(phy_id)->d2_fsm_escape_err_cnt,
1593 mipi_rx_hal_get_phy_err_int_cnt(phy_id)->d3_fsm_escape_err_cnt);
1594 }
1595 }
1596
proc_show_mipirx_crc_err(osal_proc_entry_t * s,const combo_dev_t devno_array[],int mipi_cnt)1597 static void proc_show_mipirx_crc_err(osal_proc_entry_t *s, const combo_dev_t devno_array[], int mipi_cnt)
1598 {
1599 int devno_idx;
1600 combo_dev_t devno;
1601
1602 osal_seq_printf(s,
1603 "\n-----MIPI ERROR INT INFO 1-----------------------------------------------------------\n");
1604 osal_seq_printf(s, "%8s%6s%8s%8s%8s%8s%14s%14s%14s%14s\n",
1605 "Devno", "Ecc2", "Vc0CRC", "Vc1CRC", "Vc2CRC", "Vc3CRC",
1606 "Vc0EccCorrct", "Vc1EccCorrct", "Vc2EccCorrct", "Vc3EccCorrct");
1607
1608 for (devno_idx = 0; devno_idx < mipi_cnt; devno_idx++) {
1609 devno = devno_array[devno_idx];
1610 osal_seq_printf(s, "%8d%6d%8d%8d%8d%8d%14d%14d%14d%14d\n",
1611 devno,
1612 mipi_rx_hal_get_mipi_err_int(devno)->err_ecc_double_cnt,
1613 mipi_rx_hal_get_mipi_err_int(devno)->vc0_err_crc_cnt,
1614 mipi_rx_hal_get_mipi_err_int(devno)->vc1_err_crc_cnt,
1615 mipi_rx_hal_get_mipi_err_int(devno)->vc2_err_crc_cnt,
1616 mipi_rx_hal_get_mipi_err_int(devno)->vc3_err_crc_cnt,
1617 mipi_rx_hal_get_mipi_err_int(devno)->vc0_err_ecc_corrected_cnt,
1618 mipi_rx_hal_get_mipi_err_int(devno)->vc1_err_ecc_corrected_cnt,
1619 mipi_rx_hal_get_mipi_err_int(devno)->vc2_err_ecc_corrected_cnt,
1620 mipi_rx_hal_get_mipi_err_int(devno)->vc3_err_ecc_corrected_cnt);
1621 }
1622 }
1623
proc_show_mipirx_vc_err(osal_proc_entry_t * s,const combo_dev_t devno_array[],int mipi_cnt)1624 static void proc_show_mipirx_vc_err(osal_proc_entry_t *s, const combo_dev_t devno_array[], int mipi_cnt)
1625 {
1626 int devno_idx;
1627 combo_dev_t devno;
1628
1629 osal_seq_printf(s,
1630 "\n-----MIPI ERROR INT INFO 2-----------------------------------------------------------\n");
1631 osal_seq_printf(s, "%8s%7s%7s%7s%7s%11s%11s%11s%11s\n",
1632 "Devno", "Vc0Dt", "Vc1Dt", "Vc2Dt", "Vc3Dt",
1633 "Vc0FrmCrc", "Vc1FrmCrc", "Vc2FrmCrc", "Vc3FrmCrc");
1634
1635 for (devno_idx = 0; devno_idx < mipi_cnt; devno_idx++) {
1636 devno = devno_array[devno_idx];
1637 osal_seq_printf(s, "%8d%7d%7d%7d%7d%11d%11d%11d%11d\n",
1638 devno,
1639 mipi_rx_hal_get_mipi_err_int(devno)->err_id_vc0_cnt,
1640 mipi_rx_hal_get_mipi_err_int(devno)->err_id_vc1_cnt,
1641 mipi_rx_hal_get_mipi_err_int(devno)->err_id_vc2_cnt,
1642 mipi_rx_hal_get_mipi_err_int(devno)->err_id_vc3_cnt,
1643 mipi_rx_hal_get_mipi_err_int(devno)->err_frame_data_vc0_cnt,
1644 mipi_rx_hal_get_mipi_err_int(devno)->err_frame_data_vc1_cnt,
1645 mipi_rx_hal_get_mipi_err_int(devno)->err_frame_data_vc2_cnt,
1646 mipi_rx_hal_get_mipi_err_int(devno)->err_frame_data_vc3_cnt);
1647 }
1648
1649 osal_seq_printf(s,
1650 "\n-----MIPI ERROR INT INFO 3-----------------------------------------------------------\n");
1651 osal_seq_printf(s, "%8s%11s%11s%11s%11s%12s%12s%12s%12s\n",
1652 "Devno", "Vc0FrmSeq", "Vc1FrmSeq", "Vc2FrmSeq", "Vc3FrmSeq",
1653 "Vc0BndryMt", "Vc1BndryMt", "Vc2BndryMt", "Vc3BndryMt");
1654
1655 for (devno_idx = 0; devno_idx < mipi_cnt; devno_idx++) {
1656 devno = devno_array[devno_idx];
1657 osal_seq_printf(s, "%8d%11d%11d%11d%11d%12d%12d%12d%12d\n",
1658 devno,
1659 mipi_rx_hal_get_mipi_err_int(devno)->err_f_seq_vc0_cnt,
1660 mipi_rx_hal_get_mipi_err_int(devno)->err_f_seq_vc1_cnt,
1661 mipi_rx_hal_get_mipi_err_int(devno)->err_f_seq_vc2_cnt,
1662 mipi_rx_hal_get_mipi_err_int(devno)->err_f_seq_vc3_cnt,
1663 mipi_rx_hal_get_mipi_err_int(devno)->err_f_bndry_match_vc0_cnt,
1664 mipi_rx_hal_get_mipi_err_int(devno)->err_f_bndry_match_vc1_cnt,
1665 mipi_rx_hal_get_mipi_err_int(devno)->err_f_bndry_match_vc2_cnt,
1666 mipi_rx_hal_get_mipi_err_int(devno)->err_f_bndry_match_vc3_cnt);
1667 }
1668 }
1669
proc_show_mipirx_fifo_err(osal_proc_entry_t * s,const combo_dev_t devno_array[],int mipi_cnt)1670 static void proc_show_mipirx_fifo_err(osal_proc_entry_t *s, const combo_dev_t devno_array[], int mipi_cnt)
1671 {
1672 int devno_idx;
1673 combo_dev_t devno;
1674
1675 osal_seq_printf(s,
1676 "\n-----MIPI ERROR INT INFO 4-----------------------------------------------------------\n");
1677 osal_seq_printf(s, "%8s%15s%14s%14s%15s\n",
1678 "Devno", "DataFifoRdErr", "CmdFifoRdErr", "CmdFifoWrErr", "DataFifoWrErr");
1679
1680 for (devno_idx = 0; devno_idx < mipi_cnt; devno_idx++) {
1681 devno = devno_array[devno_idx];
1682 osal_seq_printf(s, "%8d%15d%14d%14d%15d\n",
1683 devno,
1684 mipi_rx_hal_get_mipi_err_int(devno)->data_fifo_rderr_cnt,
1685 mipi_rx_hal_get_mipi_err_int(devno)->cmd_fifo_rderr_cnt,
1686 mipi_rx_hal_get_mipi_err_int(devno)->data_fifo_wrerr_cnt,
1687 mipi_rx_hal_get_mipi_err_int(devno)->cmd_fifo_wrerr_cnt);
1688 }
1689 }
1690
proc_show_mipi_int_err(osal_proc_entry_t * s,combo_dev_t devno_array[],int mipi_cnt)1691 static void proc_show_mipi_int_err(osal_proc_entry_t *s, combo_dev_t devno_array[], int mipi_cnt)
1692 {
1693 proc_show_mipirx_crc_err(s, devno_array, mipi_cnt);
1694
1695 proc_show_mipirx_vc_err(s, devno_array, mipi_cnt);
1696
1697 proc_show_mipirx_fifo_err(s, devno_array, mipi_cnt);
1698 }
1699
proc_show_lvds_int_err(osal_proc_entry_t * s,const combo_dev_t devno_array[],int lvds_cnt)1700 static void proc_show_lvds_int_err(osal_proc_entry_t *s, const combo_dev_t devno_array[], int lvds_cnt)
1701 {
1702 combo_dev_t devno;
1703 int devno_idx;
1704
1705 osal_seq_printf(s,
1706 "\n-----LVDS ERROR INT INFO -----------------------------------------------------------\n");
1707 osal_seq_printf(s, "%8s%10s%10s%8s%9s%12s%12s\n",
1708 "Devno", "CmdRdErr", "CmdWrErr", "PopErr", "StatErr", "Link0WrErr", "Link0RdErr");
1709
1710 for (devno_idx = 0; devno_idx < lvds_cnt; devno_idx++) {
1711 devno = devno_array[devno_idx];
1712 osal_seq_printf(s, "%8d%10d%10d%8d%9d%12d%12d\n",
1713 devno,
1714 mipi_rx_hal_get_lvds_err_int_cnt(devno)->cmd_rd_err_cnt,
1715 mipi_rx_hal_get_lvds_err_int_cnt(devno)->cmd_wr_err_cnt,
1716 mipi_rx_hal_get_lvds_err_int_cnt(devno)->pop_err_cnt,
1717 mipi_rx_hal_get_lvds_err_int_cnt(devno)->lvds_state_err_cnt,
1718 mipi_rx_hal_get_lvds_err_int_cnt(devno)->link0_rd_err_cnt,
1719 mipi_rx_hal_get_lvds_err_int_cnt(devno)->link0_wr_err_cnt);
1720 }
1721 }
1722
proc_show_align_int_err(osal_proc_entry_t * s)1723 static void proc_show_align_int_err(osal_proc_entry_t *s)
1724 {
1725 combo_dev_t devno;
1726
1727 osal_seq_printf(s, "\n-----ALIGN ERROR INT INFO--------------------------------------\n");
1728
1729 for (devno = 0; devno < MIPI_RX_MAX_DEV_NUM; devno++) {
1730 if (!mipi_is_dev_cfged(devno)) {
1731 continue;
1732 }
1733
1734 osal_seq_printf(s, "%8s%14s%10s%10s%10s%10s\n",
1735 "Devno", "FIFO_FullErr", "Lane0Err", "Lane1Err", "Lane2Err", "Lane3Err");
1736
1737 osal_seq_printf(s, "%8d%14d%10d%10d%10d%10d\n",
1738 devno,
1739 mipi_rx_hal_get_align_err_int_cnt(devno)->fifo_full_err_cnt,
1740 mipi_rx_hal_get_align_err_int_cnt(devno)->lane0_align_err_cnt,
1741 mipi_rx_hal_get_align_err_int_cnt(devno)->lane1_align_err_cnt,
1742 mipi_rx_hal_get_align_err_int_cnt(devno)->lane2_align_err_cnt,
1743 mipi_rx_hal_get_align_err_int_cnt(devno)->lane3_align_err_cnt);
1744 }
1745 }
1746
mipi_lvds_proc_show(int mipi_cnt,int lvds_cnt,combo_dev_t devno_mipi[MIPI_RX_MAX_DEV_NUM],combo_dev_t devno_lvds[MIPI_RX_MAX_DEV_NUM],osal_proc_entry_t * s)1747 static void mipi_lvds_proc_show(int mipi_cnt, int lvds_cnt, combo_dev_t devno_mipi[MIPI_RX_MAX_DEV_NUM],
1748 combo_dev_t devno_lvds[MIPI_RX_MAX_DEV_NUM], osal_proc_entry_t *s)
1749 {
1750 if (mipi_cnt > 0 || lvds_cnt > 0) {
1751 proc_show_mipi_hs_mode(s);
1752 proc_show_mipi_device(s);
1753 proc_show_mipi_lane(s);
1754 proc_show_mipi_phy_data(s);
1755 }
1756
1757 if (mipi_cnt > 0) {
1758 proc_show_mipi_detect_info(s, devno_mipi, mipi_cnt);
1759 }
1760
1761 if (lvds_cnt > 0) {
1762 proc_show_lvds_detect_info(s, devno_lvds, lvds_cnt);
1763 proc_show_lvds_lane_detect_info(s, devno_lvds, lvds_cnt);
1764 }
1765
1766 if (mipi_cnt > 0 || lvds_cnt > 0) {
1767 proc_show_phy_cil_int_err_cnt(s);
1768 }
1769
1770 if (mipi_cnt > 0) {
1771 proc_show_mipi_int_err(s, devno_mipi, mipi_cnt);
1772 }
1773
1774 if (lvds_cnt > 0) {
1775 proc_show_lvds_int_err(s, devno_lvds, lvds_cnt);
1776 }
1777
1778 if (mipi_cnt > 0 || lvds_cnt > 0) {
1779 proc_show_align_int_err(s);
1780 }
1781 }
1782
mipi_proc_show(osal_proc_entry_t * s)1783 void mipi_proc_show(osal_proc_entry_t *s)
1784 {
1785 combo_dev_t devno;
1786 int mipi_cnt = 0;
1787 int lvds_cnt = 0;
1788 input_mode_t input_mode;
1789 combo_dev_attr_t *pdev_attr = NULL;
1790 combo_dev_t devno_mipi[MIPI_RX_MAX_DEV_NUM] = {0};
1791 combo_dev_t devno_lvds[MIPI_RX_MAX_DEV_NUM] = {0};
1792
1793 for (devno = 0; devno < MIPI_RX_MAX_DEV_NUM; devno++) {
1794 if (!mipi_is_dev_cfged(devno)) {
1795 continue;
1796 }
1797
1798 osal_spin_lock(&g_mipirx_ctx_lock);
1799 pdev_attr = &g_mipirx_dev_ctx.combo_dev_attr[devno];
1800 input_mode = pdev_attr->input_mode;
1801 osal_spin_unlock(&g_mipirx_ctx_lock);
1802
1803 if (input_mode == INPUT_MODE_MIPI) {
1804 devno_mipi[mipi_cnt] = devno;
1805 mipi_cnt++;
1806 } else if ((input_mode == INPUT_MODE_LVDS) ||
1807 (input_mode == INPUT_MODE_SUBLVDS) ||
1808 (input_mode == INPUT_MODE_HISPI)) {
1809 devno_lvds[lvds_cnt] = devno;
1810 lvds_cnt++;
1811 }
1812 }
1813
1814 mipi_lvds_proc_show(mipi_cnt, lvds_cnt, devno_mipi, devno_lvds, s);
1815 }
1816
mipi_rx_proc_show(osal_proc_entry_t * s)1817 static int mipi_rx_proc_show(osal_proc_entry_t *s)
1818 {
1819 osal_seq_printf(s, "\nModule: [MIPI_RX], Build Time["__DATE__", "__TIME__"]\n");
1820
1821 mipi_proc_show(s);
1822
1823 return HI_SUCCESS;
1824 }
1825 #endif
1826
mipi_rx_init(void)1827 static int mipi_rx_init(void)
1828 {
1829 int ret;
1830
1831 osal_mutex_init(&g_mipirx_mutex);
1832 osal_spin_lock_init(&g_mipirx_ctx_lock);
1833
1834 ret = mipi_rx_drv_init();
1835 if (ret < 0) {
1836 HI_ERR("mipi_rx_drv_init fail!\n");
1837 return HI_FAILURE;
1838 }
1839
1840 return HI_SUCCESS;
1841 }
1842
mipi_rx_exit(void)1843 static void mipi_rx_exit(void)
1844 {
1845 mipi_rx_drv_exit();
1846
1847 osal_spin_lock_destroy(&g_mipirx_ctx_lock);
1848 osal_mutex_destroy(&g_mipirx_mutex);
1849 }
1850
mipi_rx_open(void * private_data)1851 static int mipi_rx_open(void *private_data)
1852 {
1853 hi_mipi_rx_unused(private_data);
1854 return HI_SUCCESS;
1855 }
1856
mipi_rx_release(void * private_data)1857 static int mipi_rx_release(void *private_data)
1858 {
1859 hi_mipi_rx_unused(private_data);
1860 return HI_SUCCESS;
1861 }
1862
1863 static osal_fileops_t mipi_rx_fops = {
1864 .open = mipi_rx_open,
1865 .release = mipi_rx_release,
1866 .unlocked_ioctl = mipi_rx_ioctl,
1867 #ifdef CONFIG_COMPAT
1868 .compat_ioctl = mipi_rx_compat_ioctl,
1869 #endif
1870 };
1871
mipi_rx_freeze(osal_dev_t * pdev)1872 static int mipi_rx_freeze(osal_dev_t *pdev)
1873 {
1874 hi_mipi_rx_unused(pdev);
1875 return HI_SUCCESS;
1876 }
1877
mipi_rx_restore(osal_dev_t * pdev)1878 static int mipi_rx_restore(osal_dev_t *pdev)
1879 {
1880 hi_mipi_rx_unused(pdev);
1881 return HI_SUCCESS;
1882 }
1883
1884 static osal_pmops_t mipi_rx_pmops = {
1885 .pm_freeze = mipi_rx_freeze,
1886 .pm_restore = mipi_rx_restore,
1887 };
1888
mipi_rx_mod_init(void)1889 int mipi_rx_mod_init(void)
1890 {
1891 int ret;
1892 #ifdef CONFIG_HI_PROC_SHOW_SUPPORT
1893 osal_proc_entry_t *mipi_rx_proc_entry = NULL;
1894 #endif
1895 g_mipirx_dev = osal_createdev(MIPI_RX_DEV_NAME);
1896 if (g_mipirx_dev == NULL) {
1897 HI_ERR("create mipi_rx device failed!\n");
1898 goto fail0;
1899 }
1900
1901 g_mipirx_dev->fops = &mipi_rx_fops;
1902 g_mipirx_dev->minor = HIMEDIA_DYNAMIC_MINOR;
1903 g_mipirx_dev->osal_pmops = &mipi_rx_pmops;
1904
1905 ret = osal_registerdevice(g_mipirx_dev);
1906 if (ret < 0) {
1907 HI_ERR("register mipi_rx device failed!\n");
1908 goto fail1;
1909 }
1910 #ifdef CONFIG_HI_PROC_SHOW_SUPPORT
1911 mipi_rx_proc_entry = osal_create_proc_entry(MIPI_RX_PROC_NAME, NULL);
1912 if (mipi_rx_proc_entry == NULL) {
1913 HI_ERR("create mipi_rx proc(%s) failed!\n", MIPI_RX_PROC_NAME);
1914 goto fail2;
1915 }
1916
1917 mipi_rx_proc_entry->read = mipi_rx_proc_show;
1918 mipi_rx_proc_entry->write = NULL;
1919 #endif
1920 ret = mipi_rx_init();
1921 if (ret < 0) {
1922 HI_ERR("mipi_rx_init failed!\n");
1923 goto fail3;
1924 }
1925
1926 osal_printk("load mipi_rx driver successful!\n");
1927 return HI_SUCCESS;
1928
1929 fail3:
1930 #ifdef CONFIG_HI_PROC_SHOW_SUPPORT
1931 osal_remove_proc_entry(MIPI_RX_PROC_NAME, NULL);
1932 #endif
1933 fail2:
1934 osal_deregisterdevice(g_mipirx_dev);
1935 fail1:
1936 osal_destroydev(g_mipirx_dev);
1937 g_mipirx_dev = NULL;
1938 fail0:
1939 HI_ERR("load mipi_rx driver failed!\n");
1940 return HI_FAILURE;
1941 }
1942
mipi_rx_mod_exit(void)1943 void mipi_rx_mod_exit(void)
1944 {
1945 mipi_rx_exit();
1946 #ifdef CONFIG_HI_PROC_SHOW_SUPPORT
1947 osal_remove_proc_entry(MIPI_RX_PROC_NAME, NULL);
1948 #endif
1949 osal_deregisterdevice(g_mipirx_dev);
1950
1951 osal_destroydev(g_mipirx_dev);
1952 g_mipirx_dev = NULL;
1953
1954 osal_printk("unload mipi_rx driver ok!\n");
1955 }
1956
1957 #ifdef __cplusplus
1958 #if __cplusplus
1959 }
1960
1961 #endif
1962 #endif /* End of #ifdef __cplusplus */
1963