1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2019 MediaTek Inc.
3 *
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * Roy Luo <royluo@google.com>
6 * Felix Fietkau <nbd@nbd.name>
7 * Lorenzo Bianconi <lorenzo@kernel.org>
8 */
9
10 #include <linux/etherdevice.h>
11 #include <linux/timekeeping.h>
12 #include "mt7615.h"
13 #include "../trace.h"
14 #include "../dma.h"
15 #include "mt7615_trace.h"
16 #include "mac.h"
17
18 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2)
19
20 static const struct mt7615_dfs_radar_spec etsi_radar_specs = {
21 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
22 .radar_pattern = {
23 [5] = { 1, 0, 6, 32, 28, 0, 17, 990, 5010, 1, 1 },
24 [6] = { 1, 0, 9, 32, 28, 0, 27, 615, 5010, 1, 1 },
25 [7] = { 1, 0, 15, 32, 28, 0, 27, 240, 445, 1, 1 },
26 [8] = { 1, 0, 12, 32, 28, 0, 42, 240, 510, 1, 1 },
27 [9] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 12, 32, 28 },
28 [10] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 15, 32, 24 },
29 [11] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 18, 32, 28 },
30 [12] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 27, 32, 24 },
31 },
32 };
33
34 static const struct mt7615_dfs_radar_spec fcc_radar_specs = {
35 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
36 .radar_pattern = {
37 [0] = { 1, 0, 9, 32, 28, 0, 13, 508, 3076, 1, 1 },
38 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 },
39 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 },
40 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 },
41 [4] = { 1, 0, 9, 255, 28, 0, 13, 323, 343, 1, 32 },
42 },
43 };
44
45 static const struct mt7615_dfs_radar_spec jp_radar_specs = {
46 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
47 .radar_pattern = {
48 [0] = { 1, 0, 8, 32, 28, 0, 13, 508, 3076, 1, 1 },
49 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 },
50 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 },
51 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 },
52 [4] = { 1, 0, 9, 32, 28, 0, 13, 323, 343, 1, 32 },
53 [13] = { 1, 0, 8, 32, 28, 0, 14, 3836, 3856, 1, 1 },
54 [14] = { 1, 0, 8, 32, 28, 0, 14, 3990, 4010, 1, 1 },
55 },
56 };
57
mt7615_rx_get_wcid(struct mt7615_dev * dev,u8 idx,bool unicast)58 static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev,
59 u8 idx, bool unicast)
60 {
61 struct mt7615_sta *sta;
62 struct mt76_wcid *wcid;
63
64 if (idx >= MT7615_WTBL_SIZE)
65 return NULL;
66
67 wcid = rcu_dereference(dev->mt76.wcid[idx]);
68 if (unicast || !wcid)
69 return wcid;
70
71 if (!wcid->sta)
72 return NULL;
73
74 sta = container_of(wcid, struct mt7615_sta, wcid);
75 if (!sta->vif)
76 return NULL;
77
78 return &sta->vif->sta.wcid;
79 }
80
mt7615_mac_reset_counters(struct mt7615_dev * dev)81 void mt7615_mac_reset_counters(struct mt7615_dev *dev)
82 {
83 int i;
84
85 for (i = 0; i < 4; i++) {
86 mt76_rr(dev, MT_TX_AGG_CNT(0, i));
87 mt76_rr(dev, MT_TX_AGG_CNT(1, i));
88 }
89
90 memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats));
91 dev->mt76.phy.survey_time = ktime_get_boottime();
92 if (dev->mt76.phy2)
93 dev->mt76.phy2->survey_time = ktime_get_boottime();
94
95 /* reset airtime counters */
96 mt76_rr(dev, MT_MIB_SDR9(0));
97 mt76_rr(dev, MT_MIB_SDR9(1));
98
99 mt76_rr(dev, MT_MIB_SDR36(0));
100 mt76_rr(dev, MT_MIB_SDR36(1));
101
102 mt76_rr(dev, MT_MIB_SDR37(0));
103 mt76_rr(dev, MT_MIB_SDR37(1));
104
105 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
106 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
107 }
108
mt7615_mac_set_timing(struct mt7615_phy * phy)109 void mt7615_mac_set_timing(struct mt7615_phy *phy)
110 {
111 s16 coverage_class = phy->coverage_class;
112 struct mt7615_dev *dev = phy->dev;
113 bool ext_phy = phy != &dev->phy;
114 u32 val, reg_offset;
115 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
116 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
117 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
118 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
119 int sifs, offset;
120 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ;
121
122 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
123 return;
124
125 if (is_5ghz)
126 sifs = 16;
127 else
128 sifs = 10;
129
130 if (ext_phy) {
131 coverage_class = max_t(s16, dev->phy.coverage_class,
132 coverage_class);
133 mt76_set(dev, MT_ARB_SCR,
134 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
135 } else {
136 struct mt7615_phy *phy_ext = mt7615_ext_phy(dev);
137
138 if (phy_ext)
139 coverage_class = max_t(s16, phy_ext->coverage_class,
140 coverage_class);
141 mt76_set(dev, MT_ARB_SCR,
142 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
143 }
144 udelay(1);
145
146 offset = 3 * coverage_class;
147 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
148 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
149 mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset);
150 mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset);
151
152 mt76_wr(dev, MT_TMAC_ICR(ext_phy),
153 FIELD_PREP(MT_IFS_EIFS, 360) |
154 FIELD_PREP(MT_IFS_RIFS, 2) |
155 FIELD_PREP(MT_IFS_SIFS, sifs) |
156 FIELD_PREP(MT_IFS_SLOT, phy->slottime));
157
158 if (phy->slottime < 20 || is_5ghz)
159 val = MT7615_CFEND_RATE_DEFAULT;
160 else
161 val = MT7615_CFEND_RATE_11B;
162
163 mt76_rmw_field(dev, MT_AGG_ACR(ext_phy), MT_AGG_ACR_CFEND_RATE, val);
164 if (ext_phy)
165 mt76_clear(dev, MT_ARB_SCR,
166 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
167 else
168 mt76_clear(dev, MT_ARB_SCR,
169 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
170
171 }
172
173 static void
mt7615_get_status_freq_info(struct mt7615_dev * dev,struct mt76_phy * mphy,struct mt76_rx_status * status,u8 chfreq)174 mt7615_get_status_freq_info(struct mt7615_dev *dev, struct mt76_phy *mphy,
175 struct mt76_rx_status *status, u8 chfreq)
176 {
177 if (!test_bit(MT76_HW_SCANNING, &mphy->state) &&
178 !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) &&
179 !test_bit(MT76_STATE_ROC, &mphy->state)) {
180 status->freq = mphy->chandef.chan->center_freq;
181 status->band = mphy->chandef.chan->band;
182 return;
183 }
184
185 status->band = chfreq <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
186 status->freq = ieee80211_channel_to_frequency(chfreq, status->band);
187 }
188
mt7615_mac_fill_tm_rx(struct mt7615_dev * dev,__le32 * rxv)189 static void mt7615_mac_fill_tm_rx(struct mt7615_dev *dev, __le32 *rxv)
190 {
191 #ifdef CONFIG_NL80211_TESTMODE
192 u32 rxv1 = le32_to_cpu(rxv[0]);
193 u32 rxv3 = le32_to_cpu(rxv[2]);
194 u32 rxv4 = le32_to_cpu(rxv[3]);
195 u32 rxv5 = le32_to_cpu(rxv[4]);
196 u8 cbw = FIELD_GET(MT_RXV1_FRAME_MODE, rxv1);
197 u8 mode = FIELD_GET(MT_RXV1_TX_MODE, rxv1);
198 s16 foe = FIELD_GET(MT_RXV5_FOE, rxv5);
199 u32 foe_const = (BIT(cbw + 1) & 0xf) * 10000;
200
201 if (!mode) {
202 /* CCK */
203 foe &= ~BIT(11);
204 foe *= 1000;
205 foe >>= 11;
206 } else {
207 if (foe > 2048)
208 foe -= 4096;
209
210 foe = (foe * foe_const) >> 15;
211 }
212
213 dev->test.last_freq_offset = foe;
214 dev->test.last_rcpi[0] = FIELD_GET(MT_RXV4_RCPI0, rxv4);
215 dev->test.last_rcpi[1] = FIELD_GET(MT_RXV4_RCPI1, rxv4);
216 dev->test.last_rcpi[2] = FIELD_GET(MT_RXV4_RCPI2, rxv4);
217 dev->test.last_rcpi[3] = FIELD_GET(MT_RXV4_RCPI3, rxv4);
218 dev->test.last_ib_rssi = FIELD_GET(MT_RXV3_IB_RSSI, rxv3);
219 dev->test.last_wb_rssi = FIELD_GET(MT_RXV3_WB_RSSI, rxv3);
220 #endif
221 }
222
mt7615_mac_fill_rx(struct mt7615_dev * dev,struct sk_buff * skb)223 static int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb)
224 {
225 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
226 struct mt76_phy *mphy = &dev->mt76.phy;
227 struct mt7615_phy *phy = &dev->phy;
228 struct mt7615_phy *phy2 = dev->mt76.phy2 ? dev->mt76.phy2->priv : NULL;
229 struct ieee80211_supported_band *sband;
230 struct ieee80211_hdr *hdr;
231 __le32 *rxd = (__le32 *)skb->data;
232 u32 rxd0 = le32_to_cpu(rxd[0]);
233 u32 rxd1 = le32_to_cpu(rxd[1]);
234 u32 rxd2 = le32_to_cpu(rxd[2]);
235 __le32 rxd12 = rxd[12];
236 bool unicast, remove_pad, insert_ccmp_hdr = false;
237 int phy_idx;
238 int i, idx;
239 u8 chfreq;
240
241 memset(status, 0, sizeof(*status));
242
243 chfreq = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1);
244 if (!phy2)
245 phy_idx = 0;
246 else if (phy2->chfreq == phy->chfreq)
247 phy_idx = -1;
248 else if (phy->chfreq == chfreq)
249 phy_idx = 0;
250 else if (phy2->chfreq == chfreq)
251 phy_idx = 1;
252 else
253 phy_idx = -1;
254
255 unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M;
256 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
257 status->wcid = mt7615_rx_get_wcid(dev, idx, unicast);
258
259 if (status->wcid) {
260 struct mt7615_sta *msta;
261
262 msta = container_of(status->wcid, struct mt7615_sta, wcid);
263 spin_lock_bh(&dev->sta_poll_lock);
264 if (list_empty(&msta->poll_list))
265 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
266 spin_unlock_bh(&dev->sta_poll_lock);
267 }
268
269 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
270 status->flag |= RX_FLAG_FAILED_FCS_CRC;
271
272 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
273 status->flag |= RX_FLAG_MMIC_ERROR;
274
275 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
276 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
277 status->flag |= RX_FLAG_DECRYPTED;
278 status->flag |= RX_FLAG_IV_STRIPPED;
279 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
280 }
281
282 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
283
284 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
285 return -EINVAL;
286
287 rxd += 4;
288 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
289 rxd += 4;
290 if ((u8 *)rxd - skb->data >= skb->len)
291 return -EINVAL;
292 }
293
294 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
295 u8 *data = (u8 *)rxd;
296
297 if (status->flag & RX_FLAG_DECRYPTED) {
298 status->iv[0] = data[5];
299 status->iv[1] = data[4];
300 status->iv[2] = data[3];
301 status->iv[3] = data[2];
302 status->iv[4] = data[1];
303 status->iv[5] = data[0];
304
305 insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
306 }
307 rxd += 4;
308 if ((u8 *)rxd - skb->data >= skb->len)
309 return -EINVAL;
310 }
311
312 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
313 rxd += 2;
314 if ((u8 *)rxd - skb->data >= skb->len)
315 return -EINVAL;
316 }
317
318 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
319 u32 rxdg5 = le32_to_cpu(rxd[5]);
320
321 /*
322 * If both PHYs are on the same channel and we don't have a WCID,
323 * we need to figure out which PHY this packet was received on.
324 * On the primary PHY, the noise value for the chains belonging to the
325 * second PHY will be set to the noise value of the last packet from
326 * that PHY.
327 */
328 if (phy_idx < 0) {
329 int first_chain = ffs(phy2->chainmask) - 1;
330
331 phy_idx = ((rxdg5 >> (first_chain * 8)) & 0xff) == 0;
332 }
333 }
334
335 if (phy_idx == 1 && phy2) {
336 mphy = dev->mt76.phy2;
337 phy = phy2;
338 status->ext_phy = true;
339 }
340
341 if (!mt7615_firmware_offload(dev) && chfreq != phy->chfreq)
342 return -EINVAL;
343
344 mt7615_get_status_freq_info(dev, mphy, status, chfreq);
345 if (status->band == NL80211_BAND_5GHZ)
346 sband = &mphy->sband_5g.sband;
347 else
348 sband = &mphy->sband_2g.sband;
349
350 if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
351 return -EINVAL;
352
353 if (!sband->channels)
354 return -EINVAL;
355
356 if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB |
357 MT_RXD2_NORMAL_NON_AMPDU))) {
358 status->flag |= RX_FLAG_AMPDU_DETAILS;
359
360 /* all subframes of an A-MPDU have the same timestamp */
361 if (phy->rx_ampdu_ts != rxd12) {
362 if (!++phy->ampdu_ref)
363 phy->ampdu_ref++;
364 }
365 phy->rx_ampdu_ts = rxd12;
366
367 status->ampdu_ref = phy->ampdu_ref;
368 }
369
370 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
371 u32 rxdg0 = le32_to_cpu(rxd[0]);
372 u32 rxdg1 = le32_to_cpu(rxd[1]);
373 u32 rxdg3 = le32_to_cpu(rxd[3]);
374 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
375 bool cck = false;
376
377 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
378 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
379 case MT_PHY_TYPE_CCK:
380 cck = true;
381 fallthrough;
382 case MT_PHY_TYPE_OFDM:
383 i = mt76_get_rate(&dev->mt76, sband, i, cck);
384 break;
385 case MT_PHY_TYPE_HT_GF:
386 case MT_PHY_TYPE_HT:
387 status->encoding = RX_ENC_HT;
388 if (i > 31)
389 return -EINVAL;
390 break;
391 case MT_PHY_TYPE_VHT:
392 status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1;
393 status->encoding = RX_ENC_VHT;
394 break;
395 default:
396 return -EINVAL;
397 }
398 status->rate_idx = i;
399
400 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) {
401 case MT_PHY_BW_20:
402 break;
403 case MT_PHY_BW_40:
404 status->bw = RATE_INFO_BW_40;
405 break;
406 case MT_PHY_BW_80:
407 status->bw = RATE_INFO_BW_80;
408 break;
409 case MT_PHY_BW_160:
410 status->bw = RATE_INFO_BW_160;
411 break;
412 default:
413 return -EINVAL;
414 }
415
416 if (rxdg0 & MT_RXV1_HT_SHORT_GI)
417 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
418 if (rxdg0 & MT_RXV1_HT_AD_CODE)
419 status->enc_flags |= RX_ENC_FLAG_LDPC;
420
421 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
422
423 status->chains = mphy->antenna_mask;
424 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3);
425 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3);
426 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3);
427 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3);
428 status->signal = status->chain_signal[0];
429
430 for (i = 1; i < hweight8(mphy->antenna_mask); i++) {
431 if (!(status->chains & BIT(i)))
432 continue;
433
434 status->signal = max(status->signal,
435 status->chain_signal[i]);
436 }
437
438 mt7615_mac_fill_tm_rx(dev, rxd);
439
440 rxd += 6;
441 if ((u8 *)rxd - skb->data >= skb->len)
442 return -EINVAL;
443 }
444
445 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
446
447 if (insert_ccmp_hdr) {
448 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
449
450 mt76_insert_ccmp_hdr(skb, key_id);
451 }
452
453 hdr = (struct ieee80211_hdr *)skb->data;
454 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
455 return 0;
456
457 status->aggr = unicast &&
458 !ieee80211_is_qos_nullfunc(hdr->frame_control);
459 status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
460 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
461
462 return 0;
463 }
464
mt7615_sta_ps(struct mt76_dev * mdev,struct ieee80211_sta * sta,bool ps)465 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
466 {
467 }
468 EXPORT_SYMBOL_GPL(mt7615_sta_ps);
469
470 static u16
mt7615_mac_tx_rate_val(struct mt7615_dev * dev,struct mt76_phy * mphy,const struct ieee80211_tx_rate * rate,bool stbc,u8 * bw)471 mt7615_mac_tx_rate_val(struct mt7615_dev *dev,
472 struct mt76_phy *mphy,
473 const struct ieee80211_tx_rate *rate,
474 bool stbc, u8 *bw)
475 {
476 u8 phy, nss, rate_idx;
477 u16 rateval = 0;
478
479 *bw = 0;
480
481 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
482 rate_idx = ieee80211_rate_get_vht_mcs(rate);
483 nss = ieee80211_rate_get_vht_nss(rate);
484 phy = MT_PHY_TYPE_VHT;
485 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
486 *bw = 1;
487 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
488 *bw = 2;
489 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
490 *bw = 3;
491 } else if (rate->flags & IEEE80211_TX_RC_MCS) {
492 rate_idx = rate->idx;
493 nss = 1 + (rate->idx >> 3);
494 phy = MT_PHY_TYPE_HT;
495 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
496 phy = MT_PHY_TYPE_HT_GF;
497 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
498 *bw = 1;
499 } else {
500 const struct ieee80211_rate *r;
501 int band = mphy->chandef.chan->band;
502 u16 val;
503
504 nss = 1;
505 r = &mphy->hw->wiphy->bands[band]->bitrates[rate->idx];
506 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
507 val = r->hw_value_short;
508 else
509 val = r->hw_value;
510
511 phy = val >> 8;
512 rate_idx = val & 0xff;
513 }
514
515 if (stbc && nss == 1) {
516 nss++;
517 rateval |= MT_TX_RATE_STBC;
518 }
519
520 rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
521 FIELD_PREP(MT_TX_RATE_MODE, phy) |
522 FIELD_PREP(MT_TX_RATE_NSS, nss - 1));
523
524 return rateval;
525 }
526
mt7615_mac_write_txwi(struct mt7615_dev * dev,__le32 * txwi,struct sk_buff * skb,struct mt76_wcid * wcid,struct ieee80211_sta * sta,int pid,struct ieee80211_key_conf * key,bool beacon)527 int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi,
528 struct sk_buff *skb, struct mt76_wcid *wcid,
529 struct ieee80211_sta *sta, int pid,
530 struct ieee80211_key_conf *key, bool beacon)
531 {
532 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
533 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0;
534 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
535 struct ieee80211_tx_rate *rate = &info->control.rates[0];
536 bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY;
537 bool multicast = is_multicast_ether_addr(hdr->addr1);
538 struct ieee80211_vif *vif = info->control.vif;
539 bool is_mmio = mt76_is_mmio(&dev->mt76);
540 u32 val, sz_txd = is_mmio ? MT_TXD_SIZE : MT_USB_TXD_SIZE;
541 struct mt76_phy *mphy = &dev->mphy;
542 __le16 fc = hdr->frame_control;
543 int tx_count = 8;
544 u16 seqno = 0;
545
546 if (vif) {
547 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
548
549 omac_idx = mvif->omac_idx;
550 wmm_idx = mvif->wmm_idx;
551 }
552
553 if (sta) {
554 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
555
556 tx_count = msta->rate_count;
557 }
558
559 if (ext_phy && dev->mt76.phy2)
560 mphy = dev->mt76.phy2;
561
562 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
563 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
564
565 if (beacon) {
566 p_fmt = MT_TX_TYPE_FW;
567 q_idx = ext_phy ? MT_LMAC_BCN1 : MT_LMAC_BCN0;
568 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) {
569 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF;
570 q_idx = ext_phy ? MT_LMAC_ALTX1 : MT_LMAC_ALTX0;
571 } else {
572 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF;
573 q_idx = wmm_idx * MT7615_MAX_WMM_SETS +
574 mt7615_lmac_mapping(dev, skb_get_queue_mapping(skb));
575 }
576
577 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) |
578 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) |
579 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
580 txwi[0] = cpu_to_le32(val);
581
582 val = MT_TXD1_LONG_FORMAT |
583 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
584 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
585 FIELD_PREP(MT_TXD1_HDR_INFO,
586 ieee80211_get_hdrlen_from_skb(skb) / 2) |
587 FIELD_PREP(MT_TXD1_TID,
588 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
589 FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) |
590 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
591 txwi[1] = cpu_to_le32(val);
592
593 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
594 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
595 FIELD_PREP(MT_TXD2_MULTICAST, multicast);
596 if (key) {
597 if (multicast && ieee80211_is_robust_mgmt_frame(skb) &&
598 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) {
599 val |= MT_TXD2_BIP;
600 txwi[3] = 0;
601 } else {
602 txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME);
603 }
604 } else {
605 txwi[3] = 0;
606 }
607 txwi[2] = cpu_to_le32(val);
608
609 if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
610 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
611
612 txwi[4] = 0;
613 txwi[6] = 0;
614
615 if (rate->idx >= 0 && rate->count &&
616 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
617 bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
618 u8 bw;
619 u16 rateval = mt7615_mac_tx_rate_val(dev, mphy, rate, stbc,
620 &bw);
621
622 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
623
624 val = MT_TXD6_FIXED_BW |
625 FIELD_PREP(MT_TXD6_BW, bw) |
626 FIELD_PREP(MT_TXD6_TX_RATE, rateval);
627 txwi[6] |= cpu_to_le32(val);
628
629 if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
630 txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
631
632 if (info->flags & IEEE80211_TX_CTL_LDPC)
633 txwi[6] |= cpu_to_le32(MT_TXD6_LDPC);
634
635 if (!(rate->flags & (IEEE80211_TX_RC_MCS |
636 IEEE80211_TX_RC_VHT_MCS)))
637 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
638
639 tx_count = rate->count;
640 }
641
642 if (!ieee80211_is_beacon(fc)) {
643 struct ieee80211_hw *hw = mt76_hw(dev);
644
645 val = MT_TXD5_TX_STATUS_HOST | FIELD_PREP(MT_TXD5_PID, pid);
646 if (!ieee80211_hw_check(hw, SUPPORTS_PS))
647 val |= MT_TXD5_SW_POWER_MGMT;
648 txwi[5] = cpu_to_le32(val);
649 } else {
650 txwi[5] = 0;
651 /* use maximum tx count for beacons */
652 tx_count = 0x1f;
653 }
654
655 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
656 if (info->flags & IEEE80211_TX_CTL_INJECTED) {
657 seqno = le16_to_cpu(hdr->seq_ctrl);
658
659 if (ieee80211_is_back_req(hdr->frame_control)) {
660 struct ieee80211_bar *bar;
661
662 bar = (struct ieee80211_bar *)skb->data;
663 seqno = le16_to_cpu(bar->start_seq_num);
664 }
665
666 val |= MT_TXD3_SN_VALID |
667 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno));
668 }
669
670 txwi[3] |= cpu_to_le32(val);
671
672 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
673 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK);
674
675 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
676 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype) |
677 FIELD_PREP(MT_TXD7_SPE_IDX, 0x18);
678 txwi[7] = cpu_to_le32(val);
679 if (!is_mmio) {
680 val = FIELD_PREP(MT_TXD8_L_TYPE, fc_type) |
681 FIELD_PREP(MT_TXD8_L_SUB_TYPE, fc_stype);
682 txwi[8] = cpu_to_le32(val);
683 }
684
685 return 0;
686 }
687 EXPORT_SYMBOL_GPL(mt7615_mac_write_txwi);
688
689 static void
mt7615_txp_skb_unmap_fw(struct mt76_dev * dev,struct mt7615_fw_txp * txp)690 mt7615_txp_skb_unmap_fw(struct mt76_dev *dev, struct mt7615_fw_txp *txp)
691 {
692 int i;
693
694 for (i = 0; i < txp->nbuf; i++)
695 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]),
696 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
697 }
698
699 static void
mt7615_txp_skb_unmap_hw(struct mt76_dev * dev,struct mt7615_hw_txp * txp)700 mt7615_txp_skb_unmap_hw(struct mt76_dev *dev, struct mt7615_hw_txp *txp)
701 {
702 u32 last_mask;
703 int i;
704
705 last_mask = is_mt7663(dev) ? MT_TXD_LEN_LAST : MT_TXD_LEN_MSDU_LAST;
706
707 for (i = 0; i < ARRAY_SIZE(txp->ptr); i++) {
708 struct mt7615_txp_ptr *ptr = &txp->ptr[i];
709 bool last;
710 u16 len;
711
712 len = le16_to_cpu(ptr->len0);
713 last = len & last_mask;
714 len &= MT_TXD_LEN_MASK;
715 dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf0), len,
716 DMA_TO_DEVICE);
717 if (last)
718 break;
719
720 len = le16_to_cpu(ptr->len1);
721 last = len & last_mask;
722 len &= MT_TXD_LEN_MASK;
723 dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf1), len,
724 DMA_TO_DEVICE);
725 if (last)
726 break;
727 }
728 }
729
mt7615_txp_skb_unmap(struct mt76_dev * dev,struct mt76_txwi_cache * t)730 void mt7615_txp_skb_unmap(struct mt76_dev *dev,
731 struct mt76_txwi_cache *t)
732 {
733 struct mt7615_txp_common *txp;
734
735 txp = mt7615_txwi_to_txp(dev, t);
736 if (is_mt7615(dev))
737 mt7615_txp_skb_unmap_fw(dev, &txp->fw);
738 else
739 mt7615_txp_skb_unmap_hw(dev, &txp->hw);
740 }
741 EXPORT_SYMBOL_GPL(mt7615_txp_skb_unmap);
742
mt7615_mac_wtbl_update(struct mt7615_dev * dev,int idx,u32 mask)743 bool mt7615_mac_wtbl_update(struct mt7615_dev *dev, int idx, u32 mask)
744 {
745 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
746 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
747
748 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
749 0, 5000);
750 }
751
mt7615_mac_sta_poll(struct mt7615_dev * dev)752 void mt7615_mac_sta_poll(struct mt7615_dev *dev)
753 {
754 static const u8 ac_to_tid[4] = {
755 [IEEE80211_AC_BE] = 0,
756 [IEEE80211_AC_BK] = 1,
757 [IEEE80211_AC_VI] = 4,
758 [IEEE80211_AC_VO] = 6
759 };
760 static const u8 hw_queue_map[] = {
761 [IEEE80211_AC_BK] = 0,
762 [IEEE80211_AC_BE] = 1,
763 [IEEE80211_AC_VI] = 2,
764 [IEEE80211_AC_VO] = 3,
765 };
766 struct ieee80211_sta *sta;
767 struct mt7615_sta *msta;
768 u32 addr, tx_time[4], rx_time[4];
769 struct list_head sta_poll_list;
770 int i;
771
772 INIT_LIST_HEAD(&sta_poll_list);
773 spin_lock_bh(&dev->sta_poll_lock);
774 list_splice_init(&dev->sta_poll_list, &sta_poll_list);
775 spin_unlock_bh(&dev->sta_poll_lock);
776
777 while (!list_empty(&sta_poll_list)) {
778 bool clear = false;
779
780 msta = list_first_entry(&sta_poll_list, struct mt7615_sta,
781 poll_list);
782 list_del_init(&msta->poll_list);
783
784 addr = mt7615_mac_wtbl_addr(dev, msta->wcid.idx) + 19 * 4;
785
786 for (i = 0; i < 4; i++, addr += 8) {
787 u32 tx_last = msta->airtime_ac[i];
788 u32 rx_last = msta->airtime_ac[i + 4];
789
790 msta->airtime_ac[i] = mt76_rr(dev, addr);
791 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4);
792 tx_time[i] = msta->airtime_ac[i] - tx_last;
793 rx_time[i] = msta->airtime_ac[i + 4] - rx_last;
794
795 if ((tx_last | rx_last) & BIT(30))
796 clear = true;
797 }
798
799 if (clear) {
800 mt7615_mac_wtbl_update(dev, msta->wcid.idx,
801 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
802 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
803 }
804
805 if (!msta->wcid.sta)
806 continue;
807
808 sta = container_of((void *)msta, struct ieee80211_sta,
809 drv_priv);
810 for (i = 0; i < 4; i++) {
811 u32 tx_cur = tx_time[i];
812 u32 rx_cur = rx_time[hw_queue_map[i]];
813 u8 tid = ac_to_tid[i];
814
815 if (!tx_cur && !rx_cur)
816 continue;
817
818 ieee80211_sta_register_airtime(sta, tid, tx_cur,
819 rx_cur);
820 }
821 }
822 }
823 EXPORT_SYMBOL_GPL(mt7615_mac_sta_poll);
824
825 static void
mt7615_mac_update_rate_desc(struct mt7615_phy * phy,struct mt7615_sta * sta,struct ieee80211_tx_rate * probe_rate,struct ieee80211_tx_rate * rates,struct mt7615_rate_desc * rd)826 mt7615_mac_update_rate_desc(struct mt7615_phy *phy, struct mt7615_sta *sta,
827 struct ieee80211_tx_rate *probe_rate,
828 struct ieee80211_tx_rate *rates,
829 struct mt7615_rate_desc *rd)
830 {
831 struct mt7615_dev *dev = phy->dev;
832 struct mt76_phy *mphy = phy->mt76;
833 struct ieee80211_tx_rate *ref;
834 bool rateset, stbc = false;
835 int n_rates = sta->n_rates;
836 u8 bw, bw_prev;
837 int i, j;
838
839 for (i = n_rates; i < 4; i++)
840 rates[i] = rates[n_rates - 1];
841
842 rateset = !(sta->rate_set_tsf & BIT(0));
843 memcpy(sta->rateset[rateset].rates, rates,
844 sizeof(sta->rateset[rateset].rates));
845 if (probe_rate) {
846 sta->rateset[rateset].probe_rate = *probe_rate;
847 ref = &sta->rateset[rateset].probe_rate;
848 } else {
849 sta->rateset[rateset].probe_rate.idx = -1;
850 ref = &sta->rateset[rateset].rates[0];
851 }
852
853 rates = sta->rateset[rateset].rates;
854 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) {
855 /*
856 * We don't support switching between short and long GI
857 * within the rate set. For accurate tx status reporting, we
858 * need to make sure that flags match.
859 * For improved performance, avoid duplicate entries by
860 * decrementing the MCS index if necessary
861 */
862 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI)
863 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI;
864
865 for (j = 0; j < i; j++) {
866 if (rates[i].idx != rates[j].idx)
867 continue;
868 if ((rates[i].flags ^ rates[j].flags) &
869 (IEEE80211_TX_RC_40_MHZ_WIDTH |
870 IEEE80211_TX_RC_80_MHZ_WIDTH |
871 IEEE80211_TX_RC_160_MHZ_WIDTH))
872 continue;
873
874 if (!rates[i].idx)
875 continue;
876
877 rates[i].idx--;
878 }
879 }
880
881 rd->val[0] = mt7615_mac_tx_rate_val(dev, mphy, &rates[0], stbc, &bw);
882 bw_prev = bw;
883
884 if (probe_rate) {
885 rd->probe_val = mt7615_mac_tx_rate_val(dev, mphy, probe_rate,
886 stbc, &bw);
887 if (bw)
888 rd->bw_idx = 1;
889 else
890 bw_prev = 0;
891 } else {
892 rd->probe_val = rd->val[0];
893 }
894
895 rd->val[1] = mt7615_mac_tx_rate_val(dev, mphy, &rates[1], stbc, &bw);
896 if (bw_prev) {
897 rd->bw_idx = 3;
898 bw_prev = bw;
899 }
900
901 rd->val[2] = mt7615_mac_tx_rate_val(dev, mphy, &rates[2], stbc, &bw);
902 if (bw_prev) {
903 rd->bw_idx = 5;
904 bw_prev = bw;
905 }
906
907 rd->val[3] = mt7615_mac_tx_rate_val(dev, mphy, &rates[3], stbc, &bw);
908 if (bw_prev)
909 rd->bw_idx = 7;
910
911 rd->rateset = rateset;
912 rd->bw = bw;
913 }
914
915 static int
mt7615_mac_queue_rate_update(struct mt7615_phy * phy,struct mt7615_sta * sta,struct ieee80211_tx_rate * probe_rate,struct ieee80211_tx_rate * rates)916 mt7615_mac_queue_rate_update(struct mt7615_phy *phy, struct mt7615_sta *sta,
917 struct ieee80211_tx_rate *probe_rate,
918 struct ieee80211_tx_rate *rates)
919 {
920 struct mt7615_dev *dev = phy->dev;
921 struct mt7615_wtbl_desc *wd;
922
923 if (work_pending(&dev->wtbl_work))
924 return -EBUSY;
925
926 wd = kzalloc(sizeof(*wd), GFP_ATOMIC);
927 if (!wd)
928 return -ENOMEM;
929
930 wd->type = MT7615_WTBL_RATE_DESC;
931 wd->sta = sta;
932
933 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates,
934 &wd->rate);
935 list_add_tail(&wd->node, &dev->wd_head);
936 queue_work(dev->mt76.wq, &dev->wtbl_work);
937
938 return 0;
939 }
940
mt7615_mac_get_sta_tid_sn(struct mt7615_dev * dev,int wcid,u8 tid)941 u32 mt7615_mac_get_sta_tid_sn(struct mt7615_dev *dev, int wcid, u8 tid)
942 {
943 u32 addr, val, val2;
944 u8 offset;
945
946 addr = mt7615_mac_wtbl_addr(dev, wcid) + 11 * 4;
947
948 offset = tid * 12;
949 addr += 4 * (offset / 32);
950 offset %= 32;
951
952 val = mt76_rr(dev, addr);
953 val >>= offset;
954
955 if (offset > 20) {
956 addr += 4;
957 val2 = mt76_rr(dev, addr);
958 val |= val2 << (32 - offset);
959 }
960
961 return val & GENMASK(11, 0);
962 }
963
mt7615_mac_set_rates(struct mt7615_phy * phy,struct mt7615_sta * sta,struct ieee80211_tx_rate * probe_rate,struct ieee80211_tx_rate * rates)964 void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta,
965 struct ieee80211_tx_rate *probe_rate,
966 struct ieee80211_tx_rate *rates)
967 {
968 int wcid = sta->wcid.idx, n_rates = sta->n_rates;
969 struct mt7615_dev *dev = phy->dev;
970 struct mt7615_rate_desc rd;
971 u32 w5, w27, addr;
972
973 if (!mt76_is_mmio(&dev->mt76)) {
974 mt7615_mac_queue_rate_update(phy, sta, probe_rate, rates);
975 return;
976 }
977
978 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
979 return;
980
981 memset(&rd, 0, sizeof(struct mt7615_rate_desc));
982 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, &rd);
983
984 addr = mt7615_mac_wtbl_addr(dev, wcid);
985 w27 = mt76_rr(dev, addr + 27 * 4);
986 w27 &= ~MT_WTBL_W27_CC_BW_SEL;
987 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rd.bw);
988
989 w5 = mt76_rr(dev, addr + 5 * 4);
990 w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE |
991 MT_WTBL_W5_MPDU_OK_COUNT |
992 MT_WTBL_W5_MPDU_FAIL_COUNT |
993 MT_WTBL_W5_RATE_IDX);
994 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rd.bw) |
995 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE,
996 rd.bw_idx ? rd.bw_idx - 1 : 7);
997
998 mt76_wr(dev, MT_WTBL_RIUCR0, w5);
999
1000 mt76_wr(dev, MT_WTBL_RIUCR1,
1001 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rd.probe_val) |
1002 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rd.val[0]) |
1003 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rd.val[1]));
1004
1005 mt76_wr(dev, MT_WTBL_RIUCR2,
1006 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rd.val[1] >> 8) |
1007 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rd.val[1]) |
1008 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rd.val[2]) |
1009 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rd.val[2]));
1010
1011 mt76_wr(dev, MT_WTBL_RIUCR3,
1012 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, rd.val[2] >> 4) |
1013 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, rd.val[3]) |
1014 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, rd.val[3]));
1015
1016 mt76_wr(dev, MT_WTBL_UPDATE,
1017 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
1018 MT_WTBL_UPDATE_RATE_UPDATE |
1019 MT_WTBL_UPDATE_TX_COUNT_CLEAR);
1020
1021 mt76_wr(dev, addr + 27 * 4, w27);
1022
1023 mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */
1024 sta->rate_set_tsf = mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0);
1025 sta->rate_set_tsf |= rd.rateset;
1026
1027 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
1028 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
1029
1030 sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates;
1031 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
1032 sta->rate_probe = !!probe_rate;
1033 }
1034 EXPORT_SYMBOL_GPL(mt7615_mac_set_rates);
1035
mt7615_mac_wtbl_update_key(struct mt7615_dev * dev,struct mt76_wcid * wcid,u8 * key,u8 keylen,enum mt7615_cipher_type cipher,enum set_key_cmd cmd)1036 int mt7615_mac_wtbl_update_key(struct mt7615_dev *dev,
1037 struct mt76_wcid *wcid,
1038 u8 *key, u8 keylen,
1039 enum mt7615_cipher_type cipher,
1040 enum set_key_cmd cmd)
1041 {
1042 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx) + 30 * 4;
1043 u8 data[32] = {};
1044
1045 if (keylen > sizeof(data))
1046 return -EINVAL;
1047
1048 mt76_rr_copy(dev, addr, data, sizeof(data));
1049 if (cmd == SET_KEY) {
1050 if (cipher == MT_CIPHER_TKIP) {
1051 /* Rx/Tx MIC keys are swapped */
1052 memcpy(data, key, 16);
1053 memcpy(data + 16, key + 24, 8);
1054 memcpy(data + 24, key + 16, 8);
1055 } else {
1056 if (cipher != MT_CIPHER_BIP_CMAC_128 && wcid->cipher)
1057 memmove(data + 16, data, 16);
1058 if (cipher != MT_CIPHER_BIP_CMAC_128 || !wcid->cipher)
1059 memcpy(data, key, keylen);
1060 else if (cipher == MT_CIPHER_BIP_CMAC_128)
1061 memcpy(data + 16, key, 16);
1062 }
1063 } else {
1064 if (wcid->cipher & ~BIT(cipher)) {
1065 if (cipher != MT_CIPHER_BIP_CMAC_128)
1066 memmove(data, data + 16, 16);
1067 memset(data + 16, 0, 16);
1068 } else {
1069 memset(data, 0, sizeof(data));
1070 }
1071 }
1072 mt76_wr_copy(dev, addr, data, sizeof(data));
1073
1074 return 0;
1075 }
1076 EXPORT_SYMBOL_GPL(mt7615_mac_wtbl_update_key);
1077
mt7615_mac_wtbl_update_pk(struct mt7615_dev * dev,struct mt76_wcid * wcid,enum mt7615_cipher_type cipher,int keyidx,enum set_key_cmd cmd)1078 int mt7615_mac_wtbl_update_pk(struct mt7615_dev *dev,
1079 struct mt76_wcid *wcid,
1080 enum mt7615_cipher_type cipher,
1081 int keyidx, enum set_key_cmd cmd)
1082 {
1083 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx), w0, w1;
1084
1085 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
1086 return -ETIMEDOUT;
1087
1088 w0 = mt76_rr(dev, addr);
1089 w1 = mt76_rr(dev, addr + 4);
1090 if (cmd == SET_KEY) {
1091 w0 |= MT_WTBL_W0_RX_KEY_VALID |
1092 FIELD_PREP(MT_WTBL_W0_RX_IK_VALID,
1093 cipher == MT_CIPHER_BIP_CMAC_128);
1094 if (cipher != MT_CIPHER_BIP_CMAC_128 ||
1095 !wcid->cipher)
1096 w0 |= FIELD_PREP(MT_WTBL_W0_KEY_IDX, keyidx);
1097 } else {
1098 if (!(wcid->cipher & ~BIT(cipher)))
1099 w0 &= ~(MT_WTBL_W0_RX_KEY_VALID |
1100 MT_WTBL_W0_KEY_IDX);
1101 if (cipher == MT_CIPHER_BIP_CMAC_128)
1102 w0 &= ~MT_WTBL_W0_RX_IK_VALID;
1103 }
1104 mt76_wr(dev, MT_WTBL_RICR0, w0);
1105 mt76_wr(dev, MT_WTBL_RICR1, w1);
1106
1107 if (!mt7615_mac_wtbl_update(dev, wcid->idx,
1108 MT_WTBL_UPDATE_RXINFO_UPDATE))
1109 return -ETIMEDOUT;
1110
1111 return 0;
1112 }
1113 EXPORT_SYMBOL_GPL(mt7615_mac_wtbl_update_pk);
1114
mt7615_mac_wtbl_update_cipher(struct mt7615_dev * dev,struct mt76_wcid * wcid,enum mt7615_cipher_type cipher,enum set_key_cmd cmd)1115 void mt7615_mac_wtbl_update_cipher(struct mt7615_dev *dev,
1116 struct mt76_wcid *wcid,
1117 enum mt7615_cipher_type cipher,
1118 enum set_key_cmd cmd)
1119 {
1120 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx);
1121
1122 if (cmd == SET_KEY) {
1123 if (cipher != MT_CIPHER_BIP_CMAC_128 || !wcid->cipher)
1124 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE,
1125 FIELD_PREP(MT_WTBL_W2_KEY_TYPE, cipher));
1126 } else {
1127 if (cipher != MT_CIPHER_BIP_CMAC_128 &&
1128 wcid->cipher & BIT(MT_CIPHER_BIP_CMAC_128))
1129 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE,
1130 FIELD_PREP(MT_WTBL_W2_KEY_TYPE,
1131 MT_CIPHER_BIP_CMAC_128));
1132 else if (!(wcid->cipher & ~BIT(cipher)))
1133 mt76_clear(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE);
1134 }
1135 }
1136 EXPORT_SYMBOL_GPL(mt7615_mac_wtbl_update_cipher);
1137
mt7615_mac_wtbl_set_key(struct mt7615_dev * dev,struct mt76_wcid * wcid,struct ieee80211_key_conf * key,enum set_key_cmd cmd)1138 int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev,
1139 struct mt76_wcid *wcid,
1140 struct ieee80211_key_conf *key,
1141 enum set_key_cmd cmd)
1142 {
1143 enum mt7615_cipher_type cipher;
1144 int err;
1145
1146 cipher = mt7615_mac_get_cipher(key->cipher);
1147 if (cipher == MT_CIPHER_NONE)
1148 return -EOPNOTSUPP;
1149
1150 spin_lock_bh(&dev->mt76.lock);
1151
1152 mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cmd);
1153 err = mt7615_mac_wtbl_update_key(dev, wcid, key->key, key->keylen,
1154 cipher, cmd);
1155 if (err < 0)
1156 goto out;
1157
1158 err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, key->keyidx,
1159 cmd);
1160 if (err < 0)
1161 goto out;
1162
1163 if (cmd == SET_KEY)
1164 wcid->cipher |= BIT(cipher);
1165 else
1166 wcid->cipher &= ~BIT(cipher);
1167
1168 out:
1169 spin_unlock_bh(&dev->mt76.lock);
1170
1171 return err;
1172 }
1173
mt7615_fill_txs(struct mt7615_dev * dev,struct mt7615_sta * sta,struct ieee80211_tx_info * info,__le32 * txs_data)1174 static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta,
1175 struct ieee80211_tx_info *info, __le32 *txs_data)
1176 {
1177 struct ieee80211_supported_band *sband;
1178 struct mt7615_rate_set *rs;
1179 struct mt76_phy *mphy;
1180 int first_idx = 0, last_idx;
1181 int i, idx, count;
1182 bool fixed_rate, ack_timeout;
1183 bool ampdu, cck = false;
1184 bool rs_idx;
1185 u32 rate_set_tsf;
1186 u32 final_rate, final_rate_flags, final_nss, txs;
1187
1188 txs = le32_to_cpu(txs_data[1]);
1189 ampdu = txs & MT_TXS1_AMPDU;
1190
1191 txs = le32_to_cpu(txs_data[3]);
1192 count = FIELD_GET(MT_TXS3_TX_COUNT, txs);
1193 last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs);
1194
1195 txs = le32_to_cpu(txs_data[0]);
1196 fixed_rate = txs & MT_TXS0_FIXED_RATE;
1197 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
1198 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
1199
1200 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
1201 return false;
1202
1203 if (txs & MT_TXS0_QUEUE_TIMEOUT)
1204 return false;
1205
1206 if (!ack_timeout)
1207 info->flags |= IEEE80211_TX_STAT_ACK;
1208
1209 info->status.ampdu_len = 1;
1210 info->status.ampdu_ack_len = !!(info->flags &
1211 IEEE80211_TX_STAT_ACK);
1212
1213 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
1214 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
1215
1216 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7615_RATE_RETRY);
1217
1218 if (fixed_rate) {
1219 info->status.rates[0].count = count;
1220 i = 0;
1221 goto out;
1222 }
1223
1224 rate_set_tsf = READ_ONCE(sta->rate_set_tsf);
1225 rs_idx = !((u32)(FIELD_GET(MT_TXS4_F0_TIMESTAMP, le32_to_cpu(txs_data[4])) -
1226 rate_set_tsf) < 1000000);
1227 rs_idx ^= rate_set_tsf & BIT(0);
1228 rs = &sta->rateset[rs_idx];
1229
1230 if (!first_idx && rs->probe_rate.idx >= 0) {
1231 info->status.rates[0] = rs->probe_rate;
1232
1233 spin_lock_bh(&dev->mt76.lock);
1234 if (sta->rate_probe) {
1235 struct mt7615_phy *phy = &dev->phy;
1236
1237 if (sta->wcid.ext_phy && dev->mt76.phy2)
1238 phy = dev->mt76.phy2->priv;
1239
1240 mt7615_mac_set_rates(phy, sta, NULL, sta->rates);
1241 }
1242 spin_unlock_bh(&dev->mt76.lock);
1243 } else {
1244 info->status.rates[0] = rs->rates[first_idx / 2];
1245 }
1246 info->status.rates[0].count = 0;
1247
1248 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) {
1249 struct ieee80211_tx_rate *cur_rate;
1250 int cur_count;
1251
1252 cur_rate = &rs->rates[idx / 2];
1253 cur_count = min_t(int, MT7615_RATE_RETRY, count);
1254 count -= cur_count;
1255
1256 if (idx && (cur_rate->idx != info->status.rates[i].idx ||
1257 cur_rate->flags != info->status.rates[i].flags)) {
1258 i++;
1259 if (i == ARRAY_SIZE(info->status.rates)) {
1260 i--;
1261 break;
1262 }
1263
1264 info->status.rates[i] = *cur_rate;
1265 info->status.rates[i].count = 0;
1266 }
1267
1268 info->status.rates[i].count += cur_count;
1269 }
1270
1271 out:
1272 final_rate_flags = info->status.rates[i].flags;
1273
1274 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
1275 case MT_PHY_TYPE_CCK:
1276 cck = true;
1277 fallthrough;
1278 case MT_PHY_TYPE_OFDM:
1279 mphy = &dev->mphy;
1280 if (sta->wcid.ext_phy && dev->mt76.phy2)
1281 mphy = dev->mt76.phy2;
1282
1283 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
1284 sband = &mphy->sband_5g.sband;
1285 else
1286 sband = &mphy->sband_2g.sband;
1287 final_rate &= MT_TX_RATE_IDX;
1288 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
1289 cck);
1290 final_rate_flags = 0;
1291 break;
1292 case MT_PHY_TYPE_HT_GF:
1293 case MT_PHY_TYPE_HT:
1294 final_rate_flags |= IEEE80211_TX_RC_MCS;
1295 final_rate &= MT_TX_RATE_IDX;
1296 if (final_rate > 31)
1297 return false;
1298 break;
1299 case MT_PHY_TYPE_VHT:
1300 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate);
1301
1302 if ((final_rate & MT_TX_RATE_STBC) && final_nss)
1303 final_nss--;
1304
1305 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS;
1306 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4);
1307 break;
1308 default:
1309 return false;
1310 }
1311
1312 info->status.rates[i].idx = final_rate;
1313 info->status.rates[i].flags = final_rate_flags;
1314
1315 return true;
1316 }
1317
mt7615_mac_add_txs_skb(struct mt7615_dev * dev,struct mt7615_sta * sta,int pid,__le32 * txs_data)1318 static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev,
1319 struct mt7615_sta *sta, int pid,
1320 __le32 *txs_data)
1321 {
1322 struct mt76_dev *mdev = &dev->mt76;
1323 struct sk_buff_head list;
1324 struct sk_buff *skb;
1325
1326 if (pid < MT_PACKET_ID_FIRST)
1327 return false;
1328
1329 trace_mac_txdone(mdev, sta->wcid.idx, pid);
1330
1331 mt76_tx_status_lock(mdev, &list);
1332 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
1333 if (skb) {
1334 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1335
1336 if (!mt7615_fill_txs(dev, sta, info, txs_data)) {
1337 ieee80211_tx_info_clear_status(info);
1338 info->status.rates[0].idx = -1;
1339 }
1340
1341 mt76_tx_status_skb_done(mdev, skb, &list);
1342 }
1343 mt76_tx_status_unlock(mdev, &list);
1344
1345 return !!skb;
1346 }
1347
mt7615_mac_add_txs(struct mt7615_dev * dev,void * data)1348 static void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data)
1349 {
1350 struct ieee80211_tx_info info = {};
1351 struct ieee80211_sta *sta = NULL;
1352 struct mt7615_sta *msta = NULL;
1353 struct mt76_wcid *wcid;
1354 struct mt76_phy *mphy = &dev->mt76.phy;
1355 __le32 *txs_data = data;
1356 u32 txs;
1357 u8 wcidx;
1358 u8 pid;
1359
1360 txs = le32_to_cpu(txs_data[0]);
1361 pid = FIELD_GET(MT_TXS0_PID, txs);
1362 txs = le32_to_cpu(txs_data[2]);
1363 wcidx = FIELD_GET(MT_TXS2_WCID, txs);
1364
1365 if (pid == MT_PACKET_ID_NO_ACK)
1366 return;
1367
1368 if (wcidx >= MT7615_WTBL_SIZE)
1369 return;
1370
1371 rcu_read_lock();
1372
1373 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1374 if (!wcid)
1375 goto out;
1376
1377 msta = container_of(wcid, struct mt7615_sta, wcid);
1378 sta = wcid_to_sta(wcid);
1379
1380 spin_lock_bh(&dev->sta_poll_lock);
1381 if (list_empty(&msta->poll_list))
1382 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1383 spin_unlock_bh(&dev->sta_poll_lock);
1384
1385 if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data))
1386 goto out;
1387
1388 if (wcidx >= MT7615_WTBL_STA || !sta)
1389 goto out;
1390
1391 if (wcid->ext_phy && dev->mt76.phy2)
1392 mphy = dev->mt76.phy2;
1393
1394 if (mt7615_fill_txs(dev, msta, &info, txs_data))
1395 ieee80211_tx_status_noskb(mphy->hw, sta, &info);
1396
1397 out:
1398 rcu_read_unlock();
1399 }
1400
1401 static void
mt7615_mac_tx_free_token(struct mt7615_dev * dev,u16 token)1402 mt7615_mac_tx_free_token(struct mt7615_dev *dev, u16 token)
1403 {
1404 struct mt76_dev *mdev = &dev->mt76;
1405 struct mt76_txwi_cache *txwi;
1406 __le32 *txwi_data;
1407 u32 val;
1408 u8 wcid;
1409
1410 trace_mac_tx_free(dev, token);
1411
1412 spin_lock_bh(&dev->token_lock);
1413 txwi = idr_remove(&dev->token, token);
1414 spin_unlock_bh(&dev->token_lock);
1415
1416 if (!txwi)
1417 return;
1418
1419 txwi_data = (__le32 *)mt76_get_txwi_ptr(mdev, txwi);
1420 val = le32_to_cpu(txwi_data[1]);
1421 wcid = FIELD_GET(MT_TXD1_WLAN_IDX, val);
1422
1423 mt7615_txp_skb_unmap(mdev, txwi);
1424 if (txwi->skb) {
1425 mt76_tx_complete_skb(mdev, wcid, txwi->skb);
1426 txwi->skb = NULL;
1427 }
1428
1429 mt76_put_txwi(mdev, txwi);
1430 }
1431
mt7615_mac_tx_free(struct mt7615_dev * dev,struct sk_buff * skb)1432 static void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb)
1433 {
1434 struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data;
1435 u8 i, count;
1436
1437 mt76_queue_tx_cleanup(dev, MT_TXQ_PSD, false);
1438 if (is_mt7615(&dev->mt76)) {
1439 mt76_queue_tx_cleanup(dev, MT_TXQ_BE, false);
1440 } else {
1441 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1442 mt76_queue_tx_cleanup(dev, i, false);
1443 }
1444
1445 count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl));
1446 if (is_mt7615(&dev->mt76)) {
1447 __le16 *token = &free->token[0];
1448
1449 for (i = 0; i < count; i++)
1450 mt7615_mac_tx_free_token(dev, le16_to_cpu(token[i]));
1451 } else {
1452 __le32 *token = (__le32 *)&free->token[0];
1453
1454 for (i = 0; i < count; i++)
1455 mt7615_mac_tx_free_token(dev, le32_to_cpu(token[i]));
1456 }
1457
1458 dev_kfree_skb(skb);
1459
1460 if (test_bit(MT76_STATE_PM, &dev->phy.mt76->state))
1461 return;
1462
1463 rcu_read_lock();
1464 mt7615_mac_sta_poll(dev);
1465 rcu_read_unlock();
1466
1467 mt7615_pm_power_save_sched(dev);
1468 mt76_worker_schedule(&dev->mt76.tx_worker);
1469 }
1470
mt7615_queue_rx_skb(struct mt76_dev * mdev,enum mt76_rxq_id q,struct sk_buff * skb)1471 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1472 struct sk_buff *skb)
1473 {
1474 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
1475 __le32 *rxd = (__le32 *)skb->data;
1476 __le32 *end = (__le32 *)&skb->data[skb->len];
1477 enum rx_pkt_type type;
1478 u16 flag;
1479
1480 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));
1481 flag = FIELD_GET(MT_RXD0_PKT_FLAG, le32_to_cpu(rxd[0]));
1482 if (type == PKT_TYPE_RX_EVENT && flag == 0x1)
1483 type = PKT_TYPE_NORMAL_MCU;
1484
1485 switch (type) {
1486 case PKT_TYPE_TXS:
1487 for (rxd++; rxd + 7 <= end; rxd += 7)
1488 mt7615_mac_add_txs(dev, rxd);
1489 dev_kfree_skb(skb);
1490 break;
1491 case PKT_TYPE_TXRX_NOTIFY:
1492 mt7615_mac_tx_free(dev, skb);
1493 break;
1494 case PKT_TYPE_RX_EVENT:
1495 mt7615_mcu_rx_event(dev, skb);
1496 break;
1497 case PKT_TYPE_NORMAL_MCU:
1498 case PKT_TYPE_NORMAL:
1499 if (!mt7615_mac_fill_rx(dev, skb)) {
1500 mt76_rx(&dev->mt76, q, skb);
1501 return;
1502 }
1503 fallthrough;
1504 default:
1505 dev_kfree_skb(skb);
1506 break;
1507 }
1508 }
1509 EXPORT_SYMBOL_GPL(mt7615_queue_rx_skb);
1510
1511 static void
mt7615_mac_set_sensitivity(struct mt7615_phy * phy,int val,bool ofdm)1512 mt7615_mac_set_sensitivity(struct mt7615_phy *phy, int val, bool ofdm)
1513 {
1514 struct mt7615_dev *dev = phy->dev;
1515 bool ext_phy = phy != &dev->phy;
1516
1517 if (is_mt7663(&dev->mt76)) {
1518 if (ofdm)
1519 mt76_rmw(dev, MT7663_WF_PHY_MIN_PRI_PWR(ext_phy),
1520 MT_WF_PHY_PD_OFDM_MASK(0),
1521 MT_WF_PHY_PD_OFDM(0, val));
1522 else
1523 mt76_rmw(dev, MT7663_WF_PHY_RXTD_CCK_PD(ext_phy),
1524 MT_WF_PHY_PD_CCK_MASK(ext_phy),
1525 MT_WF_PHY_PD_CCK(ext_phy, val));
1526 return;
1527 }
1528
1529 if (ofdm)
1530 mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy),
1531 MT_WF_PHY_PD_OFDM_MASK(ext_phy),
1532 MT_WF_PHY_PD_OFDM(ext_phy, val));
1533 else
1534 mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy),
1535 MT_WF_PHY_PD_CCK_MASK(ext_phy),
1536 MT_WF_PHY_PD_CCK(ext_phy, val));
1537 }
1538
1539 static void
mt7615_mac_set_default_sensitivity(struct mt7615_phy * phy)1540 mt7615_mac_set_default_sensitivity(struct mt7615_phy *phy)
1541 {
1542 /* ofdm */
1543 mt7615_mac_set_sensitivity(phy, 0x13c, true);
1544 /* cck */
1545 mt7615_mac_set_sensitivity(phy, 0x92, false);
1546
1547 phy->ofdm_sensitivity = -98;
1548 phy->cck_sensitivity = -110;
1549 phy->last_cca_adj = jiffies;
1550 }
1551
mt7615_mac_set_scs(struct mt7615_phy * phy,bool enable)1552 void mt7615_mac_set_scs(struct mt7615_phy *phy, bool enable)
1553 {
1554 struct mt7615_dev *dev = phy->dev;
1555 bool ext_phy = phy != &dev->phy;
1556 u32 reg, mask;
1557
1558 mt7615_mutex_acquire(dev);
1559
1560 if (phy->scs_en == enable)
1561 goto out;
1562
1563 if (is_mt7663(&dev->mt76)) {
1564 reg = MT7663_WF_PHY_MIN_PRI_PWR(ext_phy);
1565 mask = MT_WF_PHY_PD_BLK(0);
1566 } else {
1567 reg = MT_WF_PHY_MIN_PRI_PWR(ext_phy);
1568 mask = MT_WF_PHY_PD_BLK(ext_phy);
1569 }
1570
1571 if (enable) {
1572 mt76_set(dev, reg, mask);
1573 if (is_mt7622(&dev->mt76)) {
1574 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8);
1575 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7);
1576 }
1577 } else {
1578 mt76_clear(dev, reg, mask);
1579 }
1580
1581 mt7615_mac_set_default_sensitivity(phy);
1582 phy->scs_en = enable;
1583
1584 out:
1585 mt7615_mutex_release(dev);
1586 }
1587
mt7615_mac_enable_nf(struct mt7615_dev * dev,bool ext_phy)1588 void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy)
1589 {
1590 u32 rxtd, reg;
1591
1592 if (is_mt7663(&dev->mt76))
1593 reg = MT7663_WF_PHY_R0_PHYMUX_5;
1594 else
1595 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy);
1596
1597 if (ext_phy)
1598 rxtd = MT_WF_PHY_RXTD2(10);
1599 else
1600 rxtd = MT_WF_PHY_RXTD(12);
1601
1602 mt76_set(dev, rxtd, BIT(18) | BIT(29));
1603 mt76_set(dev, reg, 0x5 << 12);
1604 }
1605
mt7615_mac_cca_stats_reset(struct mt7615_phy * phy)1606 void mt7615_mac_cca_stats_reset(struct mt7615_phy *phy)
1607 {
1608 struct mt7615_dev *dev = phy->dev;
1609 bool ext_phy = phy != &dev->phy;
1610 u32 reg;
1611
1612 if (is_mt7663(&dev->mt76))
1613 reg = MT7663_WF_PHY_R0_PHYMUX_5;
1614 else
1615 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy);
1616
1617 /* reset PD and MDRDY counters */
1618 mt76_clear(dev, reg, GENMASK(22, 20));
1619 mt76_set(dev, reg, BIT(22) | BIT(20));
1620 }
1621
1622 static void
mt7615_mac_adjust_sensitivity(struct mt7615_phy * phy,u32 rts_err_rate,bool ofdm)1623 mt7615_mac_adjust_sensitivity(struct mt7615_phy *phy,
1624 u32 rts_err_rate, bool ofdm)
1625 {
1626 struct mt7615_dev *dev = phy->dev;
1627 int false_cca = ofdm ? phy->false_cca_ofdm : phy->false_cca_cck;
1628 bool ext_phy = phy != &dev->phy;
1629 s16 def_th = ofdm ? -98 : -110;
1630 bool update = false;
1631 s8 *sensitivity;
1632 int signal;
1633
1634 sensitivity = ofdm ? &phy->ofdm_sensitivity : &phy->cck_sensitivity;
1635 signal = mt76_get_min_avg_rssi(&dev->mt76, ext_phy);
1636 if (!signal) {
1637 mt7615_mac_set_default_sensitivity(phy);
1638 return;
1639 }
1640
1641 signal = min(signal, -72);
1642 if (false_cca > 500) {
1643 if (rts_err_rate > MT_FRAC(40, 100))
1644 return;
1645
1646 /* decrease coverage */
1647 if (*sensitivity == def_th && signal > -90) {
1648 *sensitivity = -90;
1649 update = true;
1650 } else if (*sensitivity + 2 < signal) {
1651 *sensitivity += 2;
1652 update = true;
1653 }
1654 } else if ((false_cca > 0 && false_cca < 50) ||
1655 rts_err_rate > MT_FRAC(60, 100)) {
1656 /* increase coverage */
1657 if (*sensitivity - 2 >= def_th) {
1658 *sensitivity -= 2;
1659 update = true;
1660 }
1661 }
1662
1663 if (*sensitivity > signal) {
1664 *sensitivity = signal;
1665 update = true;
1666 }
1667
1668 if (update) {
1669 u16 val = ofdm ? *sensitivity * 2 + 512 : *sensitivity + 256;
1670
1671 mt7615_mac_set_sensitivity(phy, val, ofdm);
1672 phy->last_cca_adj = jiffies;
1673 }
1674 }
1675
1676 static void
mt7615_mac_scs_check(struct mt7615_phy * phy)1677 mt7615_mac_scs_check(struct mt7615_phy *phy)
1678 {
1679 struct mt7615_dev *dev = phy->dev;
1680 struct mib_stats *mib = &phy->mib;
1681 u32 val, rts_err_rate = 0;
1682 u32 mdrdy_cck, mdrdy_ofdm, pd_cck, pd_ofdm;
1683 bool ext_phy = phy != &dev->phy;
1684
1685 if (!phy->scs_en)
1686 return;
1687
1688 if (is_mt7663(&dev->mt76))
1689 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS0(ext_phy));
1690 else
1691 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS0(ext_phy));
1692 pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val);
1693 pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val);
1694
1695 if (is_mt7663(&dev->mt76))
1696 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS5(ext_phy));
1697 else
1698 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS5(ext_phy));
1699 mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val);
1700 mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val);
1701
1702 phy->false_cca_ofdm = pd_ofdm - mdrdy_ofdm;
1703 phy->false_cca_cck = pd_cck - mdrdy_cck;
1704 mt7615_mac_cca_stats_reset(phy);
1705
1706 if (mib->rts_cnt + mib->rts_retries_cnt)
1707 rts_err_rate = MT_FRAC(mib->rts_retries_cnt,
1708 mib->rts_cnt + mib->rts_retries_cnt);
1709
1710 /* cck */
1711 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, false);
1712 /* ofdm */
1713 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, true);
1714
1715 if (time_after(jiffies, phy->last_cca_adj + 10 * HZ))
1716 mt7615_mac_set_default_sensitivity(phy);
1717 }
1718
1719 static u8
mt7615_phy_get_nf(struct mt7615_dev * dev,int idx)1720 mt7615_phy_get_nf(struct mt7615_dev *dev, int idx)
1721 {
1722 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 };
1723 u32 reg, val, sum = 0, n = 0;
1724 int i;
1725
1726 if (is_mt7663(&dev->mt76))
1727 reg = MT7663_WF_PHY_RXTD(20);
1728 else
1729 reg = idx ? MT_WF_PHY_RXTD2(17) : MT_WF_PHY_RXTD(20);
1730
1731 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) {
1732 val = mt76_rr(dev, reg);
1733 sum += val * nf_power[i];
1734 n += val;
1735 }
1736
1737 if (!n)
1738 return 0;
1739
1740 return sum / n;
1741 }
1742
1743 static void
mt7615_phy_update_channel(struct mt76_phy * mphy,int idx)1744 mt7615_phy_update_channel(struct mt76_phy *mphy, int idx)
1745 {
1746 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76);
1747 struct mt7615_phy *phy = mphy->priv;
1748 struct mt76_channel_state *state;
1749 u64 busy_time, tx_time, rx_time, obss_time;
1750 u32 obss_reg = idx ? MT_WF_RMAC_MIB_TIME6 : MT_WF_RMAC_MIB_TIME5;
1751 int nf;
1752
1753 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
1754 MT_MIB_SDR9_BUSY_MASK);
1755 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx),
1756 MT_MIB_SDR36_TXTIME_MASK);
1757 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx),
1758 MT_MIB_SDR37_RXTIME_MASK);
1759 obss_time = mt76_get_field(dev, obss_reg, MT_MIB_OBSSTIME_MASK);
1760
1761 nf = mt7615_phy_get_nf(dev, idx);
1762 if (!phy->noise)
1763 phy->noise = nf << 4;
1764 else if (nf)
1765 phy->noise += nf - (phy->noise >> 4);
1766
1767 state = mphy->chan_state;
1768 state->cc_busy += busy_time;
1769 state->cc_tx += tx_time;
1770 state->cc_rx += rx_time + obss_time;
1771 state->cc_bss_rx += rx_time;
1772 state->noise = -(phy->noise >> 4);
1773 }
1774
__mt7615_update_channel(struct mt7615_dev * dev)1775 static void __mt7615_update_channel(struct mt7615_dev *dev)
1776 {
1777 struct mt76_dev *mdev = &dev->mt76;
1778
1779 mt7615_phy_update_channel(&mdev->phy, 0);
1780 if (mdev->phy2)
1781 mt7615_phy_update_channel(mdev->phy2, 1);
1782
1783 /* reset obss airtime */
1784 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
1785 }
1786
mt7615_update_channel(struct mt76_dev * mdev)1787 void mt7615_update_channel(struct mt76_dev *mdev)
1788 {
1789 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
1790
1791 if (mt7615_pm_wake(dev))
1792 return;
1793
1794 __mt7615_update_channel(dev);
1795 mt7615_pm_power_save_sched(dev);
1796 }
1797 EXPORT_SYMBOL_GPL(mt7615_update_channel);
1798
mt7615_update_survey(struct mt7615_dev * dev)1799 static void mt7615_update_survey(struct mt7615_dev *dev)
1800 {
1801 struct mt76_dev *mdev = &dev->mt76;
1802 ktime_t cur_time;
1803
1804 __mt7615_update_channel(dev);
1805 cur_time = ktime_get_boottime();
1806
1807 mt76_update_survey_active_time(&mdev->phy, cur_time);
1808 if (mdev->phy2)
1809 mt76_update_survey_active_time(mdev->phy2, cur_time);
1810 }
1811
1812 static void
mt7615_mac_update_mib_stats(struct mt7615_phy * phy)1813 mt7615_mac_update_mib_stats(struct mt7615_phy *phy)
1814 {
1815 struct mt7615_dev *dev = phy->dev;
1816 struct mib_stats *mib = &phy->mib;
1817 bool ext_phy = phy != &dev->phy;
1818 int i, aggr;
1819 u32 val, val2;
1820
1821 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
1822 MT_MIB_SDR3_FCS_ERR_MASK);
1823
1824 val = mt76_get_field(dev, MT_MIB_SDR14(ext_phy),
1825 MT_MIB_AMPDU_MPDU_COUNT);
1826 if (val) {
1827 val2 = mt76_get_field(dev, MT_MIB_SDR15(ext_phy),
1828 MT_MIB_AMPDU_ACK_COUNT);
1829 mib->aggr_per = 1000 * (val - val2) / val;
1830 }
1831
1832 aggr = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
1833 for (i = 0; i < 4; i++) {
1834 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i));
1835 mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
1836 mib->ack_fail_cnt += FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK,
1837 val);
1838
1839 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i));
1840 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
1841 mib->rts_retries_cnt += FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK,
1842 val);
1843
1844 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
1845 dev->mt76.aggr_stats[aggr++] += val & 0xffff;
1846 dev->mt76.aggr_stats[aggr++] += val >> 16;
1847 }
1848 }
1849
mt7615_pm_wake_work(struct work_struct * work)1850 void mt7615_pm_wake_work(struct work_struct *work)
1851 {
1852 struct mt7615_dev *dev;
1853 struct mt76_phy *mphy;
1854 int i;
1855
1856 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev,
1857 pm.wake_work);
1858 mphy = dev->phy.mt76;
1859
1860 if (mt7615_mcu_set_drv_ctrl(dev)) {
1861 dev_err(mphy->dev->dev, "failed to wake device\n");
1862 goto out;
1863 }
1864
1865 spin_lock_bh(&dev->pm.txq_lock);
1866 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
1867 struct mt7615_sta *msta = dev->pm.tx_q[i].msta;
1868 struct ieee80211_sta *sta = NULL;
1869 struct mt76_wcid *wcid;
1870
1871 if (!dev->pm.tx_q[i].skb)
1872 continue;
1873
1874 wcid = msta ? &msta->wcid : &dev->mt76.global_wcid;
1875 if (msta && wcid->sta)
1876 sta = container_of((void *)msta, struct ieee80211_sta,
1877 drv_priv);
1878
1879 mt76_tx(mphy, sta, wcid, dev->pm.tx_q[i].skb);
1880 dev->pm.tx_q[i].skb = NULL;
1881 }
1882 spin_unlock_bh(&dev->pm.txq_lock);
1883
1884 mt76_worker_schedule(&dev->mt76.tx_worker);
1885
1886 out:
1887 ieee80211_wake_queues(mphy->hw);
1888 complete_all(&dev->pm.wake_cmpl);
1889 }
1890
mt7615_pm_wake(struct mt7615_dev * dev)1891 int mt7615_pm_wake(struct mt7615_dev *dev)
1892 {
1893 struct mt76_phy *mphy = dev->phy.mt76;
1894
1895 if (!mt7615_firmware_offload(dev))
1896 return 0;
1897
1898 if (!mt76_is_mmio(mphy->dev))
1899 return 0;
1900
1901 if (!test_bit(MT76_STATE_PM, &mphy->state))
1902 return 0;
1903
1904 if (test_bit(MT76_HW_SCANNING, &mphy->state) ||
1905 test_bit(MT76_HW_SCHED_SCANNING, &mphy->state))
1906 return 0;
1907
1908 if (queue_work(dev->mt76.wq, &dev->pm.wake_work))
1909 reinit_completion(&dev->pm.wake_cmpl);
1910
1911 if (!wait_for_completion_timeout(&dev->pm.wake_cmpl, 3 * HZ)) {
1912 ieee80211_wake_queues(mphy->hw);
1913 return -ETIMEDOUT;
1914 }
1915
1916 return 0;
1917 }
1918 EXPORT_SYMBOL_GPL(mt7615_pm_wake);
1919
mt7615_pm_power_save_sched(struct mt7615_dev * dev)1920 void mt7615_pm_power_save_sched(struct mt7615_dev *dev)
1921 {
1922 struct mt76_phy *mphy = dev->phy.mt76;
1923
1924 if (!mt7615_firmware_offload(dev))
1925 return;
1926
1927 if (!mt76_is_mmio(mphy->dev))
1928 return;
1929
1930 if (!dev->pm.enable || !test_bit(MT76_STATE_RUNNING, &mphy->state))
1931 return;
1932
1933 dev->pm.last_activity = jiffies;
1934
1935 if (test_bit(MT76_HW_SCANNING, &mphy->state) ||
1936 test_bit(MT76_HW_SCHED_SCANNING, &mphy->state))
1937 return;
1938
1939 if (!test_bit(MT76_STATE_PM, &mphy->state))
1940 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work,
1941 dev->pm.idle_timeout);
1942 }
1943 EXPORT_SYMBOL_GPL(mt7615_pm_power_save_sched);
1944
mt7615_pm_power_save_work(struct work_struct * work)1945 void mt7615_pm_power_save_work(struct work_struct *work)
1946 {
1947 struct mt7615_dev *dev;
1948 unsigned long delta;
1949
1950 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev,
1951 pm.ps_work.work);
1952
1953 delta = dev->pm.idle_timeout;
1954 if (time_is_after_jiffies(dev->pm.last_activity + delta)) {
1955 delta = dev->pm.last_activity + delta - jiffies;
1956 goto out;
1957 }
1958
1959 if (!mt7615_mcu_set_fw_ctrl(dev))
1960 return;
1961 out:
1962 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta);
1963 }
1964
1965 static void
mt7615_pm_interface_iter(void * priv,u8 * mac,struct ieee80211_vif * vif)1966 mt7615_pm_interface_iter(void *priv, u8 *mac, struct ieee80211_vif *vif)
1967 {
1968 struct mt7615_phy *phy = priv;
1969 struct mt7615_dev *dev = phy->dev;
1970 bool ext_phy = phy != &dev->phy;
1971
1972 if (mt7615_mcu_set_bss_pm(dev, vif, dev->pm.enable))
1973 return;
1974
1975 if (dev->pm.enable) {
1976 vif->driver_flags |= IEEE80211_VIF_BEACON_FILTER;
1977 mt76_set(dev, MT_WF_RFCR(ext_phy),
1978 MT_WF_RFCR_DROP_OTHER_BEACON);
1979 } else {
1980 vif->driver_flags &= ~IEEE80211_VIF_BEACON_FILTER;
1981 mt76_clear(dev, MT_WF_RFCR(ext_phy),
1982 MT_WF_RFCR_DROP_OTHER_BEACON);
1983 }
1984 }
1985
mt7615_pm_set_enable(struct mt7615_dev * dev,bool enable)1986 int mt7615_pm_set_enable(struct mt7615_dev *dev, bool enable)
1987 {
1988 struct mt76_phy *mphy = dev->phy.mt76;
1989
1990 if (!mt7615_firmware_offload(dev) || !mt76_is_mmio(&dev->mt76))
1991 return -EOPNOTSUPP;
1992
1993 mt7615_mutex_acquire(dev);
1994
1995 if (dev->pm.enable == enable)
1996 goto out;
1997
1998 dev->pm.enable = enable;
1999 ieee80211_iterate_active_interfaces(mphy->hw,
2000 IEEE80211_IFACE_ITER_RESUME_ALL,
2001 mt7615_pm_interface_iter, mphy->priv);
2002 out:
2003 mt7615_mutex_release(dev);
2004
2005 return 0;
2006 }
2007
mt7615_mac_work(struct work_struct * work)2008 void mt7615_mac_work(struct work_struct *work)
2009 {
2010 struct mt7615_phy *phy;
2011 struct mt76_dev *mdev;
2012
2013 phy = (struct mt7615_phy *)container_of(work, struct mt7615_phy,
2014 mac_work.work);
2015 mdev = &phy->dev->mt76;
2016
2017 mt7615_mutex_acquire(phy->dev);
2018
2019 mt7615_update_survey(phy->dev);
2020 if (++phy->mac_work_count == 5) {
2021 phy->mac_work_count = 0;
2022
2023 mt7615_mac_update_mib_stats(phy);
2024 mt7615_mac_scs_check(phy);
2025 }
2026
2027 mt7615_mutex_release(phy->dev);
2028
2029 mt76_tx_status_check(mdev, NULL, false);
2030 ieee80211_queue_delayed_work(phy->mt76->hw, &phy->mac_work,
2031 MT7615_WATCHDOG_TIME);
2032 }
2033
2034 static bool
mt7615_wait_reset_state(struct mt7615_dev * dev,u32 state)2035 mt7615_wait_reset_state(struct mt7615_dev *dev, u32 state)
2036 {
2037 bool ret;
2038
2039 ret = wait_event_timeout(dev->reset_wait,
2040 (READ_ONCE(dev->reset_state) & state),
2041 MT7615_RESET_TIMEOUT);
2042 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state);
2043 return ret;
2044 }
2045
2046 static void
mt7615_update_vif_beacon(void * priv,u8 * mac,struct ieee80211_vif * vif)2047 mt7615_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif)
2048 {
2049 struct ieee80211_hw *hw = priv;
2050 struct mt7615_dev *dev = mt7615_hw_dev(hw);
2051
2052 mt7615_mcu_add_beacon(dev, hw, vif, vif->bss_conf.enable_beacon);
2053 }
2054
2055 static void
mt7615_update_beacons(struct mt7615_dev * dev)2056 mt7615_update_beacons(struct mt7615_dev *dev)
2057 {
2058 ieee80211_iterate_active_interfaces(dev->mt76.hw,
2059 IEEE80211_IFACE_ITER_RESUME_ALL,
2060 mt7615_update_vif_beacon, dev->mt76.hw);
2061
2062 if (!dev->mt76.phy2)
2063 return;
2064
2065 ieee80211_iterate_active_interfaces(dev->mt76.phy2->hw,
2066 IEEE80211_IFACE_ITER_RESUME_ALL,
2067 mt7615_update_vif_beacon, dev->mt76.phy2->hw);
2068 }
2069
mt7615_dma_reset(struct mt7615_dev * dev)2070 void mt7615_dma_reset(struct mt7615_dev *dev)
2071 {
2072 int i;
2073
2074 mt76_clear(dev, MT_WPDMA_GLO_CFG,
2075 MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
2076 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
2077 usleep_range(1000, 2000);
2078
2079 for (i = 0; i < __MT_TXQ_MAX; i++)
2080 mt76_queue_tx_cleanup(dev, i, true);
2081
2082 mt76_for_each_q_rx(&dev->mt76, i) {
2083 mt76_queue_rx_reset(dev, i);
2084 }
2085
2086 mt76_set(dev, MT_WPDMA_GLO_CFG,
2087 MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
2088 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
2089 }
2090 EXPORT_SYMBOL_GPL(mt7615_dma_reset);
2091
mt7615_tx_token_put(struct mt7615_dev * dev)2092 void mt7615_tx_token_put(struct mt7615_dev *dev)
2093 {
2094 struct mt76_txwi_cache *txwi;
2095 int id;
2096
2097 spin_lock_bh(&dev->token_lock);
2098 idr_for_each_entry(&dev->token, txwi, id) {
2099 mt7615_txp_skb_unmap(&dev->mt76, txwi);
2100 if (txwi->skb) {
2101 struct ieee80211_hw *hw;
2102
2103 hw = mt76_tx_status_get_hw(&dev->mt76, txwi->skb);
2104 ieee80211_free_txskb(hw, txwi->skb);
2105 }
2106 mt76_put_txwi(&dev->mt76, txwi);
2107 }
2108 spin_unlock_bh(&dev->token_lock);
2109 idr_destroy(&dev->token);
2110 }
2111 EXPORT_SYMBOL_GPL(mt7615_tx_token_put);
2112
mt7615_mac_reset_work(struct work_struct * work)2113 void mt7615_mac_reset_work(struct work_struct *work)
2114 {
2115 struct mt7615_phy *phy2;
2116 struct mt76_phy *ext_phy;
2117 struct mt7615_dev *dev;
2118
2119 dev = container_of(work, struct mt7615_dev, reset_work);
2120 ext_phy = dev->mt76.phy2;
2121 phy2 = ext_phy ? ext_phy->priv : NULL;
2122
2123 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_PDMA))
2124 return;
2125
2126 ieee80211_stop_queues(mt76_hw(dev));
2127 if (ext_phy)
2128 ieee80211_stop_queues(ext_phy->hw);
2129
2130 set_bit(MT76_RESET, &dev->mphy.state);
2131 set_bit(MT76_MCU_RESET, &dev->mphy.state);
2132 wake_up(&dev->mt76.mcu.wait);
2133 cancel_delayed_work_sync(&dev->phy.mac_work);
2134 del_timer_sync(&dev->phy.roc_timer);
2135 cancel_work_sync(&dev->phy.roc_work);
2136 if (phy2) {
2137 cancel_delayed_work_sync(&phy2->mac_work);
2138 del_timer_sync(&phy2->roc_timer);
2139 cancel_work_sync(&phy2->roc_work);
2140 }
2141
2142 /* lock/unlock all queues to ensure that no tx is pending */
2143 mt76_txq_schedule_all(&dev->mphy);
2144 if (ext_phy)
2145 mt76_txq_schedule_all(ext_phy);
2146
2147 mt76_worker_disable(&dev->mt76.tx_worker);
2148 napi_disable(&dev->mt76.napi[0]);
2149 napi_disable(&dev->mt76.napi[1]);
2150 napi_disable(&dev->mt76.tx_napi);
2151
2152 mt7615_mutex_acquire(dev);
2153
2154 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_PDMA_STOPPED);
2155
2156 mt7615_tx_token_put(dev);
2157 idr_init(&dev->token);
2158
2159 if (mt7615_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) {
2160 mt7615_dma_reset(dev);
2161
2162 mt76_wr(dev, MT_WPDMA_MEM_RNG_ERR, 0);
2163
2164 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_PDMA_INIT);
2165 mt7615_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE);
2166 }
2167
2168 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
2169 clear_bit(MT76_RESET, &dev->mphy.state);
2170
2171 mt76_worker_enable(&dev->mt76.tx_worker);
2172 napi_enable(&dev->mt76.tx_napi);
2173 napi_schedule(&dev->mt76.tx_napi);
2174
2175 napi_enable(&dev->mt76.napi[0]);
2176 napi_schedule(&dev->mt76.napi[0]);
2177
2178 napi_enable(&dev->mt76.napi[1]);
2179 napi_schedule(&dev->mt76.napi[1]);
2180
2181 ieee80211_wake_queues(mt76_hw(dev));
2182 if (ext_phy)
2183 ieee80211_wake_queues(ext_phy->hw);
2184
2185 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE);
2186 mt7615_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
2187
2188 mt7615_update_beacons(dev);
2189
2190 mt7615_mutex_release(dev);
2191
2192 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->phy.mac_work,
2193 MT7615_WATCHDOG_TIME);
2194 if (phy2)
2195 ieee80211_queue_delayed_work(ext_phy->hw, &phy2->mac_work,
2196 MT7615_WATCHDOG_TIME);
2197
2198 }
2199
mt7615_dfs_stop_radar_detector(struct mt7615_phy * phy)2200 static void mt7615_dfs_stop_radar_detector(struct mt7615_phy *phy)
2201 {
2202 struct mt7615_dev *dev = phy->dev;
2203
2204 if (phy->rdd_state & BIT(0))
2205 mt7615_mcu_rdd_cmd(dev, RDD_STOP, 0, MT_RX_SEL0, 0);
2206 if (phy->rdd_state & BIT(1))
2207 mt7615_mcu_rdd_cmd(dev, RDD_STOP, 1, MT_RX_SEL0, 0);
2208 }
2209
mt7615_dfs_start_rdd(struct mt7615_dev * dev,int chain)2210 static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain)
2211 {
2212 int err;
2213
2214 err = mt7615_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0);
2215 if (err < 0)
2216 return err;
2217
2218 return mt7615_mcu_rdd_cmd(dev, RDD_DET_MODE, chain,
2219 MT_RX_SEL0, 1);
2220 }
2221
mt7615_dfs_start_radar_detector(struct mt7615_phy * phy)2222 static int mt7615_dfs_start_radar_detector(struct mt7615_phy *phy)
2223 {
2224 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2225 struct mt7615_dev *dev = phy->dev;
2226 bool ext_phy = phy != &dev->phy;
2227 int err;
2228
2229 /* start CAC */
2230 err = mt7615_mcu_rdd_cmd(dev, RDD_CAC_START, ext_phy, MT_RX_SEL0, 0);
2231 if (err < 0)
2232 return err;
2233
2234 err = mt7615_dfs_start_rdd(dev, ext_phy);
2235 if (err < 0)
2236 return err;
2237
2238 phy->rdd_state |= BIT(ext_phy);
2239
2240 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
2241 chandef->width == NL80211_CHAN_WIDTH_80P80) {
2242 err = mt7615_dfs_start_rdd(dev, 1);
2243 if (err < 0)
2244 return err;
2245
2246 phy->rdd_state |= BIT(1);
2247 }
2248
2249 return 0;
2250 }
2251
2252 static int
mt7615_dfs_init_radar_specs(struct mt7615_phy * phy)2253 mt7615_dfs_init_radar_specs(struct mt7615_phy *phy)
2254 {
2255 const struct mt7615_dfs_radar_spec *radar_specs;
2256 struct mt7615_dev *dev = phy->dev;
2257 int err, i;
2258
2259 switch (dev->mt76.region) {
2260 case NL80211_DFS_FCC:
2261 radar_specs = &fcc_radar_specs;
2262 err = mt7615_mcu_set_fcc5_lpn(dev, 8);
2263 if (err < 0)
2264 return err;
2265 break;
2266 case NL80211_DFS_ETSI:
2267 radar_specs = &etsi_radar_specs;
2268 break;
2269 case NL80211_DFS_JP:
2270 radar_specs = &jp_radar_specs;
2271 break;
2272 default:
2273 return -EINVAL;
2274 }
2275
2276 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
2277 err = mt7615_mcu_set_radar_th(dev, i,
2278 &radar_specs->radar_pattern[i]);
2279 if (err < 0)
2280 return err;
2281 }
2282
2283 return mt7615_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
2284 }
2285
mt7615_dfs_init_radar_detector(struct mt7615_phy * phy)2286 int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy)
2287 {
2288 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2289 struct mt7615_dev *dev = phy->dev;
2290 bool ext_phy = phy != &dev->phy;
2291 int err;
2292
2293 if (is_mt7663(&dev->mt76))
2294 return 0;
2295
2296 if (dev->mt76.region == NL80211_DFS_UNSET) {
2297 phy->dfs_state = -1;
2298 if (phy->rdd_state)
2299 goto stop;
2300
2301 return 0;
2302 }
2303
2304 if (test_bit(MT76_SCANNING, &phy->mt76->state))
2305 return 0;
2306
2307 if (phy->dfs_state == chandef->chan->dfs_state)
2308 return 0;
2309
2310 err = mt7615_dfs_init_radar_specs(phy);
2311 if (err < 0) {
2312 phy->dfs_state = -1;
2313 goto stop;
2314 }
2315
2316 phy->dfs_state = chandef->chan->dfs_state;
2317
2318 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) {
2319 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE)
2320 return mt7615_dfs_start_radar_detector(phy);
2321
2322 return mt7615_mcu_rdd_cmd(dev, RDD_CAC_END, ext_phy,
2323 MT_RX_SEL0, 0);
2324 }
2325
2326 stop:
2327 err = mt7615_mcu_rdd_cmd(dev, RDD_NORMAL_START, ext_phy, MT_RX_SEL0, 0);
2328 if (err < 0)
2329 return err;
2330
2331 mt7615_dfs_stop_radar_detector(phy);
2332 return 0;
2333 }
2334