1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
4 */
5
6 #ifndef _CCU_COMMON_H_
7 #define _CCU_COMMON_H_
8
9 #include <linux/compiler.h>
10 #include <linux/clk-provider.h>
11
12 #define CCU_FEATURE_FRACTIONAL BIT(0)
13 #define CCU_FEATURE_VARIABLE_PREDIV BIT(1)
14 #define CCU_FEATURE_FIXED_PREDIV BIT(2)
15 #define CCU_FEATURE_FIXED_POSTDIV BIT(3)
16 #define CCU_FEATURE_ALL_PREDIV BIT(4)
17 #define CCU_FEATURE_LOCK_REG BIT(5)
18 #define CCU_FEATURE_MMC_TIMING_SWITCH BIT(6)
19 #define CCU_FEATURE_SIGMA_DELTA_MOD BIT(7)
20
21 /* Support key-field reg setting */
22 #define CCU_FEATURE_KEY_FIELD_MOD BIT(8)
23
24 /* New formula support in MP: clk = parent / M / P */
25 #define CCU_FEATURE_MP_NO_INDEX_MODE BIT(9)
26
27 /* Support fixed rate in gate-clk */
28 #define CCU_FEATURE_FIXED_RATE_GATE BIT(10)
29
30 /* Some clks need config the mux reg repeatedly to fix ic bug */
31 #define CCU_FEATURE_REPEAT_SET_MUX BIT(11)
32
33 /* MMC timing mode switch bit */
34 #define CCU_MMC_NEW_TIMING_MODE BIT(30)
35
36 struct device_node;
37
38 /**
39 * struct ccu_reg_dump: register dump of clock controller registers.
40 * @offset: clock register offset from the controller base address.
41 * @value: the value to be register at offset.
42 */
43 struct ccu_reg_dump {
44 u32 offset;
45 u32 value;
46 };
47
48 struct ccu_common {
49 void __iomem *base;
50 u16 reg;
51 u16 lock_reg;
52 u32 prediv;
53 u32 key_value;
54
55 unsigned long features;
56 spinlock_t *lock;
57 struct clk_hw hw;
58 };
59
hw_to_ccu_common(struct clk_hw * hw)60 static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw)
61 {
62 return container_of(hw, struct ccu_common, hw);
63 }
64
65 struct sunxi_ccu_desc {
66 struct ccu_common **ccu_clks;
67 unsigned long num_ccu_clks;
68
69 struct clk_hw_onecell_data *hw_clks;
70
71 struct ccu_reset_map *resets;
72 unsigned long num_resets;
73 };
74
75 void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock);
76
77 struct ccu_pll_nb {
78 struct notifier_block clk_nb;
79 struct ccu_common *common;
80
81 u32 enable;
82 u32 lock;
83 };
84
85 #define to_ccu_pll_nb(_nb) container_of(_nb, struct ccu_pll_nb, clk_nb)
86
87 int ccu_pll_notifier_register(struct ccu_pll_nb *pll_nb);
88
89 int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
90 const struct sunxi_ccu_desc *desc);
91
92 void sunxi_ccu_sleep_init(void __iomem *reg_base,
93 struct ccu_common **rdump,
94 unsigned long nr_rdump,
95 const struct ccu_reg_dump *rsuspend,
96 unsigned long nr_rsuspend);
97
98 void set_reg(char __iomem *addr, u32 val, u8 bw, u8 bs);
99
100 void set_reg_key(char __iomem *addr,
101 u32 key, u8 kbw, u8 kbs,
102 u32 val, u8 bw, u8 bs);
103 #endif /* _CCU_COMMON_H_ */
104