1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 /*******************************************************
34 * when antenna test utility is on or some testing need to disable antenna
35 * diversity call this function to disable all ODM related mechanisms which
36 * will switch antenna.
37 *****************************************************
38 */
39 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
40 #if (RTL8710C_SUPPORT == 1)
odm_s0s1_sw_ant_div_init_8710c(void * dm_void)41 void odm_s0s1_sw_ant_div_init_8710c(void *dm_void)
42 {
43 struct dm_struct *dm = (struct dm_struct *)dm_void;
44 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
45 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
46
47 PHYDM_DBG(dm, DBG_ANT_DIV,
48 "***8710C AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
49 /*MAC setting*/
50 HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xdc, HAL_READ32(SYSTEM_CTRL_BASE, R_0xdc) | BIT18 | BIT17 | BIT16);
51 HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xac, HAL_READ32(SYSTEM_CTRL_BASE, R_0xac) | BIT24 | BIT6);
52 HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x10, 0x307);
53 HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x08, 0x80000111);
54 HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x1208, 0x800000);
55
56 /* Status init */
57 fat_tab->is_become_linked = false;
58 swat_tab->try_flag = SWAW_STEP_INIT;
59 swat_tab->double_chk_flag = 0;
60 swat_tab->cur_antenna = MAIN_ANT;
61 swat_tab->pre_ant = MAIN_ANT;
62 dm->antdiv_counter = CONFIG_ANTDIV_PERIOD;
63 }
64
odm_trx_hw_ant_div_init_8710c(void * dm_void)65 void odm_trx_hw_ant_div_init_8710c(void *dm_void)
66 {
67 struct dm_struct *dm = (struct dm_struct *)dm_void;
68
69 PHYDM_DBG(dm, DBG_ANT_DIV,
70 "[8710C] AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV]\n");
71 odm_set_mac_reg(dm, R_0x74, BIT(13) | BIT(12), 1);
72 odm_set_mac_reg(dm, R_0x74, BIT(4), 1);
73
74 /*@BT Coexistence*/
75 /*@keep antsel_map when GNT_BT = 1*/
76 odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
77
78 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
79 odm_set_bb_reg(dm, R_0x874, BIT(23), 1);
80 odm_set_bb_reg(dm, R_0x930, 0xF00, 8); /* RFE CTRL_2 ANTSEL0 */
81
82 odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
83 odm_set_bb_reg(dm, R_0x804, BIT(8), 0); /* r_keep_rfpin */
84
85 /*@Mapping Table*/
86 //odm_set_bb_reg(dm, R_0x864, BIT2|BIT1|BIT0, 2);
87 odm_set_bb_reg(dm, R_0x944, 0xFFFF, 0xffff);
88 odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
89 odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
90 /*@antenna training */
91 odm_set_bb_reg(dm, R_0xe08, BIT(16), 0);
92
93 //need to check!!!!!!!!!!
94 /* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */
95 odm_set_bb_reg(dm, R_0xccc, BIT(12), 0);
96 /* @Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */
97 odm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01);
98 /* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */
99 odm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0);
100 /* @b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable (CCK)*/
101 odm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06);
102 /* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable (CCK) */
103 odm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00);
104
105 /*OFDM HW AntDiv Parameters*/
106 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0x80);
107 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00);
108 odm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04);
109
110 /*@CCK HW AntDiv Parameters*/
111 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
112 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
113 odm_set_bb_reg(dm, R_0xaa8, BIT(8), 0);
114
115 odm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf);
116 odm_set_bb_reg(dm, R_0xa14, 0x1F, 0xf);
117 odm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1);
118 odm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0);
119 odm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1);
120 }
odm_update_rx_idle_ant_8710c(void * dm_void,u8 ant,u32 default_ant,u32 optional_ant)121 void odm_update_rx_idle_ant_8710c(void *dm_void, u8 ant, u32 default_ant,
122 u32 optional_ant)
123 {
124 struct dm_struct *dm = (struct dm_struct *)dm_void;
125 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
126 void *adapter = dm->adapter;
127
128 PHYDM_DBG(dm, DBG_ANT_DIV,
129 "***odm_update_rx_idle_ant_8710c!!!\n");
130 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
131 if (default_ant == 0x0)
132 HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x1210,0x800000);
133 else
134 HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x1214,0x800000);
135
136 fat_tab->rx_idle_ant = ant;
137 }else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
138 odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);
139 /*@Default RX*/
140 odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);
141 /*@Optional RX*/
142 odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);
143 /*@Default TX*/
144 fat_tab->rx_idle_ant = ant;
145 }
146 }
147 #endif
148
149 #if (RTL8721D_SUPPORT == 1)
150
odm_update_rx_idle_ant_8721d(void * dm_void,u8 ant,u32 default_ant,u32 optional_ant)151 void odm_update_rx_idle_ant_8721d(void *dm_void, u8 ant, u32 default_ant,
152 u32 optional_ant)
153 {
154 struct dm_struct *dm = (struct dm_struct *)dm_void;
155 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
156
157 odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);
158 /*@Default RX*/
159 odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);
160 /*@Optional RX*/
161 odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);
162 /*@Default TX*/
163 fat_tab->rx_idle_ant = ant;
164 }
165
odm_trx_hw_ant_div_init_8721d(void * dm_void)166 void odm_trx_hw_ant_div_init_8721d(void *dm_void)
167 {
168 struct dm_struct *dm = (struct dm_struct *)dm_void;
169
170 PHYDM_DBG(dm, DBG_ANT_DIV,
171 "[8721D] AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV]\n");
172
173 /*@BT Coexistence*/
174 /*@keep antsel_map when GNT_BT = 1*/
175 odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
176 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
177 odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
178 /* @Disable hw antsw & fast_train.antsw when BT TX/RX */
179 odm_set_bb_reg(dm, R_0xe64, 0xFFFF0000, 0x000c);
180
181 switch (dm->antdiv_gpio) {
182 case ANTDIV_GPIO_PA2PA4: {
183 PAD_CMD(_PA_2, ENABLE);
184 Pinmux_Config(_PA_2, PINMUX_FUNCTION_RFE);
185 PAD_CMD(_PA_4, ENABLE);
186 Pinmux_Config(_PA_4, PINMUX_FUNCTION_RFE);
187 break;
188 }
189 case ANTDIV_GPIO_PA5PA6: {
190 PAD_CMD(_PA_5, ENABLE);
191 Pinmux_Config(_PA_5, PINMUX_FUNCTION_RFE);
192 PAD_CMD(_PA_6, ENABLE);
193 Pinmux_Config(_PA_6, PINMUX_FUNCTION_RFE);
194 break;
195 }
196 case ANTDIV_GPIO_PA12PA13: {
197 PAD_CMD(_PA_12, ENABLE);
198 Pinmux_Config(_PA_12, PINMUX_FUNCTION_RFE);
199 PAD_CMD(_PA_13, ENABLE);
200 Pinmux_Config(_PA_13, PINMUX_FUNCTION_RFE);
201 break;
202 }
203 case ANTDIV_GPIO_PA14PA15: {
204 PAD_CMD(_PA_14, ENABLE);
205 Pinmux_Config(_PA_14, PINMUX_FUNCTION_RFE);
206 PAD_CMD(_PA_15, ENABLE);
207 Pinmux_Config(_PA_15, PINMUX_FUNCTION_RFE);
208 break;
209 }
210 case ANTDIV_GPIO_PA16PA17: {
211 PAD_CMD(_PA_16, ENABLE);
212 Pinmux_Config(_PA_16, PINMUX_FUNCTION_RFE);
213 PAD_CMD(_PA_17, ENABLE);
214 Pinmux_Config(_PA_17, PINMUX_FUNCTION_RFE);
215 break;
216 }
217 case ANTDIV_GPIO_PB1PB2: {
218 PAD_CMD(_PB_1, ENABLE);
219 Pinmux_Config(_PB_1, PINMUX_FUNCTION_RFE);
220 PAD_CMD(_PB_2, ENABLE);
221 Pinmux_Config(_PB_2, PINMUX_FUNCTION_RFE);
222 break;
223 }
224 case ANTDIV_GPIO_PB26PB29: {
225 PAD_CMD(_PB_26, ENABLE);
226 Pinmux_Config(_PB_26, PINMUX_FUNCTION_RFE);
227 PAD_CMD(_PB_29, ENABLE);
228 Pinmux_Config(_PB_29, PINMUX_FUNCTION_RFE);
229 break;
230 }
231 case ANTDIV_GPIO_PB1PB2PB26:{
232 PAD_CMD(_PB_1, ENABLE);
233 Pinmux_Config(_PB_1, PINMUX_FUNCTION_RFE);
234 PAD_CMD(_PB_2, ENABLE);
235 Pinmux_Config(_PB_2, PINMUX_FUNCTION_RFE);
236 PAD_CMD(_PB_26, ENABLE);
237 Pinmux_Config(_PB_26, PINMUX_FUNCTION_RFE);
238 break;
239 }
240 default: {
241 }
242 }
243
244 if (dm->antdiv_gpio == ANTDIV_GPIO_PA12PA13 ||
245 dm->antdiv_gpio == ANTDIV_GPIO_PA14PA15 ||
246 dm->antdiv_gpio == ANTDIV_GPIO_PA16PA17 ||
247 dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2) {
248 /* ANT_SEL_P, ANT_SEL_N */
249 odm_set_bb_reg(dm, R_0x930, 0xF, 8);
250 odm_set_bb_reg(dm, R_0x930, 0xF0, 8);
251 odm_set_bb_reg(dm, R_0x92c, BIT(1) | BIT(0), 2);
252 odm_set_bb_reg(dm, R_0x944, 0x00000003, 0x3);
253 } else if (dm->antdiv_gpio == ANTDIV_GPIO_PA2PA4 ||
254 dm->antdiv_gpio == ANTDIV_GPIO_PA5PA6 ||
255 dm->antdiv_gpio == ANTDIV_GPIO_PB26PB29) {
256 /* TRSW_P, TRSW_N */
257 odm_set_bb_reg(dm, R_0x930, 0xF00, 8);
258 odm_set_bb_reg(dm, R_0x930, 0xF000, 8);
259 odm_set_bb_reg(dm, R_0x92c, BIT(3) | BIT(2), 2);
260 odm_set_bb_reg(dm, R_0x944, 0x0000000C, 0x3);
261 }
262 else if(dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2PB26){
263 /* 3 antenna diversity for AmebaD only */
264 odm_set_bb_reg(dm, R_0x930, 0xF, 8);
265 odm_set_bb_reg(dm, R_0x930, 0xF0, 9);
266 odm_set_bb_reg(dm, R_0x930, 0xF00,0xa); /* set the RFE control table to select antenna*/
267 odm_set_bb_reg(dm, R_0x944, 0x00000007, 0x7);
268 }
269
270 u32 sysreg208 = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0);
271
272 sysreg208 |= BIT(28);
273 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0, sysreg208);
274
275 u32 sysreg344 =
276 HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL);
277
278 sysreg344 |= BIT(9);
279 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344);
280
281 u32 sysreg280 = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0);
282
283 sysreg280 |= 0x7;
284 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0, sysreg280);
285
286 sysreg344 |= BIT(8);
287 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344);
288
289 sysreg344 |= BIT(0);
290 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344);
291
292 odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
293 odm_set_bb_reg(dm, R_0x804, 0xF00, 1); /* r_keep_rfpin */
294
295 /*PTA setting: WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL)*/
296 /*odm_set_bb_reg(dm, R_0x948, BIT6, 0);*/
297 /*odm_set_bb_reg(dm, R_0x948, BIT8, 0);*/
298 /*@GNT_WL tx*/
299 odm_set_bb_reg(dm, R_0x950, BIT(29), 0);
300
301 /*@Mapping Table*/
302 odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
303 odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
304 if (dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2PB26) {
305 odm_set_bb_reg(dm, R_0x914, 0x00000F, 0x1);
306 odm_set_bb_reg(dm, R_0x914, 0x000F00, 0x2);
307 odm_set_bb_reg(dm, R_0x914, 0x0F0000, 0x4);
308 }
309 /* odm_set_bb_reg(dm, R_0x864, BIT5|BIT4|BIT3, 0); */
310 /* odm_set_bb_reg(dm, R_0x864, BIT8|BIT7|BIT6, 1); */
311
312 /* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */
313 odm_set_bb_reg(dm, R_0xccc, BIT(12), 0);
314 /* @Low-to-High threshold for WLBB_SEL_RF_ON */
315 /*when OFDM enable */
316 odm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01);
317 /* @High-to-Low threshold for WLBB_SEL_RF_ON */
318 /* when OFDM enable */
319 odm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0);
320 /* @b Low-to-High threshold for WLBB_SEL_RF_ON*/
321 /*when OFDM disable ( only CCK ) */
322 odm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06);
323 /* @High-to-Low threshold for WLBB_SEL_RF_ON*/
324 /* when OFDM disable ( only CCK ) */
325 odm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00);
326
327 /*OFDM HW AntDiv Parameters*/
328 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0);
329 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00);
330 odm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04);
331
332 /*@CCK HW AntDiv Parameters*/
333 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
334 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 0);
335 odm_set_bb_reg(dm, R_0xaa8, BIT(8), 0);
336
337 odm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf);
338 odm_set_bb_reg(dm, R_0xa14, 0x1F, 0x8);
339 odm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1);
340 odm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0);
341 odm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1);
342
343 /*@disable antenna training */
344 odm_set_bb_reg(dm, R_0xe08, BIT(16), 0);
345 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
346 }
347 #endif
348
odm_stop_antenna_switch_dm(void * dm_void)349 void odm_stop_antenna_switch_dm(void *dm_void)
350 {
351 struct dm_struct *dm = (struct dm_struct *)dm_void;
352 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
353 /* @disable ODM antenna diversity */
354 dm->support_ability &= ~ODM_BB_ANT_DIV;
355 #if (RTL8710C_SUPPORT == 1)
356 dm->support_ability |= ODM_BB_ANT_DIV;
357 #endif
358 if (fat_tab->div_path_type == ANT_PATH_A)
359 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
360 else if (fat_tab->div_path_type == ANT_PATH_B)
361 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
362 else if (fat_tab->div_path_type == ANT_PATH_AB)
363 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
364 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
365 PHYDM_DBG(dm, DBG_ANT_DIV, "STOP Antenna Diversity\n");
366 }
367
phydm_enable_antenna_diversity(void * dm_void)368 void phydm_enable_antenna_diversity(void *dm_void)
369 {
370 struct dm_struct *dm = (struct dm_struct *)dm_void;
371
372 dm->support_ability |= ODM_BB_ANT_DIV;
373 dm->antdiv_select = 0;
374 PHYDM_DBG(dm, DBG_ANT_DIV, "AntDiv is enabled & Re-Init AntDiv\n");
375 odm_antenna_diversity_init(dm);
376 }
377
odm_set_ant_config(void * dm_void,u8 ant_setting)378 void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C,...*/)
379 {
380 struct dm_struct *dm = (struct dm_struct *)dm_void;
381
382 if (dm->support_ic_type == ODM_RTL8723B) {
383 if (ant_setting == 0) /* @ant A*/
384 odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000000);
385 else if (ant_setting == 1)
386 odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000280);
387 } else if (dm->support_ic_type == ODM_RTL8723D) {
388 if (ant_setting == 0) /* @ant A*/
389 odm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0000);
390 else if (ant_setting == 1)
391 odm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0280);
392 }
393 }
394
395 /* ****************************************************** */
396
odm_sw_ant_div_rest_after_link(void * dm_void)397 void odm_sw_ant_div_rest_after_link(void *dm_void)
398 {
399 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
400 struct dm_struct *dm = (struct dm_struct *)dm_void;
401 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
402 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
403 u32 i;
404
405 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
406 swat_tab->try_flag = SWAW_STEP_INIT;
407 swat_tab->rssi_trying = 0;
408 swat_tab->double_chk_flag = 0;
409 fat_tab->rx_idle_ant = MAIN_ANT;
410
411 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
412 phydm_antdiv_reset_statistic(dm, i);
413 }
414
415 #endif
416 }
417
phydm_n_on_off(void * dm_void,u8 swch,u8 path)418 void phydm_n_on_off(void *dm_void, u8 swch, u8 path)
419 {
420 struct dm_struct *dm = (struct dm_struct *)dm_void;
421 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
422
423 if (path == ANT_PATH_A) {
424 odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
425 } else if (path == ANT_PATH_B) {
426 odm_set_bb_reg(dm, R_0xc58, BIT(7), swch);
427 } else if (path == ANT_PATH_AB) {
428 odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
429 odm_set_bb_reg(dm, R_0xc58, BIT(7), swch);
430 }
431 odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
432 #if (RTL8723D_SUPPORT == 1)
433 /*@Mingzhi 2017-05-08*/
434 if (dm->support_ic_type == ODM_RTL8723D) {
435 if (swch == ANTDIV_ON) {
436 odm_set_bb_reg(dm, R_0xce0, BIT(1), 1);
437 odm_set_bb_reg(dm, R_0x948, BIT(6), 1);
438 /*@1:HW ctrl 0:SW ctrl*/
439 } else {
440 odm_set_bb_reg(dm, R_0xce0, BIT(1), 0);
441 odm_set_bb_reg(dm, R_0x948, BIT(6), 0);
442 /*@1:HW ctrl 0:SW ctrl*/
443 }
444 }
445 #endif
446 }
447
phydm_ac_on_off(void * dm_void,u8 swch,u8 path)448 void phydm_ac_on_off(void *dm_void, u8 swch, u8 path)
449 {
450 struct dm_struct *dm = (struct dm_struct *)dm_void;
451 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
452
453 if (dm->support_ic_type & ODM_RTL8812) {
454 odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
455 /* OFDM AntDiv function block enable */
456 odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
457 /* @CCK AntDiv function block enable */
458 } else if (dm->support_ic_type & ODM_RTL8822B) {
459 odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
460 odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
461 if (path == ANT_PATH_A) {
462 odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
463 } else if (path == ANT_PATH_B) {
464 odm_set_bb_reg(dm, R_0xe50, BIT(7), swch);
465 } else if (path == ANT_PATH_AB) {
466 odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
467 odm_set_bb_reg(dm, R_0xe50, BIT(7), swch);
468 }
469 } else {
470 odm_set_bb_reg(dm, R_0x8d4, BIT(24), swch);
471 /* OFDM AntDiv function block enable */
472
473 if (dm->cut_version >= ODM_CUT_C &&
474 dm->support_ic_type == ODM_RTL8821 &&
475 dm->ant_div_type != S0S1_SW_ANTDIV) {
476 PHYDM_DBG(dm, DBG_ANT_DIV, "(Turn %s) CCK HW-AntDiv\n",
477 (swch == ANTDIV_ON) ? "ON" : "OFF");
478 odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
479 odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
480 /* @CCK AntDiv function block enable */
481 } else {
482 PHYDM_DBG(dm, DBG_ANT_DIV, "(Turn %s) CCK HW-AntDiv\n",
483 (swch == ANTDIV_ON) ? "ON" : "OFF");
484 odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
485 odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
486 /* @CCK AntDiv function block enable */
487 }
488 }
489 }
490
phydm_jgr3_on_off(void * dm_void,u8 swch,u8 path)491 void phydm_jgr3_on_off(void *dm_void, u8 swch, u8 path)
492 {
493 struct dm_struct *dm = (struct dm_struct *)dm_void;
494 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
495
496 odm_set_bb_reg(dm, R_0x8a0, BIT(17), swch);
497 /* OFDM AntDiv function block enable */
498 if (dm->support_ic_type & ODM_RTL8723F) {
499 odm_set_bb_reg(dm, R_0x1a48, BIT(16), swch);
500 /* @CCK AntDiv function block enable */
501 }
502 else{
503 odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
504 /* @CCK AntDiv function block enable */
505 }
506 PHYDM_DBG(dm, DBG_ANT_DIV,
507 "[8723F] AntDiv_on\n");
508 }
509
odm_ant_div_on_off(void * dm_void,u8 swch,u8 path)510 void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path)
511 {
512 struct dm_struct *dm = (struct dm_struct *)dm_void;
513 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
514
515 if (fat_tab->ant_div_on_off != swch) {
516 if (dm->ant_div_type == S0S1_SW_ANTDIV)
517 return;
518
519 if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
520 PHYDM_DBG(dm, DBG_ANT_DIV,
521 "(( Turn %s )) N-Series HW-AntDiv block\n",
522 (swch == ANTDIV_ON) ? "ON" : "OFF");
523 phydm_n_on_off(dm, swch, path);
524
525 } else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
526 PHYDM_DBG(dm, DBG_ANT_DIV,
527 "(( Turn %s )) AC-Series HW-AntDiv block\n",
528 (swch == ANTDIV_ON) ? "ON" : "OFF");
529 phydm_ac_on_off(dm, swch, path);
530 } else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT) {
531 PHYDM_DBG(dm, DBG_ANT_DIV,
532 "(( Turn %s )) JGR3 HW-AntDiv block\n",
533 (swch == ANTDIV_ON) ? "ON" : "OFF");
534 phydm_jgr3_on_off(dm, swch, path);
535 }
536 }
537 fat_tab->ant_div_on_off = swch;
538 }
539
odm_tx_by_tx_desc_or_reg(void * dm_void,u8 swch)540 void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch)
541 {
542 struct dm_struct *dm = (struct dm_struct *)dm_void;
543 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
544 u8 enable;
545
546 if (fat_tab->b_fix_tx_ant == NO_FIX_TX_ANT)
547 enable = (swch == TX_BY_DESC) ? 1 : 0;
548 else
549 enable = 0; /*@Force TX by Reg*/
550
551 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
552 if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
553 odm_set_bb_reg(dm, R_0x80c, BIT(21), enable);
554 else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)
555 odm_set_bb_reg(dm, R_0x900, BIT(18), enable);
556 else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT)
557 odm_set_bb_reg(dm, R_0x186c, BIT(1), enable);
558
559 PHYDM_DBG(dm, DBG_ANT_DIV, "[AntDiv] TX_Ant_BY (( %s ))\n",
560 (enable == TX_BY_DESC) ? "DESC" : "REG");
561 }
562 }
563
phydm_antdiv_reset_statistic(void * dm_void,u32 macid)564 void phydm_antdiv_reset_statistic(void *dm_void, u32 macid)
565 {
566 struct dm_struct *dm = (struct dm_struct *)dm_void;
567 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
568
569 fat_tab->main_sum[macid] = 0;
570 fat_tab->aux_sum[macid] = 0;
571 fat_tab->main_cnt[macid] = 0;
572 fat_tab->aux_cnt[macid] = 0;
573 fat_tab->main_sum_cck[macid] = 0;
574 fat_tab->aux_sum_cck[macid] = 0;
575 fat_tab->main_cnt_cck[macid] = 0;
576 fat_tab->aux_cnt_cck[macid] = 0;
577 }
578
phydm_fast_training_enable(void * dm_void,u8 swch)579 void phydm_fast_training_enable(void *dm_void, u8 swch)
580 {
581 struct dm_struct *dm = (struct dm_struct *)dm_void;
582 u8 enable;
583
584 if (swch == FAT_ON)
585 enable = 1;
586 else
587 enable = 0;
588
589 PHYDM_DBG(dm, DBG_ANT_DIV, "Fast ant Training_en = ((%d))\n", enable);
590
591 if (dm->support_ic_type == ODM_RTL8188E) {
592 odm_set_bb_reg(dm, R_0xe08, BIT(16), enable);
593 /*@enable fast training*/
594 } else if (dm->support_ic_type == ODM_RTL8192E) {
595 odm_set_bb_reg(dm, R_0xb34, BIT(28), enable);
596 /*@enable fast training (path-A)*/
597 #if 0
598 odm_set_bb_reg(dm, R_0xb34, BIT(29), enable);
599 /*enable fast training (path-B)*/
600 #endif
601 } else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8822B)) {
602 odm_set_bb_reg(dm, R_0x900, BIT(19), enable);
603 /*@enable fast training */
604 }
605 }
606
phydm_keep_rx_ack_ant_by_tx_ant_time(void * dm_void,u32 time)607 void phydm_keep_rx_ack_ant_by_tx_ant_time(void *dm_void, u32 time)
608 {
609 struct dm_struct *dm = (struct dm_struct *)dm_void;
610
611 /* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/
612 if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
613 odm_set_bb_reg(dm, R_0xe20, 0xf00000, time);
614 else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)
615 odm_set_bb_reg(dm, R_0x818, 0xf00000, time);
616 if (dm->support_ic_type & ODM_RTL8723F) {
617 odm_set_bb_reg(dm, R_0x1c8c, 0xf00, time);
618 /* keep antenna index after tx */
619 }
620
621
622 }
623
phydm_update_rx_idle_ac(void * dm_void,u8 ant,u32 default_ant,u32 optional_ant,u32 default_tx_ant)624 void phydm_update_rx_idle_ac(void *dm_void, u8 ant, u32 default_ant,
625 u32 optional_ant, u32 default_tx_ant)
626 {
627 struct dm_struct *dm = (struct dm_struct *)dm_void;
628
629 u16 value16 = odm_read_2byte(dm, ODM_REG_TRMUX_11AC + 2);
630 /* @2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to */
631 /* @prevnt incorrect 0xc08 bit0-15.We still not know why it is changed*/
632 value16 &= ~(BIT(11) | BIT(10) | BIT(9) | BIT(8) | BIT(7) | BIT(6) |
633 BIT(5) | BIT(4) | BIT(3));
634 value16 |= ((u16)default_ant << 3);
635 value16 |= ((u16)optional_ant << 6);
636 value16 |= ((u16)default_tx_ant << 9);
637 odm_write_2byte(dm, ODM_REG_TRMUX_11AC + 2, value16);
638 #if 0
639 odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0x380000, default_ant);
640 /* @Default RX */
641 odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0x1c00000, optional_ant);
642 /* Optional RX */
643 odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0xe000000, default_ant);
644 /* @Default TX */
645 #endif
646 }
647
phydm_update_rx_idle_n(void * dm_void,u8 ant,u32 default_ant,u32 optional_ant,u32 default_tx_ant)648 void phydm_update_rx_idle_n(void *dm_void, u8 ant, u32 default_ant,
649 u32 optional_ant, u32 default_tx_ant)
650 {
651 struct dm_struct *dm = (struct dm_struct *)dm_void;
652 u32 value32;
653
654 if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F)) {
655 odm_set_bb_reg(dm, R_0xb38, 0x38, default_ant);
656 /* @Default RX */
657 odm_set_bb_reg(dm, R_0xb38, 0x1c0, optional_ant);
658 /* Optional RX */
659 odm_set_bb_reg(dm, R_0x860, 0x7000, default_ant);
660 /* @Default TX */
661 #if (RTL8723B_SUPPORT == 1)
662 } else if (dm->support_ic_type == ODM_RTL8723B) {
663 value32 = odm_get_bb_reg(dm, R_0x948, 0xFFF);
664
665 if (value32 != 0x280)
666 odm_update_rx_idle_ant_8723b(dm, ant, default_ant,
667 optional_ant);
668 else
669 PHYDM_DBG(dm, DBG_ANT_DIV,
670 "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n");
671 #endif
672
673 #if (RTL8723D_SUPPORT == 1) /*@Mingzhi 2017-05-08*/
674 } else if (dm->support_ic_type == ODM_RTL8723D) {
675 phydm_set_tx_ant_pwr_8723d(dm, ant);
676 odm_update_rx_idle_ant_8723d(dm, ant, default_ant,
677 optional_ant);
678 #endif
679
680 #if (RTL8721D_SUPPORT == 1)
681 } else if (dm->support_ic_type == ODM_RTL8721D) {
682 odm_update_rx_idle_ant_8721d(dm, ant, default_ant,
683 optional_ant);
684 #endif
685
686 #if (RTL8710C_SUPPORT == 1)
687 } else if (dm->support_ic_type == ODM_RTL8710C) {
688 odm_update_rx_idle_ant_8710c(dm, ant, default_ant,
689 optional_ant);
690 #endif
691
692 } else {
693 /*@8188E & 8188F*/
694 /*@ if (dm->support_ic_type == ODM_RTL8723D) {*/
695 /*#if (RTL8723D_SUPPORT == 1)*/
696 /* phydm_set_tx_ant_pwr_8723d(dm, ant);*/
697 /*#endif*/
698 /* }*/
699 #if (RTL8188F_SUPPORT == 1)
700 if (dm->support_ic_type == ODM_RTL8188F)
701 phydm_update_rx_idle_antenna_8188F(dm, default_ant);
702 #endif
703
704 odm_set_bb_reg(dm, R_0x864, 0x38, default_ant);/*@Default RX*/
705 odm_set_bb_reg(dm, R_0x864, 0x1c0, optional_ant);
706 /*Optional RX*/
707 odm_set_bb_reg(dm, R_0x860, 0x7000, default_tx_ant);
708 /*@Default TX*/
709 }
710 }
711
phydm_update_rx_idle_jgr3(void * dm_void,u8 ant,u32 default_ant,u32 optional_ant,u32 default_tx_ant)712 void phydm_update_rx_idle_jgr3(void *dm_void, u8 ant, u32 default_ant,
713 u32 optional_ant, u32 default_tx_ant)
714 {
715 struct dm_struct *dm = (struct dm_struct *)dm_void;
716 u32 value32;
717
718 odm_set_bb_reg(dm, R_0x1884, 0xf0, default_ant);/*@Default RX*/
719 odm_set_bb_reg(dm, R_0x1884, 0xf00, optional_ant);
720 /*Optional RX*/
721 odm_set_bb_reg(dm, R_0x1884, 0xf000, default_tx_ant);
722 /*@Default TX*/
723 }
odm_update_rx_idle_ant(void * dm_void,u8 ant)724 void odm_update_rx_idle_ant(void *dm_void, u8 ant)
725 {
726 struct dm_struct *dm = (struct dm_struct *)dm_void;
727 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
728 u32 default_ant, optional_ant, value32, default_tx_ant;
729 if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT) {
730 PHYDM_DBG(dm, DBG_ANT_DIV,"JGR3 HW-AntDiv block\n");
731 }
732 else{
733 PHYDM_DBG(dm, DBG_ANT_DIV,"not suppoty JGR3 HW-AntDiv block\n");
734 PHYDM_DBG(dm, DBG_ANT_DIV,"dm->support_ic_type=%d\n",dm->support_ic_type);
735 }
736 if (fat_tab->rx_idle_ant != ant) {
737 PHYDM_DBG(dm, DBG_ANT_DIV,
738 "[ Update Rx-Idle-ant ] rx_idle_ant =%s\n",
739 (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
740
741 if (!(dm->support_ic_type & ODM_RTL8723B))
742 fat_tab->rx_idle_ant = ant;
743
744 if (ant == MAIN_ANT) {
745 default_ant = ANT1_2G;
746 optional_ant = ANT2_2G;
747 } else {
748 default_ant = ANT2_2G;
749 optional_ant = ANT1_2G;
750 }
751
752 if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
753 default_tx_ant = (fat_tab->b_fix_tx_ant ==
754 FIX_TX_AT_MAIN) ? 0 : 1;
755 else
756 default_tx_ant = default_ant;
757
758 if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
759 phydm_update_rx_idle_n(dm, ant, default_ant,
760 optional_ant, default_tx_ant);
761 } else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
762 phydm_update_rx_idle_ac(dm, ant, default_ant,
763 optional_ant, default_tx_ant);
764 } else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT) {
765 phydm_update_rx_idle_jgr3(dm, ant, default_ant,
766 optional_ant, default_tx_ant);
767 }
768 /*PathA Resp Tx*/
769 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B |
770 ODM_RTL8814A | ODM_RTL8195B))
771 odm_set_mac_reg(dm, R_0x6d8, 0x7, default_tx_ant);
772 else if (dm->support_ic_type == ODM_RTL8188E)
773 odm_set_mac_reg(dm, R_0x6d8, 0xc0, default_tx_ant);
774 else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT)
775 odm_set_mac_reg(dm, R_0x6f8, 0xf, default_tx_ant);
776 else
777 odm_set_mac_reg(dm, R_0x6d8, 0x700, default_tx_ant);
778
779 } else { /* @fat_tab->rx_idle_ant == ant */
780 PHYDM_DBG(dm, DBG_ANT_DIV,
781 "[ Stay in Ori-ant ] rx_idle_ant =%s\n",
782 (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
783 fat_tab->rx_idle_ant = ant;
784 }
785 }
786
787 #if (RTL8721D_SUPPORT)
odm_update_rx_idle_ant_sp3t(void * dm_void,u8 ant)788 void odm_update_rx_idle_ant_sp3t(void *dm_void, u8 ant) /* added by Jiao Qi on May.25,2020, for AmebaD SP3T only */
789 {
790 struct dm_struct *dm = (struct dm_struct *)dm_void;
791 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
792 u32 default_ant, optional_ant, value32, default_tx_ant;
793
794 if (!(dm->support_ic_type & ODM_RTL8723B))
795 fat_tab->rx_idle_ant = ant;
796
797 default_ant = fat_tab->ant_idx_vec[0]-1;
798 optional_ant = fat_tab->ant_idx_vec[1]-1;
799
800 if(fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
801 default_tx_ant = (fat_tab->b_fix_tx_ant ==
802 FIX_TX_AT_MAIN) ? 0 : 1;
803 else
804 default_tx_ant = default_ant;
805
806 odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);
807 /*@Default RX*/
808 odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);
809 /*@Optional RX*/
810 odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);
811 /*@Default TX*/
812
813 /*PathA Resp Tx*/
814 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B |
815 ODM_RTL8814A))
816 odm_set_mac_reg(dm, R_0x6d8, 0x7, default_tx_ant);
817 else if (dm->support_ic_type == ODM_RTL8188E)
818 odm_set_mac_reg(dm, R_0x6d8, 0xc0, default_tx_ant);
819 else
820 odm_set_mac_reg(dm, R_0x6d8, 0x700, default_tx_ant);
821
822 }
823 #endif
phydm_update_rx_idle_ant_pathb(void * dm_void,u8 ant)824 void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant)
825 {
826 struct dm_struct *dm = (struct dm_struct *)dm_void;
827 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
828 u32 default_ant, optional_ant, value32, default_tx_ant;
829
830 if (fat_tab->rx_idle_ant2 != ant) {
831 PHYDM_DBG(dm, DBG_ANT_DIV,
832 "[ Update Rx-Idle-ant2 ] rx_idle_ant2 =%s\n",
833 (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
834 if (ant == MAIN_ANT) {
835 default_ant = ANT1_2G;
836 optional_ant = ANT2_2G;
837 } else {
838 default_ant = ANT2_2G;
839 optional_ant = ANT1_2G;
840 }
841
842 if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
843 default_tx_ant = (fat_tab->b_fix_tx_ant ==
844 FIX_TX_AT_MAIN) ? 0 : 1;
845 else
846 default_tx_ant = default_ant;
847 if (dm->support_ic_type & ODM_RTL8822B) {
848 u16 v16 = odm_read_2byte(dm, ODM_REG_ANT_11AC_B + 2);
849
850 v16 &= ~(0xff8);/*0xE08[11:3]*/
851 v16 |= ((u16)default_ant << 3);
852 v16 |= ((u16)optional_ant << 6);
853 v16 |= ((u16)default_tx_ant << 9);
854 odm_write_2byte(dm, ODM_REG_ANT_11AC_B + 2, v16);
855 odm_set_mac_reg(dm, R_0x6d8, 0x38, default_tx_ant);
856 /*PathB Resp Tx*/
857 }
858 } else {
859 /* fat_tab->rx_idle_ant2 == ant */
860 PHYDM_DBG(dm, DBG_ANT_DIV, "[Stay Ori Ant] rx_idle_ant2 = %s\n",
861 (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
862 fat_tab->rx_idle_ant2 = ant;
863 }
864 }
865
phydm_set_antdiv_val(void * dm_void,u32 * val_buf,u8 val_len)866 void phydm_set_antdiv_val(void *dm_void, u32 *val_buf, u8 val_len)
867 {
868 struct dm_struct *dm = (struct dm_struct *)dm_void;
869
870 if (!(dm->support_ability & ODM_BB_ANT_DIV))
871 return;
872
873 if (val_len != 1) {
874 PHYDM_DBG(dm, ODM_COMP_API, "[Error][antdiv]Need val_len=1\n");
875 return;
876 }
877
878 odm_update_rx_idle_ant(dm, (u8)(*val_buf));
879 }
880
odm_update_tx_ant(void * dm_void,u8 ant,u32 mac_id)881 void odm_update_tx_ant(void *dm_void, u8 ant, u32 mac_id)
882 {
883 struct dm_struct *dm = (struct dm_struct *)dm_void;
884 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
885 u8 tx_ant;
886
887 if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
888 ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ?
889 MAIN_ANT : AUX_ANT;
890
891 if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
892 tx_ant = ant;
893 else {
894 if (ant == MAIN_ANT)
895 tx_ant = ANT1_2G;
896 else
897 tx_ant = ANT2_2G;
898 }
899 #if (RTL8721D_SUPPORT)
900 if (dm->antdiv_gpio != ANTDIV_GPIO_PB1PB2PB26) {
901 if (ant == MAIN_ANT)
902 tx_ant = ANT1_2G;
903 else
904 tx_ant = ANT2_2G;
905 }
906 else
907 tx_ant = fat_tab->ant_idx_vec[0]-1;
908 #endif
909 fat_tab->antsel_a[mac_id] = tx_ant & BIT(0);
910 fat_tab->antsel_b[mac_id] = (tx_ant & BIT(1)) >> 1;
911 fat_tab->antsel_c[mac_id] = (tx_ant & BIT(2)) >> 2;
912
913 PHYDM_DBG(dm, DBG_ANT_DIV,
914 "[Set TX-DESC value]: mac_id:(( %d )), tx_ant = (( %s ))\n",
915 mac_id, (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
916 #if 0
917 PHYDM_DBG(dm, DBG_ANT_DIV,
918 "antsel_tr_mux=(( 3'b%d%d%d ))\n",
919 fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
920 fat_tab->antsel_a[mac_id]);
921 #endif
922 }
923
924 #ifdef PHYDM_BEAMFORMING_SUPPORT
925 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
926
odm_bdc_init(void * dm_void)927 void odm_bdc_init(
928 void *dm_void)
929 {
930 struct dm_struct *dm = (struct dm_struct *)dm_void;
931 struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
932
933 PHYDM_DBG(dm, DBG_ANT_DIV, "\n[ BDC Initialization......]\n");
934 dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
935 dm_bdc_table->bdc_mode = BDC_MODE_NULL;
936 dm_bdc_table->bdc_try_flag = 0;
937 dm_bdc_table->bd_ccoex_type_wbfer = 0;
938 dm->bdc_holdstate = 0xff;
939
940 if (dm->support_ic_type == ODM_RTL8192E) {
941 odm_set_bb_reg(dm, R_0xd7c, 0x0FFFFFFF, 0x1081008);
942 odm_set_bb_reg(dm, R_0xd80, 0x0FFFFFFF, 0);
943 } else if (dm->support_ic_type == ODM_RTL8812) {
944 odm_set_bb_reg(dm, R_0x9b0, 0x0FFFFFFF, 0x1081008);
945 /* @0x9b0[30:0] = 01081008 */
946 odm_set_bb_reg(dm, R_0x9b4, 0x0FFFFFFF, 0);
947 /* @0x9b4[31:0] = 00000000 */
948 }
949 }
950
odm_CSI_on_off(void * dm_void,u8 CSI_en)951 void odm_CSI_on_off(
952 void *dm_void,
953 u8 CSI_en)
954 {
955 struct dm_struct *dm = (struct dm_struct *)dm_void;
956 if (CSI_en == CSI_ON) {
957 if (dm->support_ic_type == ODM_RTL8192E)
958 odm_set_mac_reg(dm, R_0xd84, BIT(11), 1);
959 /* @0xd84[11]=1 */
960 else if (dm->support_ic_type == ODM_RTL8812)
961 odm_set_mac_reg(dm, R_0x9b0, BIT(31), 1);
962 /* @0x9b0[31]=1 */
963
964 } else if (CSI_en == CSI_OFF) {
965 if (dm->support_ic_type == ODM_RTL8192E)
966 odm_set_mac_reg(dm, R_0xd84, BIT(11), 0);
967 /* @0xd84[11]=0 */
968 else if (dm->support_ic_type == ODM_RTL8812)
969 odm_set_mac_reg(dm, R_0x9b0, BIT(31), 0);
970 /* @0x9b0[31]=0 */
971 }
972 }
973
odm_bd_ccoex_type_with_bfer_client(void * dm_void,u8 swch)974 void odm_bd_ccoex_type_with_bfer_client(
975 void *dm_void,
976 u8 swch)
977 {
978 struct dm_struct *dm = (struct dm_struct *)dm_void;
979 struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
980 u8 bd_ccoex_type_wbfer;
981
982 if (swch == DIVON_CSIOFF) {
983 PHYDM_DBG(dm, DBG_ANT_DIV,
984 "[BDCcoexType: 1] {DIV,CSI} ={1,0}\n");
985 bd_ccoex_type_wbfer = 1;
986
987 if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {
988 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
989 odm_CSI_on_off(dm, CSI_OFF);
990 dm_bdc_table->bd_ccoex_type_wbfer = 1;
991 }
992 } else if (swch == DIVOFF_CSION) {
993 PHYDM_DBG(dm, DBG_ANT_DIV,
994 "[BDCcoexType: 2] {DIV,CSI} ={0,1}\n");
995 bd_ccoex_type_wbfer = 2;
996
997 if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {
998 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
999 odm_CSI_on_off(dm, CSI_ON);
1000 dm_bdc_table->bd_ccoex_type_wbfer = 2;
1001 }
1002 }
1003 }
1004
odm_bf_ant_div_mode_arbitration(void * dm_void)1005 void odm_bf_ant_div_mode_arbitration(
1006 void *dm_void)
1007 {
1008 struct dm_struct *dm = (struct dm_struct *)dm_void;
1009 struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
1010 u8 current_bdc_mode;
1011
1012 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1013 PHYDM_DBG(dm, DBG_ANT_DIV, "\n");
1014
1015 /* @2 mode 1 */
1016 if (dm_bdc_table->num_txbfee_client != 0 &&
1017 dm_bdc_table->num_txbfer_client == 0) {
1018 current_bdc_mode = BDC_MODE_1;
1019
1020 if (current_bdc_mode != dm_bdc_table->bdc_mode) {
1021 dm_bdc_table->bdc_mode = BDC_MODE_1;
1022 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
1023 dm_bdc_table->bdc_rx_idle_update_counter = 1;
1024 PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode1 ))\n");
1025 }
1026
1027 PHYDM_DBG(dm, DBG_ANT_DIV,
1028 "[Antdiv + BF coextance mode] : (( Mode1 ))\n");
1029 }
1030 /* @2 mode 2 */
1031 else if ((dm_bdc_table->num_txbfee_client == 0) &&
1032 (dm_bdc_table->num_txbfer_client != 0)) {
1033 current_bdc_mode = BDC_MODE_2;
1034
1035 if (current_bdc_mode != dm_bdc_table->bdc_mode) {
1036 dm_bdc_table->bdc_mode = BDC_MODE_2;
1037 dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
1038 dm_bdc_table->bdc_try_flag = 0;
1039 PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode2 ))\n");
1040 }
1041 PHYDM_DBG(dm, DBG_ANT_DIV,
1042 "[Antdiv + BF coextance mode] : (( Mode2 ))\n");
1043 }
1044 /* @2 mode 3 */
1045 else if ((dm_bdc_table->num_txbfee_client != 0) &&
1046 (dm_bdc_table->num_txbfer_client != 0)) {
1047 current_bdc_mode = BDC_MODE_3;
1048
1049 if (current_bdc_mode != dm_bdc_table->bdc_mode) {
1050 dm_bdc_table->bdc_mode = BDC_MODE_3;
1051 dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
1052 dm_bdc_table->bdc_try_flag = 0;
1053 dm_bdc_table->bdc_rx_idle_update_counter = 1;
1054 PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode3 ))\n");
1055 }
1056
1057 PHYDM_DBG(dm, DBG_ANT_DIV,
1058 "[Antdiv + BF coextance mode] : (( Mode3 ))\n");
1059 }
1060 /* @2 mode 4 */
1061 else if ((dm_bdc_table->num_txbfee_client == 0) &&
1062 (dm_bdc_table->num_txbfer_client == 0)) {
1063 current_bdc_mode = BDC_MODE_4;
1064
1065 if (current_bdc_mode != dm_bdc_table->bdc_mode) {
1066 dm_bdc_table->bdc_mode = BDC_MODE_4;
1067 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
1068 PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode4 ))\n");
1069 }
1070
1071 PHYDM_DBG(dm, DBG_ANT_DIV,
1072 "[Antdiv + BF coextance mode] : (( Mode4 ))\n");
1073 }
1074 #endif
1075 }
1076
odm_div_train_state_setting(void * dm_void)1077 void odm_div_train_state_setting(
1078 void *dm_void)
1079 {
1080 struct dm_struct *dm = (struct dm_struct *)dm_void;
1081 struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
1082
1083 PHYDM_DBG(dm, DBG_ANT_DIV,
1084 "\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE]\n");
1085 dm_bdc_table->bdc_try_counter = 2;
1086 dm_bdc_table->bdc_try_flag = 1;
1087 dm_bdc_table->BDC_state = bdc_bfer_train_state;
1088 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
1089 }
1090
odm_bd_ccoex_bfee_rx_div_arbitration(void * dm_void)1091 void odm_bd_ccoex_bfee_rx_div_arbitration(
1092 void *dm_void)
1093 {
1094 struct dm_struct *dm = (struct dm_struct *)dm_void;
1095 struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
1096 boolean stop_bf_flag;
1097 u8 bdc_active_mode;
1098
1099 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1100
1101 PHYDM_DBG(dm, DBG_ANT_DIV,
1102 "***{ num_BFee, num_BFer, num_client} = (( %d , %d , %d))\n",
1103 dm_bdc_table->num_txbfee_client,
1104 dm_bdc_table->num_txbfer_client, dm_bdc_table->num_client);
1105 PHYDM_DBG(dm, DBG_ANT_DIV,
1106 "***{ num_BF_tars, num_DIV_tars } = (( %d , %d ))\n",
1107 dm_bdc_table->num_bf_tar, dm_bdc_table->num_div_tar);
1108
1109 /* @2 [ MIB control ] */
1110 if (dm->bdc_holdstate == 2) {
1111 odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
1112 dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
1113 PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ BF STATE]\n");
1114 return;
1115 } else if (dm->bdc_holdstate == 1) {
1116 dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
1117 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
1118 PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n");
1119 return;
1120 }
1121
1122 /* @------------------------------------------------------------ */
1123
1124 /* @2 mode 2 & 3 */
1125 if (dm_bdc_table->bdc_mode == BDC_MODE_2 ||
1126 dm_bdc_table->bdc_mode == BDC_MODE_3) {
1127 PHYDM_DBG(dm, DBG_ANT_DIV,
1128 "\n{ Try_flag, Try_counter } = { %d , %d }\n",
1129 dm_bdc_table->bdc_try_flag,
1130 dm_bdc_table->bdc_try_counter);
1131 PHYDM_DBG(dm, DBG_ANT_DIV, "BDCcoexType = (( %d ))\n\n",
1132 dm_bdc_table->bd_ccoex_type_wbfer);
1133
1134 /* @All Client have Bfer-Cap------------------------------- */
1135 if (dm_bdc_table->num_txbfer_client == dm_bdc_table->num_client) {
1136 /* @BFer STA Only?: yes */
1137 PHYDM_DBG(dm, DBG_ANT_DIV,
1138 "BFer STA only? (( Yes ))\n");
1139 dm_bdc_table->bdc_try_flag = 0;
1140 dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
1141 odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
1142 return;
1143 } else
1144 PHYDM_DBG(dm, DBG_ANT_DIV,
1145 "BFer STA only? (( No ))\n");
1146 if (dm_bdc_table->is_all_bf_sta_idle == false && dm_bdc_table->is_all_div_sta_idle == true) {
1147 PHYDM_DBG(dm, DBG_ANT_DIV,
1148 "All DIV-STA are idle, but BF-STA not\n");
1149 dm_bdc_table->bdc_try_flag = 0;
1150 dm_bdc_table->BDC_state = bdc_bfer_train_state;
1151 odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
1152 return;
1153 } else if (dm_bdc_table->is_all_bf_sta_idle == true && dm_bdc_table->is_all_div_sta_idle == false) {
1154 PHYDM_DBG(dm, DBG_ANT_DIV,
1155 "All BF-STA are idle, but DIV-STA not\n");
1156 dm_bdc_table->bdc_try_flag = 0;
1157 dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
1158 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
1159 return;
1160 }
1161
1162 /* Select active mode-------------------------------------- */
1163 if (dm_bdc_table->num_bf_tar == 0) { /* Selsect_1, Selsect_2 */
1164 if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
1165 PHYDM_DBG(dm, DBG_ANT_DIV,
1166 "Select active mode (( 1 ))\n");
1167 dm_bdc_table->bdc_active_mode = 1;
1168 } else {
1169 PHYDM_DBG(dm, DBG_ANT_DIV,
1170 "Select active mode (( 2 ))\n");
1171 dm_bdc_table->bdc_active_mode = 2;
1172 }
1173 dm_bdc_table->bdc_try_flag = 0;
1174 dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
1175 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
1176 return;
1177 } else { /* num_bf_tar > 0 */
1178 if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
1179 PHYDM_DBG(dm, DBG_ANT_DIV,
1180 "Select active mode (( 3 ))\n");
1181 dm_bdc_table->bdc_active_mode = 3;
1182 dm_bdc_table->bdc_try_flag = 0;
1183 dm_bdc_table->BDC_state = bdc_bfer_train_state;
1184 odm_bd_ccoex_type_with_bfer_client(dm,
1185 DIVOFF_CSION)
1186 ;
1187 return;
1188 } else { /* Selsect_4 */
1189 bdc_active_mode = 4;
1190 PHYDM_DBG(dm, DBG_ANT_DIV,
1191 "Select active mode (( 4 ))\n");
1192
1193 if (bdc_active_mode != dm_bdc_table->bdc_active_mode) {
1194 dm_bdc_table->bdc_active_mode = 4;
1195 PHYDM_DBG(dm, DBG_ANT_DIV, "Change to active mode (( 4 )) & return!!!\n");
1196 return;
1197 }
1198 }
1199 }
1200
1201 #if 1
1202 if (dm->bdc_holdstate == 0xff) {
1203 dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
1204 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
1205 PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n");
1206 return;
1207 }
1208 #endif
1209
1210 /* @Does Client number changed ? ------------------------------- */
1211 if (dm_bdc_table->num_client != dm_bdc_table->pre_num_client) {
1212 dm_bdc_table->bdc_try_flag = 0;
1213 dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
1214 PHYDM_DBG(dm, DBG_ANT_DIV,
1215 "[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE ))\n");
1216 }
1217 dm_bdc_table->pre_num_client = dm_bdc_table->num_client;
1218
1219 if (dm_bdc_table->bdc_try_flag == 0) {
1220 /* @2 DIV_TRAIN_STATE (mode 2-0) */
1221 if (dm_bdc_table->BDC_state == BDC_DIV_TRAIN_STATE)
1222 odm_div_train_state_setting(dm);
1223 /* @2 BFer_TRAIN_STATE (mode 2-1) */
1224 else if (dm_bdc_table->BDC_state == bdc_bfer_train_state) {
1225 PHYDM_DBG(dm, DBG_ANT_DIV,
1226 "*****[2-1. BFer_TRAIN_STATE ]*****\n");
1227
1228 #if 0
1229 /* @if(dm_bdc_table->num_bf_tar==0) */
1230 /* @{ */
1231 /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( No )), [ bdc_bfer_train_state ] >> [BDC_DIV_TRAIN_STATE]\n"); */
1232 /* odm_div_train_state_setting( dm); */
1233 /* @} */
1234 /* else */ /* num_bf_tar != 0 */
1235 /* @{ */
1236 #endif
1237 dm_bdc_table->bdc_try_counter = 2;
1238 dm_bdc_table->bdc_try_flag = 1;
1239 dm_bdc_table->BDC_state = BDC_DECISION_STATE;
1240 odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
1241 PHYDM_DBG(dm, DBG_ANT_DIV,
1242 "BF_tars exist? : (( Yes )), [ bdc_bfer_train_state ] >> [BDC_DECISION_STATE]\n");
1243 /* @} */
1244 }
1245 /* @2 DECISION_STATE (mode 2-2) */
1246 else if (dm_bdc_table->BDC_state == BDC_DECISION_STATE) {
1247 PHYDM_DBG(dm, DBG_ANT_DIV,
1248 "*****[2-2. DECISION_STATE]*****\n");
1249 #if 0
1250 /* @if(dm_bdc_table->num_bf_tar==0) */
1251 /* @{ */
1252 /* ODM_AntDiv_Printk(("BF_tars exist? : (( No )), [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */
1253 /* odm_div_train_state_setting( dm); */
1254 /* @} */
1255 /* else */ /* num_bf_tar != 0 */
1256 /* @{ */
1257 #endif
1258 if (dm_bdc_table->BF_pass == false || dm_bdc_table->DIV_pass == false)
1259 stop_bf_flag = true;
1260 else
1261 stop_bf_flag = false;
1262
1263 PHYDM_DBG(dm, DBG_ANT_DIV,
1264 "BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, stop_bf_flag } = { %d, %d, %d }\n",
1265 dm_bdc_table->BF_pass,
1266 dm_bdc_table->DIV_pass, stop_bf_flag);
1267
1268 if (stop_bf_flag == true) { /* @DIV_en */
1269 dm_bdc_table->bdc_hold_counter = 10; /* @20 */
1270 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
1271 dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
1272 PHYDM_DBG(dm, DBG_ANT_DIV, "[ stop_bf_flag= ((true)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE]\n");
1273 } else { /* @BF_en */
1274 dm_bdc_table->bdc_hold_counter = 10; /* @20 */
1275 odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
1276 dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
1277 PHYDM_DBG(dm, DBG_ANT_DIV, "[stop_bf_flag= ((false)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE]\n");
1278 }
1279 /* @} */
1280 }
1281 /* @2 BF-HOLD_STATE (mode 2-3) */
1282 else if (dm_bdc_table->BDC_state == BDC_BF_HOLD_STATE) {
1283 PHYDM_DBG(dm, DBG_ANT_DIV,
1284 "*****[2-3. BF_HOLD_STATE ]*****\n");
1285
1286 PHYDM_DBG(dm, DBG_ANT_DIV,
1287 "bdc_hold_counter = (( %d ))\n",
1288 dm_bdc_table->bdc_hold_counter);
1289
1290 if (dm_bdc_table->bdc_hold_counter == 1) {
1291 PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n");
1292 odm_div_train_state_setting(dm);
1293 } else {
1294 dm_bdc_table->bdc_hold_counter--;
1295
1296 #if 0
1297 /* @if(dm_bdc_table->num_bf_tar==0) */
1298 /* @{ */
1299 /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); */
1300 /* odm_div_train_state_setting( dm); */
1301 /* @} */
1302 /* else */ /* num_bf_tar != 0 */
1303 /* @{ */
1304 /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( Yes ))\n"); */
1305 #endif
1306 dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
1307 odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
1308 PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE]\n");
1309 /* @} */
1310 }
1311 }
1312 /* @2 DIV-HOLD_STATE (mode 2-4) */
1313 else if (dm_bdc_table->BDC_state == BDC_DIV_HOLD_STATE) {
1314 PHYDM_DBG(dm, DBG_ANT_DIV,
1315 "*****[2-4. DIV_HOLD_STATE ]*****\n");
1316
1317 PHYDM_DBG(dm, DBG_ANT_DIV,
1318 "bdc_hold_counter = (( %d ))\n",
1319 dm_bdc_table->bdc_hold_counter);
1320
1321 if (dm_bdc_table->bdc_hold_counter == 1) {
1322 PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n");
1323 odm_div_train_state_setting(dm);
1324 } else {
1325 dm_bdc_table->bdc_hold_counter--;
1326 dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
1327 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
1328 PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE]\n");
1329 }
1330 }
1331
1332 } else if (dm_bdc_table->bdc_try_flag == 1) {
1333 /* @2 Set Training counter */
1334 if (dm_bdc_table->bdc_try_counter > 1) {
1335 dm_bdc_table->bdc_try_counter--;
1336 if (dm_bdc_table->bdc_try_counter == 1)
1337 dm_bdc_table->bdc_try_flag = 0;
1338
1339 PHYDM_DBG(dm, DBG_ANT_DIV, "Training !!\n");
1340 /* return ; */
1341 }
1342 }
1343 }
1344
1345 PHYDM_DBG(dm, DBG_ANT_DIV, "\n[end]\n");
1346
1347 #endif /* @#if(DM_ODM_SUPPORT_TYPE == ODM_AP) */
1348 }
1349
1350 #endif
1351 #endif /* @#ifdef PHYDM_BEAMFORMING_SUPPORT*/
1352
1353 #if (RTL8188E_SUPPORT == 1)
1354
odm_rx_hw_ant_div_init_88e(void * dm_void)1355 void odm_rx_hw_ant_div_init_88e(void *dm_void)
1356 {
1357 struct dm_struct *dm = (struct dm_struct *)dm_void;
1358 u32 value32;
1359 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1360
1361 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1362
1363 /* @MAC setting */
1364 value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
1365 odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD,
1366 value32 | (BIT(23) | BIT(25)));
1367 /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
1368 /* Pin Settings */
1369 odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
1370 /* reg870[8]=1'b0, reg870[9]=1'b0 */
1371 /* antsel antselb by HW */
1372 odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
1373 /* reg864[10]=1'b0 */ /* antsel2 by HW */
1374 odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1);
1375 /* regb2c[22]=1'b0 */ /* disable CS/CG switch */
1376 odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
1377 /* regb2c[31]=1'b1 */ /* output at CG only */
1378 /* OFDM Settings */
1379 odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
1380 /* @CCK Settings */
1381 odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
1382 /* @Fix CCK PHY status report issue */
1383 odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
1384 /* @CCK complete HW AntDiv within 64 samples */
1385
1386 odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0001);
1387 /* @antenna mapping table */
1388
1389 fat_tab->enable_ctrl_frame_antdiv = 1;
1390 }
1391
odm_trx_hw_ant_div_init_88e(void * dm_void)1392 void odm_trx_hw_ant_div_init_88e(void *dm_void)
1393 {
1394 struct dm_struct *dm = (struct dm_struct *)dm_void;
1395 u32 value32;
1396 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1397
1398
1399 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1400
1401 /* @MAC setting */
1402 value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
1403 odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD,
1404 value32 | (BIT(23) | BIT(25)));
1405 /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
1406 /* Pin Settings */
1407 odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
1408 /* reg870[8]=1'b0, reg870[9]=1'b0 */
1409 /* antsel antselb by HW */
1410 odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
1411 /* reg864[10]=1'b0 */ /* antsel2 by HW */
1412 odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0);
1413 /* regb2c[22]=1'b0 */ /* disable CS/CG switch */
1414 odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
1415 /* regb2c[31]=1'b1 */ /* output at CG only */
1416 /* OFDM Settings */
1417 odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
1418 /* @CCK Settings */
1419 odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
1420 /* @Fix CCK PHY status report issue */
1421 odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
1422 /* @CCK complete HW AntDiv within 64 samples */
1423
1424 /* @antenna mapping table */
1425 if (!dm->is_mp_chip) { /* testchip */
1426 odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, 0x700, 1);
1427 /* Reg858[10:8]=3'b001 */
1428 odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, 0x3800, 2);
1429 /* Reg858[13:11]=3'b010 */
1430 } else /* @MPchip */
1431 odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, MASKDWORD, 0x0201);
1432 /*Reg914=3'b010, Reg915=3'b001*/
1433
1434 fat_tab->enable_ctrl_frame_antdiv = 1;
1435 }
1436
1437 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
odm_smart_hw_ant_div_init_88e(void * dm_void)1438 void odm_smart_hw_ant_div_init_88e(
1439 void *dm_void)
1440 {
1441 struct dm_struct *dm = (struct dm_struct *)dm_void;
1442 u32 value32, i;
1443 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1444
1445 PHYDM_DBG(dm, DBG_ANT_DIV,
1446 "***8188E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n");
1447
1448 #if 0
1449 if (*dm->mp_mode == true) {
1450 PHYDM_DBG(dm, ODM_COMP_INIT, "dm->ant_div_type: %d\n",
1451 dm->ant_div_type);
1452 return;
1453 }
1454 #endif
1455
1456 fat_tab->train_idx = 0;
1457 fat_tab->fat_state = FAT_PREPARE_STATE;
1458
1459 dm->fat_comb_a = 5;
1460 dm->antdiv_intvl = 0x64; /* @100ms */
1461
1462 for (i = 0; i < 6; i++)
1463 fat_tab->bssid[i] = 0;
1464 for (i = 0; i < (dm->fat_comb_a); i++) {
1465 fat_tab->ant_sum_rssi[i] = 0;
1466 fat_tab->ant_rssi_cnt[i] = 0;
1467 fat_tab->ant_ave_rssi[i] = 0;
1468 }
1469
1470 /* @MAC setting */
1471 value32 = odm_get_mac_reg(dm, R_0x4c, MASKDWORD);
1472 odm_set_mac_reg(dm, R_0x4c, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
1473 value32 = odm_get_mac_reg(dm, R_0x7b4, MASKDWORD);
1474 odm_set_mac_reg(dm, R_0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
1475 /* value32 = platform_efio_read_4byte(adapter, 0x7B4); */
1476 /* platform_efio_write_4byte(adapter, 0x7b4, value32|BIT(18)); */ /* append MACID in reponse packet */
1477
1478 /* @Match MAC ADDR */
1479 odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, 0);
1480 odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, 0);
1481
1482 odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); /* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */
1483 odm_set_bb_reg(dm, R_0x864, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */
1484 odm_set_bb_reg(dm, R_0xb2c, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */
1485 odm_set_bb_reg(dm, R_0xb2c, BIT(31), 0); /* regb2c[31]=1'b1 */ /* output at CS only */
1486 odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x000000a0);
1487
1488 /* @antenna mapping table */
1489 if (dm->fat_comb_a == 2) {
1490 if (!dm->is_mp_chip) { /* testchip */
1491 odm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
1492 odm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
1493 } else { /* @MPchip */
1494 odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 1);
1495 odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2);
1496 }
1497 } else {
1498 if (!dm->is_mp_chip) { /* testchip */
1499 odm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 0); /* Reg858[10:8]=3'b000 */
1500 odm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 1); /* Reg858[13:11]=3'b001 */
1501 odm_set_bb_reg(dm, R_0x878, BIT(16), 0);
1502 odm_set_bb_reg(dm, R_0x858, BIT(15) | BIT(14), 2); /* @(Reg878[0],Reg858[14:15])=3'b010 */
1503 odm_set_bb_reg(dm, R_0x878, BIT(19) | BIT(18) | BIT(17), 3); /* Reg878[3:1]=3b'011 */
1504 odm_set_bb_reg(dm, R_0x878, BIT(22) | BIT(21) | BIT(20), 4); /* Reg878[6:4]=3b'100 */
1505 odm_set_bb_reg(dm, R_0x878, BIT(25) | BIT(24) | BIT(23), 5); /* Reg878[9:7]=3b'101 */
1506 odm_set_bb_reg(dm, R_0x878, BIT(28) | BIT(27) | BIT(26), 6); /* Reg878[12:10]=3b'110 */
1507 odm_set_bb_reg(dm, R_0x878, BIT(31) | BIT(30) | BIT(29), 7); /* Reg878[15:13]=3b'111 */
1508 } else { /* @MPchip */
1509 odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 4); /* @0: 3b'000 */
1510 odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2); /* @1: 3b'001 */
1511 odm_set_bb_reg(dm, R_0x914, MASKBYTE2, 0); /* @2: 3b'010 */
1512 odm_set_bb_reg(dm, R_0x914, MASKBYTE3, 1); /* @3: 3b'011 */
1513 odm_set_bb_reg(dm, R_0x918, MASKBYTE0, 3); /* @4: 3b'100 */
1514 odm_set_bb_reg(dm, R_0x918, MASKBYTE1, 5); /* @5: 3b'101 */
1515 odm_set_bb_reg(dm, R_0x918, MASKBYTE2, 6); /* @6: 3b'110 */
1516 odm_set_bb_reg(dm, R_0x918, MASKBYTE3, 255); /* @7: 3b'111 */
1517 }
1518 }
1519
1520 /* @Default ant setting when no fast training */
1521 odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), 0); /* @Default RX */
1522 odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */
1523 odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), 0); /* @Default TX */
1524
1525 /* @Enter Traing state */
1526 odm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), (dm->fat_comb_a - 1)); /* reg864[2:0]=3'd6 */ /* ant combination=reg864[2:0]+1 */
1527
1528 #if 0
1529 /* SW Control */
1530 /* phy_set_bb_reg(adapter, 0x864, BIT10, 1); */
1531 /* phy_set_bb_reg(adapter, 0x870, BIT9, 1); */
1532 /* phy_set_bb_reg(adapter, 0x870, BIT8, 1); */
1533 /* phy_set_bb_reg(adapter, 0x864, BIT11, 1); */
1534 /* phy_set_bb_reg(adapter, 0x860, BIT9, 0); */
1535 /* phy_set_bb_reg(adapter, 0x860, BIT8, 0); */
1536 #endif
1537 }
1538 #endif
1539
1540 #endif /* @#if (RTL8188E_SUPPORT == 1) */
1541
1542 #if (RTL8192E_SUPPORT == 1)
odm_rx_hw_ant_div_init_92e(void * dm_void)1543 void odm_rx_hw_ant_div_init_92e(void *dm_void)
1544 {
1545 struct dm_struct *dm = (struct dm_struct *)dm_void;
1546 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1547
1548 #if 0
1549 if (*dm->mp_mode == true) {
1550 odm_ant_div_on_off(dm, ANTDIV_OFF);
1551 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
1552 /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */
1553 odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);
1554 /* @1:CG, 0:CS */
1555 return;
1556 }
1557 #endif
1558
1559 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1560
1561 /* Pin Settings */
1562 odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
1563 /* reg870[8]=1'b0, antsel is controled by HWs */
1564 odm_set_bb_reg(dm, R_0xc50, BIT(8), 1);
1565 /* regc50[8]=1'b1 CS/CG switching is controled by HWs*/
1566
1567 /* @Mapping table */
1568 odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
1569 /* @antenna mapping table */
1570
1571 /* OFDM Settings */
1572 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
1573 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
1574
1575 /* @CCK Settings */
1576 odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
1577 /* Select which path to receive for CCK_1 & CCK_2 */
1578 odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
1579 /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1580 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
1581 /* @Fix CCK PHY status report issue */
1582 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
1583 /* @CCK complete HW AntDiv within 64 samples */
1584
1585 #ifdef ODM_EVM_ENHANCE_ANTDIV
1586 phydm_evm_sw_antdiv_init(dm);
1587 #endif
1588 }
1589
odm_trx_hw_ant_div_init_92e(void * dm_void)1590 void odm_trx_hw_ant_div_init_92e(void *dm_void)
1591 {
1592 struct dm_struct *dm = (struct dm_struct *)dm_void;
1593
1594 #if 0
1595 if (*dm->mp_mode == true) {
1596 odm_ant_div_on_off(dm, ANTDIV_OFF);
1597 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */
1598 odm_set_bb_reg(dm, R_0xc50, BIT(9), 1); /* @1:CG, 0:CS */
1599 return;
1600 }
1601 #endif
1602
1603 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1604
1605 /* @3 --RFE pin setting--------- */
1606 /* @[MAC] */
1607 odm_set_mac_reg(dm, R_0x38, BIT(11), 1);
1608 /* @DBG PAD Driving control (GPIO 8) */
1609 odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* path-A, RFE_CTRL_3 */
1610 odm_set_mac_reg(dm, R_0x4c, BIT(29), 1); /* path-A, RFE_CTRL_8 */
1611 /* @[BB] */
1612 odm_set_bb_reg(dm, R_0x944, BIT(3), 1); /* RFE_buffer */
1613 odm_set_bb_reg(dm, R_0x944, BIT(8), 1);
1614 odm_set_bb_reg(dm, R_0x940, BIT(7) | BIT(6), 0x0);
1615 /* r_rfe_path_sel_ (RFE_CTRL_3) */
1616 odm_set_bb_reg(dm, R_0x940, BIT(17) | BIT(16), 0x0);
1617 /* r_rfe_path_sel_ (RFE_CTRL_8) */
1618 odm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer */
1619 odm_set_bb_reg(dm, R_0x92c, BIT(3), 0); /* rfe_inv (RFE_CTRL_3) */
1620 odm_set_bb_reg(dm, R_0x92c, BIT(8), 1); /* rfe_inv (RFE_CTRL_8) */
1621 odm_set_bb_reg(dm, R_0x930, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */
1622 odm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */
1623 /* @3 ------------------------- */
1624
1625 /* Pin Settings */
1626 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
1627 /* path-A */ /* disable CS/CG switch */
1628
1629 #if 0
1630 /* @Let it follows PHY_REG for bit9 setting */
1631 if (dm->priv->pshare->rf_ft_var.use_ext_pa ||
1632 dm->priv->pshare->rf_ft_var.use_ext_lna)
1633 odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);/* path-A output at CS */
1634 else
1635 odm_set_bb_reg(dm, R_0xc50, BIT(9), 0);
1636 /* path-A output at CG ->normal power */
1637 #endif
1638
1639 odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
1640 /* path-A*/ /* antsel antselb by HW */
1641 odm_set_bb_reg(dm, R_0xb38, BIT(10), 0);/* path-A*/ /* antsel2 by HW */
1642
1643 /* @Mapping table */
1644 odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
1645 /* @antenna mapping table */
1646
1647 /* OFDM Settings */
1648 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
1649 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
1650
1651 /* @CCK Settings */
1652 odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
1653 /* Select which path to receive for CCK_1 & CCK_2 */
1654 odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
1655 /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1656 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
1657 /* @Fix CCK PHY status report issue */
1658 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
1659 /* @CCK complete HW AntDiv within 64 samples */
1660
1661 #ifdef ODM_EVM_ENHANCE_ANTDIV
1662 phydm_evm_sw_antdiv_init(dm);
1663 #endif
1664 }
1665
1666 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
odm_smart_hw_ant_div_init_92e(void * dm_void)1667 void odm_smart_hw_ant_div_init_92e(
1668 void *dm_void)
1669 {
1670 struct dm_struct *dm = (struct dm_struct *)dm_void;
1671
1672 PHYDM_DBG(dm, DBG_ANT_DIV,
1673 "***8192E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n");
1674 }
1675 #endif
1676
1677 #endif /* @#if (RTL8192E_SUPPORT == 1) */
1678
1679 #if (RTL8192F_SUPPORT == 1)
odm_rx_hw_ant_div_init_92f(void * dm_void)1680 void odm_rx_hw_ant_div_init_92f(void *dm_void)
1681 {
1682 struct dm_struct *dm = (struct dm_struct *)dm_void;
1683 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1684
1685 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1686
1687 /* Pin Settings */
1688 odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
1689 /* reg870[8]=1'b0, "antsel" is controlled by HWs */
1690 odm_set_bb_reg(dm, R_0xc50, BIT(8), 1);
1691 /* regc50[8]=1'b1, " CS/CG switching" is controlled by HWs */
1692
1693 /* @Mapping table */
1694 odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
1695 /* @antenna mapping table */
1696
1697 /* OFDM Settings */
1698 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
1699 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
1700
1701 /* @CCK Settings */
1702 odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
1703 /* Select which path to receive for CCK_1 & CCK_2 */
1704 odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
1705 /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1706 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
1707 /* @Fix CCK PHY status report issue */
1708 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
1709 /* @CCK complete HW AntDiv within 64 samples */
1710
1711 #ifdef ODM_EVM_ENHANCE_ANTDIV
1712 phydm_evm_sw_antdiv_init(dm);
1713 #endif
1714 }
1715
odm_trx_hw_ant_div_init_92f(void * dm_void)1716 void odm_trx_hw_ant_div_init_92f(void *dm_void)
1717
1718 {
1719 struct dm_struct *dm = (struct dm_struct *)dm_void;
1720
1721 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1722 /* @3 --RFE pin setting--------- */
1723 /* @[MAC] */
1724 odm_set_mac_reg(dm, R_0x1048, BIT(0), 1);
1725 /* @DBG PAD Driving control (gpioA_0) */
1726 odm_set_mac_reg(dm, R_0x1048, BIT(1), 1);
1727 /* @DBG PAD Driving control (gpioA_1) */
1728 odm_set_mac_reg(dm, R_0x4c, BIT(24), 1);
1729 odm_set_mac_reg(dm, R_0x1038, BIT(25) | BIT(24) | BIT(23), 0);
1730 /* @gpioA_0,gpioA_1*/
1731 odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
1732 /* @[BB] */
1733 odm_set_bb_reg(dm, R_0x944, BIT(8), 1); /* output enable */
1734 odm_set_bb_reg(dm, R_0x944, BIT(9), 1);
1735 odm_set_bb_reg(dm, R_0x940, BIT(16) | BIT(17), 0x0);
1736 /* r_rfe_path_sel_ (RFE_CTRL_8) */
1737 odm_set_bb_reg(dm, R_0x940, BIT(18) | BIT(19), 0x0);
1738 /* r_rfe_path_sel_ (RFE_CTRL_9) */
1739 odm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer_en */
1740 odm_set_bb_reg(dm, R_0x92c, BIT(8), 0); /* rfe_inv (RFE_CTRL_8) */
1741 odm_set_bb_reg(dm, R_0x92c, BIT(9), 1); /* rfe_inv (RFE_CTRL_9) */
1742 odm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */
1743 odm_set_bb_reg(dm, R_0x934, 0xF0, 0x8); /* path-A, RFE_CTRL_9 */
1744 /* @3 ------------------------- */
1745
1746 /* Pin Settings */
1747 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
1748 /* path-A,disable CS/CG switch */
1749 odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
1750 /* path-A*, antsel antselb by HW */
1751 odm_set_bb_reg(dm, R_0xb38, BIT(10), 0); /* path-A ,antsel2 by HW */
1752
1753 /* @Mapping table */
1754 odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
1755 /* @antenna mapping table */
1756
1757 /* OFDM Settings */
1758 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
1759 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
1760
1761 /* @CCK Settings */
1762 odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
1763 /* Select which path to receive for CCK_1 & CCK_2 */
1764 odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
1765 /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1766 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
1767 /* @Fix CCK PHY status report issue */
1768 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
1769 /* @CCK complete HW AntDiv within 64 samples */
1770
1771 #ifdef ODM_EVM_ENHANCE_ANTDIV
1772 phydm_evm_sw_antdiv_init(dm);
1773 #endif
1774 }
1775
1776 #endif /* @#if (RTL8192F_SUPPORT == 1) */
1777
1778 #if (RTL8822B_SUPPORT == 1)
phydm_trx_hw_ant_div_init_22b(void * dm_void)1779 void phydm_trx_hw_ant_div_init_22b(void *dm_void)
1780 {
1781 struct dm_struct *dm = (struct dm_struct *)dm_void;
1782
1783 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1784
1785 /* Pin Settings */
1786 odm_set_bb_reg(dm, R_0xcb8, BIT(21) | BIT(20), 0x1);
1787 odm_set_bb_reg(dm, R_0xcb8, BIT(23) | BIT(22), 0x1);
1788 odm_set_bb_reg(dm, R_0xc1c, BIT(7) | BIT(6), 0x0);
1789 /* @------------------------- */
1790
1791 /* @Mapping table */
1792 /* @antenna mapping table */
1793 odm_set_bb_reg(dm, R_0xca4, 0xFFFF, 0x0100);
1794
1795 /* OFDM Settings */
1796 /* thershold */
1797 odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0);
1798 /* @bias */
1799 odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0);
1800 odm_set_bb_reg(dm, R_0x668, BIT(3), 0x1);
1801
1802 /* @CCK Settings */
1803 /* Select which path to receive for CCK_1 & CCK_2 */
1804 odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
1805 /* @Fix CCK PHY status report issue */
1806 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
1807 /* @CCK complete HW AntDiv within 64 samples */
1808 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
1809 /* @BT Coexistence */
1810 /* @keep antsel_map when GNT_BT = 1 */
1811 odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
1812 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1813 odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
1814 /* response TX ant by RX ant */
1815 odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
1816 #if (defined(CONFIG_2T4R_ANTENNA))
1817 PHYDM_DBG(dm, DBG_ANT_DIV,
1818 "***8822B AntDiv_Init => 2T4R case\n");
1819 /* Pin Settings */
1820 odm_set_bb_reg(dm, R_0xeb8, BIT(21) | BIT(20), 0x1);
1821 odm_set_bb_reg(dm, R_0xeb8, BIT(23) | BIT(22), 0x1);
1822 odm_set_bb_reg(dm, R_0xe1c, BIT(7) | BIT(6), 0x0);
1823 /* @BT Coexistence */
1824 odm_set_bb_reg(dm, R_0xeac, BIT(9), 1);
1825 /* @keep antsel_map when GNT_BT = 1 */
1826 /* Mapping table */
1827 /* antenna mapping table */
1828 odm_set_bb_reg(dm, R_0xea4, 0xFFFF, 0x0100);
1829 /*odm_set_bb_reg(dm, R_0x900, 0x30000, 0x3);*/
1830 #endif
1831
1832 #ifdef ODM_EVM_ENHANCE_ANTDIV
1833 phydm_evm_sw_antdiv_init(dm);
1834 #endif
1835 }
1836 #endif /* @#if (RTL8822B_SUPPORT == 1) */
1837
1838 #if (RTL8197F_SUPPORT == 1)
phydm_rx_hw_ant_div_init_97f(void * dm_void)1839 void phydm_rx_hw_ant_div_init_97f(void *dm_void)
1840 {
1841 struct dm_struct *dm = (struct dm_struct *)dm_void;
1842 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1843
1844 #if 0
1845 if (*dm->mp_mode == true) {
1846 odm_ant_div_on_off(dm, ANTDIV_OFF);
1847 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
1848 /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */
1849 odm_set_bb_reg(dm, R_0xc50, BIT(9), 1); /* @1:CG, 0:CS */
1850 return;
1851 }
1852 #endif
1853 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1854
1855 /* Pin Settings */
1856 odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
1857 /* reg870[8]=1'b0, */ /* "antsel" is controlled by HWs */
1858 odm_set_bb_reg(dm, R_0xc50, BIT(8), 1);
1859 /* regc50[8]=1'b1 *//*"CS/CG switching" is controlled by HWs */
1860
1861 /* @Mapping table */
1862 odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
1863 /* @antenna mapping table */
1864
1865 /* OFDM Settings */
1866 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
1867 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
1868
1869 /* @CCK Settings */
1870 odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
1871 /* Select which path to receive for CCK_1 & CCK_2 */
1872 odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
1873 /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1874 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
1875 /* @Fix CCK PHY status report issue */
1876 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
1877 /* @CCK complete HW AntDiv within 64 samples */
1878
1879 #ifdef ODM_EVM_ENHANCE_ANTDIV
1880 phydm_evm_sw_antdiv_init(dm);
1881 #endif
1882 }
1883 #endif //#if (RTL8197F_SUPPORT == 1)
1884
1885 #if (RTL8197G_SUPPORT == 1)
phydm_rx_hw_ant_div_init_97g(void * dm_void)1886 void phydm_rx_hw_ant_div_init_97g(void *dm_void)
1887 {
1888 struct dm_struct *dm = (struct dm_struct *)dm_void;
1889 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1890
1891 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1892
1893 /* Pin Settings */
1894 odm_set_bb_reg(dm, R_0x1884, BIT(23), 0);
1895 /* reg1844[23]=1'b0 *//*"CS/CG switching" is controlled by HWs*/
1896 odm_set_bb_reg(dm, R_0x1884, BIT(16), 1);
1897 /* reg1844[16]=1'b1 *//*"antsel" is controlled by HWs*/
1898
1899 /* @Mapping table */
1900 odm_set_bb_reg(dm, R_0x1870, 0xFFFF, 0x0100);
1901 /* @antenna mapping table */
1902
1903 /* OFDM Settings */
1904 odm_set_bb_reg(dm, R_0x1938, 0xFFE0, 0xA0); /* thershold */
1905 odm_set_bb_reg(dm, R_0x1938, 0x7FF0000, 0x0); /* @bias */
1906
1907
1908 #ifdef ODM_EVM_ENHANCE_ANTDIV
1909 phydm_evm_sw_antdiv_init(dm);
1910 #endif
1911 }
1912 #endif //#if (RTL8197F_SUPPORT == 1)
1913
1914 #if (RTL8723F_SUPPORT == 1)
phydm_rx_hw_ant_div_init_23f(void * dm_void)1915 void phydm_rx_hw_ant_div_init_23f(void *dm_void)
1916 {
1917 struct dm_struct *dm = (struct dm_struct *)dm_void;
1918 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1919
1920 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1921 /* @3 --RFE pin setting--------- */
1922 /* @[MAC] */
1923 /* @gpioA_11,gpioA_12*/
1924 odm_set_mac_reg(dm, R_0x10d8, 0xFF000000, 0x16);
1925 odm_set_mac_reg(dm, R_0x10dc, 0xFF, 0x16);
1926 /* @[BB] */
1927 odm_set_bb_reg(dm, R_0x1c94, BIT(2) | BIT(3), 0x3); /* output enable */
1928 odm_set_bb_reg(dm, R_0x1ca0, BIT(2) | BIT(3), 0x0);
1929 odm_set_bb_reg(dm, R_0x1c98, BIT(4) | BIT(5), 0x0);
1930 /* r_rfe_path_sel_ (RFE_CTRL_2) */
1931 odm_set_bb_reg(dm, R_0x1c98, BIT(6) | BIT(7), 0x0);
1932 /* r_rfe_path_sel_ (RFE_CTRL_3) */
1933 odm_set_bb_reg(dm, R_0x1838, BIT(28), 0); /* RFE_buffer_en */
1934 odm_set_bb_reg(dm, R_0x183c, BIT(2), 1); /* rfe_inv (RFE_CTRL_2) */
1935 odm_set_bb_reg(dm, R_0x183c, BIT(3), 0); /* rfe_inv (RFE_CTRL_3) */
1936 odm_set_bb_reg(dm, R_0x1840, 0xF00, 0x8); /* path-A, RFE_CTRL_2 */
1937 odm_set_bb_reg(dm, R_0x1840, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */
1938 /* @3 ------------------------- */
1939
1940 /* Pin Settings */
1941 odm_set_bb_reg(dm, R_0x1884, BIT(23), 0);
1942 odm_set_bb_reg(dm, R_0x1884, BIT(25), 0);
1943 /* reg1844[23]=1'b0 *//*"CG switching" is controlled by HWs*/
1944 /* reg1844[25]=1'b0 *//*"CG switching" is controlled by HWs*/
1945 odm_set_bb_reg(dm, R_0x1884, BIT(16), 1);
1946 /* reg1844[16]=1'b1 *//*"antsel" is controlled by HWs*/
1947
1948 /* @Mapping table */
1949 odm_set_bb_reg(dm, R_0x1870, 0xFFFF, 0x0100);
1950 /* @antenna mapping table */
1951
1952 /* OFDM Settings */
1953 odm_set_bb_reg(dm, R_0x1938, 0xFFE0, 0xA0); /* thershold */
1954 odm_set_bb_reg(dm, R_0x1938, 0x7FF0000, 0x0); /* @bias */
1955 #ifdef ODM_EVM_ENHANCE_ANTDIV
1956 phydm_evm_sw_antdiv_init(dm);
1957 #endif
1958 }
1959 #endif //#if (RTL8723F_SUPPORT == 1)
1960
1961 #if (RTL8723D_SUPPORT == 1)
odm_trx_hw_ant_div_init_8723d(void * dm_void)1962 void odm_trx_hw_ant_div_init_8723d(void *dm_void)
1963 {
1964 struct dm_struct *dm = (struct dm_struct *)dm_void;
1965
1966 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1967
1968 /*@BT Coexistence*/
1969 /*@keep antsel_map when GNT_BT = 1*/
1970 odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
1971 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1972 odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
1973 /* @Disable hw antsw & fast_train.antsw when BT TX/RX */
1974 odm_set_bb_reg(dm, R_0xe64, 0xFFFF0000, 0x000c);
1975
1976 odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
1977 #if 0
1978 /*PTA setting: WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL)*/
1979 /*odm_set_bb_reg(dm, R_0x948, BIT6, 0);*/
1980 /*odm_set_bb_reg(dm, R_0x948, BIT8, 0);*/
1981 #endif
1982 /*@GNT_WL tx*/
1983 odm_set_bb_reg(dm, R_0x950, BIT(29), 0);
1984
1985 /*@Mapping Table*/
1986 odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
1987 odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 3);
1988 #if 0
1989 /* odm_set_bb_reg(dm, R_0x864, BIT5|BIT4|BIT3, 0); */
1990 /* odm_set_bb_reg(dm, R_0x864, BIT8|BIT7|BIT6, 1); */
1991 #endif
1992
1993 /* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */
1994 odm_set_bb_reg(dm, R_0xccc, BIT(12), 0);
1995 /* @Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */
1996 odm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01);
1997 /* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */
1998 odm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0);
1999 /* @b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable (CCK)*/
2000 odm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06);
2001 /* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable (CCK) */
2002 odm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00);
2003
2004 /*OFDM HW AntDiv Parameters*/
2005 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0);
2006 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00);
2007 odm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04);
2008
2009 /*@CCK HW AntDiv Parameters*/
2010 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
2011 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
2012 odm_set_bb_reg(dm, R_0xaa8, BIT(8), 0);
2013
2014 odm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf);
2015 odm_set_bb_reg(dm, R_0xa14, 0x1F, 0x8);
2016 odm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1);
2017 odm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0);
2018 odm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1);
2019
2020 /*@disable antenna training */
2021 odm_set_bb_reg(dm, R_0xe08, BIT(16), 0);
2022 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
2023 }
2024 /*@Mingzhi 2017-05-08*/
2025
odm_s0s1_sw_ant_div_init_8723d(void * dm_void)2026 void odm_s0s1_sw_ant_div_init_8723d(void *dm_void)
2027 {
2028 struct dm_struct *dm = (struct dm_struct *)dm_void;
2029 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
2030 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2031
2032 PHYDM_DBG(dm, DBG_ANT_DIV,
2033 "***8723D AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
2034
2035 /*@keep antsel_map when GNT_BT = 1*/
2036 odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
2037
2038 /* @Disable antsw when GNT_BT=1 */
2039 odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
2040
2041 /* @Mapping Table */
2042 odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
2043 odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
2044
2045 /* Output Pin Settings */
2046 #if 0
2047 /* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */
2048 #endif
2049 odm_set_bb_reg(dm, R_0x870, BIT(8), 1);
2050 odm_set_bb_reg(dm, R_0x870, BIT(9), 1);
2051
2052 /* Status init */
2053 fat_tab->is_become_linked = false;
2054 swat_tab->try_flag = SWAW_STEP_INIT;
2055 swat_tab->double_chk_flag = 0;
2056 swat_tab->cur_antenna = MAIN_ANT;
2057 swat_tab->pre_ant = MAIN_ANT;
2058 dm->antdiv_counter = CONFIG_ANTDIV_PERIOD;
2059
2060 /* @2 [--For HW Bug setting] */
2061 odm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant by Reg */
2062 }
2063
odm_update_rx_idle_ant_8723d(void * dm_void,u8 ant,u32 default_ant,u32 optional_ant)2064 void odm_update_rx_idle_ant_8723d(void *dm_void, u8 ant, u32 default_ant,
2065 u32 optional_ant)
2066 {
2067 struct dm_struct *dm = (struct dm_struct *)dm_void;
2068 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2069 void *adapter = dm->adapter;
2070 u8 count = 0;
2071
2072 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
2073 /*score board to BT ,a002:WL to do ant-div*/
2074 odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa002);
2075 ODM_delay_us(50);
2076 #endif
2077 #if 0
2078 /* odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1); */
2079 #endif
2080 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
2081 odm_set_bb_reg(dm, R_0x860, BIT(8), default_ant);
2082 odm_set_bb_reg(dm, R_0x860, BIT(9), default_ant);
2083 }
2084 odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);
2085 /*@Default RX*/
2086 odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);
2087 /*Optional RX*/
2088 odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);
2089 /*@Default TX*/
2090 fat_tab->rx_idle_ant = ant;
2091 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
2092 /*score board to BT ,a000:WL@S1 a001:WL@S0*/
2093 if (default_ant == ANT1_2G)
2094 odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa000);
2095 else
2096 odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa001);
2097 #endif
2098 }
2099
phydm_set_tx_ant_pwr_8723d(void * dm_void,u8 ant)2100 void phydm_set_tx_ant_pwr_8723d(void *dm_void, u8 ant)
2101 {
2102 struct dm_struct *dm = (struct dm_struct *)dm_void;
2103 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2104 void *adapter = dm->adapter;
2105
2106 fat_tab->rx_idle_ant = ant;
2107
2108 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2109 ((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel);
2110 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
2111 rtw_hal_set_tx_power_level(adapter, *dm->channel);
2112 #endif
2113 }
2114 #endif
2115
2116 #if (RTL8723B_SUPPORT == 1)
odm_trx_hw_ant_div_init_8723b(void * dm_void)2117 void odm_trx_hw_ant_div_init_8723b(void *dm_void)
2118 {
2119 struct dm_struct *dm = (struct dm_struct *)dm_void;
2120
2121 PHYDM_DBG(dm, DBG_ANT_DIV,
2122 "***8723B AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV(DPDT)]\n");
2123
2124 /* @Mapping Table */
2125 odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
2126 odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
2127
2128 /* OFDM HW AntDiv Parameters */
2129 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0); /* thershold */
2130 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00); /* @bias */
2131
2132 /* @CCK HW AntDiv Parameters */
2133 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
2134 /* patch for clk from 88M to 80M */
2135 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
2136 /* @do 64 samples */
2137
2138 /* @BT Coexistence */
2139 odm_set_bb_reg(dm, R_0x864, BIT(12), 0);
2140 /* @keep antsel_map when GNT_BT = 1 */
2141 odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
2142 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
2143
2144 /* Output Pin Settings */
2145 odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
2146
2147 odm_set_bb_reg(dm, R_0x948, BIT(6), 0);
2148 /* WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL) */
2149 odm_set_bb_reg(dm, R_0x948, BIT(7), 0);
2150
2151 odm_set_mac_reg(dm, R_0x40, BIT(3), 1);
2152 odm_set_mac_reg(dm, R_0x38, BIT(11), 1);
2153 odm_set_mac_reg(dm, R_0x4c, BIT(24) | BIT(23), 2);
2154 /* select DPDT_P and DPDT_N as output pin */
2155
2156 odm_set_bb_reg(dm, R_0x944, BIT(0) | BIT(1), 3); /* @in/out */
2157 odm_set_bb_reg(dm, R_0x944, BIT(31), 0);
2158
2159 odm_set_bb_reg(dm, R_0x92c, BIT(1), 0); /* @DPDT_P non-inverse */
2160 odm_set_bb_reg(dm, R_0x92c, BIT(0), 1); /* @DPDT_N inverse */
2161
2162 odm_set_bb_reg(dm, R_0x930, 0xF0, 8); /* @DPDT_P = ANTSEL[0] */
2163 odm_set_bb_reg(dm, R_0x930, 0xF, 8); /* @DPDT_N = ANTSEL[0] */
2164
2165 /* @2 [--For HW Bug setting] */
2166 if (dm->ant_type == ODM_AUTO_ANT)
2167 odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
2168 /* @CCK AntDiv function block enable */
2169 }
2170
odm_s0s1_sw_ant_div_init_8723b(void * dm_void)2171 void odm_s0s1_sw_ant_div_init_8723b(void *dm_void)
2172 {
2173 struct dm_struct *dm = (struct dm_struct *)dm_void;
2174 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
2175 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2176
2177 PHYDM_DBG(dm, DBG_ANT_DIV,
2178 "***8723B AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
2179
2180 /* @Mapping Table */
2181 odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
2182 odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
2183
2184 #if 0
2185 /* Output Pin Settings */
2186 /* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */
2187 #endif
2188 odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
2189
2190 fat_tab->is_become_linked = false;
2191 swat_tab->try_flag = SWAW_STEP_INIT;
2192 swat_tab->double_chk_flag = 0;
2193
2194 /* @2 [--For HW Bug setting] */
2195 odm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant by Reg */
2196 }
2197
odm_update_rx_idle_ant_8723b(void * dm_void,u8 ant,u32 default_ant,u32 optional_ant)2198 void odm_update_rx_idle_ant_8723b(
2199 void *dm_void,
2200 u8 ant,
2201 u32 default_ant,
2202 u32 optional_ant)
2203 {
2204 struct dm_struct *dm = (struct dm_struct *)dm_void;
2205 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2206 void *adapter = dm->adapter;
2207 u8 count = 0;
2208 /*u8 u1_temp;*/
2209 /*u8 h2c_parameter;*/
2210
2211 if (!dm->is_linked && dm->ant_type == ODM_AUTO_ANT) {
2212 PHYDM_DBG(dm, DBG_ANT_DIV,
2213 "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to no link\n");
2214 return;
2215 }
2216
2217 #if 0
2218 /* Send H2C command to FW */
2219 /* @Enable wifi calibration */
2220 h2c_parameter = true;
2221 odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
2222
2223 /* @Check if H2C command sucess or not (0x1e6) */
2224 u1_temp = odm_read_1byte(dm, 0x1e6);
2225 while ((u1_temp != 0x1) && (count < 100)) {
2226 ODM_delay_us(10);
2227 u1_temp = odm_read_1byte(dm, 0x1e6);
2228 count++;
2229 }
2230 PHYDM_DBG(dm, DBG_ANT_DIV,
2231 "[ Update Rx-Idle-ant ] 8723B: H2C command status = %d, count = %d\n",
2232 u1_temp, count);
2233
2234 if (u1_temp == 0x1) {
2235 /* @Check if BT is doing IQK (0x1e7) */
2236 count = 0;
2237 u1_temp = odm_read_1byte(dm, 0x1e7);
2238 while ((!(u1_temp & BIT(0))) && (count < 100)) {
2239 ODM_delay_us(50);
2240 u1_temp = odm_read_1byte(dm, 0x1e7);
2241 count++;
2242 }
2243 PHYDM_DBG(dm, DBG_ANT_DIV,
2244 "[ Update Rx-Idle-ant ] 8723B: BT IQK status = %d, count = %d\n",
2245 u1_temp, count);
2246
2247 if (u1_temp & BIT(0)) {
2248 odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);
2249 odm_set_bb_reg(dm, R_0x948, BIT(9), default_ant);
2250 odm_set_bb_reg(dm, R_0x864, 0x38, default_ant);
2251 /* @Default RX */
2252 odm_set_bb_reg(dm, R_0x864, 0x1c0, optional_ant);
2253 /* @Optional RX */
2254 odm_set_bb_reg(dm, R_0x860, 0x7000, default_ant);
2255 /* @Default TX */
2256 fat_tab->rx_idle_ant = ant;
2257
2258 /* Set TX AGC by S0/S1 */
2259 /* Need to consider Linux driver */
2260 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2261 adapter->hal_func.set_tx_power_level_handler(adapter, *dm->channel);
2262 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
2263 rtw_hal_set_tx_power_level(adapter, *dm->channel);
2264 #endif
2265
2266 /* Set IQC by S0/S1 */
2267 odm_set_iqc_by_rfpath(dm, default_ant);
2268 PHYDM_DBG(dm, DBG_ANT_DIV,
2269 "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n");
2270 } else
2271 PHYDM_DBG(dm, DBG_ANT_DIV,
2272 "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to BT IQK\n");
2273 } else
2274 PHYDM_DBG(dm, DBG_ANT_DIV,
2275 "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to H2C command fail\n");
2276
2277 /* Send H2C command to FW */
2278 /* @Disable wifi calibration */
2279 h2c_parameter = false;
2280 odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
2281 #else
2282
2283 odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);
2284 odm_set_bb_reg(dm, R_0x948, BIT(9), default_ant);
2285 odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);
2286 /*@Default RX*/
2287 odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);
2288 /*Optional RX*/
2289 odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);
2290 /*@Default TX*/
2291 fat_tab->rx_idle_ant = ant;
2292
2293 /* Set TX AGC by S0/S1 */
2294 /* Need to consider Linux driver */
2295 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2296 ((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel);
2297 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
2298 rtw_hal_set_tx_power_level(adapter, *dm->channel);
2299 #endif
2300
2301 /* Set IQC by S0/S1 */
2302 odm_set_iqc_by_rfpath(dm, default_ant);
2303 PHYDM_DBG(dm, DBG_ANT_DIV,
2304 "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n");
2305
2306 #endif
2307 }
2308
2309 boolean
phydm_is_bt_enable_8723b(void * dm_void)2310 phydm_is_bt_enable_8723b(void *dm_void)
2311 {
2312 struct dm_struct *dm = (struct dm_struct *)dm_void;
2313 u32 bt_state;
2314 #if 0
2315 /*u32 reg75;*/
2316
2317 /*reg75 = odm_get_bb_reg(dm, R_0x74, BIT8);*/
2318 /*odm_set_bb_reg(dm, R_0x74, BIT8, 0x0);*/
2319 #endif
2320 odm_set_bb_reg(dm, R_0xa0, BIT(24) | BIT(25) | BIT(26), 0x5);
2321 bt_state = odm_get_bb_reg(dm, R_0xa0, 0xf);
2322 #if 0
2323 /*odm_set_bb_reg(dm, R_0x74, BIT8, reg75);*/
2324 #endif
2325
2326 if (bt_state == 4 || bt_state == 7 || bt_state == 9 || bt_state == 13)
2327 return true;
2328 else
2329 return false;
2330 }
2331 #endif /* @#if (RTL8723B_SUPPORT == 1) */
2332
2333 #if (RTL8821A_SUPPORT == 1)
2334
odm_trx_hw_ant_div_init_8821a(void * dm_void)2335 void odm_trx_hw_ant_div_init_8821a(void *dm_void)
2336 {
2337 struct dm_struct *dm = (struct dm_struct *)dm_void;
2338
2339 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
2340
2341 /* Output Pin Settings */
2342 odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
2343
2344 odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
2345 odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
2346
2347 odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
2348
2349 odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
2350 /* select DPDT_P and DPDT_N as output pin */
2351 odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
2352 odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
2353 odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
2354 odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
2355 odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
2356
2357 /* @Mapping Table */
2358 odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
2359 odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
2360
2361 /* OFDM HW AntDiv Parameters */
2362 odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
2363 odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
2364
2365 /* @CCK HW AntDiv Parameters */
2366 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
2367 /* patch for clk from 88M to 80M */
2368 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
2369
2370 odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
2371 /* @ANTSEL_CCK sent to the smart_antenna circuit */
2372 odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
2373 /* @CCK AntDiv function block enable */
2374
2375 /* @BT Coexistence */
2376 odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
2377 /* @keep antsel_map when GNT_BT = 1 */
2378 odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
2379 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
2380
2381 odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
2382 /* settling time of antdiv by RF LNA = 100ns */
2383
2384 /* response TX ant by RX ant */
2385 odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
2386 }
2387
odm_s0s1_sw_ant_div_init_8821a(void * dm_void)2388 void odm_s0s1_sw_ant_div_init_8821a(void *dm_void)
2389 {
2390 struct dm_struct *dm = (struct dm_struct *)dm_void;
2391 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
2392
2393 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
2394
2395 /* Output Pin Settings */
2396 odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
2397
2398 odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
2399 odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
2400
2401 odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
2402
2403 odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
2404 /* select DPDT_P and DPDT_N as output pin */
2405 odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
2406 odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
2407 odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
2408 odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
2409 odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
2410
2411 /* @Mapping Table */
2412 odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
2413 odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
2414
2415 /* OFDM HW AntDiv Parameters */
2416 odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
2417 odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
2418
2419 /* @CCK HW AntDiv Parameters */
2420 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
2421 /* patch for clk from 88M to 80M */
2422 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
2423
2424 odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
2425 /* @ANTSEL_CCK sent to the smart_antenna circuit */
2426 odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
2427 /* @CCK AntDiv function block enable */
2428
2429 /* @BT Coexistence */
2430 odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
2431 /* @keep antsel_map when GNT_BT = 1 */
2432 odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
2433 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
2434
2435 odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
2436 /* settling time of antdiv by RF LNA = 100ns */
2437
2438 /* response TX ant by RX ant */
2439 odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
2440
2441 odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
2442
2443 swat_tab->try_flag = SWAW_STEP_INIT;
2444 swat_tab->double_chk_flag = 0;
2445 swat_tab->cur_antenna = MAIN_ANT;
2446 swat_tab->pre_ant = MAIN_ANT;
2447 swat_tab->swas_no_link_state = 0;
2448 }
2449 #endif /* @#if (RTL8821A_SUPPORT == 1) */
2450
2451 #if (RTL8821C_SUPPORT == 1)
odm_trx_hw_ant_div_init_8821c(void * dm_void)2452 void odm_trx_hw_ant_div_init_8821c(void *dm_void)
2453 {
2454 struct dm_struct *dm = (struct dm_struct *)dm_void;
2455
2456 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
2457 /* Output Pin Settings */
2458 odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
2459
2460 odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
2461 odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
2462
2463 odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
2464
2465 odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
2466 /* select DPDT_P and DPDT_N as output pin */
2467 odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
2468 odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
2469 odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
2470 odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
2471 odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
2472
2473 /* @Mapping Table */
2474 odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
2475 odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
2476
2477 /* OFDM HW AntDiv Parameters */
2478 odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
2479 odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
2480
2481 /* @CCK HW AntDiv Parameters */
2482 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
2483 /* patch for clk from 88M to 80M */
2484 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
2485
2486 odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
2487 /* @ANTSEL_CCK sent to the smart_antenna circuit */
2488 odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
2489 /* @CCK AntDiv function block enable */
2490
2491 /* @BT Coexistence */
2492 odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
2493 /* @keep antsel_map when GNT_BT = 1 */
2494 odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
2495 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
2496
2497 /* Timming issue */
2498 odm_set_bb_reg(dm, R_0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), 0);
2499 /*@keep antidx after tx for ACK ( unit x 3.2 mu sec)*/
2500 odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
2501 /* settling time of antdiv by RF LNA = 100ns */
2502
2503 /* response TX ant by RX ant */
2504 odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
2505 }
2506
phydm_s0s1_sw_ant_div_init_8821c(void * dm_void)2507 void phydm_s0s1_sw_ant_div_init_8821c(void *dm_void)
2508 {
2509 struct dm_struct *dm = (struct dm_struct *)dm_void;
2510 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
2511
2512 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
2513
2514 /* Output Pin Settings */
2515 odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
2516
2517 odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
2518 odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
2519
2520 odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
2521
2522 odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
2523 /* select DPDT_P and DPDT_N as output pin */
2524 odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
2525 odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
2526 odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
2527 odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
2528 odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
2529
2530 /* @Mapping Table */
2531 odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
2532 odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
2533
2534 /* OFDM HW AntDiv Parameters */
2535 odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
2536 odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x00); /* @bias */
2537
2538 /* @CCK HW AntDiv Parameters */
2539 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
2540 /* patch for clk from 88M to 80M */
2541 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
2542
2543 odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
2544 /* @ANTSEL_CCK sent to the smart_antenna circuit */
2545 odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
2546 /* @CCK AntDiv function block enable */
2547
2548 /* @BT Coexistence */
2549 odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
2550 /* @keep antsel_map when GNT_BT = 1 */
2551 odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
2552 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
2553
2554 odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
2555 /* settling time of antdiv by RF LNA = 100ns */
2556
2557 /* response TX ant by RX ant */
2558 odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
2559
2560 odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
2561
2562 swat_tab->try_flag = SWAW_STEP_INIT;
2563 swat_tab->double_chk_flag = 0;
2564 swat_tab->cur_antenna = MAIN_ANT;
2565 swat_tab->pre_ant = MAIN_ANT;
2566 swat_tab->swas_no_link_state = 0;
2567 }
2568 #endif /* @#if (RTL8821C_SUPPORT == 1) */
2569
2570 #if (RTL8195B_SUPPORT == 1)
odm_trx_hw_ant_div_init_8195b(void * dm_void)2571 void odm_trx_hw_ant_div_init_8195b(void *dm_void)
2572 {
2573 struct dm_struct *dm = (struct dm_struct *)dm_void;
2574
2575 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
2576
2577 odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
2578 /*RFE control pin 0,1*/
2579 odm_set_bb_reg(dm, R_0xcb0, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
2580 odm_set_bb_reg(dm, R_0xcb0, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
2581 odm_set_bb_reg(dm, R_0xcb4, BIT(20), 0); /* @DPDT_P non-inverse */
2582 odm_set_bb_reg(dm, R_0xcb4, BIT(21), 1); /* @DPDT_N inverse */
2583
2584 /* @Mapping Table */
2585 odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
2586 odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
2587
2588 /* OFDM HW AntDiv Parameters */
2589 odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
2590 odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
2591
2592 /* @CCK HW AntDiv Parameters */
2593 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
2594 /* patch for clk from 88M to 80M */
2595 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
2596
2597 odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
2598 /* @ANTSEL_CCK sent to the smart_antenna circuit */
2599 odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
2600 /* @CCK AntDiv function block enable */
2601
2602 /* @BT Coexistence */
2603 odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
2604 /* @keep antsel_map when GNT_BT = 1 */
2605 odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
2606 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
2607
2608 /* Timming issue */
2609 odm_set_bb_reg(dm, R_0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), 0);
2610 /*@keep antidx after tx for ACK ( unit x 3.2 mu sec)*/
2611 odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
2612 /* settling time of antdiv by RF LNA = 100ns */
2613
2614 /* response TX ant by RX ant */
2615 odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
2616 }
2617 #endif /* @#if (RTL8195B_SUPPORT == 1) */
2618
2619 #if (RTL8881A_SUPPORT == 1)
odm_trx_hw_ant_div_init_8881a(void * dm_void)2620 void odm_trx_hw_ant_div_init_8881a(void *dm_void)
2621 {
2622 struct dm_struct *dm = (struct dm_struct *)dm_void;
2623
2624 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
2625
2626 /* Output Pin Settings */
2627 /* @[SPDT related] */
2628 odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
2629 odm_set_mac_reg(dm, R_0x4c, BIT(26), 0);
2630 odm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */
2631 odm_set_bb_reg(dm, R_0xcb4, BIT(22), 0);
2632 odm_set_bb_reg(dm, R_0xcb4, BIT(24), 1);
2633 odm_set_bb_reg(dm, R_0xcb0, 0xF00, 8); /* @DPDT_P = ANTSEL[0] */
2634 odm_set_bb_reg(dm, R_0xcb0, 0xF0000, 8); /* @DPDT_N = ANTSEL[0] */
2635
2636 /* @Mapping Table */
2637 odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
2638 odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
2639
2640 /* OFDM HW AntDiv Parameters */
2641 odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
2642 odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */
2643 odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
2644 /* settling time of antdiv by RF LNA = 100ns */
2645
2646 /* @CCK HW AntDiv Parameters */
2647 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
2648 /* patch for clk from 88M to 80M */
2649 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
2650
2651 /* @2 [--For HW Bug setting] */
2652
2653 odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
2654 /* TX ant by Reg *//* A-cut bug */
2655 }
2656
2657 #endif /* @#if (RTL8881A_SUPPORT == 1) */
2658
2659 #if (RTL8812A_SUPPORT == 1)
odm_trx_hw_ant_div_init_8812a(void * dm_void)2660 void odm_trx_hw_ant_div_init_8812a(void *dm_void)
2661 {
2662 struct dm_struct *dm = (struct dm_struct *)dm_void;
2663
2664 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
2665
2666 /* @3 */ /* @3 --RFE pin setting--------- */
2667 /* @[BB] */
2668 odm_set_bb_reg(dm, R_0x900, BIT(10) | BIT(9) | BIT(8), 0x0);
2669 /* @disable SW switch */
2670 odm_set_bb_reg(dm, R_0x900, BIT(17) | BIT(16), 0x0);
2671 odm_set_bb_reg(dm, R_0x974, BIT(7) | BIT(6), 0x3); /* @in/out */
2672 odm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */
2673 odm_set_bb_reg(dm, R_0xcb4, BIT(26), 0);
2674 odm_set_bb_reg(dm, R_0xcb4, BIT(27), 1);
2675 odm_set_bb_reg(dm, R_0xcb0, 0xF000000, 8); /* @DPDT_P = ANTSEL[0] */
2676 odm_set_bb_reg(dm, R_0xcb0, 0xF0000000, 8); /* @DPDT_N = ANTSEL[0] */
2677 /* @3 ------------------------- */
2678
2679 /* @Mapping Table */
2680 odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
2681 odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
2682
2683 /* OFDM HW AntDiv Parameters */
2684 odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
2685 odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */
2686 odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
2687 /* settling time of antdiv by RF LNA = 100ns */
2688
2689 /* @CCK HW AntDiv Parameters */
2690 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
2691 /* patch for clk from 88M to 80M */
2692 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
2693
2694 /* @2 [--For HW Bug setting] */
2695
2696 odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
2697 /* TX ant by Reg */ /* A-cut bug */
2698 }
2699
2700 #endif /* @#if (RTL8812A_SUPPORT == 1) */
2701
2702 #if (RTL8188F_SUPPORT == 1)
odm_s0s1_sw_ant_div_init_8188f(void * dm_void)2703 void odm_s0s1_sw_ant_div_init_8188f(void *dm_void)
2704 {
2705 struct dm_struct *dm = (struct dm_struct *)dm_void;
2706 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
2707 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2708
2709 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
2710
2711 #if 0
2712 /*@GPIO setting*/
2713 /*odm_set_mac_reg(dm, R_0x64, BIT(18), 0); */
2714 /*odm_set_mac_reg(dm, R_0x44, BIT(28)|BIT(27), 0);*/
2715 /*odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3);*/
2716 /*enable_output for P_GPIO[4:3]*/
2717 /*odm_set_mac_reg(dm, R_0x44, BIT(12)|BIT(11), 0);*/ /*output value*/
2718 /*odm_set_mac_reg(dm, R_0x40, BIT(1)|BIT(0), 0);*/ /*GPIO function*/
2719 #endif
2720
2721 if (dm->support_ic_type == ODM_RTL8188F) {
2722 if (dm->support_interface == ODM_ITRF_USB)
2723 odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3);
2724 /*@enable_output for P_GPIO[4:3]*/
2725 else if (dm->support_interface == ODM_ITRF_SDIO)
2726 odm_set_mac_reg(dm, R_0x44, BIT(18), 0x1);
2727 /*@enable_output for P_GPIO[2]*/
2728 }
2729
2730 fat_tab->is_become_linked = false;
2731 swat_tab->try_flag = SWAW_STEP_INIT;
2732 swat_tab->double_chk_flag = 0;
2733 }
2734
phydm_update_rx_idle_antenna_8188F(void * dm_void,u32 default_ant)2735 void phydm_update_rx_idle_antenna_8188F(void *dm_void, u32 default_ant)
2736 {
2737 struct dm_struct *dm = (struct dm_struct *)dm_void;
2738 u8 codeword;
2739
2740 if (dm->support_ic_type == ODM_RTL8188F) {
2741 if (dm->support_interface == ODM_ITRF_USB) {
2742 if (default_ant == ANT1_2G)
2743 codeword = 1; /*@2'b01*/
2744 else
2745 codeword = 2; /*@2'b10*/
2746 odm_set_mac_reg(dm, R_0x44, 0x1800, codeword);
2747 /*@GPIO[4:3] output value*/
2748 } else if (dm->support_interface == ODM_ITRF_SDIO) {
2749 if (default_ant == ANT1_2G) {
2750 codeword = 0; /*@1'b0*/
2751 odm_set_bb_reg(dm, R_0x870, 0x300, 0x3);
2752 odm_set_bb_reg(dm, R_0x860, 0x300, 0x1);
2753 } else {
2754 codeword = 1; /*@1'b1*/
2755 odm_set_bb_reg(dm, R_0x870, 0x300, 0x3);
2756 odm_set_bb_reg(dm, R_0x860, 0x300, 0x2);
2757 }
2758 odm_set_mac_reg(dm, R_0x44, BIT(10), codeword);
2759 /*@GPIO[2] output value*/
2760 }
2761 }
2762 }
2763 #endif
2764
2765 #ifdef ODM_EVM_ENHANCE_ANTDIV
phydm_rx_rate_for_antdiv(void * dm_void,void * pkt_info_void)2766 void phydm_rx_rate_for_antdiv(void *dm_void, void *pkt_info_void)
2767 {
2768 struct dm_struct *dm = (struct dm_struct *)dm_void;
2769 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2770 struct phydm_perpkt_info_struct *pktinfo = NULL;
2771 u8 data_rate = 0;
2772
2773 pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
2774 data_rate = pktinfo->data_rate & 0x7f;
2775
2776 if (!fat_tab->get_stats)
2777 return;
2778
2779 if (fat_tab->antsel_rx_keep_0 == ANT1_2G) {
2780 if (data_rate >= ODM_RATEMCS0 &&
2781 data_rate <= ODM_RATEMCS15)
2782 fat_tab->main_ht_cnt[data_rate - ODM_RATEMCS0]++;
2783 else if (data_rate >= ODM_RATEVHTSS1MCS0 &&
2784 data_rate <= ODM_RATEVHTSS2MCS9)
2785 fat_tab->main_vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++;
2786 } else { /*ANT2_2G*/
2787 if (data_rate >= ODM_RATEMCS0 &&
2788 data_rate <= ODM_RATEMCS15)
2789 fat_tab->aux_ht_cnt[data_rate - ODM_RATEMCS0]++;
2790 else if (data_rate >= ODM_RATEVHTSS1MCS0 &&
2791 data_rate <= ODM_RATEVHTSS2MCS9)
2792 fat_tab->aux_vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++;
2793 }
2794 }
2795
phydm_antdiv_reset_rx_rate(void * dm_void)2796 void phydm_antdiv_reset_rx_rate(void *dm_void)
2797 {
2798 struct dm_struct *dm = (struct dm_struct *)dm_void;
2799 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2800
2801 odm_memory_set(dm, &fat_tab->main_ht_cnt[0], 0, HT_IDX * 2);
2802 odm_memory_set(dm, &fat_tab->aux_ht_cnt[0], 0, HT_IDX * 2);
2803 odm_memory_set(dm, &fat_tab->main_vht_cnt[0], 0, VHT_IDX * 2);
2804 odm_memory_set(dm, &fat_tab->aux_vht_cnt[0], 0, VHT_IDX * 2);
2805 }
2806
phydm_statistics_evm_1ss(void * dm_void,void * phy_info_void,u8 antsel_tr_mux,u32 id,u32 utility)2807 void phydm_statistics_evm_1ss(void *dm_void, void *phy_info_void,
2808 u8 antsel_tr_mux, u32 id, u32 utility)
2809 {
2810 struct dm_struct *dm = (struct dm_struct *)dm_void;
2811 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2812 struct phydm_phyinfo_struct *phy_info = NULL;
2813
2814 phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
2815 if (antsel_tr_mux == ANT1_2G) {
2816 fat_tab->main_evm_sum[id] += ((phy_info->rx_mimo_evm_dbm[0])
2817 << 5);
2818 fat_tab->main_evm_cnt[id]++;
2819 } else {
2820 fat_tab->aux_evm_sum[id] += ((phy_info->rx_mimo_evm_dbm[0])
2821 << 5);
2822 fat_tab->aux_evm_cnt[id]++;
2823 }
2824 }
2825
phydm_statistics_evm_2ss(void * dm_void,void * phy_info_void,u8 antsel_tr_mux,u32 id,u32 utility)2826 void phydm_statistics_evm_2ss(void *dm_void, void *phy_info_void,
2827 u8 antsel_tr_mux, u32 id, u32 utility)
2828 {
2829 struct dm_struct *dm = (struct dm_struct *)dm_void;
2830 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2831 struct phydm_phyinfo_struct *phy_info = NULL;
2832
2833 phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
2834 if (antsel_tr_mux == ANT1_2G) {
2835 fat_tab->main_evm_2ss_sum[id][0] += phy_info->rx_mimo_evm_dbm[0]
2836 << 5;
2837 fat_tab->main_evm_2ss_sum[id][1] += phy_info->rx_mimo_evm_dbm[1]
2838 << 5;
2839 fat_tab->main_evm_2ss_cnt[id]++;
2840
2841 } else {
2842 fat_tab->aux_evm_2ss_sum[id][0] += (phy_info->rx_mimo_evm_dbm[0]
2843 << 5);
2844 fat_tab->aux_evm_2ss_sum[id][1] += (phy_info->rx_mimo_evm_dbm[1]
2845 << 5);
2846 fat_tab->aux_evm_2ss_cnt[id]++;
2847 }
2848 }
2849
phydm_evm_sw_antdiv_init(void * dm_void)2850 void phydm_evm_sw_antdiv_init(void *dm_void)
2851 {
2852 struct dm_struct *dm = (struct dm_struct *)dm_void;
2853 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2854
2855 /*@EVM enhance AntDiv method init----------------*/
2856 fat_tab->evm_method_enable = 0;
2857 fat_tab->fat_state = NORMAL_STATE_MIAN;
2858 fat_tab->fat_state_cnt = 0;
2859 fat_tab->pre_antdiv_rssi = 0;
2860
2861 dm->antdiv_intvl = 30;
2862 dm->antdiv_delay = 20;
2863 dm->antdiv_train_num = 4;
2864 if (dm->support_ic_type & ODM_RTL8192E)
2865 odm_set_bb_reg(dm, R_0x910, 0x3f, 0xf);
2866 dm->antdiv_evm_en = 1;
2867 /*@dm->antdiv_period=1;*/
2868 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2869 dm->evm_antdiv_period = 1;
2870 #else
2871 dm->evm_antdiv_period = 3;
2872 #endif
2873 dm->stop_antdiv_rssi_th = 3;
2874 dm->stop_antdiv_tp_th = 80;
2875 dm->antdiv_tp_period = 3;
2876 dm->stop_antdiv_tp_diff_th = 5;
2877 }
2878
odm_evm_fast_ant_reset(void * dm_void)2879 void odm_evm_fast_ant_reset(void *dm_void)
2880 {
2881 struct dm_struct *dm = (struct dm_struct *)dm_void;
2882 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2883
2884 fat_tab->evm_method_enable = 0;
2885 if (fat_tab->div_path_type == ANT_PATH_A)
2886 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
2887 else if (fat_tab->div_path_type == ANT_PATH_B)
2888 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
2889 else if (fat_tab->div_path_type == ANT_PATH_AB)
2890 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
2891 fat_tab->fat_state = NORMAL_STATE_MIAN;
2892 fat_tab->fat_state_cnt = 0;
2893 dm->antdiv_period = 0;
2894 odm_set_mac_reg(dm, R_0x608, BIT(8), 0);
2895 }
2896
odm_evm_enhance_ant_div(void * dm_void)2897 void odm_evm_enhance_ant_div(void *dm_void)
2898 {
2899 struct dm_struct *dm = (struct dm_struct *)dm_void;
2900 u32 main_rssi, aux_rssi;
2901 u32 main_crc_utility = 0, aux_crc_utility = 0, utility_ratio = 1;
2902 u32 main_evm, aux_evm, diff_rssi = 0, diff_EVM = 0;
2903 u32 main_2ss_evm[2], aux_2ss_evm[2];
2904 u32 main_1ss_evm, aux_1ss_evm;
2905 u32 main_2ss_evm_sum, aux_2ss_evm_sum;
2906 u8 score_EVM = 0, score_CRC = 0;
2907 u8 rssi_larger_ant = 0;
2908 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2909 u32 value32, i, mac_id;
2910 boolean main_above1 = false, aux_above1 = false;
2911 boolean force_antenna = false;
2912 struct cmn_sta_info *sta;
2913 u32 main_tp_avg, aux_tp_avg;
2914 u8 curr_rssi, rssi_diff;
2915 u32 tp_diff, tp_diff_avg;
2916 u16 main_max_cnt = 0, aux_max_cnt = 0;
2917 u16 main_max_idx = 0, aux_max_idx = 0;
2918 u16 main_cnt_all = 0, aux_cnt_all = 0;
2919 u8 rate_num = dm->num_rf_path;
2920 u8 rate_ss_shift = 0;
2921 u8 tp_diff_return = 0, tp_return = 0, rssi_return = 0;
2922 u8 target_ant_evm_1ss, target_ant_evm_2ss;
2923 u8 decision_evm_ss;
2924 u8 next_ant;
2925
2926 fat_tab->target_ant_enhance = 0xFF;
2927
2928 if ((dm->support_ic_type & ODM_EVM_ANTDIV_IC)) {
2929 if (dm->is_one_entry_only) {
2930 #if 0
2931 /* PHYDM_DBG(dm,DBG_ANT_DIV, "[One Client only]\n"); */
2932 #endif
2933 mac_id = dm->one_entry_macid;
2934 sta = dm->phydm_sta_info[mac_id];
2935
2936 main_rssi = (fat_tab->main_cnt[mac_id] != 0) ? (fat_tab->main_sum[mac_id] / fat_tab->main_cnt[mac_id]) : 0;
2937 aux_rssi = (fat_tab->aux_cnt[mac_id] != 0) ? (fat_tab->aux_sum[mac_id] / fat_tab->aux_cnt[mac_id]) : 0;
2938
2939 if ((main_rssi == 0 && aux_rssi != 0 && aux_rssi >= FORCE_RSSI_DIFF) || (main_rssi != 0 && aux_rssi == 0 && main_rssi >= FORCE_RSSI_DIFF))
2940 diff_rssi = FORCE_RSSI_DIFF;
2941 else if (main_rssi != 0 && aux_rssi != 0)
2942 diff_rssi = (main_rssi >= aux_rssi) ? (main_rssi - aux_rssi) : (aux_rssi - main_rssi);
2943
2944 if (main_rssi >= aux_rssi)
2945 rssi_larger_ant = MAIN_ANT;
2946 else
2947 rssi_larger_ant = AUX_ANT;
2948
2949 PHYDM_DBG(dm, DBG_ANT_DIV,
2950 "Main_Cnt=(( %d )), main_rssi=(( %d ))\n",
2951 fat_tab->main_cnt[mac_id], main_rssi);
2952 PHYDM_DBG(dm, DBG_ANT_DIV,
2953 "Aux_Cnt=(( %d )), aux_rssi=(( %d ))\n",
2954 fat_tab->aux_cnt[mac_id], aux_rssi);
2955
2956 if (((main_rssi >= evm_rssi_th_high || aux_rssi >= evm_rssi_th_high) || fat_tab->evm_method_enable == 1)
2957 /* @&& (diff_rssi <= FORCE_RSSI_DIFF + 1) */
2958 ) {
2959 PHYDM_DBG(dm, DBG_ANT_DIV,
2960 "> TH_H || evm_method_enable==1\n");
2961
2962 if ((main_rssi >= evm_rssi_th_low || aux_rssi >= evm_rssi_th_low)) {
2963 PHYDM_DBG(dm, DBG_ANT_DIV, "> TH_L, fat_state_cnt =((%d))\n", fat_tab->fat_state_cnt);
2964
2965 /*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)============================================================*/
2966 if (fat_tab->fat_state_cnt < (dm->antdiv_train_num << 1)) {
2967 if (fat_tab->fat_state_cnt == 0) {
2968 /*Reset EVM 1SS Method */
2969 fat_tab->main_evm_sum[mac_id] = 0;
2970 fat_tab->aux_evm_sum[mac_id] = 0;
2971 fat_tab->main_evm_cnt[mac_id] = 0;
2972 fat_tab->aux_evm_cnt[mac_id] = 0;
2973 /*Reset EVM 2SS Method */
2974 fat_tab->main_evm_2ss_sum[mac_id][0] = 0;
2975 fat_tab->main_evm_2ss_sum[mac_id][1] = 0;
2976 fat_tab->aux_evm_2ss_sum[mac_id][0] = 0;
2977 fat_tab->aux_evm_2ss_sum[mac_id][1] = 0;
2978 fat_tab->main_evm_2ss_cnt[mac_id] = 0;
2979 fat_tab->aux_evm_2ss_cnt[mac_id] = 0;
2980
2981 /*Reset TP Method */
2982 fat_tab->main_tp = 0;
2983 fat_tab->aux_tp = 0;
2984 fat_tab->main_tp_cnt = 0;
2985 fat_tab->aux_tp_cnt = 0;
2986 phydm_antdiv_reset_rx_rate(dm);
2987
2988 /*Reset CRC Method */
2989 fat_tab->main_crc32_ok_cnt = 0;
2990 fat_tab->main_crc32_fail_cnt = 0;
2991 fat_tab->aux_crc32_ok_cnt = 0;
2992 fat_tab->aux_crc32_fail_cnt = 0;
2993
2994 #ifdef SKIP_EVM_ANTDIV_TRAINING_PATCH
2995 if ((*dm->band_width == CHANNEL_WIDTH_20) && sta->mimo_type == RF_2T2R) {
2996 /*@1. Skip training: RSSI*/
2997 #if 0
2998 /*PHYDM_DBG(pDM_Odm,DBG_ANT_DIV, "TargetAnt_enhance=((%d)), RxIdleAnt=((%d))\n", pDM_FatTable->TargetAnt_enhance, pDM_FatTable->RxIdleAnt);*/
2999 #endif
3000 curr_rssi = (u8)((fat_tab->rx_idle_ant == MAIN_ANT) ? main_rssi : aux_rssi);
3001 rssi_diff = (curr_rssi > fat_tab->pre_antdiv_rssi) ? (curr_rssi - fat_tab->pre_antdiv_rssi) : (fat_tab->pre_antdiv_rssi - curr_rssi);
3002
3003 PHYDM_DBG(dm, DBG_ANT_DIV, "[1] rssi_return, curr_rssi=((%d)), pre_rssi=((%d))\n", curr_rssi, fat_tab->pre_antdiv_rssi);
3004
3005 fat_tab->pre_antdiv_rssi = curr_rssi;
3006 if (rssi_diff < dm->stop_antdiv_rssi_th && curr_rssi != 0)
3007 rssi_return = 1;
3008
3009 /*@2. Skip training: TP Diff*/
3010 tp_diff = (dm->rx_tp > fat_tab->pre_antdiv_tp) ? (dm->rx_tp - fat_tab->pre_antdiv_tp) : (fat_tab->pre_antdiv_tp - dm->rx_tp);
3011
3012 PHYDM_DBG(dm, DBG_ANT_DIV, "[2] tp_diff_return, curr_tp=((%d)), pre_tp=((%d))\n", dm->rx_tp, fat_tab->pre_antdiv_tp);
3013 fat_tab->pre_antdiv_tp = dm->rx_tp;
3014 if ((tp_diff < (u32)(dm->stop_antdiv_tp_diff_th) && dm->rx_tp != 0))
3015 tp_diff_return = 1;
3016
3017 PHYDM_DBG(dm, DBG_ANT_DIV, "[3] tp_return, curr_rx_tp=((%d))\n", dm->rx_tp);
3018 /*@3. Skip training: TP*/
3019 if (dm->rx_tp >= (u32)(dm->stop_antdiv_tp_th))
3020 tp_return = 1;
3021
3022 PHYDM_DBG(dm, DBG_ANT_DIV, "[4] Return {rssi, tp_diff, tp} = {%d, %d, %d}\n", rssi_return, tp_diff_return, tp_return);
3023 /*@4. Joint Return Decision*/
3024 if (tp_return) {
3025 if (tp_diff_return || rssi_diff) {
3026 PHYDM_DBG(dm, DBG_ANT_DIV, "***Return EVM SW AntDiv\n");
3027 return;
3028 }
3029 }
3030 }
3031 #endif
3032
3033 fat_tab->evm_method_enable = 1;
3034 if (fat_tab->div_path_type == ANT_PATH_A)
3035 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
3036 else if (fat_tab->div_path_type == ANT_PATH_B)
3037 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
3038 else if (fat_tab->div_path_type == ANT_PATH_AB)
3039 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
3040 dm->antdiv_period = dm->evm_antdiv_period;
3041 odm_set_mac_reg(dm, R_0x608, BIT(8), 1); /*RCR accepts CRC32-Error packets*/
3042 fat_tab->fat_state_cnt++;
3043 fat_tab->get_stats = false;
3044 next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? MAIN_ANT : AUX_ANT;
3045 odm_update_rx_idle_ant(dm, next_ant);
3046 PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv Delay ]\n");
3047 odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_delay); //ms
3048 } else if ((fat_tab->fat_state_cnt % 2) != 0) {
3049 fat_tab->fat_state_cnt++;
3050 fat_tab->get_stats = true;
3051 odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_intvl); //ms
3052 } else if ((fat_tab->fat_state_cnt % 2) == 0) {
3053 fat_tab->fat_state_cnt++;
3054 fat_tab->get_stats = false;
3055 next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
3056 odm_update_rx_idle_ant(dm, next_ant);
3057 PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv Delay ]\n");
3058 odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_delay); //ms
3059 }
3060 }
3061 /*@Decision state: 4==============================================================*/
3062 else {
3063 fat_tab->get_stats = false;
3064 fat_tab->fat_state_cnt = 0;
3065 PHYDM_DBG(dm, DBG_ANT_DIV, "[Decisoin state ]\n");
3066
3067 /* @3 [CRC32 statistic] */
3068 #if 0
3069 if ((fat_tab->main_crc32_ok_cnt > (fat_tab->aux_crc32_ok_cnt << 1)) || (diff_rssi >= 40 && rssi_larger_ant == MAIN_ANT)) {
3070 fat_tab->target_ant_crc32 = MAIN_ANT;
3071 force_antenna = true;
3072 PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Main\n");
3073 } else if ((fat_tab->aux_crc32_ok_cnt > ((fat_tab->main_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == AUX_ANT))) {
3074 fat_tab->target_ant_crc32 = AUX_ANT;
3075 force_antenna = true;
3076 PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Aux\n");
3077 } else
3078 #endif
3079 {
3080 if (fat_tab->main_crc32_fail_cnt <= 5)
3081 fat_tab->main_crc32_fail_cnt = 5;
3082
3083 if (fat_tab->aux_crc32_fail_cnt <= 5)
3084 fat_tab->aux_crc32_fail_cnt = 5;
3085
3086 if (fat_tab->main_crc32_ok_cnt > fat_tab->main_crc32_fail_cnt)
3087 main_above1 = true;
3088
3089 if (fat_tab->aux_crc32_ok_cnt > fat_tab->aux_crc32_fail_cnt)
3090 aux_above1 = true;
3091
3092 if (main_above1 == true && aux_above1 == false) {
3093 force_antenna = true;
3094 fat_tab->target_ant_crc32 = MAIN_ANT;
3095 } else if (main_above1 == false && aux_above1 == true) {
3096 force_antenna = true;
3097 fat_tab->target_ant_crc32 = AUX_ANT;
3098 } else if (main_above1 == true && aux_above1 == true) {
3099 main_crc_utility = ((fat_tab->main_crc32_ok_cnt) << 7) / fat_tab->main_crc32_fail_cnt;
3100 aux_crc_utility = ((fat_tab->aux_crc32_ok_cnt) << 7) / fat_tab->aux_crc32_fail_cnt;
3101 fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility >= aux_crc_utility) ? MAIN_ANT : AUX_ANT);
3102
3103 if (main_crc_utility != 0 && aux_crc_utility != 0) {
3104 if (main_crc_utility >= aux_crc_utility)
3105 utility_ratio = (main_crc_utility << 1) / aux_crc_utility;
3106 else
3107 utility_ratio = (aux_crc_utility << 1) / main_crc_utility;
3108 }
3109 } else if (main_above1 == false && aux_above1 == false) {
3110 if (fat_tab->main_crc32_ok_cnt == 0)
3111 fat_tab->main_crc32_ok_cnt = 1;
3112 if (fat_tab->aux_crc32_ok_cnt == 0)
3113 fat_tab->aux_crc32_ok_cnt = 1;
3114
3115 main_crc_utility = ((fat_tab->main_crc32_fail_cnt) << 7) / fat_tab->main_crc32_ok_cnt;
3116 aux_crc_utility = ((fat_tab->aux_crc32_fail_cnt) << 7) / fat_tab->aux_crc32_ok_cnt;
3117 fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility <= aux_crc_utility) ? MAIN_ANT : AUX_ANT);
3118
3119 if (main_crc_utility != 0 && aux_crc_utility != 0) {
3120 if (main_crc_utility >= aux_crc_utility)
3121 utility_ratio = (main_crc_utility << 1) / (aux_crc_utility);
3122 else
3123 utility_ratio = (aux_crc_utility << 1) / (main_crc_utility);
3124 }
3125 }
3126 }
3127 odm_set_mac_reg(dm, R_0x608, BIT(8), 0); /* NOT Accept CRC32 Error packets. */
3128 PHYDM_DBG(dm, DBG_ANT_DIV, "MAIN_CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->main_crc32_ok_cnt, fat_tab->main_crc32_fail_cnt, main_crc_utility);
3129 PHYDM_DBG(dm, DBG_ANT_DIV, "AUX__CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->aux_crc32_ok_cnt, fat_tab->aux_crc32_fail_cnt, aux_crc_utility);
3130 PHYDM_DBG(dm, DBG_ANT_DIV, "***1.TargetAnt_CRC32 = ((%s))\n", (fat_tab->target_ant_crc32 == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
3131
3132 for (i = 0; i < HT_IDX; i++) {
3133 main_cnt_all += fat_tab->main_ht_cnt[i];
3134 aux_cnt_all += fat_tab->aux_ht_cnt[i];
3135
3136 if (fat_tab->main_ht_cnt[i] > main_max_cnt) {
3137 main_max_cnt = fat_tab->main_ht_cnt[i];
3138 main_max_idx = i;
3139 }
3140
3141 if (fat_tab->aux_ht_cnt[i] > aux_max_cnt) {
3142 aux_max_cnt = fat_tab->aux_ht_cnt[i];
3143 aux_max_idx = i;
3144 }
3145 }
3146
3147 for (i = 0; i < rate_num; i++) {
3148 rate_ss_shift = (i << 3);
3149 PHYDM_DBG(dm, DBG_ANT_DIV, "*main_ht_cnt HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
3150 (rate_ss_shift), (rate_ss_shift + 7),
3151 fat_tab->main_ht_cnt[rate_ss_shift + 0], fat_tab->main_ht_cnt[rate_ss_shift + 1],
3152 fat_tab->main_ht_cnt[rate_ss_shift + 2], fat_tab->main_ht_cnt[rate_ss_shift + 3],
3153 fat_tab->main_ht_cnt[rate_ss_shift + 4], fat_tab->main_ht_cnt[rate_ss_shift + 5],
3154 fat_tab->main_ht_cnt[rate_ss_shift + 6], fat_tab->main_ht_cnt[rate_ss_shift + 7]);
3155 }
3156
3157 for (i = 0; i < rate_num; i++) {
3158 rate_ss_shift = (i << 3);
3159 PHYDM_DBG(dm, DBG_ANT_DIV, "*aux_ht_cnt HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
3160 (rate_ss_shift), (rate_ss_shift + 7),
3161 fat_tab->aux_ht_cnt[rate_ss_shift + 0], fat_tab->aux_ht_cnt[rate_ss_shift + 1],
3162 fat_tab->aux_ht_cnt[rate_ss_shift + 2], fat_tab->aux_ht_cnt[rate_ss_shift + 3],
3163 fat_tab->aux_ht_cnt[rate_ss_shift + 4], fat_tab->aux_ht_cnt[rate_ss_shift + 5],
3164 fat_tab->aux_ht_cnt[rate_ss_shift + 6], fat_tab->aux_ht_cnt[rate_ss_shift + 7]);
3165 }
3166
3167 /* @3 [EVM statistic] */
3168 /*@1SS EVM*/
3169 main_1ss_evm = (fat_tab->main_evm_cnt[mac_id] != 0) ? (fat_tab->main_evm_sum[mac_id] / fat_tab->main_evm_cnt[mac_id]) : 0;
3170 aux_1ss_evm = (fat_tab->aux_evm_cnt[mac_id] != 0) ? (fat_tab->aux_evm_sum[mac_id] / fat_tab->aux_evm_cnt[mac_id]) : 0;
3171 target_ant_evm_1ss = (main_1ss_evm == aux_1ss_evm) ? (fat_tab->pre_target_ant_enhance) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT);
3172
3173 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main1ss_EVM= (( %d ))\n", fat_tab->main_evm_cnt[mac_id], main_1ss_evm);
3174 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_1ss_EVM = (( %d ))\n", fat_tab->aux_evm_cnt[mac_id], aux_1ss_evm);
3175
3176 /*@2SS EVM*/
3177 main_2ss_evm[0] = (fat_tab->main_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->main_evm_2ss_sum[mac_id][0] / fat_tab->main_evm_2ss_cnt[mac_id]) : 0;
3178 main_2ss_evm[1] = (fat_tab->main_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->main_evm_2ss_sum[mac_id][1] / fat_tab->main_evm_2ss_cnt[mac_id]) : 0;
3179 main_2ss_evm_sum = main_2ss_evm[0] + main_2ss_evm[1];
3180
3181 aux_2ss_evm[0] = (fat_tab->aux_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->aux_evm_2ss_sum[mac_id][0] / fat_tab->aux_evm_2ss_cnt[mac_id]) : 0;
3182 aux_2ss_evm[1] = (fat_tab->aux_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->aux_evm_2ss_sum[mac_id][1] / fat_tab->aux_evm_2ss_cnt[mac_id]) : 0;
3183 aux_2ss_evm_sum = aux_2ss_evm[0] + aux_2ss_evm[1];
3184
3185 target_ant_evm_2ss = (main_2ss_evm_sum == aux_2ss_evm_sum) ? (fat_tab->pre_target_ant_enhance) : ((main_2ss_evm_sum >= aux_2ss_evm_sum) ? MAIN_ANT : AUX_ANT);
3186
3187 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main2ss_EVM{A,B,Sum} = {%d, %d, %d}\n",
3188 fat_tab->main_evm_2ss_cnt[mac_id], main_2ss_evm[0], main_2ss_evm[1], main_2ss_evm_sum);
3189 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_2ss_EVM{A,B,Sum} = {%d, %d, %d}\n",
3190 fat_tab->aux_evm_2ss_cnt[mac_id], aux_2ss_evm[0], aux_2ss_evm[1], aux_2ss_evm_sum);
3191
3192 if ((main_2ss_evm_sum + aux_2ss_evm_sum) != 0) {
3193 decision_evm_ss = 2;
3194 main_evm = main_2ss_evm_sum;
3195 aux_evm = aux_2ss_evm_sum;
3196 fat_tab->target_ant_evm = target_ant_evm_2ss;
3197 } else {
3198 decision_evm_ss = 1;
3199 main_evm = main_1ss_evm;
3200 aux_evm = aux_1ss_evm;
3201 fat_tab->target_ant_evm = target_ant_evm_1ss;
3202 }
3203
3204 if ((main_evm == 0 || aux_evm == 0))
3205 diff_EVM = 100;
3206 else if (main_evm >= aux_evm)
3207 diff_EVM = main_evm - aux_evm;
3208 else
3209 diff_EVM = aux_evm - main_evm;
3210
3211 PHYDM_DBG(dm, DBG_ANT_DIV, "***2.TargetAnt_EVM((%d-ss)) = ((%s))\n", decision_evm_ss, (fat_tab->target_ant_evm == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
3212
3213 //3 [TP statistic]
3214 main_tp_avg = (fat_tab->main_tp_cnt != 0) ? (fat_tab->main_tp / fat_tab->main_tp_cnt) : 0;
3215 aux_tp_avg = (fat_tab->aux_tp_cnt != 0) ? (fat_tab->aux_tp / fat_tab->aux_tp_cnt) : 0;
3216 tp_diff_avg = DIFF_2(main_tp_avg, aux_tp_avg);
3217 fat_tab->target_ant_tp = (tp_diff_avg < 100) ? (fat_tab->pre_target_ant_enhance) : ((main_tp_avg >= aux_tp_avg) ? MAIN_ANT : AUX_ANT);
3218
3219 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main_TP = ((%d))\n", fat_tab->main_tp_cnt, main_tp_avg);
3220 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_TP = ((%d))\n", fat_tab->aux_tp_cnt, aux_tp_avg);
3221 PHYDM_DBG(dm, DBG_ANT_DIV, "***3.TargetAnt_TP = ((%s))\n", (fat_tab->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
3222
3223 /*Reset TP Method */
3224 fat_tab->main_tp = 0;
3225 fat_tab->aux_tp = 0;
3226 fat_tab->main_tp_cnt = 0;
3227 fat_tab->aux_tp_cnt = 0;
3228
3229 /* @2 [ Decision state ] */
3230 #if 1
3231 if (main_max_idx == aux_max_idx && ((main_cnt_all + aux_cnt_all) != 0)) {
3232 PHYDM_DBG(dm, DBG_ANT_DIV, "Decision EVM, main_max_idx = ((MCS%d)), aux_max_idx = ((MCS%d))\n", main_max_idx, aux_max_idx);
3233 fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
3234 } else {
3235 PHYDM_DBG(dm, DBG_ANT_DIV, "Decision TP, main_max_idx = ((MCS%d)), aux_max_idx = ((MCS%d))\n", main_max_idx, aux_max_idx);
3236 fat_tab->target_ant_enhance = fat_tab->target_ant_tp;
3237 }
3238 #else
3239 if (fat_tab->target_ant_evm == fat_tab->target_ant_crc32) {
3240 PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
3241
3242 if ((utility_ratio < 2 && force_antenna == false) && diff_EVM <= 30)
3243 fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance;
3244 else
3245 fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
3246 }
3247 #if 0
3248 else if ((diff_EVM <= 50 && (utility_ratio > 4 && force_antenna == false)) || (force_antenna == true)) {
3249 PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
3250 fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
3251 }
3252 #endif
3253 else if (diff_EVM >= 20) {
3254 PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
3255 fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
3256 } else if (utility_ratio >= 6 && force_antenna == false) {
3257 PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
3258 fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
3259 } else {
3260 PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
3261
3262 if (force_antenna == true)
3263 score_CRC = 2;
3264 else if (utility_ratio >= 5) /*@>2.5*/
3265 score_CRC = 2;
3266 else if (utility_ratio >= 4) /*@>2*/
3267 score_CRC = 1;
3268 else
3269 score_CRC = 0;
3270
3271 if (diff_EVM >= 15)
3272 score_EVM = 3;
3273 else if (diff_EVM >= 10)
3274 score_EVM = 2;
3275 else if (diff_EVM >= 5)
3276 score_EVM = 1;
3277 else
3278 score_EVM = 0;
3279
3280 if (score_CRC > score_EVM)
3281 fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
3282 else if (score_CRC < score_EVM)
3283 fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
3284 else
3285 fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance;
3286 }
3287 #endif
3288 fat_tab->pre_target_ant_enhance = fat_tab->target_ant_enhance;
3289
3290 PHYDM_DBG(dm, DBG_ANT_DIV, "*** 4.TargetAnt_enhance = (( %s ))******\n", (fat_tab->target_ant_enhance == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
3291 }
3292 } else { /* RSSI< = evm_rssi_th_low */
3293 PHYDM_DBG(dm, DBG_ANT_DIV, "[ <TH_L: escape from > TH_L ]\n");
3294 odm_evm_fast_ant_reset(dm);
3295 }
3296 } else {
3297 PHYDM_DBG(dm, DBG_ANT_DIV,
3298 "[escape from> TH_H || evm_method_enable==1]\n");
3299 odm_evm_fast_ant_reset(dm);
3300 }
3301 } else {
3302 PHYDM_DBG(dm, DBG_ANT_DIV, "[multi-Client]\n");
3303 odm_evm_fast_ant_reset(dm);
3304 }
3305 }
3306 }
3307
3308 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
phydm_evm_antdiv_callback(struct phydm_timer_list * timer)3309 void phydm_evm_antdiv_callback(
3310 struct phydm_timer_list *timer)
3311 {
3312 void *adapter = (void *)timer->Adapter;
3313 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
3314 struct dm_struct *dm = &hal_data->DM_OutSrc;
3315
3316 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
3317 #if USE_WORKITEM
3318 odm_schedule_work_item(&dm->phydm_evm_antdiv_workitem);
3319 #else
3320 {
3321 odm_hw_ant_div(dm);
3322 }
3323 #endif
3324 #else
3325 odm_schedule_work_item(&dm->phydm_evm_antdiv_workitem);
3326 #endif
3327 }
3328
phydm_evm_antdiv_workitem_callback(void * context)3329 void phydm_evm_antdiv_workitem_callback(
3330 void *context)
3331 {
3332 void *adapter = (void *)context;
3333 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
3334 struct dm_struct *dm = &hal_data->DM_OutSrc;
3335
3336 odm_hw_ant_div(dm);
3337 }
3338
3339 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
phydm_evm_antdiv_callback(void * dm_void)3340 void phydm_evm_antdiv_callback(void *dm_void)
3341 {
3342 struct dm_struct *dm = (struct dm_struct *)dm_void;
3343 void *padapter = dm->adapter;
3344
3345 if (*dm->is_net_closed)
3346 return;
3347 if (dm->support_interface == ODM_ITRF_PCIE) {
3348 odm_hw_ant_div(dm);
3349 } else {
3350 /* @Can't do I/O in timer callback*/
3351 phydm_run_in_thread_cmd(dm,
3352 phydm_evm_antdiv_workitem_callback,
3353 padapter);
3354 }
3355 }
3356
phydm_evm_antdiv_workitem_callback(void * context)3357 void phydm_evm_antdiv_workitem_callback(void *context)
3358 {
3359 void *adapter = (void *)context;
3360 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
3361 struct dm_struct *dm = &hal_data->odmpriv;
3362
3363 odm_hw_ant_div(dm);
3364 }
3365
3366 #else
phydm_evm_antdiv_callback(void * dm_void)3367 void phydm_evm_antdiv_callback(
3368 void *dm_void)
3369 {
3370 struct dm_struct *dm = (struct dm_struct *)dm_void;
3371
3372 PHYDM_DBG(dm, DBG_ANT_DIV, "******AntDiv_Callback******\n");
3373 odm_hw_ant_div(dm);
3374 }
3375 #endif
3376
3377 #endif
3378
odm_hw_ant_div(void * dm_void)3379 void odm_hw_ant_div(void *dm_void)
3380 {
3381 struct dm_struct *dm = (struct dm_struct *)dm_void;
3382 u32 i, min_max_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0;
3383 u32 main_rssi, aux_rssi, mian_cnt, aux_cnt, local_max_rssi;
3384 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
3385 u8 rx_idle_ant = fat_tab->rx_idle_ant, target_ant = 7;
3386 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3387 struct cmn_sta_info *sta;
3388
3389 #ifdef PHYDM_BEAMFORMING_SUPPORT
3390 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3391 struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
3392 u32 TH1 = 500000;
3393 u32 TH2 = 10000000;
3394 u32 ma_rx_temp, degrade_TP_temp, improve_TP_temp;
3395 u8 monitor_rssi_threshold = 30;
3396
3397 dm_bdc_table->BF_pass = true;
3398 dm_bdc_table->DIV_pass = true;
3399 dm_bdc_table->is_all_div_sta_idle = true;
3400 dm_bdc_table->is_all_bf_sta_idle = true;
3401 dm_bdc_table->num_bf_tar = 0;
3402 dm_bdc_table->num_div_tar = 0;
3403 dm_bdc_table->num_client = 0;
3404 #endif
3405 #endif
3406
3407 if (!dm->is_linked) { /* @is_linked==False */
3408 PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
3409
3410 if (fat_tab->is_become_linked) {
3411 if (fat_tab->div_path_type == ANT_PATH_A)
3412 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
3413 else if (fat_tab->div_path_type == ANT_PATH_B)
3414 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
3415 else if (fat_tab->div_path_type == ANT_PATH_AB)
3416 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
3417 odm_update_rx_idle_ant(dm, MAIN_ANT);
3418 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
3419 dm->antdiv_period = 0;
3420
3421 fat_tab->is_become_linked = dm->is_linked;
3422 }
3423 return;
3424 } else {
3425 if (!fat_tab->is_become_linked) {
3426 PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
3427 if (fat_tab->div_path_type == ANT_PATH_A)
3428 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
3429 else if (fat_tab->div_path_type == ANT_PATH_B)
3430 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
3431 else if (fat_tab->div_path_type == ANT_PATH_AB)
3432 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
3433 #if 0
3434 /*odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);*/
3435
3436 /* @if(dm->support_ic_type == ODM_RTL8821 ) */
3437 /* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */
3438 /* CCK AntDiv function disable */
3439
3440 /* @#if(DM_ODM_SUPPORT_TYPE == ODM_AP) */
3441 /* @else if(dm->support_ic_type == ODM_RTL8881A) */
3442 /* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */
3443 /* CCK AntDiv function disable */
3444 /* @#endif */
3445
3446 /* @else if(dm->support_ic_type == ODM_RTL8723B ||*/
3447 /* @dm->support_ic_type == ODM_RTL8812) */
3448 /* odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); */
3449 /* CCK AntDiv function disable */
3450 #endif
3451
3452 fat_tab->is_become_linked = dm->is_linked;
3453
3454 if (dm->support_ic_type == ODM_RTL8723B &&
3455 dm->ant_div_type == CG_TRX_HW_ANTDIV) {
3456 odm_set_bb_reg(dm, R_0x930, 0xF0, 8);
3457 /* @DPDT_P = ANTSEL[0] for 8723B AntDiv */
3458 odm_set_bb_reg(dm, R_0x930, 0xF, 8);
3459 /* @DPDT_N = ANTSEL[0] */
3460 }
3461
3462 /* @ BDC Init */
3463 #ifdef PHYDM_BEAMFORMING_SUPPORT
3464 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3465 odm_bdc_init(dm);
3466 #endif
3467 #endif
3468
3469 #ifdef ODM_EVM_ENHANCE_ANTDIV
3470 odm_evm_fast_ant_reset(dm);
3471 #endif
3472 }
3473 }
3474
3475 if (!(*fat_tab->p_force_tx_by_desc)) {
3476 if (dm->is_one_entry_only)
3477 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
3478 else
3479 odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
3480 }
3481
3482 #ifdef ODM_EVM_ENHANCE_ANTDIV
3483 if (dm->antdiv_evm_en == 1) {
3484 odm_evm_enhance_ant_div(dm);
3485 if (fat_tab->fat_state_cnt != 0)
3486 return;
3487 } else
3488 odm_evm_fast_ant_reset(dm);
3489 #endif
3490
3491 /* @2 BDC mode Arbitration */
3492 #ifdef PHYDM_BEAMFORMING_SUPPORT
3493 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3494 if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0)
3495 odm_bf_ant_div_mode_arbitration(dm);
3496 #endif
3497 #endif
3498
3499 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
3500 sta = dm->phydm_sta_info[i];
3501 if (!is_sta_active(sta)) {
3502 phydm_antdiv_reset_statistic(dm, i);
3503 continue;
3504 }
3505
3506 /* @2 Caculate RSSI per Antenna */
3507 if (fat_tab->main_cnt[i] != 0 || fat_tab->aux_cnt[i] != 0) {
3508 mian_cnt = fat_tab->main_cnt[i];
3509 aux_cnt = fat_tab->aux_cnt[i];
3510 main_rssi = (mian_cnt != 0) ?
3511 (fat_tab->main_sum[i] / mian_cnt) : 0;
3512 aux_rssi = (aux_cnt != 0) ?
3513 (fat_tab->aux_sum[i] / aux_cnt) : 0;
3514 target_ant = (mian_cnt == aux_cnt) ?
3515 fat_tab->rx_idle_ant :
3516 ((mian_cnt >= aux_cnt) ?
3517 fat_tab->ant_idx_vec[0]:fat_tab->ant_idx_vec[1]);
3518 /*Use counter number for OFDM*/
3519
3520 } else { /*@CCK only case*/
3521 mian_cnt = fat_tab->main_cnt_cck[i];
3522 aux_cnt = fat_tab->aux_cnt_cck[i];
3523 main_rssi = (mian_cnt != 0) ?
3524 (fat_tab->main_sum_cck[i] / mian_cnt) : 0;
3525 aux_rssi = (aux_cnt != 0) ?
3526 (fat_tab->aux_sum_cck[i] / aux_cnt) : 0;
3527 target_ant = (main_rssi == aux_rssi) ?
3528 fat_tab->rx_idle_ant :
3529 ((main_rssi >= aux_rssi) ?
3530 fat_tab->ant_idx_vec[0]:fat_tab->ant_idx_vec[1]);
3531 /*Use RSSI for CCK only case*/
3532 }
3533 #if (RTL8721D_SUPPORT)
3534 if(dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2PB26) { /* added by Jiao Qi on May.25,2020, only for 3 antenna diversity */
3535 u8 tmp;
3536 if(target_ant == fat_tab->ant_idx_vec[0]){/* switch the second & third ant index */
3537 tmp = fat_tab->ant_idx_vec[1];
3538 fat_tab->ant_idx_vec[1] = fat_tab->ant_idx_vec[2];
3539 fat_tab->ant_idx_vec[2] = tmp;
3540 }else{
3541 /* switch the first & second ant index */
3542 tmp = fat_tab->ant_idx_vec[0];
3543 fat_tab->ant_idx_vec[0] = fat_tab->ant_idx_vec[1];
3544 fat_tab->ant_idx_vec[1] = tmp;
3545 /* switch the second & third ant index */
3546 tmp = fat_tab->ant_idx_vec[1];
3547 fat_tab->ant_idx_vec[1] = fat_tab->ant_idx_vec[2];
3548 fat_tab->ant_idx_vec[2] = tmp;
3549 }
3550 }
3551 #endif
3552
3553 PHYDM_DBG(dm, DBG_ANT_DIV,
3554 "*** Client[ %d ] : Main_Cnt = (( %d )) , CCK_Main_Cnt = (( %d )) , main_rssi= (( %d ))\n",
3555 i, fat_tab->main_cnt[i],
3556 fat_tab->main_cnt_cck[i], main_rssi);
3557 PHYDM_DBG(dm, DBG_ANT_DIV,
3558 "*** Client[ %d ] : Aux_Cnt = (( %d )) , CCK_Aux_Cnt = (( %d )) , aux_rssi = (( %d ))\n",
3559 i, fat_tab->aux_cnt[i],
3560 fat_tab->aux_cnt_cck[i], aux_rssi);
3561
3562 local_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi;
3563 /* @ Select max_rssi for DIG */
3564 if (local_max_rssi > ant_div_max_rssi && local_max_rssi < 40)
3565 ant_div_max_rssi = local_max_rssi;
3566 if (local_max_rssi > max_rssi)
3567 max_rssi = local_max_rssi;
3568
3569 /* @ Select RX Idle Antenna */
3570 if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) {
3571 rx_idle_ant = target_ant;
3572 min_max_rssi = local_max_rssi;
3573 }
3574
3575 #ifdef ODM_EVM_ENHANCE_ANTDIV
3576 if (dm->antdiv_evm_en == 1) {
3577 if (fat_tab->target_ant_enhance != 0xFF) {
3578 target_ant = fat_tab->target_ant_enhance;
3579 rx_idle_ant = fat_tab->target_ant_enhance;
3580 }
3581 }
3582 #endif
3583
3584 /* @2 Select TX Antenna */
3585 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
3586 #ifdef PHYDM_BEAMFORMING_SUPPORT
3587 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3588 if (dm_bdc_table->w_bfee_client[i] == 0)
3589 #endif
3590 #endif
3591 {
3592 odm_update_tx_ant(dm, target_ant, i);
3593 }
3594 }
3595
3596 /* @------------------------------------------------------------ */
3597
3598 #ifdef PHYDM_BEAMFORMING_SUPPORT
3599 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3600
3601 dm_bdc_table->num_client++;
3602
3603 if (dm_bdc_table->bdc_mode == BDC_MODE_2 || dm_bdc_table->bdc_mode == BDC_MODE_3) {
3604 /* @2 Byte counter */
3605
3606 ma_rx_temp = sta->rx_moving_average_tp; /* RX TP ( bit /sec) */
3607
3608 if (dm_bdc_table->BDC_state == bdc_bfer_train_state)
3609 dm_bdc_table->MA_rx_TP_DIV[i] = ma_rx_temp;
3610 else
3611 dm_bdc_table->MA_rx_TP[i] = ma_rx_temp;
3612
3613 if (ma_rx_temp < TH2 && ma_rx_temp > TH1 && local_max_rssi <= monitor_rssi_threshold) {
3614 if (dm_bdc_table->w_bfer_client[i] == 1) { /* @Bfer_Target */
3615 dm_bdc_table->num_bf_tar++;
3616
3617 if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) {
3618 improve_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 9) >> 3; /* @* 1.125 */
3619 dm_bdc_table->BF_pass = (dm_bdc_table->MA_rx_TP[i] > improve_TP_temp) ? true : false;
3620 PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : { MA_rx_TP,improve_TP_temp, MA_rx_TP_DIV, BF_pass}={ %d, %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], improve_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->BF_pass);
3621 }
3622 } else { /* @DIV_Target */
3623 dm_bdc_table->num_div_tar++;
3624
3625 if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) {
3626 degrade_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 5) >> 3; /* @* 0.625 */
3627 dm_bdc_table->DIV_pass = (dm_bdc_table->MA_rx_TP[i] > degrade_TP_temp) ? true : false;
3628 PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : { MA_rx_TP, degrade_TP_temp, MA_rx_TP_DIV, DIV_pass}=\n{ %d, %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], degrade_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->DIV_pass);
3629 }
3630 }
3631 }
3632
3633 if (ma_rx_temp > TH1) {
3634 if (dm_bdc_table->w_bfer_client[i] == 1) /* @Bfer_Target */
3635 dm_bdc_table->is_all_bf_sta_idle = false;
3636 else /* @DIV_Target */
3637 dm_bdc_table->is_all_div_sta_idle = false;
3638 }
3639
3640 PHYDM_DBG(dm, DBG_ANT_DIV,
3641 "*** Client[ %d ] : { BFmeeCap, BFmerCap} = { %d , %d }\n",
3642 i, dm_bdc_table->w_bfee_client[i],
3643 dm_bdc_table->w_bfer_client[i]);
3644
3645 if (dm_bdc_table->BDC_state == bdc_bfer_train_state)
3646 PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : MA_rx_TP_DIV = (( %d ))\n", i, dm_bdc_table->MA_rx_TP_DIV[i]);
3647
3648 else
3649 PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : MA_rx_TP = (( %d ))\n", i, dm_bdc_table->MA_rx_TP[i]);
3650 }
3651 #endif
3652 #endif
3653
3654 #ifdef PHYDM_BEAMFORMING_SUPPORT
3655 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3656 if (dm_bdc_table->bdc_try_flag == 0)
3657 #endif
3658 #endif
3659 {
3660 phydm_antdiv_reset_statistic(dm, i);
3661 }
3662 }
3663
3664 /* @2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) */
3665 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3666 PHYDM_DBG(dm, DBG_ANT_DIV, "*** rx_idle_ant = (( %s ))\n",
3667 (rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
3668
3669 #ifdef PHYDM_BEAMFORMING_SUPPORT
3670 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3671 if (dm_bdc_table->bdc_mode == BDC_MODE_1 || dm_bdc_table->bdc_mode == BDC_MODE_3) {
3672 PHYDM_DBG(dm, DBG_ANT_DIV,
3673 "*** bdc_rx_idle_update_counter = (( %d ))\n",
3674 dm_bdc_table->bdc_rx_idle_update_counter);
3675
3676 if (dm_bdc_table->bdc_rx_idle_update_counter == 1) {
3677 PHYDM_DBG(dm, DBG_ANT_DIV,
3678 "***Update RxIdle Antenna!!!\n");
3679 dm_bdc_table->bdc_rx_idle_update_counter = 30;
3680 odm_update_rx_idle_ant(dm, rx_idle_ant);
3681 } else {
3682 dm_bdc_table->bdc_rx_idle_update_counter--;
3683 PHYDM_DBG(dm, DBG_ANT_DIV,
3684 "***NOT update RxIdle Antenna because of BF ( need to fix TX-ant)\n");
3685 }
3686 } else
3687 #endif
3688 #endif
3689 odm_update_rx_idle_ant(dm, rx_idle_ant);
3690 #else
3691 #if (RTL8721D_SUPPORT)
3692 if (dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2PB26) {
3693 if(odm_get_bb_reg(dm,R_0xc50,0x80) || odm_get_bb_reg(dm, R_0xa00, 0x8000))
3694 odm_update_rx_idle_ant_sp3t(dm, rx_idle_ant);
3695 }
3696 else
3697 #endif
3698 odm_update_rx_idle_ant(dm, rx_idle_ant);
3699
3700 #endif /* @#if(DM_ODM_SUPPORT_TYPE == ODM_AP) */
3701
3702 /* @2 BDC Main Algorithm */
3703 #ifdef PHYDM_BEAMFORMING_SUPPORT
3704 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3705 if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0)
3706 odm_bd_ccoex_bfee_rx_div_arbitration(dm);
3707
3708 dm_bdc_table->num_txbfee_client = 0;
3709 dm_bdc_table->num_txbfer_client = 0;
3710 #endif
3711 #endif
3712
3713 if (ant_div_max_rssi == 0)
3714 dig_t->ant_div_rssi_max = dm->rssi_min;
3715 else
3716 dig_t->ant_div_rssi_max = ant_div_max_rssi;
3717
3718 PHYDM_DBG(dm, DBG_ANT_DIV, "***AntDiv End***\n\n");
3719 }
3720
3721 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3722
odm_s0s1_sw_ant_div_reset(void * dm_void)3723 void odm_s0s1_sw_ant_div_reset(void *dm_void)
3724 {
3725 struct dm_struct *dm = (struct dm_struct *)dm_void;
3726 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
3727 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
3728
3729 fat_tab->is_become_linked = false;
3730 swat_tab->try_flag = SWAW_STEP_INIT;
3731 swat_tab->double_chk_flag = 0;
3732
3733 PHYDM_DBG(dm, DBG_ANT_DIV, "%s: fat_tab->is_become_linked = %d\n",
3734 __func__, fat_tab->is_become_linked);
3735 }
3736
phydm_sw_antdiv_train_time(void * dm_void)3737 void phydm_sw_antdiv_train_time(void *dm_void)
3738 {
3739 struct dm_struct *dm = (struct dm_struct *)dm_void;
3740 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
3741 u8 high_traffic_train_time_u = 0x32, high_traffic_train_time_l = 0;
3742 u8 low_traffic_train_time_u = 200, low_traffic_train_time_l = 0;
3743 u8 train_time_temp;
3744
3745 if (dm->traffic_load == TRAFFIC_HIGH) {
3746 train_time_temp = swat_tab->train_time;
3747
3748 if (swat_tab->train_time_flag == 3) {
3749 high_traffic_train_time_l = 0xa;
3750
3751 if (train_time_temp <= 16)
3752 train_time_temp = high_traffic_train_time_l;
3753 else
3754 train_time_temp -= 16;
3755
3756 } else if (swat_tab->train_time_flag == 2) {
3757 train_time_temp -= 8;
3758 high_traffic_train_time_l = 0xf;
3759 } else if (swat_tab->train_time_flag == 1) {
3760 train_time_temp -= 4;
3761 high_traffic_train_time_l = 0x1e;
3762 } else if (swat_tab->train_time_flag == 0) {
3763 train_time_temp += 8;
3764 high_traffic_train_time_l = 0x28;
3765 }
3766
3767 if (dm->support_ic_type == ODM_RTL8188F) {
3768 if (dm->support_interface == ODM_ITRF_SDIO)
3769 high_traffic_train_time_l += 0xa;
3770 }
3771
3772 /* @-- */
3773 if (train_time_temp > high_traffic_train_time_u)
3774 train_time_temp = high_traffic_train_time_u;
3775
3776 else if (train_time_temp < high_traffic_train_time_l)
3777 train_time_temp = high_traffic_train_time_l;
3778
3779 swat_tab->train_time = train_time_temp; /*@10ms~200ms*/
3780
3781 PHYDM_DBG(dm, DBG_ANT_DIV,
3782 "train_time_flag=((%d)), train_time=((%d))\n",
3783 swat_tab->train_time_flag,
3784 swat_tab->train_time);
3785
3786 } else if ((dm->traffic_load == TRAFFIC_MID) ||
3787 (dm->traffic_load == TRAFFIC_LOW)) {
3788 train_time_temp = swat_tab->train_time;
3789
3790 if (swat_tab->train_time_flag == 3) {
3791 low_traffic_train_time_l = 10;
3792 if (train_time_temp < 50)
3793 train_time_temp = low_traffic_train_time_l;
3794 else
3795 train_time_temp -= 50;
3796 } else if (swat_tab->train_time_flag == 2) {
3797 train_time_temp -= 30;
3798 low_traffic_train_time_l = 36;
3799 } else if (swat_tab->train_time_flag == 1) {
3800 train_time_temp -= 10;
3801 low_traffic_train_time_l = 40;
3802 } else {
3803 train_time_temp += 10;
3804 low_traffic_train_time_l = 50;
3805 }
3806
3807 if (dm->support_ic_type == ODM_RTL8188F) {
3808 if (dm->support_interface == ODM_ITRF_SDIO)
3809 low_traffic_train_time_l += 10;
3810 }
3811
3812 /* @-- */
3813 if (train_time_temp >= low_traffic_train_time_u)
3814 train_time_temp = low_traffic_train_time_u;
3815
3816 else if (train_time_temp <= low_traffic_train_time_l)
3817 train_time_temp = low_traffic_train_time_l;
3818
3819 swat_tab->train_time = train_time_temp; /*@10ms~200ms*/
3820
3821 PHYDM_DBG(dm, DBG_ANT_DIV,
3822 "train_time_flag=((%d)) , train_time=((%d))\n",
3823 swat_tab->train_time_flag, swat_tab->train_time);
3824
3825 } else {
3826 swat_tab->train_time = 0xc8; /*@200ms*/
3827 }
3828 }
3829
phydm_sw_antdiv_decision(void * dm_void)3830 void phydm_sw_antdiv_decision(void *dm_void)
3831 {
3832 struct dm_struct *dm = (struct dm_struct *)dm_void;
3833 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
3834 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
3835 u32 i, min_max_rssi = 0xFF, local_max_rssi, local_min_rssi;
3836 u32 main_rssi, aux_rssi;
3837 u8 rx_idle_ant = swat_tab->pre_ant;
3838 u8 target_ant = swat_tab->pre_ant, next_ant = 0;
3839 struct cmn_sta_info *entry = NULL;
3840 u32 main_cnt = 0, aux_cnt = 0, main_sum = 0, aux_sum = 0;
3841 u32 main_ctrl_cnt = 0, aux_ctrl_cnt = 0;
3842 boolean is_by_ctrl_frame = false;
3843 boolean cond_23d_main, cond_23d_aux;
3844 u64 pkt_cnt_total = 0;
3845
3846 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
3847 entry = dm->phydm_sta_info[i];
3848 if (!is_sta_active(entry)) {
3849 phydm_antdiv_reset_statistic(dm, i);
3850 continue;
3851 }
3852
3853 /* @2 Caculate RSSI per Antenna */
3854 if (fat_tab->main_cnt[i] != 0 || fat_tab->aux_cnt[i] != 0) {
3855 main_cnt = (u32)fat_tab->main_cnt[i];
3856 aux_cnt = (u32)fat_tab->aux_cnt[i];
3857 main_rssi = (main_cnt != 0) ?
3858 (fat_tab->main_sum[i] / main_cnt) : 0;
3859 aux_rssi = (aux_cnt != 0) ?
3860 (fat_tab->aux_sum[i] / aux_cnt) : 0;
3861 if (dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710C) {
3862 cond_23d_main = (aux_cnt > main_cnt) &&
3863 ((main_rssi - aux_rssi < 5) ||
3864 (aux_rssi > main_rssi));
3865 cond_23d_aux = (main_cnt > aux_cnt) &&
3866 ((aux_rssi - main_rssi < 5) ||
3867 (main_rssi > aux_rssi));
3868 if (swat_tab->pre_ant == MAIN_ANT) {
3869 if (main_cnt == 0)
3870 target_ant = (aux_cnt != 0) ?
3871 AUX_ANT :
3872 swat_tab->pre_ant;
3873 else
3874 target_ant = cond_23d_main ?
3875 AUX_ANT :
3876 swat_tab->pre_ant;
3877 } else {
3878 if (aux_cnt == 0)
3879 target_ant = (main_cnt != 0) ?
3880 MAIN_ANT :
3881 swat_tab->pre_ant;
3882 else
3883 target_ant = cond_23d_aux ?
3884 MAIN_ANT :
3885 swat_tab->pre_ant;
3886 }
3887 } else {
3888 if (swat_tab->pre_ant == MAIN_ANT) {
3889 target_ant = (aux_rssi > main_rssi) ?
3890 AUX_ANT :
3891 swat_tab->pre_ant;
3892 } else if (swat_tab->pre_ant == AUX_ANT) {
3893 target_ant = (main_rssi > aux_rssi) ?
3894 MAIN_ANT :
3895 swat_tab->pre_ant;
3896 }
3897 }
3898 } else { /*@CCK only case*/
3899 main_cnt = fat_tab->main_cnt_cck[i];
3900 aux_cnt = fat_tab->aux_cnt_cck[i];
3901 main_rssi = (main_cnt != 0) ?
3902 (fat_tab->main_sum_cck[i] / main_cnt) : 0;
3903 aux_rssi = (aux_cnt != 0) ?
3904 (fat_tab->aux_sum_cck[i] / aux_cnt) : 0;
3905 target_ant = (main_rssi == aux_rssi) ?
3906 swat_tab->pre_ant :
3907 ((main_rssi >= aux_rssi) ?
3908 MAIN_ANT : AUX_ANT);
3909 /*Use RSSI for CCK only case*/
3910 }
3911 local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi;
3912 local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi;
3913
3914 PHYDM_DBG(dm, DBG_ANT_DIV,
3915 "*** CCK_counter_main = (( %d )) , CCK_counter_aux= (( %d ))\n",
3916 fat_tab->main_cnt_cck[i], fat_tab->aux_cnt_cck[i]);
3917 PHYDM_DBG(dm, DBG_ANT_DIV,
3918 "*** OFDM_counter_main = (( %d )) , OFDM_counter_aux= (( %d ))\n",
3919 fat_tab->main_cnt[i], fat_tab->aux_cnt[i]);
3920 PHYDM_DBG(dm, DBG_ANT_DIV,
3921 "*** main_Cnt = (( %d )) , aux_Cnt = (( %d ))\n",
3922 main_cnt, aux_cnt);
3923 PHYDM_DBG(dm, DBG_ANT_DIV,
3924 "*** main_rssi= (( %d )) , aux_rssi = (( %d ))\n",
3925 main_rssi, aux_rssi);
3926 PHYDM_DBG(dm, DBG_ANT_DIV,
3927 "*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i,
3928 (target_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
3929
3930 /* @2 Select RX Idle Antenna */
3931
3932 if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) {
3933 rx_idle_ant = target_ant;
3934 min_max_rssi = local_max_rssi;
3935 PHYDM_DBG(dm, DBG_ANT_DIV,
3936 "*** local_max_rssi-local_min_rssi = ((%d))\n",
3937 (local_max_rssi - local_min_rssi));
3938
3939 if ((local_max_rssi - local_min_rssi) > 8) {
3940 if (local_min_rssi != 0) {
3941 swat_tab->train_time_flag = 3;
3942 } else {
3943 if (min_max_rssi > RSSI_CHECK_THRESHOLD)
3944 swat_tab->train_time_flag = 0;
3945 else
3946 swat_tab->train_time_flag = 3;
3947 }
3948 } else if ((local_max_rssi - local_min_rssi) > 5) {
3949 swat_tab->train_time_flag = 2;
3950 } else if ((local_max_rssi - local_min_rssi) > 2) {
3951 swat_tab->train_time_flag = 1;
3952 } else {
3953 swat_tab->train_time_flag = 0;
3954 }
3955 }
3956
3957 /* @2 Select TX Antenna */
3958 if (target_ant == MAIN_ANT)
3959 fat_tab->antsel_a[i] = ANT1_2G;
3960 else
3961 fat_tab->antsel_a[i] = ANT2_2G;
3962
3963 phydm_antdiv_reset_statistic(dm, i);
3964 pkt_cnt_total += (main_cnt + aux_cnt);
3965 }
3966
3967 if (swat_tab->is_sw_ant_div_by_ctrl_frame) {
3968 odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_DETERMINE);
3969 is_by_ctrl_frame = true;
3970 }
3971
3972 PHYDM_DBG(dm, DBG_ANT_DIV,
3973 "Control frame packet counter = %d, data frame packet counter = %llu\n",
3974 swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame, pkt_cnt_total);
3975
3976 if (min_max_rssi == 0xff || ((pkt_cnt_total <
3977 (swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame >> 1)) &&
3978 dm->phy_dbg_info.num_qry_beacon_pkt < 2)) {
3979 min_max_rssi = 0;
3980 PHYDM_DBG(dm, DBG_ANT_DIV,
3981 "Check RSSI of control frame because min_max_rssi == 0xff\n");
3982 PHYDM_DBG(dm, DBG_ANT_DIV, "is_by_ctrl_frame = %d\n",
3983 is_by_ctrl_frame);
3984
3985 if (is_by_ctrl_frame) {
3986 main_ctrl_cnt = fat_tab->main_ctrl_cnt;
3987 aux_ctrl_cnt = fat_tab->aux_ctrl_cnt;
3988 main_rssi = (main_ctrl_cnt != 0) ?
3989 (fat_tab->main_ctrl_sum / main_ctrl_cnt) :
3990 0;
3991 aux_rssi = (aux_ctrl_cnt != 0) ?
3992 (fat_tab->aux_ctrl_sum / aux_ctrl_cnt) : 0;
3993
3994 if (main_ctrl_cnt <= 1 &&
3995 fat_tab->cck_ctrl_frame_cnt_main >= 1)
3996 main_rssi = 0;
3997
3998 if (aux_ctrl_cnt <= 1 &&
3999 fat_tab->cck_ctrl_frame_cnt_aux >= 1)
4000 aux_rssi = 0;
4001
4002 if (main_rssi != 0 || aux_rssi != 0) {
4003 rx_idle_ant = (main_rssi == aux_rssi) ?
4004 swat_tab->pre_ant :
4005 ((main_rssi >= aux_rssi) ?
4006 MAIN_ANT : AUX_ANT);
4007 local_max_rssi = (main_rssi >= aux_rssi) ?
4008 main_rssi : aux_rssi;
4009 local_min_rssi = (main_rssi >= aux_rssi) ?
4010 aux_rssi : main_rssi;
4011
4012 if ((local_max_rssi - local_min_rssi) > 8)
4013 swat_tab->train_time_flag = 3;
4014 else if ((local_max_rssi - local_min_rssi) > 5)
4015 swat_tab->train_time_flag = 2;
4016 else if ((local_max_rssi - local_min_rssi) > 2)
4017 swat_tab->train_time_flag = 1;
4018 else
4019 swat_tab->train_time_flag = 0;
4020
4021 PHYDM_DBG(dm, DBG_ANT_DIV,
4022 "Control frame: main_rssi = %d, aux_rssi = %d\n",
4023 main_rssi, aux_rssi);
4024 PHYDM_DBG(dm, DBG_ANT_DIV,
4025 "rx_idle_ant decided by control frame = %s\n",
4026 (rx_idle_ant == MAIN_ANT ?
4027 "MAIN" : "AUX"));
4028 }
4029 }
4030 }
4031
4032 fat_tab->min_max_rssi = min_max_rssi;
4033 swat_tab->try_flag = SWAW_STEP_PEEK;
4034
4035 if (swat_tab->double_chk_flag == 1) {
4036 swat_tab->double_chk_flag = 0;
4037
4038 if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD) {
4039 PHYDM_DBG(dm, DBG_ANT_DIV,
4040 " [Double check] min_max_rssi ((%d)) > %d again!!\n",
4041 fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD);
4042
4043 odm_update_rx_idle_ant(dm, rx_idle_ant);
4044
4045 PHYDM_DBG(dm, DBG_ANT_DIV,
4046 "[reset try_flag = 0] Training accomplished !!!]\n\n\n");
4047 } else {
4048 PHYDM_DBG(dm, DBG_ANT_DIV,
4049 " [Double check] min_max_rssi ((%d)) <= %d !!\n",
4050 fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD);
4051
4052 next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ?
4053 AUX_ANT : MAIN_ANT;
4054 swat_tab->try_flag = SWAW_STEP_PEEK;
4055 swat_tab->reset_idx = RSSI_CHECK_RESET_PERIOD;
4056 PHYDM_DBG(dm, DBG_ANT_DIV,
4057 "[set try_flag=0] Normal state: Need to tryg again!!\n\n\n");
4058 }
4059 } else {
4060 if (fat_tab->min_max_rssi < RSSI_CHECK_THRESHOLD)
4061 swat_tab->reset_idx = RSSI_CHECK_RESET_PERIOD;
4062
4063 swat_tab->pre_ant = rx_idle_ant;
4064 odm_update_rx_idle_ant(dm, rx_idle_ant);
4065 PHYDM_DBG(dm, DBG_ANT_DIV,
4066 "[reset try_flag = 0] Training accomplished !!!]\n\n\n");
4067 }
4068 }
4069
odm_s0s1_sw_ant_div(void * dm_void,u8 step)4070 void odm_s0s1_sw_ant_div(void *dm_void, u8 step)
4071 {
4072 struct dm_struct *dm = (struct dm_struct *)dm_void;
4073 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
4074 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4075 u32 value32;
4076 u8 next_ant = 0;
4077
4078 if (!dm->is_linked) { /* @is_linked==False */
4079 PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
4080 if (fat_tab->is_become_linked == true) {
4081 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
4082 if (dm->support_ic_type == ODM_RTL8723B) {
4083 PHYDM_DBG(dm, DBG_ANT_DIV,
4084 "Set REG 948[9:6]=0x0\n");
4085 odm_set_bb_reg(dm, R_0x948, 0x3c0, 0x0);
4086 }
4087 fat_tab->is_become_linked = dm->is_linked;
4088 }
4089 return;
4090 } else {
4091 if (fat_tab->is_become_linked == false) {
4092 PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
4093
4094 if (dm->support_ic_type == ODM_RTL8723B) {
4095 value32 = odm_get_bb_reg(dm, R_0x864, 0x38);
4096
4097 #if (RTL8723B_SUPPORT == 1)
4098 if (value32 == 0x0)
4099 odm_update_rx_idle_ant_8723b(dm,
4100 MAIN_ANT,
4101 ANT1_2G,
4102 ANT2_2G);
4103 else if (value32 == 0x1)
4104 odm_update_rx_idle_ant_8723b(dm,
4105 AUX_ANT,
4106 ANT2_2G,
4107 ANT1_2G);
4108 #endif
4109
4110 PHYDM_DBG(dm, DBG_ANT_DIV,
4111 "8723B: First link! Force antenna to %s\n",
4112 (value32 == 0x0 ? "MAIN" : "AUX"));
4113 }
4114
4115 if (dm->support_ic_type == ODM_RTL8723D) {
4116 value32 = odm_get_bb_reg(dm, R_0x864, 0x38);
4117 #if (RTL8723D_SUPPORT == 1)
4118 if (value32 == 0x0)
4119 odm_update_rx_idle_ant_8723d(dm,
4120 MAIN_ANT,
4121 ANT1_2G,
4122 ANT2_2G);
4123 else if (value32 == 0x1)
4124 odm_update_rx_idle_ant_8723d(dm,
4125 AUX_ANT,
4126 ANT2_2G,
4127 ANT1_2G);
4128 PHYDM_DBG(dm, DBG_ANT_DIV,
4129 "8723D: First link! Force antenna to %s\n",
4130 (value32 == 0x0 ? "MAIN" : "AUX"));
4131 #endif
4132 }
4133 if (dm->support_ic_type == ODM_RTL8710C) {
4134 #if (RTL8710C_SUPPORT == 1)
4135 value32 = (HAL_READ32(SYSTEM_CTRL_BASE, R_0x121c) & 0x800000);
4136 if (value32 == 0x0)
4137 odm_update_rx_idle_ant_8710c(dm,
4138 MAIN_ANT,
4139 ANT1_2G,
4140 ANT2_2G);
4141 else if (value32 == 0x1)
4142 odm_update_rx_idle_ant_8710c(dm,
4143 AUX_ANT,
4144 ANT2_2G,
4145 ANT1_2G);
4146 PHYDM_DBG(dm, DBG_ANT_DIV,
4147 "8710C: First link! Force antenna to %s\n",
4148 (value32 == 0x0 ? "MAIN" : "AUX"));
4149 #endif
4150 }
4151 fat_tab->is_become_linked = dm->is_linked;
4152 }
4153 }
4154
4155 if (!(*fat_tab->p_force_tx_by_desc)) {
4156 if (dm->is_one_entry_only == true)
4157 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
4158 else
4159 odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
4160 }
4161
4162 PHYDM_DBG(dm, DBG_ANT_DIV,
4163 "[%d] { try_flag=(( %d )), step=(( %d )), double_chk_flag = (( %d )) }\n",
4164 __LINE__, swat_tab->try_flag, step,
4165 swat_tab->double_chk_flag);
4166
4167 /* @ Handling step mismatch condition. */
4168 /* @ Peak step is not finished at last time. */
4169 /* @ Recover the variable and check again. */
4170 if (step != swat_tab->try_flag) {
4171 PHYDM_DBG(dm, DBG_ANT_DIV,
4172 "[step != try_flag] Need to Reset After Link\n");
4173 odm_sw_ant_div_rest_after_link(dm);
4174 }
4175
4176 if (swat_tab->try_flag == SWAW_STEP_INIT) {
4177 swat_tab->try_flag = SWAW_STEP_PEEK;
4178 swat_tab->train_time_flag = 0;
4179 PHYDM_DBG(dm, DBG_ANT_DIV,
4180 "[set try_flag = 0] Prepare for peek!\n\n");
4181 return;
4182
4183 } else {
4184 /* @1 Normal state (Begin Trying) */
4185 if (swat_tab->try_flag == SWAW_STEP_PEEK) {
4186 PHYDM_DBG(dm, DBG_ANT_DIV,
4187 "TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), traffic_load = (%d))\n",
4188 dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt,
4189 dm->traffic_load);
4190 phydm_sw_antdiv_train_time(dm);
4191
4192 PHYDM_DBG(dm, DBG_ANT_DIV,
4193 "Current min_max_rssi is ((%d))\n",
4194 fat_tab->min_max_rssi);
4195
4196 /* @---reset index--- */
4197 if (swat_tab->reset_idx >= RSSI_CHECK_RESET_PERIOD) {
4198 fat_tab->min_max_rssi = 0;
4199 swat_tab->reset_idx = 0;
4200 }
4201 PHYDM_DBG(dm, DBG_ANT_DIV, "reset_idx = (( %d ))\n",
4202 swat_tab->reset_idx);
4203
4204 swat_tab->reset_idx++;
4205
4206 /* @---double check flag--- */
4207 if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD &&
4208 swat_tab->double_chk_flag == 0) {
4209 PHYDM_DBG(dm, DBG_ANT_DIV,
4210 " min_max_rssi is ((%d)), and > %d\n",
4211 fat_tab->min_max_rssi,
4212 RSSI_CHECK_THRESHOLD);
4213
4214 swat_tab->double_chk_flag = 1;
4215 swat_tab->try_flag = SWAW_STEP_DETERMINE;
4216 swat_tab->rssi_trying = 0;
4217
4218 PHYDM_DBG(dm, DBG_ANT_DIV,
4219 "Test the current ant for (( %d )) ms again\n",
4220 swat_tab->train_time);
4221 odm_update_rx_idle_ant(dm,
4222 fat_tab->rx_idle_ant);
4223 odm_set_timer(dm, &swat_tab->sw_antdiv_timer,
4224 swat_tab->train_time); /*@ms*/
4225 return;
4226 }
4227
4228 next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ?
4229 AUX_ANT : MAIN_ANT;
4230
4231 swat_tab->try_flag = SWAW_STEP_DETERMINE;
4232
4233 if (swat_tab->reset_idx <= 1)
4234 swat_tab->rssi_trying = 2;
4235 else
4236 swat_tab->rssi_trying = 1;
4237
4238 odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_PEEK);
4239 PHYDM_DBG(dm, DBG_ANT_DIV,
4240 "[set try_flag=1] Normal state: Begin Trying!!\n");
4241
4242 } else if ((swat_tab->try_flag == SWAW_STEP_DETERMINE) &&
4243 (swat_tab->double_chk_flag == 0)) {
4244 next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ?
4245 AUX_ANT : MAIN_ANT;
4246 swat_tab->rssi_trying--;
4247 }
4248
4249 /* @1 Decision state */
4250 if (swat_tab->try_flag == SWAW_STEP_DETERMINE &&
4251 swat_tab->rssi_trying == 0) {
4252 phydm_sw_antdiv_decision(dm);
4253 return;
4254 }
4255 }
4256
4257 /* @1 4.Change TRX antenna */
4258
4259 PHYDM_DBG(dm, DBG_ANT_DIV,
4260 "rssi_trying = (( %d )), ant: (( %s )) >>> (( %s ))\n",
4261 swat_tab->rssi_trying,
4262 (fat_tab->rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"),
4263 (next_ant == MAIN_ANT ? "MAIN" : "AUX"));
4264
4265 odm_update_rx_idle_ant(dm, next_ant);
4266
4267 /* @1 5.Reset Statistics */
4268
4269 fat_tab->rx_idle_ant = next_ant;
4270
4271 if (dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710C) {
4272
4273 if (fat_tab->rx_idle_ant == MAIN_ANT) {
4274 fat_tab->main_sum[0] = 0;
4275 fat_tab->main_cnt[0] = 0;
4276 fat_tab->main_sum_cck[0] = 0;
4277 fat_tab->main_cnt_cck[0] = 0;
4278 } else {
4279 fat_tab->aux_sum[0] = 0;
4280 fat_tab->aux_cnt[0] = 0;
4281 fat_tab->aux_sum_cck[0] = 0;
4282 fat_tab->aux_cnt_cck[0] = 0;
4283 }
4284 }
4285
4286 if (dm->support_ic_type == ODM_RTL8188F) {
4287 if (dm->support_interface == ODM_ITRF_SDIO) {
4288 ODM_delay_us(200);
4289
4290 if (fat_tab->rx_idle_ant == MAIN_ANT) {
4291 fat_tab->main_sum[0] = 0;
4292 fat_tab->main_cnt[0] = 0;
4293 fat_tab->main_sum_cck[0] = 0;
4294 fat_tab->main_cnt_cck[0] = 0;
4295 } else {
4296 fat_tab->aux_sum[0] = 0;
4297 fat_tab->aux_cnt[0] = 0;
4298 fat_tab->aux_sum_cck[0] = 0;
4299 fat_tab->aux_cnt_cck[0] = 0;
4300 }
4301 }
4302 }
4303 /* @1 6.Set next timer (Trying state) */
4304 PHYDM_DBG(dm, DBG_ANT_DIV, " Test ((%s)) ant for (( %d )) ms\n",
4305 (next_ant == MAIN_ANT ? "MAIN" : "AUX"),
4306 swat_tab->train_time);
4307 odm_set_timer(dm, &swat_tab->sw_antdiv_timer, swat_tab->train_time);
4308 /*@ms*/
4309 }
4310
4311 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
odm_sw_antdiv_callback(struct phydm_timer_list * timer)4312 void odm_sw_antdiv_callback(struct phydm_timer_list *timer)
4313 {
4314 void *adapter = (void *)timer->Adapter;
4315 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
4316 struct sw_antenna_switch *swat_tab = &hal_data->DM_OutSrc.dm_swat_table;
4317
4318 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
4319 #if USE_WORKITEM
4320 odm_schedule_work_item(&swat_tab->phydm_sw_antenna_switch_workitem);
4321 #else
4322 {
4323 #if 0
4324 /* @dbg_print("SW_antdiv_Callback"); */
4325 #endif
4326 odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE);
4327 }
4328 #endif
4329 #else
4330 odm_schedule_work_item(&swat_tab->phydm_sw_antenna_switch_workitem);
4331 #endif
4332 }
4333
odm_sw_antdiv_workitem_callback(void * context)4334 void odm_sw_antdiv_workitem_callback(void *context)
4335 {
4336 void *adapter = (void *)context;
4337 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
4338
4339 #if 0
4340 /* @dbg_print("SW_antdiv_Workitem_Callback"); */
4341 #endif
4342 odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE);
4343 }
4344
4345 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
4346
odm_sw_antdiv_workitem_callback(void * context)4347 void odm_sw_antdiv_workitem_callback(void *context)
4348 {
4349 void *
4350 adapter = (void *)context;
4351 HAL_DATA_TYPE
4352 *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
4353
4354 #if 0
4355 /*@dbg_print("SW_antdiv_Workitem_Callback");*/
4356 #endif
4357 odm_s0s1_sw_ant_div(&hal_data->odmpriv, SWAW_STEP_DETERMINE);
4358 }
4359
odm_sw_antdiv_callback(void * function_context)4360 void odm_sw_antdiv_callback(void *function_context)
4361 {
4362 struct dm_struct *dm = (struct dm_struct *)function_context;
4363 void *padapter = dm->adapter;
4364 if (*dm->is_net_closed == true)
4365 return;
4366
4367 #if 0 /* @Can't do I/O in timer callback*/
4368 odm_s0s1_sw_ant_div(dm, SWAW_STEP_DETERMINE);
4369 #else
4370 rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback,
4371 padapter);
4372 #endif
4373 }
4374
4375 #elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
odm_sw_antdiv_callback(void * dm_void)4376 void odm_sw_antdiv_callback(void *dm_void)
4377 {
4378 struct dm_struct *dm = (struct dm_struct *)dm_void;
4379
4380 PHYDM_DBG(dm, DBG_ANT_DIV, "******AntDiv_Callback******\n");
4381 odm_s0s1_sw_ant_div(dm, SWAW_STEP_DETERMINE);
4382 }
4383 #endif
4384
odm_s0s1_sw_ant_div_by_ctrl_frame(void * dm_void,u8 step)4385 void odm_s0s1_sw_ant_div_by_ctrl_frame(void *dm_void, u8 step)
4386 {
4387 struct dm_struct *dm = (struct dm_struct *)dm_void;
4388 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
4389 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4390
4391 switch (step) {
4392 case SWAW_STEP_PEEK:
4393 swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame = 0;
4394 swat_tab->is_sw_ant_div_by_ctrl_frame = true;
4395 fat_tab->main_ctrl_cnt = 0;
4396 fat_tab->aux_ctrl_cnt = 0;
4397 fat_tab->main_ctrl_sum = 0;
4398 fat_tab->aux_ctrl_sum = 0;
4399 fat_tab->cck_ctrl_frame_cnt_main = 0;
4400 fat_tab->cck_ctrl_frame_cnt_aux = 0;
4401 fat_tab->ofdm_ctrl_frame_cnt_main = 0;
4402 fat_tab->ofdm_ctrl_frame_cnt_aux = 0;
4403 PHYDM_DBG(dm, DBG_ANT_DIV,
4404 "odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n");
4405 break;
4406 case SWAW_STEP_DETERMINE:
4407 swat_tab->is_sw_ant_div_by_ctrl_frame = false;
4408 PHYDM_DBG(dm, DBG_ANT_DIV,
4409 "odm_S0S1_SwAntDivForAPMode(): Stop peek\n");
4410 break;
4411 default:
4412 swat_tab->is_sw_ant_div_by_ctrl_frame = false;
4413 break;
4414 }
4415 }
4416
odm_antsel_statistics_ctrl(void * dm_void,u8 antsel_tr_mux,u32 rx_pwdb_all)4417 void odm_antsel_statistics_ctrl(void *dm_void, u8 antsel_tr_mux,
4418 u32 rx_pwdb_all)
4419 {
4420 struct dm_struct *dm = (struct dm_struct *)dm_void;
4421 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4422
4423 if (antsel_tr_mux == ANT1_2G) {
4424 fat_tab->main_ctrl_sum += rx_pwdb_all;
4425 fat_tab->main_ctrl_cnt++;
4426 } else {
4427 fat_tab->aux_ctrl_sum += rx_pwdb_all;
4428 fat_tab->aux_ctrl_cnt++;
4429 }
4430 }
4431
odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void * dm_void,void * phy_info_void,void * pkt_info_void)4432 void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void *dm_void,
4433 void *phy_info_void,
4434 void *pkt_info_void
4435 /* struct phydm_phyinfo_struct* phy_info, */
4436 /* struct phydm_perpkt_info_struct* pktinfo */
4437 )
4438 {
4439 struct dm_struct *dm = (struct dm_struct *)dm_void;
4440 struct phydm_phyinfo_struct *phy_info = NULL;
4441 struct phydm_perpkt_info_struct *pktinfo = NULL;
4442 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
4443 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4444 u8 rssi_cck;
4445
4446 phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
4447 pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
4448
4449 if (!(dm->support_ability & ODM_BB_ANT_DIV))
4450 return;
4451
4452 if (dm->ant_div_type != S0S1_SW_ANTDIV)
4453 return;
4454
4455 /* @In try state */
4456 if (!swat_tab->is_sw_ant_div_by_ctrl_frame)
4457 return;
4458
4459 /* No HW error and match receiver address */
4460 if (!pktinfo->is_to_self)
4461 return;
4462
4463 swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame++;
4464
4465 if (pktinfo->is_cck_rate) {
4466 rssi_cck = phy_info->rx_mimo_signal_strength[RF_PATH_A];
4467 fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ?
4468 ANT1_2G : ANT2_2G;
4469
4470 if (fat_tab->antsel_rx_keep_0 == ANT1_2G)
4471 fat_tab->cck_ctrl_frame_cnt_main++;
4472 else
4473 fat_tab->cck_ctrl_frame_cnt_aux++;
4474
4475 odm_antsel_statistics_ctrl(dm, fat_tab->antsel_rx_keep_0,
4476 rssi_cck);
4477 } else {
4478 fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ?
4479 ANT1_2G : ANT2_2G;
4480
4481 if (fat_tab->antsel_rx_keep_0 == ANT1_2G)
4482 fat_tab->ofdm_ctrl_frame_cnt_main++;
4483 else
4484 fat_tab->ofdm_ctrl_frame_cnt_aux++;
4485
4486 odm_antsel_statistics_ctrl(dm, fat_tab->antsel_rx_keep_0,
4487 phy_info->rx_pwdb_all);
4488 }
4489 }
4490
4491 #endif /* @#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) */
4492
odm_set_next_mac_addr_target(void * dm_void)4493 void odm_set_next_mac_addr_target(void *dm_void)
4494 {
4495 struct dm_struct *dm = (struct dm_struct *)dm_void;
4496 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4497 struct cmn_sta_info *entry;
4498 u32 value32, i;
4499
4500 PHYDM_DBG(dm, DBG_ANT_DIV, "%s ==>\n", __func__);
4501
4502 if (dm->is_linked) {
4503 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
4504 if ((fat_tab->train_idx + 1) == ODM_ASSOCIATE_ENTRY_NUM)
4505 fat_tab->train_idx = 0;
4506 else
4507 fat_tab->train_idx++;
4508
4509 entry = dm->phydm_sta_info[fat_tab->train_idx];
4510
4511 if (is_sta_active(entry)) {
4512 /*@Match MAC ADDR*/
4513 value32 = (entry->mac_addr[5] << 8) | entry->mac_addr[4];
4514
4515 odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, value32); /*@0x7b4~0x7b5*/
4516
4517 value32 = (entry->mac_addr[3] << 24) | (entry->mac_addr[2] << 16) | (entry->mac_addr[1] << 8) | entry->mac_addr[0];
4518
4519 odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, value32); /*@0x7b0~0x7b3*/
4520
4521 PHYDM_DBG(dm, DBG_ANT_DIV,
4522 "fat_tab->train_idx=%d\n",
4523 fat_tab->train_idx);
4524
4525 PHYDM_DBG(dm, DBG_ANT_DIV,
4526 "Training MAC addr = %x:%x:%x:%x:%x:%x\n",
4527 entry->mac_addr[5],
4528 entry->mac_addr[4],
4529 entry->mac_addr[3],
4530 entry->mac_addr[2],
4531 entry->mac_addr[1],
4532 entry->mac_addr[0]);
4533
4534 break;
4535 }
4536 }
4537 }
4538 }
4539
4540 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
4541
odm_fast_ant_training(void * dm_void)4542 void odm_fast_ant_training(
4543 void *dm_void)
4544 {
4545 struct dm_struct *dm = (struct dm_struct *)dm_void;
4546 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4547
4548 u32 max_rssi_path_a = 0, pckcnt_path_a = 0;
4549 u8 i, target_ant_path_a = 0;
4550 boolean is_pkt_filter_macth_path_a = false;
4551 #if (RTL8192E_SUPPORT == 1)
4552 u32 max_rssi_path_b = 0, pckcnt_path_b = 0;
4553 u8 target_ant_path_b = 0;
4554 boolean is_pkt_filter_macth_path_b = false;
4555 #endif
4556
4557 if (!dm->is_linked) { /* @is_linked==False */
4558 PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
4559
4560 if (fat_tab->is_become_linked == true) {
4561 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
4562 phydm_fast_training_enable(dm, FAT_OFF);
4563 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
4564 fat_tab->is_become_linked = dm->is_linked;
4565 }
4566 return;
4567 } else {
4568 if (fat_tab->is_become_linked == false) {
4569 PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked!!!]\n");
4570 fat_tab->is_become_linked = dm->is_linked;
4571 }
4572 }
4573
4574 if (!(*fat_tab->p_force_tx_by_desc)) {
4575 if (dm->is_one_entry_only == true)
4576 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
4577 else
4578 odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
4579 }
4580
4581 if (dm->support_ic_type == ODM_RTL8188E)
4582 odm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1));
4583 #if (RTL8192E_SUPPORT == 1)
4584 else if (dm->support_ic_type == ODM_RTL8192E) {
4585 odm_set_bb_reg(dm, R_0xb38, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1)); /* path-A */ /* ant combination=regB38[2:0]+1 */
4586 odm_set_bb_reg(dm, R_0xb38, BIT(18) | BIT(17) | BIT(16), ((dm->fat_comb_b) - 1)); /* path-B */ /* ant combination=regB38[18:16]+1 */
4587 }
4588 #endif
4589
4590 PHYDM_DBG(dm, DBG_ANT_DIV, "==>%s\n", __func__);
4591
4592 /* @1 TRAINING STATE */
4593 if (fat_tab->fat_state == FAT_TRAINING_STATE) {
4594 /* @2 Caculate RSSI per Antenna */
4595
4596 /* @3 [path-A]--------------------------- */
4597 for (i = 0; i < (dm->fat_comb_a); i++) { /* @i : antenna index */
4598 if (fat_tab->ant_rssi_cnt[i] == 0)
4599 fat_tab->ant_ave_rssi[i] = 0;
4600 else {
4601 fat_tab->ant_ave_rssi[i] = fat_tab->ant_sum_rssi[i] / fat_tab->ant_rssi_cnt[i];
4602 is_pkt_filter_macth_path_a = true;
4603 }
4604
4605 if (fat_tab->ant_ave_rssi[i] > max_rssi_path_a) {
4606 max_rssi_path_a = fat_tab->ant_ave_rssi[i];
4607 pckcnt_path_a = fat_tab->ant_rssi_cnt[i];
4608 target_ant_path_a = i;
4609 } else if (fat_tab->ant_ave_rssi[i] == max_rssi_path_a) {
4610 if (fat_tab->ant_rssi_cnt[i] > pckcnt_path_a) {
4611 max_rssi_path_a = fat_tab->ant_ave_rssi[i];
4612 pckcnt_path_a = fat_tab->ant_rssi_cnt[i];
4613 target_ant_path_a = i;
4614 }
4615 }
4616
4617 PHYDM_DBG(
4618 "*** ant-index : [ %d ], counter = (( %d )), Avg RSSI = (( %d ))\n",
4619 i, fat_tab->ant_rssi_cnt[i],
4620 fat_tab->ant_ave_rssi[i]);
4621 }
4622
4623 #if 0
4624 #if (RTL8192E_SUPPORT == 1)
4625 /* @3 [path-B]--------------------------- */
4626 for (i = 0; i < (dm->fat_comb_b); i++) {
4627 if (fat_tab->antRSSIcnt_pathB[i] == 0)
4628 fat_tab->antAveRSSI_pathB[i] = 0;
4629 else { /* @(ant_rssi_cnt[i] != 0) */
4630 fat_tab->antAveRSSI_pathB[i] = fat_tab->antSumRSSI_pathB[i] / fat_tab->antRSSIcnt_pathB[i];
4631 is_pkt_filter_macth_path_b = true;
4632 }
4633 if (fat_tab->antAveRSSI_pathB[i] > max_rssi_path_b) {
4634 max_rssi_path_b = fat_tab->antAveRSSI_pathB[i];
4635 pckcnt_path_b = fat_tab->antRSSIcnt_pathB[i];
4636 target_ant_path_b = (u8)i;
4637 }
4638 if (fat_tab->antAveRSSI_pathB[i] == max_rssi_path_b) {
4639 if (fat_tab->antRSSIcnt_pathB > pckcnt_path_b) {
4640 max_rssi_path_b = fat_tab->antAveRSSI_pathB[i];
4641 target_ant_path_b = (u8)i;
4642 }
4643 }
4644 if (dm->fat_print_rssi == 1) {
4645 PHYDM_DBG(dm, DBG_ANT_DIV,
4646 "***{path-B}: Sum RSSI[%d] = (( %d )), cnt RSSI [%d] = (( %d )), Avg RSSI[%d] = (( %d ))\n",
4647 i, fat_tab->antSumRSSI_pathB[i], i,
4648 fat_tab->antRSSIcnt_pathB[i], i,
4649 fat_tab->antAveRSSI_pathB[i]);
4650 }
4651 }
4652 #endif
4653 #endif
4654
4655 /* @1 DECISION STATE */
4656
4657 /* @2 Select TRX Antenna */
4658
4659 phydm_fast_training_enable(dm, FAT_OFF);
4660
4661 /* @3 [path-A]--------------------------- */
4662 if (is_pkt_filter_macth_path_a == false) {
4663 #if 0
4664 /* PHYDM_DBG(dm,DBG_ANT_DIV, "{path-A}: None Packet is matched\n"); */
4665 #endif
4666 PHYDM_DBG(dm, DBG_ANT_DIV,
4667 "{path-A}: None Packet is matched\n");
4668 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
4669 } else {
4670 PHYDM_DBG(
4671 "target_ant_path_a = (( %d )) , max_rssi_path_a = (( %d ))\n",
4672 target_ant_path_a, max_rssi_path_a);
4673
4674 /* @3 [ update RX-optional ant ] Default RX is Omni, Optional RX is the best decision by FAT */
4675 if (dm->support_ic_type == ODM_RTL8188E)
4676 odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), target_ant_path_a);
4677 else if (dm->support_ic_type == ODM_RTL8192E)
4678 odm_set_bb_reg(dm, R_0xb38, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); /* Optional RX [pth-A] */
4679
4680 /* @3 [ update TX ant ] */
4681 odm_update_tx_ant(dm, target_ant_path_a, (fat_tab->train_idx));
4682
4683 if (target_ant_path_a == 0)
4684 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
4685 }
4686 #if 0
4687 #if (RTL8192E_SUPPORT == 1)
4688 /* @3 [path-B]--------------------------- */
4689 if (is_pkt_filter_macth_path_b == false) {
4690 if (dm->fat_print_rssi == 1)
4691 PHYDM_DBG(dm, DBG_ANT_DIV,
4692 "***[%d]{path-B}: None Packet is matched\n\n\n",
4693 __LINE__);
4694 } else {
4695 if (dm->fat_print_rssi == 1) {
4696 PHYDM_DBG(dm, DBG_ANT_DIV,
4697 " ***target_ant_path_b = (( %d )) *** max_rssi = (( %d ))***\n\n\n",
4698 target_ant_path_b, max_rssi_path_b);
4699 }
4700 odm_set_bb_reg(dm, R_0xb38, BIT(21) | BIT20 | BIT19, target_ant_path_b); /* @Default RX is Omni, Optional RX is the best decision by FAT */
4701 odm_set_bb_reg(dm, R_0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 //from TX Info */
4702
4703 fat_tab->antsel_pathB[fat_tab->train_idx] = target_ant_path_b;
4704 }
4705 #endif
4706 #endif
4707
4708 /* @2 Reset counter */
4709 for (i = 0; i < (dm->fat_comb_a); i++) {
4710 fat_tab->ant_sum_rssi[i] = 0;
4711 fat_tab->ant_rssi_cnt[i] = 0;
4712 }
4713 /*@
4714 #if (RTL8192E_SUPPORT == 1)
4715 for(i=0; i<=(dm->fat_comb_b); i++)
4716 {
4717 fat_tab->antSumRSSI_pathB[i] = 0;
4718 fat_tab->antRSSIcnt_pathB[i] = 0;
4719 }
4720 #endif
4721 */
4722
4723 fat_tab->fat_state = FAT_PREPARE_STATE;
4724 return;
4725 }
4726
4727 /* @1 NORMAL STATE */
4728 if (fat_tab->fat_state == FAT_PREPARE_STATE) {
4729 PHYDM_DBG(dm, DBG_ANT_DIV, "[ Start Prepare state ]\n");
4730
4731 odm_set_next_mac_addr_target(dm);
4732
4733 /* @2 Prepare Training */
4734 fat_tab->fat_state = FAT_TRAINING_STATE;
4735 phydm_fast_training_enable(dm, FAT_ON);
4736 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
4737 /* @enable HW AntDiv */
4738 PHYDM_DBG(dm, DBG_ANT_DIV, "[Start Training state]\n");
4739
4740 odm_set_timer(dm, &dm->fast_ant_training_timer, dm->antdiv_intvl); /* @ms */
4741 }
4742 }
4743
odm_fast_ant_training_callback(void * dm_void)4744 void odm_fast_ant_training_callback(
4745 void *dm_void)
4746 {
4747 struct dm_struct *dm = (struct dm_struct *)dm_void;
4748
4749 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
4750 if (*(dm->is_net_closed) == true)
4751 return;
4752 #endif
4753
4754 #if USE_WORKITEM
4755 odm_schedule_work_item(&dm->fast_ant_training_workitem);
4756 #else
4757 PHYDM_DBG(dm, DBG_ANT_DIV, "******%s******\n", __func__);
4758 odm_fast_ant_training(dm);
4759 #endif
4760 }
4761
odm_fast_ant_training_work_item_callback(void * dm_void)4762 void odm_fast_ant_training_work_item_callback(
4763 void *dm_void)
4764 {
4765 struct dm_struct *dm = (struct dm_struct *)dm_void;
4766
4767 PHYDM_DBG(dm, DBG_ANT_DIV, "******%s******\n", __func__);
4768 odm_fast_ant_training(dm);
4769 }
4770
4771 #endif
4772
odm_ant_div_init(void * dm_void)4773 void odm_ant_div_init(void *dm_void)
4774 {
4775 struct dm_struct *dm = (struct dm_struct *)dm_void;
4776 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4777 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
4778 u8 i;
4779 if (!(dm->support_ability & ODM_BB_ANT_DIV)) {
4780 PHYDM_DBG(dm, DBG_ANT_DIV,
4781 "[Return!!!] Not Support Antenna Diversity Function\n");
4782 return;
4783 }
4784 /* @--- */
4785 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
4786 if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) {
4787 PHYDM_DBG(dm, DBG_ANT_DIV,
4788 "[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n");
4789 if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC))
4790 return;
4791 } else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) {
4792 PHYDM_DBG(dm, DBG_ANT_DIV,
4793 "[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n");
4794 if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC))
4795 return;
4796 } else if (fat_tab->ant_div_2g_5g == (ODM_ANTDIV_2G | ODM_ANTDIV_5G))
4797 PHYDM_DBG(dm, DBG_ANT_DIV,
4798 "[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n");
4799
4800 #endif
4801 /* @--- */
4802
4803 /* @2 [--General---] */
4804 dm->antdiv_period = 0;
4805
4806 fat_tab->is_become_linked = false;
4807 fat_tab->ant_div_on_off = 0xff;
4808
4809 for(i=0;i<3;i++)
4810 fat_tab->ant_idx_vec[i]=i+1; /* initialize ant_idx_vec for SP3T */
4811
4812
4813 /* @3 - AP - */
4814 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
4815
4816 #ifdef PHYDM_BEAMFORMING_SUPPORT
4817 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
4818 odm_bdc_init(dm);
4819 #endif
4820 #endif
4821
4822 /* @3 - WIN - */
4823 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4824 swat_tab->ant_5g = MAIN_ANT;
4825 swat_tab->ant_2g = MAIN_ANT;
4826 //#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
4827 // swat_tab->ant_2g = MAIN_ANT;
4828 #endif
4829
4830 /* @2 [---Set MAIN_ANT as default antenna if Auto-ant enable---] */
4831 if (fat_tab->div_path_type == ANT_PATH_A)
4832 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
4833 else if (fat_tab->div_path_type == ANT_PATH_B)
4834 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
4835 else if (fat_tab->div_path_type == ANT_PATH_AB)
4836 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
4837
4838 dm->ant_type = ODM_AUTO_ANT;
4839
4840 fat_tab->rx_idle_ant = 0xff;
4841
4842 if (dm->support_ic_type == ODM_RTL8710C) {
4843 /* Soft ware*/
4844 #if (RTL8710C_SUPPORT == 1)
4845 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
4846 HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xdc, HAL_READ32(SYSTEM_CTRL_BASE, R_0xdc) | BIT18 | BIT17 | BIT16);
4847 HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xac, HAL_READ32(SYSTEM_CTRL_BASE, R_0xac) | BIT24 | BIT6);
4848 HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x10, 0x307);// 1: enable gpio db32 clock , 1: enable gpio pclock
4849 HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x08, 0x80000111);
4850 HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x1208, 0x800000);
4851 } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
4852 HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xdc, HAL_READ32(SYSTEM_CTRL_BASE, R_0xdc) | BIT18 | BIT17);
4853 HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xdc, HAL_READ32(SYSTEM_CTRL_BASE, R_0xdc) & (~BIT16));
4854 HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xac, HAL_READ32(SYSTEM_CTRL_BASE, R_0xac) | BIT24 | BIT6);
4855 } else {
4856 PHYDM_DBG(dm, DBG_ANT_DIV,
4857 "[Return!!!] 8710C Not Supprrt This AntDiv type\n");
4858 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4859 return;
4860 }
4861 #endif
4862 }
4863
4864 /*to make RX-idle-antenna will be updated absolutly*/
4865 odm_update_rx_idle_ant(dm, MAIN_ANT);
4866 phydm_keep_rx_ack_ant_by_tx_ant_time(dm, 0);
4867 /* Timming issue: keep Rx ant after tx for ACK(5 x 3.2 mu = 16mu sec)*/
4868
4869 /* @2 [---Set TX Antenna---] */
4870 if (!fat_tab->p_force_tx_by_desc) {
4871 fat_tab->force_tx_by_desc = 0;
4872 fat_tab->p_force_tx_by_desc = &fat_tab->force_tx_by_desc;
4873 }
4874 PHYDM_DBG(dm, DBG_ANT_DIV, "p_force_tx_by_desc = %d\n",
4875 *fat_tab->p_force_tx_by_desc);
4876
4877 if (*fat_tab->p_force_tx_by_desc)
4878 odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
4879 else
4880 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
4881
4882 /* @2 [--88E---] */
4883 if (dm->support_ic_type == ODM_RTL8188E) {
4884 #if (RTL8188E_SUPPORT == 1)
4885 /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
4886 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
4887 /* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
4888
4889 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV &&
4890 dm->ant_div_type != CG_TRX_HW_ANTDIV &&
4891 dm->ant_div_type != CG_TRX_SMART_ANTDIV) {
4892 PHYDM_DBG(dm, DBG_ANT_DIV,
4893 "[Return!!!] 88E Not Supprrt This AntDiv type\n");
4894 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4895 return;
4896 }
4897
4898 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
4899 odm_rx_hw_ant_div_init_88e(dm);
4900 else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
4901 odm_trx_hw_ant_div_init_88e(dm);
4902 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
4903 else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
4904 odm_smart_hw_ant_div_init_88e(dm);
4905 #endif
4906 #endif
4907 }
4908
4909 /* @2 [--92E---] */
4910 #if (RTL8192E_SUPPORT == 1)
4911 else if (dm->support_ic_type == ODM_RTL8192E) {
4912 /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
4913 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
4914 /* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
4915
4916 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV &&
4917 dm->ant_div_type != CG_TRX_HW_ANTDIV &&
4918 dm->ant_div_type != CG_TRX_SMART_ANTDIV) {
4919 PHYDM_DBG(dm, DBG_ANT_DIV,
4920 "[Return!!!] 8192E Not Supprrt This AntDiv type\n");
4921 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4922 return;
4923 }
4924
4925 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
4926 odm_rx_hw_ant_div_init_92e(dm);
4927 else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
4928 odm_trx_hw_ant_div_init_92e(dm);
4929 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
4930 else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
4931 odm_smart_hw_ant_div_init_92e(dm);
4932 #endif
4933 }
4934 #endif
4935
4936 /* @2 [--92F---] */
4937 #if (RTL8192F_SUPPORT == 1)
4938 else if (dm->support_ic_type == ODM_RTL8192F) {
4939 /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
4940 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
4941 /* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
4942
4943 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
4944 if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
4945 PHYDM_DBG(dm, DBG_ANT_DIV,
4946 "[Return!!!] 8192F Not Supprrt This AntDiv type\n");
4947 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4948 return;
4949 }
4950 }
4951 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
4952 odm_rx_hw_ant_div_init_92f(dm);
4953 else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
4954 odm_trx_hw_ant_div_init_92f(dm);
4955 }
4956 #endif
4957
4958 #if (RTL8197F_SUPPORT == 1)
4959 else if (dm->support_ic_type == ODM_RTL8197F) {
4960 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
4961
4962 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
4963 PHYDM_DBG(dm, DBG_ANT_DIV,
4964 "[Return!!!] 8197F Not Supprrt This AntDiv type\n");
4965 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4966 return;
4967 }
4968 phydm_rx_hw_ant_div_init_97f(dm);
4969 }
4970 #endif
4971
4972 #if (RTL8197G_SUPPORT == 1)
4973 else if (dm->support_ic_type == ODM_RTL8197G) {
4974 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
4975
4976 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
4977 PHYDM_DBG(dm, DBG_ANT_DIV,
4978 "[Return!!!] 8197F Not Supprrt This AntDiv type\n");
4979 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4980 return;
4981 }
4982 phydm_rx_hw_ant_div_init_97g(dm);
4983 }
4984 #endif
4985
4986 #if (RTL8723F_SUPPORT == 1)
4987 else if (dm->support_ic_type == ODM_RTL8723F) {
4988 dm->ant_div_type = CG_TRX_HW_ANTDIV;
4989
4990 if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
4991 PHYDM_DBG(dm, DBG_ANT_DIV,
4992 "[Return!!!] 8723F Not Supprrt This AntDiv type\n");
4993 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4994 return;
4995 }
4996 phydm_rx_hw_ant_div_init_23f(dm);
4997 }
4998 #endif
4999 /* @2 [--8723B---] */
5000 #if (RTL8723B_SUPPORT == 1)
5001 else if (dm->support_ic_type == ODM_RTL8723B) {
5002 dm->ant_div_type = S0S1_SW_ANTDIV;
5003 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
5004
5005 if (dm->ant_div_type != S0S1_SW_ANTDIV &&
5006 dm->ant_div_type != CG_TRX_HW_ANTDIV) {
5007 PHYDM_DBG(dm, DBG_ANT_DIV,
5008 "[Return!!!] 8723B Not Supprrt This AntDiv type\n");
5009 dm->support_ability &= ~(ODM_BB_ANT_DIV);
5010 return;
5011 }
5012
5013 if (dm->ant_div_type == S0S1_SW_ANTDIV)
5014 odm_s0s1_sw_ant_div_init_8723b(dm);
5015 else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
5016 odm_trx_hw_ant_div_init_8723b(dm);
5017 }
5018 #endif
5019 /*@2 [--8723D---]*/
5020 #if (RTL8723D_SUPPORT == 1)
5021 else if (dm->support_ic_type == ODM_RTL8723D) {
5022 if (fat_tab->p_default_s0_s1 == NULL) {
5023 fat_tab->default_s0_s1 = 1;
5024 fat_tab->p_default_s0_s1 = &fat_tab->default_s0_s1;
5025 }
5026 PHYDM_DBG(dm, DBG_ANT_DIV, "default_s0_s1 = %d\n",
5027 *fat_tab->p_default_s0_s1);
5028
5029 if (*fat_tab->p_default_s0_s1 == true)
5030 odm_update_rx_idle_ant(dm, MAIN_ANT);
5031 else
5032 odm_update_rx_idle_ant(dm, AUX_ANT);
5033
5034 if (dm->ant_div_type == S0S1_TRX_HW_ANTDIV)
5035 odm_trx_hw_ant_div_init_8723d(dm);
5036 else if (dm->ant_div_type == S0S1_SW_ANTDIV)
5037 odm_s0s1_sw_ant_div_init_8723d(dm);
5038 else {
5039 PHYDM_DBG(dm, DBG_ANT_DIV,
5040 "[Return!!!] 8723D Not Supprrt This AntDiv type\n");
5041 dm->support_ability &= ~(ODM_BB_ANT_DIV);
5042 return;
5043 }
5044 }
5045 #endif
5046 #if (RTL8710C_SUPPORT == 1)
5047 else if (dm->support_ic_type == ODM_RTL8710C) {
5048 if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
5049 odm_trx_hw_ant_div_init_8710c(dm);
5050 else if(dm->ant_div_type == S0S1_SW_ANTDIV){
5051 if (fat_tab->p_default_s0_s1 == NULL){
5052 fat_tab->default_s0_s1 = 1;
5053 fat_tab->p_default_s0_s1 = &fat_tab->default_s0_s1;
5054 }
5055 PHYDM_DBG(dm, DBG_ANT_DIV, "default_s0_s1 = %d\n",
5056 *fat_tab->p_default_s0_s1);
5057 if (*fat_tab->p_default_s0_s1 == true)
5058 odm_update_rx_idle_ant(dm, MAIN_ANT);
5059 else
5060 odm_update_rx_idle_ant(dm, AUX_ANT);
5061 odm_s0s1_sw_ant_div_init_8710c(dm);
5062 }
5063 }
5064 #endif
5065 #if (RTL8721D_SUPPORT == 1)
5066 else if (dm->support_ic_type == ODM_RTL8721D) {
5067 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
5068
5069 if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
5070 PHYDM_DBG(dm, DBG_ANT_DIV,
5071 "[Return!!!] 8721D Not Supprrt This AntDiv type\n");
5072 dm->support_ability &= ~(ODM_BB_ANT_DIV);
5073 return;
5074 }
5075 if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
5076 odm_trx_hw_ant_div_init_8721d(dm);
5077 }
5078 #endif
5079 /* @2 [--8811A 8821A---] */
5080 #if (RTL8821A_SUPPORT == 1)
5081 else if (dm->support_ic_type == ODM_RTL8821) {
5082 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
5083 dm->ant_div_type = HL_SW_SMART_ANT_TYPE1;
5084
5085 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
5086 odm_trx_hw_ant_div_init_8821a(dm);
5087 phydm_hl_smart_ant_type1_init_8821a(dm);
5088 } else
5089 #endif
5090 {
5091 #ifdef ODM_CONFIG_BT_COEXIST
5092 dm->ant_div_type = S0S1_SW_ANTDIV;
5093 #else
5094 dm->ant_div_type = CG_TRX_HW_ANTDIV;
5095 #endif
5096
5097 if (dm->ant_div_type != CG_TRX_HW_ANTDIV &&
5098 dm->ant_div_type != S0S1_SW_ANTDIV) {
5099 PHYDM_DBG(dm, DBG_ANT_DIV,
5100 "[Return!!!] 8821A & 8811A Not Supprrt This AntDiv type\n");
5101 dm->support_ability &= ~(ODM_BB_ANT_DIV);
5102 return;
5103 }
5104 if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
5105 odm_trx_hw_ant_div_init_8821a(dm);
5106 else if (dm->ant_div_type == S0S1_SW_ANTDIV)
5107 odm_s0s1_sw_ant_div_init_8821a(dm);
5108 }
5109 }
5110 #endif
5111
5112 /* @2 [--8821C---] */
5113 #if (RTL8821C_SUPPORT == 1)
5114 else if (dm->support_ic_type == ODM_RTL8821C) {
5115 dm->ant_div_type = S0S1_SW_ANTDIV;
5116 if (dm->ant_div_type != S0S1_SW_ANTDIV) {
5117 PHYDM_DBG(dm, DBG_ANT_DIV,
5118 "[Return!!!] 8821C Not Supprrt This AntDiv type\n");
5119 dm->support_ability &= ~(ODM_BB_ANT_DIV);
5120 return;
5121 }
5122 phydm_s0s1_sw_ant_div_init_8821c(dm);
5123 odm_trx_hw_ant_div_init_8821c(dm);
5124 }
5125 #endif
5126
5127 /* @2 [--8195B---] */
5128 #if (RTL8195B_SUPPORT == 1)
5129 else if (dm->support_ic_type == ODM_RTL8195B) {
5130 dm->ant_div_type = CG_TRX_HW_ANTDIV;
5131 if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
5132 PHYDM_DBG(dm, DBG_ANT_DIV,
5133 "[Return!!!] 8821C Not Supprrt This AntDiv type\n");
5134 dm->support_ability &= ~(ODM_BB_ANT_DIV);
5135 return;
5136 }
5137 odm_trx_hw_ant_div_init_8195b(dm);
5138 }
5139 #endif
5140
5141 /* @2 [--8881A---] */
5142 #if (RTL8881A_SUPPORT == 1)
5143 else if (dm->support_ic_type == ODM_RTL8881A) {
5144 /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
5145 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
5146
5147 if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
5148 odm_trx_hw_ant_div_init_8881a(dm);
5149 } else {
5150 PHYDM_DBG(dm, DBG_ANT_DIV,
5151 "[Return!!!] 8881A Not Supprrt This AntDiv type\n");
5152 dm->support_ability &= ~(ODM_BB_ANT_DIV);
5153 return;
5154 }
5155
5156 odm_trx_hw_ant_div_init_8881a(dm);
5157 }
5158 #endif
5159
5160 /* @2 [--8812---] */
5161 #if (RTL8812A_SUPPORT == 1)
5162 else if (dm->support_ic_type == ODM_RTL8812) {
5163 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
5164
5165 if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
5166 PHYDM_DBG(dm, DBG_ANT_DIV,
5167 "[Return!!!] 8812A Not Supprrt This AntDiv type\n");
5168 dm->support_ability &= ~(ODM_BB_ANT_DIV);
5169 return;
5170 }
5171 odm_trx_hw_ant_div_init_8812a(dm);
5172 }
5173 #endif
5174
5175 /*@[--8188F---]*/
5176 #if (RTL8188F_SUPPORT == 1)
5177 else if (dm->support_ic_type == ODM_RTL8188F) {
5178 dm->ant_div_type = S0S1_SW_ANTDIV;
5179 odm_s0s1_sw_ant_div_init_8188f(dm);
5180 }
5181 #endif
5182
5183 /*@[--8822B---]*/
5184 #if (RTL8822B_SUPPORT == 1)
5185 else if (dm->support_ic_type == ODM_RTL8822B) {
5186 dm->ant_div_type = CG_TRX_HW_ANTDIV;
5187
5188 if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
5189 PHYDM_DBG(dm, DBG_ANT_DIV,
5190 "[Return!!!] 8822B Not Supprrt This AntDiv type\n");
5191 dm->support_ability &= ~(ODM_BB_ANT_DIV);
5192 return;
5193 }
5194 phydm_trx_hw_ant_div_init_22b(dm);
5195 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
5196 dm->ant_div_type = HL_SW_SMART_ANT_TYPE2;
5197
5198 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2)
5199 phydm_hl_smart_ant_type2_init_8822b(dm);
5200 #endif
5201 }
5202 #endif
5203
5204 /*@PHYDM_DBG(dm, DBG_ANT_DIV, "*** support_ic_type=[%lu]\n",*/
5205 /*dm->support_ic_type);*/
5206 /*PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv support_ability=[%lu]\n",*/
5207 /* (dm->support_ability & ODM_BB_ANT_DIV)>>6);*/
5208 /*PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv type=[%d]\n",dm->ant_div_type);*/
5209 }
5210
odm_ant_div(void * dm_void)5211 void odm_ant_div(void *dm_void)
5212 {
5213 struct dm_struct *dm = (struct dm_struct *)dm_void;
5214 void *adapter = dm->adapter;
5215 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5216 #if (defined(CONFIG_HL_SMART_ANTENNA))
5217 struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
5218 #endif
5219
5220 if (!(dm->support_ability & ODM_BB_ANT_DIV))
5221 return;
5222
5223 #ifdef ODM_EVM_ENHANCE_ANTDIV
5224 if (dm->is_linked) {
5225 PHYDM_DBG(dm, DBG_ANT_DIV,
5226 "tp_active_occur=((%d)), evm_method_enable=((%d))\n",
5227 dm->tp_active_occur, fat_tab->evm_method_enable);
5228
5229 if (dm->tp_active_occur == 1 &&
5230 fat_tab->evm_method_enable == 1) {
5231 fat_tab->idx_ant_div_counter_5g = dm->antdiv_period;
5232 fat_tab->idx_ant_div_counter_2g = dm->antdiv_period;
5233 }
5234 }
5235 #endif
5236
5237 if (*dm->band_type == ODM_BAND_5G) {
5238 if (fat_tab->idx_ant_div_counter_5g < dm->antdiv_period) {
5239 fat_tab->idx_ant_div_counter_5g++;
5240 return;
5241 } else
5242 fat_tab->idx_ant_div_counter_5g = 0;
5243 } else if (*dm->band_type == ODM_BAND_2_4G) {
5244 if (fat_tab->idx_ant_div_counter_2g < dm->antdiv_period) {
5245 fat_tab->idx_ant_div_counter_2g++;
5246 return;
5247 } else
5248 fat_tab->idx_ant_div_counter_2g = 0;
5249 }
5250
5251 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN || DM_ODM_SUPPORT_TYPE == ODM_CE)
5252
5253 if (fat_tab->enable_ctrl_frame_antdiv) {
5254 if (dm->data_frame_num <= 10 && dm->is_linked)
5255 fat_tab->use_ctrl_frame_antdiv = 1;
5256 else
5257 fat_tab->use_ctrl_frame_antdiv = 0;
5258
5259 PHYDM_DBG(dm, DBG_ANT_DIV,
5260 "use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n",
5261 fat_tab->use_ctrl_frame_antdiv, dm->data_frame_num);
5262 dm->data_frame_num = 0;
5263 }
5264
5265 {
5266 #ifdef PHYDM_BEAMFORMING_SUPPORT
5267
5268 enum beamforming_cap beamform_cap = phydm_get_beamform_cap(dm);
5269 PHYDM_DBG(dm, DBG_ANT_DIV, "is_bt_continuous_turn = ((%d))\n",
5270 dm->is_bt_continuous_turn);
5271 PHYDM_DBG(dm, DBG_ANT_DIV,
5272 "[ AntDiv Beam Cap ] cap= ((%d))\n", beamform_cap);
5273 if (!dm->is_bt_continuous_turn) {
5274 if ((beamform_cap & BEAMFORMEE_CAP) &&
5275 (!(*fat_tab->is_no_csi_feedback))) {
5276 /* @BFmee On && Div On->Div Off */
5277 PHYDM_DBG(dm, DBG_ANT_DIV,
5278 "[ AntDiv : OFF ] BFmee ==1; cap= ((%d))\n",
5279 beamform_cap);
5280 PHYDM_DBG(dm, DBG_ANT_DIV,
5281 "[ AntDiv BF] is_no_csi_feedback= ((%d))\n",
5282 *(fat_tab->is_no_csi_feedback));
5283 if (fat_tab->fix_ant_bfee == 0) {
5284 odm_ant_div_on_off(dm, ANTDIV_OFF,
5285 ANT_PATH_A);
5286 fat_tab->fix_ant_bfee = 1;
5287 }
5288 return;
5289 } else { /* @BFmee Off && Div Off->Div On */
5290 if (fat_tab->fix_ant_bfee == 1 &&
5291 dm->is_linked) {
5292 PHYDM_DBG(dm, DBG_ANT_DIV,
5293 "[ AntDiv : ON ] BFmee ==0; cap=((%d))\n",
5294 beamform_cap);
5295 PHYDM_DBG(dm, DBG_ANT_DIV,
5296 "[ AntDiv BF] is_no_csi_feedback= ((%d))\n",
5297 *fat_tab->is_no_csi_feedback);
5298 if (dm->ant_div_type != S0S1_SW_ANTDIV)
5299 odm_ant_div_on_off(dm, ANTDIV_ON
5300 , ANT_PATH_A)
5301 ;
5302 fat_tab->fix_ant_bfee = 0;
5303 }
5304 }
5305 } else {
5306 if (fat_tab->div_path_type == ANT_PATH_A)
5307 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
5308 else if (fat_tab->div_path_type == ANT_PATH_B)
5309 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
5310 else if (fat_tab->div_path_type == ANT_PATH_AB)
5311 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
5312 }
5313 #endif
5314 }
5315 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
5316 /* @----------just for fool proof */
5317
5318 if (dm->antdiv_rssi)
5319 dm->debug_components |= DBG_ANT_DIV;
5320 else
5321 dm->debug_components &= ~DBG_ANT_DIV;
5322
5323 if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) {
5324 if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC))
5325 return;
5326 } else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) {
5327 if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC))
5328 return;
5329 }
5330 #endif
5331
5332 /* @---------- */
5333
5334 if (dm->antdiv_select == 1)
5335 dm->ant_type = ODM_FIX_MAIN_ANT;
5336 else if (dm->antdiv_select == 2)
5337 dm->ant_type = ODM_FIX_AUX_ANT;
5338 else { /* @if (dm->antdiv_select==0) */
5339 dm->ant_type = ODM_AUTO_ANT;
5340
5341 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
5342 /*Stop Antenna diversity for CMW500 testing case*/
5343 if (dm->consecutive_idlel_time >= 10) {
5344 dm->ant_type = ODM_FIX_MAIN_ANT;
5345 PHYDM_DBG(dm, DBG_ANT_DIV,
5346 "[AntDiv: OFF] No TP case, consecutive_idlel_time=((%d))\n",
5347 dm->consecutive_idlel_time);
5348 }
5349 #endif
5350 }
5351
5352 /*PHYDM_DBG(dm, DBG_ANT_DIV,"ant_type= (%d), pre_ant_type= (%d)\n",*/
5353 /*dm->ant_type,dm->pre_ant_type); */
5354
5355 if (dm->ant_type != ODM_AUTO_ANT) {
5356 PHYDM_DBG(dm, DBG_ANT_DIV, "Fix Antenna at (( %s ))\n",
5357 (dm->ant_type == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX");
5358
5359 if (dm->ant_type != dm->pre_ant_type) {
5360 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
5361 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
5362
5363 if (dm->ant_type == ODM_FIX_MAIN_ANT)
5364 odm_update_rx_idle_ant(dm, MAIN_ANT);
5365 else if (dm->ant_type == ODM_FIX_AUX_ANT)
5366 odm_update_rx_idle_ant(dm, AUX_ANT);
5367 }
5368 dm->pre_ant_type = dm->ant_type;
5369 return;
5370 } else {
5371 if (dm->ant_type != dm->pre_ant_type) {
5372 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
5373 odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
5374 }
5375 dm->pre_ant_type = dm->ant_type;
5376 }
5377 #if (defined(CONFIG_2T4R_ANTENNA))
5378 if (dm->ant_type2 != ODM_AUTO_ANT) {
5379 PHYDM_DBG(dm, DBG_ANT_DIV, "PathB Fix Ant at (( %s ))\n",
5380 (dm->ant_type2 == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX");
5381
5382 if (dm->ant_type2 != dm->pre_ant_type2) {
5383 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
5384 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
5385
5386 if (dm->ant_type2 == ODM_FIX_MAIN_ANT)
5387 phydm_update_rx_idle_ant_pathb(dm, MAIN_ANT);
5388 else if (dm->ant_type2 == ODM_FIX_AUX_ANT)
5389 phydm_update_rx_idle_ant_pathb(dm, AUX_ANT);
5390 }
5391 dm->pre_ant_type2 = dm->ant_type2;
5392 return;
5393 }
5394 if (dm->ant_type2 != dm->pre_ant_type2) {
5395 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
5396 odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
5397 }
5398 dm->pre_ant_type2 = dm->ant_type2;
5399
5400 #endif
5401
5402 /*@ ----------------------------------------------- */
5403 /*@ [--8188E--] */
5404 if (dm->support_ic_type == ODM_RTL8188E) {
5405 #if (RTL8188E_SUPPORT == 1)
5406 if (dm->ant_div_type == CG_TRX_HW_ANTDIV ||
5407 dm->ant_div_type == CGCS_RX_HW_ANTDIV)
5408 odm_hw_ant_div(dm);
5409
5410 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
5411 (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
5412 else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
5413 odm_fast_ant_training(dm);
5414 #endif
5415
5416 #endif
5417 }
5418 /*@ [--8192E--] */
5419 #if (RTL8192E_SUPPORT == 1)
5420 else if (dm->support_ic_type == ODM_RTL8192E) {
5421 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV ||
5422 dm->ant_div_type == CG_TRX_HW_ANTDIV)
5423 odm_hw_ant_div(dm);
5424
5425 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
5426 (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
5427 else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
5428 odm_fast_ant_training(dm);
5429 #endif
5430 }
5431 #endif
5432 /*@ [--8197F--] */
5433 #if (RTL8197F_SUPPORT == 1)
5434 else if (dm->support_ic_type == ODM_RTL8197F) {
5435 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
5436 odm_hw_ant_div(dm);
5437 }
5438 #endif
5439
5440 /*@ [--8197G--] */
5441 #if (RTL8197G_SUPPORT == 1)
5442 else if (dm->support_ic_type == ODM_RTL8197G) {
5443 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
5444 odm_hw_ant_div(dm);
5445 }
5446 #endif
5447
5448 /*@ [--8723F--] */
5449 #if (RTL8723F_SUPPORT == 1)
5450 else if (dm->support_ic_type == ODM_RTL8723F) {
5451 if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
5452 odm_hw_ant_div(dm);
5453 }
5454 #endif
5455
5456 #if (RTL8723B_SUPPORT == 1)
5457 /*@ [--8723B---] */
5458 else if (dm->support_ic_type == ODM_RTL8723B) {
5459 if (phydm_is_bt_enable_8723b(dm)) {
5460 PHYDM_DBG(dm, DBG_ANT_DIV, "[BT is enable!!!]\n");
5461 if (fat_tab->is_become_linked == true) {
5462 PHYDM_DBG(dm, DBG_ANT_DIV,
5463 "Set REG 948[9:6]=0x0\n");
5464 if (dm->support_ic_type == ODM_RTL8723B)
5465 odm_set_bb_reg(dm, R_0x948, 0x3c0, 0x0)
5466 ;
5467
5468 fat_tab->is_become_linked = false;
5469 }
5470 } else {
5471 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
5472 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5473 odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
5474 #endif
5475 } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
5476 odm_hw_ant_div(dm);
5477 }
5478 }
5479 #endif
5480 /*@ [--8723D--]*/
5481 #if (RTL8723D_SUPPORT == 1)
5482 else if (dm->support_ic_type == ODM_RTL8723D) {
5483 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
5484 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5485 if (dm->antdiv_counter == CONFIG_ANTDIV_PERIOD) {
5486 odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
5487 dm->antdiv_counter--;
5488 } else {
5489 dm->antdiv_counter--;
5490 }
5491 if (dm->antdiv_counter == 0)
5492 dm->antdiv_counter = CONFIG_ANTDIV_PERIOD;
5493 #endif
5494 } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
5495 odm_hw_ant_div(dm);
5496 }
5497 }
5498 #endif
5499 #if (RTL8721D_SUPPORT == 1)
5500 else if (dm->support_ic_type == ODM_RTL8721D) {
5501 if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
5502 odm_hw_ant_div(dm);
5503 }
5504 }
5505 #endif
5506 #if (RTL8710C_SUPPORT == 1)
5507 else if (dm->support_ic_type == ODM_RTL8710C) {
5508 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
5509 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5510 if (dm->antdiv_counter == CONFIG_ANTDIV_PERIOD) {
5511 odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
5512 dm->antdiv_counter--;
5513 } else {
5514 dm->antdiv_counter--;
5515 }
5516 if (dm->antdiv_counter == 0)
5517 dm->antdiv_counter = CONFIG_ANTDIV_PERIOD;
5518 #endif
5519 } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
5520 odm_hw_ant_div(dm);
5521 }
5522 }
5523 #endif
5524 /*@ [--8821A--] */
5525 #if (RTL8821A_SUPPORT == 1)
5526 else if (dm->support_ic_type == ODM_RTL8821) {
5527 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
5528 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
5529 if (sat_tab->fix_beam_pattern_en != 0) {
5530 PHYDM_DBG(dm, DBG_ANT_DIV,
5531 " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n",
5532 sat_tab->fix_beam_pattern_codeword);
5533 /*return;*/
5534 } else {
5535 odm_fast_ant_training_hl_smart_antenna_type1(dm);
5536 }
5537
5538 } else
5539 #endif
5540 {
5541 #ifdef ODM_CONFIG_BT_COEXIST
5542 if (!dm->bt_info_table.is_bt_enabled) { /*@BT disabled*/
5543 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
5544 dm->ant_div_type = CG_TRX_HW_ANTDIV;
5545 PHYDM_DBG(dm, DBG_ANT_DIV,
5546 " [S0S1_SW_ANTDIV] -> [CG_TRX_HW_ANTDIV]\n");
5547 /*odm_set_bb_reg(dm, 0x8d4, BIT24, 1);*/
5548 if (fat_tab->is_become_linked == true)
5549 odm_ant_div_on_off(dm,
5550 ANTDIV_ON,
5551 ANT_PATH_A);
5552 }
5553
5554 } else { /*@BT enabled*/
5555
5556 if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
5557 dm->ant_div_type = S0S1_SW_ANTDIV;
5558 PHYDM_DBG(dm, DBG_ANT_DIV,
5559 " [CG_TRX_HW_ANTDIV] -> [S0S1_SW_ANTDIV]\n");
5560 /*odm_set_bb_reg(dm, 0x8d4, BIT24, 0);*/
5561 odm_ant_div_on_off(dm, ANTDIV_OFF,
5562 ANT_PATH_A);
5563 }
5564 }
5565 #endif
5566
5567 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
5568 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5569 odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
5570 #endif
5571 } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
5572 odm_hw_ant_div(dm);
5573 }
5574 }
5575 }
5576 #endif
5577
5578 /*@ [--8821C--] */
5579 #if (RTL8821C_SUPPORT == 1)
5580 else if (dm->support_ic_type == ODM_RTL8821C) {
5581 if (!dm->is_bt_continuous_turn) {
5582 dm->ant_div_type = S0S1_SW_ANTDIV;
5583 PHYDM_DBG(dm, DBG_ANT_DIV,
5584 "is_bt_continuous_turn = ((%d)) ==> SW AntDiv\n",
5585 dm->is_bt_continuous_turn);
5586
5587 } else {
5588 dm->ant_div_type = CG_TRX_HW_ANTDIV;
5589 PHYDM_DBG(dm, DBG_ANT_DIV,
5590 "is_bt_continuous_turn = ((%d)) ==> HW AntDiv\n",
5591 dm->is_bt_continuous_turn);
5592 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
5593 }
5594
5595 if (fat_tab->force_antdiv_type)
5596 dm->ant_div_type = fat_tab->antdiv_type_dbg;
5597
5598 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
5599 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5600 odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
5601 #endif
5602 } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
5603 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
5604 odm_hw_ant_div(dm);
5605 }
5606 }
5607 #endif
5608
5609 /* @ [--8195B--] */
5610 #if (RTL8195B_SUPPORT == 1)
5611 else if (dm->support_ic_type == ODM_RTL8195B) {
5612 if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
5613 odm_hw_ant_div(dm);
5614 }
5615 }
5616 #endif
5617
5618 /* @ [--8881A--] */
5619 #if (RTL8881A_SUPPORT == 1)
5620 else if (dm->support_ic_type == ODM_RTL8881A)
5621 odm_hw_ant_div(dm);
5622 #endif
5623
5624 /*@ [--8812A--] */
5625 #if (RTL8812A_SUPPORT == 1)
5626 else if (dm->support_ic_type == ODM_RTL8812)
5627 odm_hw_ant_div(dm);
5628 #endif
5629
5630 #if (RTL8188F_SUPPORT == 1)
5631 /*@ [--8188F--]*/
5632 else if (dm->support_ic_type == ODM_RTL8188F) {
5633 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5634 odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
5635 #endif
5636 }
5637 #endif
5638
5639 /*@ [--8822B--]*/
5640 #if (RTL8822B_SUPPORT == 1)
5641 else if (dm->support_ic_type == ODM_RTL8822B) {
5642 if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
5643 odm_hw_ant_div(dm);
5644 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
5645 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) {
5646 if (sat_tab->fix_beam_pattern_en != 0)
5647 PHYDM_DBG(dm, DBG_ANT_DIV,
5648 " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n",
5649 sat_tab->fix_beam_pattern_codeword);
5650 else
5651 phydm_fast_ant_training_hl_smart_antenna_type2(dm);
5652 }
5653 #endif
5654 }
5655 #endif
5656 }
5657
odm_antsel_statistics(void * dm_void,void * phy_info_void,u8 antsel_tr_mux,u32 mac_id,u32 utility,u8 method,u8 is_cck_rate)5658 void odm_antsel_statistics(void *dm_void, void *phy_info_void,
5659 u8 antsel_tr_mux, u32 mac_id, u32 utility, u8 method,
5660 u8 is_cck_rate)
5661 {
5662 struct dm_struct *dm = (struct dm_struct *)dm_void;
5663 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5664 struct phydm_phyinfo_struct *phy_info = NULL;
5665
5666 phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
5667
5668 if (method == RSSI_METHOD) {
5669 if (is_cck_rate) {
5670 if (antsel_tr_mux == fat_tab->ant_idx_vec[0]-1) {
5671 /*to prevent u16 overflow, max(RSSI)=100, 65435+100 = 65535 (u16)*/
5672 if (fat_tab->main_sum_cck[mac_id] > 65435)
5673 return;
5674
5675 fat_tab->main_sum_cck[mac_id] += (u16)utility;
5676 fat_tab->main_cnt_cck[mac_id]++;
5677 } else {
5678 if (fat_tab->aux_sum_cck[mac_id] > 65435)
5679 return;
5680
5681 fat_tab->aux_sum_cck[mac_id] += (u16)utility;
5682 fat_tab->aux_cnt_cck[mac_id]++;
5683 }
5684
5685 } else { /*ofdm rate*/
5686
5687 if (antsel_tr_mux == fat_tab->ant_idx_vec[0]-1) {
5688 if (fat_tab->main_sum[mac_id] > 65435)
5689 return;
5690
5691 fat_tab->main_sum[mac_id] += (u16)utility;
5692 fat_tab->main_cnt[mac_id]++;
5693 } else {
5694 if (fat_tab->aux_sum[mac_id] > 65435)
5695 return;
5696
5697 fat_tab->aux_sum[mac_id] += (u16)utility;
5698 fat_tab->aux_cnt[mac_id]++;
5699 }
5700 }
5701 }
5702 #ifdef ODM_EVM_ENHANCE_ANTDIV
5703 else if (method == EVM_METHOD) {
5704 if (!fat_tab->get_stats)
5705 return;
5706
5707 if (dm->rate_ss == 1) {
5708 phydm_statistics_evm_1ss(dm, phy_info, antsel_tr_mux,
5709 mac_id, utility);
5710 } else { /*@>= 2SS*/
5711 phydm_statistics_evm_2ss(dm, phy_info, antsel_tr_mux,
5712 mac_id, utility);
5713 }
5714
5715 } else if (method == CRC32_METHOD) {
5716 if (antsel_tr_mux == ANT1_2G) {
5717 fat_tab->main_crc32_ok_cnt += utility;
5718 fat_tab->main_crc32_fail_cnt++;
5719 } else {
5720 fat_tab->aux_crc32_ok_cnt += utility;
5721 fat_tab->aux_crc32_fail_cnt++;
5722 }
5723
5724 } else if (method == TP_METHOD) {
5725 if (!fat_tab->get_stats)
5726 return;
5727 if (utility <= ODM_RATEMCS15 && utility >= ODM_RATEMCS0) {
5728 if (antsel_tr_mux == ANT1_2G) {
5729 fat_tab->main_tp += (phy_rate_table[utility])
5730 << 5;
5731 fat_tab->main_tp_cnt++;
5732 } else {
5733 fat_tab->aux_tp += (phy_rate_table[utility])
5734 << 5;
5735 fat_tab->aux_tp_cnt++;
5736 }
5737 }
5738 }
5739 #endif
5740 }
5741
odm_process_rssi_smart(void * dm_void,void * phy_info_void,void * pkt_info_void,u8 rx_power_ant0)5742 void odm_process_rssi_smart(void *dm_void, void *phy_info_void,
5743 void *pkt_info_void, u8 rx_power_ant0)
5744 {
5745 struct dm_struct *dm = (struct dm_struct *)dm_void;
5746 struct phydm_phyinfo_struct *phy_info = NULL;
5747 struct phydm_perpkt_info_struct *pktinfo = NULL;
5748 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5749
5750 phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
5751 pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
5752
5753 if ((dm->support_ic_type & ODM_SMART_ANT_SUPPORT) &&
5754 pktinfo->is_packet_to_self &&
5755 fat_tab->fat_state == FAT_TRAINING_STATE) {
5756 /* @(pktinfo->is_packet_match_bssid && (!pktinfo->is_packet_beacon)) */
5757 u8 antsel_tr_mux;
5758
5759 antsel_tr_mux = (fat_tab->antsel_rx_keep_2 << 2) |
5760 (fat_tab->antsel_rx_keep_1 << 1) |
5761 fat_tab->antsel_rx_keep_0;
5762 fat_tab->ant_sum_rssi[antsel_tr_mux] += rx_power_ant0;
5763 fat_tab->ant_rssi_cnt[antsel_tr_mux]++;
5764 }
5765 }
5766
odm_process_rssi_normal(void * dm_void,void * phy_info_void,void * pkt_info_void,u8 rx_pwr0)5767 void odm_process_rssi_normal(void *dm_void, void *phy_info_void,
5768 void *pkt_info_void, u8 rx_pwr0)
5769 {
5770 struct dm_struct *dm = (struct dm_struct *)dm_void;
5771 struct phydm_phyinfo_struct *phy_info = NULL;
5772 struct phydm_perpkt_info_struct *pktinfo = NULL;
5773 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5774 u8 rx_evm0, rx_evm1;
5775 boolean b_main;
5776
5777 phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
5778 pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
5779 rx_evm0 = phy_info->rx_mimo_signal_quality[0];
5780 rx_evm1 = phy_info->rx_mimo_signal_quality[1];
5781
5782 if (!(pktinfo->is_packet_to_self || fat_tab->use_ctrl_frame_antdiv))
5783 return;
5784
5785 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
5786 if (pktinfo->is_cck_rate ||
5787 dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8710C) {
5788
5789 b_main = (fat_tab->rx_idle_ant == MAIN_ANT);
5790 fat_tab->antsel_rx_keep_0 = b_main ? ANT1_2G : ANT2_2G;
5791 }
5792
5793 odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,
5794 pktinfo->station_id, rx_pwr0, RSSI_METHOD,
5795 pktinfo->is_cck_rate);
5796 } else {
5797 odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,
5798 pktinfo->station_id, rx_pwr0, RSSI_METHOD,
5799 pktinfo->is_cck_rate);
5800
5801 #ifdef ODM_EVM_ENHANCE_ANTDIV
5802 if (!(dm->support_ic_type & ODM_EVM_ANTDIV_IC))
5803 return;
5804 if (pktinfo->is_cck_rate)
5805 return;
5806
5807 odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,
5808 pktinfo->station_id, rx_evm0, EVM_METHOD,
5809 pktinfo->is_cck_rate);
5810 odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,
5811 pktinfo->station_id, pktinfo->data_rate,
5812 TP_METHOD, pktinfo->is_cck_rate);
5813 #endif
5814 }
5815 }
5816
odm_process_rssi_for_ant_div(void * dm_void,void * phy_info_void,void * pkt_info_void)5817 void odm_process_rssi_for_ant_div(void *dm_void, void *phy_info_void,
5818 void *pkt_info_void)
5819 {
5820 struct dm_struct *dm = (struct dm_struct *)dm_void;
5821 struct phydm_phyinfo_struct *phy_info = NULL;
5822 struct phydm_perpkt_info_struct *pktinfo = NULL;
5823 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5824 #if (defined(CONFIG_HL_SMART_ANTENNA))
5825 struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
5826 u32 beam_tmp;
5827 u8 next_ant;
5828 u8 train_pkt_number;
5829 #endif
5830 boolean b_main;
5831 u8 rx_power_ant0, rx_power_ant1;
5832 u8 rx_evm_ant0, rx_evm_ant1;
5833 u8 rssi_avg;
5834 u64 rssi_linear = 0;
5835
5836 phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
5837 pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
5838 rx_power_ant0 = phy_info->rx_mimo_signal_strength[0];
5839 rx_power_ant1 = phy_info->rx_mimo_signal_strength[1];
5840 rx_evm_ant0 = phy_info->rx_mimo_signal_quality[0];
5841 rx_evm_ant1 = phy_info->rx_mimo_signal_quality[1];
5842
5843 if ((dm->support_ic_type & ODM_IC_2SS) && !pktinfo->is_cck_rate) {
5844 if (rx_power_ant1 < 100) {
5845 rssi_linear = phydm_db_2_linear(rx_power_ant0) +
5846 phydm_db_2_linear(rx_power_ant1);
5847 /* @Rounding and removing fractional bits */
5848 rssi_linear = (rssi_linear +
5849 (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
5850 /* @Calculate average RSSI */
5851 rssi_linear = DIVIDED_2(rssi_linear);
5852 /* @averaged PWDB */
5853 rssi_avg = (u8)odm_convert_to_db(rssi_linear);
5854 }
5855
5856 } else {
5857 rx_power_ant0 = (u8)phy_info->rx_pwdb_all;
5858 rssi_avg = rx_power_ant0;
5859 }
5860
5861 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
5862 if ((dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) && (fat_tab->fat_state == FAT_TRAINING_STATE))
5863 phydm_process_rssi_for_hb_smtant_type2(dm, phy_info, pktinfo, rssi_avg); /*@for 8822B*/
5864 else
5865 #endif
5866
5867 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
5868 #ifdef CONFIG_FAT_PATCH
5869 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1 && fat_tab->fat_state == FAT_TRAINING_STATE) {
5870 /*@[Beacon]*/
5871 if (pktinfo->is_packet_beacon) {
5872 sat_tab->beacon_counter++;
5873 PHYDM_DBG(dm, DBG_ANT_DIV,
5874 "MatchBSSID_beacon_counter = ((%d))\n",
5875 sat_tab->beacon_counter);
5876
5877 if (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) {
5878 if (sat_tab->ant_num > 1) {
5879 next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
5880 odm_update_rx_idle_ant(dm, next_ant);
5881 }
5882
5883 sat_tab->update_beam_idx++;
5884
5885 PHYDM_DBG(dm, DBG_ANT_DIV,
5886 "pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n",
5887 sat_tab->pre_beacon_counter,
5888 sat_tab->pkt_counter,
5889 sat_tab->update_beam_idx);
5890
5891 sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
5892 sat_tab->pkt_counter = 0;
5893 }
5894 }
5895 /*@[data]*/
5896 else if (pktinfo->is_packet_to_self) {
5897 if (sat_tab->pkt_skip_statistic_en == 0) {
5898 /*@
5899 PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
5900 pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0);
5901 */
5902 PHYDM_DBG(dm, DBG_ANT_DIV,
5903 "ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\n",
5904 pktinfo->station_id,
5905 sat_tab->pkt_counter,
5906 fat_tab->antsel_rx_keep_0,
5907 sat_tab->fast_training_beam_num,
5908 rx_power_ant0);
5909
5910 sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0;
5911 sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++;
5912 sat_tab->pkt_counter++;
5913
5914 #if 1
5915 train_pkt_number = sat_tab->beam_train_cnt[fat_tab->rx_idle_ant - 1][sat_tab->fast_training_beam_num];
5916 #else
5917 train_pkt_number = sat_tab->per_beam_training_pkt_num;
5918 #endif
5919
5920 /*Swich Antenna erery N pkts*/
5921 if (sat_tab->pkt_counter == train_pkt_number) {
5922 if (sat_tab->ant_num > 1) {
5923 PHYDM_DBG(dm, DBG_ANT_DIV, "packet enugh ((%d ))pkts ---> Switch antenna\n", train_pkt_number);
5924 next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
5925 odm_update_rx_idle_ant(dm, next_ant);
5926 }
5927
5928 sat_tab->update_beam_idx++;
5929 PHYDM_DBG(dm, DBG_ANT_DIV, "pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\n",
5930 sat_tab->pre_beacon_counter, sat_tab->update_beam_idx);
5931
5932 sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
5933 sat_tab->pkt_counter = 0;
5934 }
5935 }
5936 }
5937
5938 /*Swich Beam after switch "sat_tab->ant_num" antennas*/
5939 if (sat_tab->update_beam_idx == sat_tab->ant_num) {
5940 sat_tab->update_beam_idx = 0;
5941 sat_tab->pkt_counter = 0;
5942 beam_tmp = sat_tab->fast_training_beam_num;
5943
5944 if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {
5945 fat_tab->fat_state = FAT_DECISION_STATE;
5946
5947 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
5948 if (dm->support_interface == ODM_ITRF_PCIE)
5949 odm_fast_ant_training_hl_smart_antenna_type1(dm);
5950 #endif
5951 #if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
5952 if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
5953 odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);
5954 #endif
5955
5956 } else {
5957 sat_tab->fast_training_beam_num++;
5958 PHYDM_DBG(dm, DBG_ANT_DIV,
5959 "Update Beam_num (( %d )) -> (( %d ))\n",
5960 beam_tmp,
5961 sat_tab->fast_training_beam_num);
5962 phydm_set_all_ant_same_beam_num(dm);
5963
5964 fat_tab->fat_state = FAT_TRAINING_STATE;
5965 }
5966 }
5967 }
5968 #else
5969
5970 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
5971 if ((dm->support_ic_type & ODM_HL_SMART_ANT_TYPE1_SUPPORT) &&
5972 pktinfo->is_packet_to_self &&
5973 fat_tab->fat_state == FAT_TRAINING_STATE) {
5974 if (sat_tab->pkt_skip_statistic_en == 0) {
5975 /*@
5976 PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
5977 pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0);
5978 */
5979 PHYDM_DBG(dm, DBG_ANT_DIV,
5980 "StaID[%d]: antsel_pathA = ((%d)), is_packet_to_self = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
5981 pktinfo->station_id,
5982 fat_tab->antsel_rx_keep_0,
5983 pktinfo->is_packet_to_self,
5984 sat_tab->fast_training_beam_num,
5985 rx_power_ant0);
5986
5987 sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0;
5988 sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++;
5989 sat_tab->pkt_counter++;
5990
5991 /*swich beam every N pkt*/
5992 if (sat_tab->pkt_counter >= sat_tab->per_beam_training_pkt_num) {
5993 sat_tab->pkt_counter = 0;
5994 beam_tmp = sat_tab->fast_training_beam_num;
5995
5996 if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {
5997 fat_tab->fat_state = FAT_DECISION_STATE;
5998
5999 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
6000 if (dm->support_interface == ODM_ITRF_PCIE)
6001 odm_fast_ant_training_hl_smart_antenna_type1(dm);
6002 #endif
6003 #if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
6004 if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
6005 odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);
6006 #endif
6007
6008 } else {
6009 sat_tab->fast_training_beam_num++;
6010 phydm_set_all_ant_same_beam_num(dm);
6011
6012 fat_tab->fat_state = FAT_TRAINING_STATE;
6013 PHYDM_DBG(dm, DBG_ANT_DIV, "Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, sat_tab->fast_training_beam_num);
6014 }
6015 }
6016 }
6017 }
6018 }
6019 #endif
6020 else
6021 #endif
6022 if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) {
6023 odm_process_rssi_smart(dm, phy_info, pktinfo,
6024 rx_power_ant0);
6025 } else { /* @ant_div_type != CG_TRX_SMART_ANTDIV */
6026 odm_process_rssi_normal(dm, phy_info, pktinfo,
6027 rx_power_ant0);
6028 }
6029 #if 0
6030 /* PHYDM_DBG(dm,DBG_ANT_DIV,"is_cck_rate=%d, pwdb_all=%d\n",
6031 * pktinfo->is_cck_rate, phy_info->rx_pwdb_all);
6032 * PHYDM_DBG(dm,DBG_ANT_DIV,"antsel_tr_mux=3'b%d%d%d\n",
6033 * fat_tab->antsel_rx_keep_2, fat_tab->antsel_rx_keep_1,
6034 * fat_tab->antsel_rx_keep_0);
6035 */
6036 #endif
6037 }
6038
6039 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
odm_set_tx_ant_by_tx_info(void * dm_void,u8 * desc,u8 mac_id)6040 void odm_set_tx_ant_by_tx_info(void *dm_void, u8 *desc, u8 mac_id)
6041 {
6042 struct dm_struct *dm = (struct dm_struct *)dm_void;
6043 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
6044
6045 if (!(dm->support_ability & ODM_BB_ANT_DIV))
6046 return;
6047
6048 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
6049 return;
6050
6051 if (dm->support_ic_type == (ODM_RTL8723B | ODM_RTL8721D)) {
6052 #if (RTL8723B_SUPPORT == 1 || RTL8721D_SUPPORT == 1)
6053 SET_TX_DESC_ANTSEL_A_8723B(desc, fat_tab->antsel_a[mac_id]);
6054 /*PHYDM_DBG(dm,DBG_ANT_DIV,
6055 * "[8723B] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
6056 * mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
6057 * fat_tab->antsel_a[mac_id]);
6058 */
6059 #endif
6060 } else if (dm->support_ic_type == ODM_RTL8821) {
6061 #if (RTL8821A_SUPPORT == 1)
6062 SET_TX_DESC_ANTSEL_A_8812(desc, fat_tab->antsel_a[mac_id]);
6063 /*PHYDM_DBG(dm,DBG_ANT_DIV,
6064 * "[8821A] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
6065 * mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
6066 * fat_tab->antsel_a[mac_id]);
6067 */
6068 #endif
6069 } else if (dm->support_ic_type == ODM_RTL8188E) {
6070 #if (RTL8188E_SUPPORT == 1)
6071 SET_TX_DESC_ANTSEL_A_88E(desc, fat_tab->antsel_a[mac_id]);
6072 SET_TX_DESC_ANTSEL_B_88E(desc, fat_tab->antsel_b[mac_id]);
6073 SET_TX_DESC_ANTSEL_C_88E(desc, fat_tab->antsel_c[mac_id]);
6074 /*PHYDM_DBG(dm,DBG_ANT_DIV,
6075 * "[8188E] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
6076 * mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
6077 * fat_tab->antsel_a[mac_id]);
6078 */
6079 #endif
6080 } else if (dm->support_ic_type == ODM_RTL8821C) {
6081 #if (RTL8821C_SUPPORT == 1)
6082 SET_TX_DESC_ANTSEL_A_8821C(desc, fat_tab->antsel_a[mac_id]);
6083 /*PHYDM_DBG(dm,DBG_ANT_DIV,
6084 * "[8821C] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
6085 * mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
6086 * fat_tab->antsel_a[mac_id]);
6087 */
6088 #endif
6089 } else if (dm->support_ic_type == ODM_RTL8195B) {
6090 #if (RTL8195B_SUPPORT == 1)
6091 SET_TX_DESC_ANTSEL_A_8195B(desc, fat_tab->antsel_a[mac_id]);
6092 #endif
6093 } else if (dm->support_ic_type == ODM_RTL8822B) {
6094 #if (RTL8822B_SUPPORT == 1)
6095 SET_TX_DESC_ANTSEL_A_8822B(desc, fat_tab->antsel_a[mac_id]);
6096 #endif
6097
6098 }
6099 }
6100 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
6101
odm_set_tx_ant_by_tx_info(struct rtl8192cd_priv * priv,struct tx_desc * pdesc,unsigned short aid)6102 void odm_set_tx_ant_by_tx_info(
6103 struct rtl8192cd_priv *priv,
6104 struct tx_desc *pdesc,
6105 unsigned short aid)
6106 {
6107 struct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/
6108 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
6109
6110 if (!(dm->support_ability & ODM_BB_ANT_DIV))
6111 return;
6112
6113 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
6114 return;
6115
6116 if (dm->support_ic_type == ODM_RTL8881A) {
6117 #if 0
6118 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__); */
6119 #endif
6120 pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16)));
6121 pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
6122 } else if (dm->support_ic_type == ODM_RTL8192E) {
6123 #if 0
6124 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__); */
6125 #endif
6126 pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16)));
6127 pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
6128 } else if (dm->support_ic_type == ODM_RTL8197F) {
6129 #if 0
6130 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__); */
6131 #endif
6132 pdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16)));
6133 pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
6134 } else if (dm->support_ic_type == ODM_RTL8822B) {
6135 pdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16)));
6136 pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
6137 } else if (dm->support_ic_type == ODM_RTL8188E) {
6138 #if 0
6139 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8188E******\n",__FUNCTION__,__LINE__);*/
6140 #endif
6141 pdesc->Dword2 &= set_desc(~BIT(24));
6142 pdesc->Dword2 &= set_desc(~BIT(25));
6143 pdesc->Dword7 &= set_desc(~BIT(29));
6144
6145 pdesc->Dword2 |= set_desc(fat_tab->antsel_a[aid] << 24);
6146 pdesc->Dword2 |= set_desc(fat_tab->antsel_b[aid] << 25);
6147 pdesc->Dword7 |= set_desc(fat_tab->antsel_c[aid] << 29);
6148
6149 } else if (dm->support_ic_type == ODM_RTL8812) {
6150 /*@[path-A]*/
6151 #if 0
6152 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);*/
6153 #endif
6154
6155 pdesc->Dword6 &= set_desc(~BIT(16));
6156 pdesc->Dword6 &= set_desc(~BIT(17));
6157 pdesc->Dword6 &= set_desc(~BIT(18));
6158
6159 pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
6160 pdesc->Dword6 |= set_desc(fat_tab->antsel_b[aid] << 17);
6161 pdesc->Dword6 |= set_desc(fat_tab->antsel_c[aid] << 18);
6162 }
6163 }
6164
6165 #if 1 /*@def CONFIG_WLAN_HAL*/
odm_set_tx_ant_by_tx_info_hal(struct rtl8192cd_priv * priv,void * pdesc_data,u16 aid)6166 void odm_set_tx_ant_by_tx_info_hal(
6167 struct rtl8192cd_priv *priv,
6168 void *pdesc_data,
6169 u16 aid)
6170 {
6171 struct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/
6172 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
6173 PTX_DESC_DATA_88XX pdescdata = (PTX_DESC_DATA_88XX)pdesc_data;
6174
6175 if (!(dm->support_ability & ODM_BB_ANT_DIV))
6176 return;
6177
6178 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
6179 return;
6180
6181 if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8814A |
6182 ODM_RTL8197F | ODM_RTL8822B)) {
6183 #if 0
6184 /*panic_printk("[%s] [%d] **odm_set_tx_ant_by_tx_info_hal**\n",
6185 * __FUNCTION__,__LINE__);
6186 */
6187 #endif
6188 pdescdata->ant_sel = 1;
6189 pdescdata->ant_sel_a = fat_tab->antsel_a[aid];
6190 }
6191 }
6192 #endif /*@#ifdef CONFIG_WLAN_HAL*/
6193
6194 #endif
6195
odm_ant_div_config(void * dm_void)6196 void odm_ant_div_config(void *dm_void)
6197 {
6198 struct dm_struct *dm = (struct dm_struct *)dm_void;
6199 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
6200 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
6201 PHYDM_DBG(dm, DBG_ANT_DIV, "WIN Config Antenna Diversity\n");
6202 /*@
6203 if(dm->support_ic_type==ODM_RTL8723B)
6204 {
6205 if((!dm->swat_tab.ANTA_ON || !dm->swat_tab.ANTB_ON))
6206 dm->support_ability &= ~(ODM_BB_ANT_DIV);
6207 }
6208 */
6209 #if (defined(CONFIG_2T3R_ANTENNA))
6210 #if (RTL8822B_SUPPORT == 1)
6211 dm->rfe_type = ANT_2T3R_RFE_TYPE;
6212 #endif
6213 #endif
6214
6215 #if (defined(CONFIG_2T4R_ANTENNA))
6216 #if (RTL8822B_SUPPORT == 1)
6217 dm->rfe_type = ANT_2T4R_RFE_TYPE;
6218 #endif
6219 #endif
6220
6221 if (dm->support_ic_type == ODM_RTL8723D)
6222 dm->ant_div_type = S0S1_SW_ANTDIV;
6223 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
6224
6225 PHYDM_DBG(dm, DBG_ANT_DIV, "CE Config Antenna Diversity\n");
6226
6227 if (dm->support_ic_type == ODM_RTL8723B)
6228 dm->ant_div_type = S0S1_SW_ANTDIV;
6229
6230 if (dm->support_ic_type == ODM_RTL8723D)
6231 dm->ant_div_type = S0S1_SW_ANTDIV;
6232 #elif (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
6233
6234 PHYDM_DBG(dm, DBG_ANT_DIV, "IOT Config Antenna Diversity\n");
6235
6236 if (dm->support_ic_type == ODM_RTL8721D)
6237 dm->ant_div_type = CG_TRX_HW_ANTDIV;
6238 if (dm->support_ic_type == ODM_RTL8710C){
6239 if(dm->cut_version > ODM_CUT_C)
6240 dm->ant_div_type = CG_TRX_HW_ANTDIV;
6241 else
6242 dm->ant_div_type = S0S1_SW_ANTDIV;
6243 }
6244
6245 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
6246
6247 PHYDM_DBG(dm, DBG_ANT_DIV, "AP Config Antenna Diversity\n");
6248
6249 /* @2 [ NOT_SUPPORT_ANTDIV ] */
6250 #if (defined(CONFIG_NOT_SUPPORT_ANTDIV))
6251 dm->support_ability &= ~(ODM_BB_ANT_DIV);
6252 PHYDM_DBG(dm, DBG_ANT_DIV,
6253 "[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n");
6254
6255 /* @2 [ 2G&5G_SUPPORT_ANTDIV ] */
6256 #elif (defined(CONFIG_2G5G_SUPPORT_ANTDIV))
6257 PHYDM_DBG(dm, DBG_ANT_DIV,
6258 "[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously\n");
6259 fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G | ODM_ANTDIV_5G);
6260
6261 if (dm->support_ic_type & ODM_ANTDIV_SUPPORT)
6262 dm->support_ability |= ODM_BB_ANT_DIV;
6263 if (*dm->band_type == ODM_BAND_5G) {
6264 #if (defined(CONFIG_5G_CGCS_RX_DIVERSITY))
6265 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
6266 PHYDM_DBG(dm, DBG_ANT_DIV,
6267 "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
6268 panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
6269 #elif (defined(CONFIG_5G_CG_TRX_DIVERSITY) ||\
6270 defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))
6271 dm->ant_div_type = CG_TRX_HW_ANTDIV;
6272 PHYDM_DBG(dm, DBG_ANT_DIV,
6273 "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
6274 panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
6275 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
6276 dm->ant_div_type = CG_TRX_SMART_ANTDIV;
6277 PHYDM_DBG(dm, DBG_ANT_DIV,
6278 "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n");
6279 #elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY))
6280 dm->ant_div_type = S0S1_SW_ANTDIV;
6281 PHYDM_DBG(dm, DBG_ANT_DIV,
6282 "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n");
6283 #endif
6284 } else if (*dm->band_type == ODM_BAND_2_4G) {
6285 #if (defined(CONFIG_2G_CGCS_RX_DIVERSITY))
6286 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
6287 PHYDM_DBG(dm, DBG_ANT_DIV,
6288 "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
6289 #elif (defined(CONFIG_2G_CG_TRX_DIVERSITY) ||\
6290 defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))
6291 dm->ant_div_type = CG_TRX_HW_ANTDIV;
6292 PHYDM_DBG(dm, DBG_ANT_DIV,
6293 "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
6294 #elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
6295 dm->ant_div_type = CG_TRX_SMART_ANTDIV;
6296 PHYDM_DBG(dm, DBG_ANT_DIV,
6297 "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n");
6298 #elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY))
6299 dm->ant_div_type = S0S1_SW_ANTDIV;
6300 PHYDM_DBG(dm, DBG_ANT_DIV,
6301 "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n");
6302 #endif
6303 }
6304
6305 /* @2 [ 5G_SUPPORT_ANTDIV ] */
6306 #elif (defined(CONFIG_5G_SUPPORT_ANTDIV))
6307 PHYDM_DBG(dm, DBG_ANT_DIV,
6308 "[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n");
6309 panic_printk("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n");
6310 fat_tab->ant_div_2g_5g = (ODM_ANTDIV_5G);
6311 if (*dm->band_type == ODM_BAND_5G) {
6312 if (dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)
6313 dm->support_ability |= ODM_BB_ANT_DIV;
6314 #if (defined(CONFIG_5G_CGCS_RX_DIVERSITY))
6315 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
6316 PHYDM_DBG(dm, DBG_ANT_DIV,
6317 "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
6318 panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
6319 #elif (defined(CONFIG_5G_CG_TRX_DIVERSITY))
6320 dm->ant_div_type = CG_TRX_HW_ANTDIV;
6321 panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
6322 PHYDM_DBG(dm, DBG_ANT_DIV,
6323 "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
6324 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
6325 dm->ant_div_type = CG_TRX_SMART_ANTDIV;
6326 PHYDM_DBG(dm, DBG_ANT_DIV,
6327 "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n");
6328 #elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY))
6329 dm->ant_div_type = S0S1_SW_ANTDIV;
6330 PHYDM_DBG(dm, DBG_ANT_DIV,
6331 "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n");
6332 #endif
6333 } else if (*dm->band_type == ODM_BAND_2_4G) {
6334 PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 2G ant_div_type\n");
6335 dm->support_ability &= ~(ODM_BB_ANT_DIV);
6336 }
6337
6338 /* @2 [ 2G_SUPPORT_ANTDIV ] */
6339 #elif (defined(CONFIG_2G_SUPPORT_ANTDIV))
6340 PHYDM_DBG(dm, DBG_ANT_DIV,
6341 "[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n");
6342 fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G);
6343 if (*dm->band_type == ODM_BAND_2_4G) {
6344 if (dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)
6345 dm->support_ability |= ODM_BB_ANT_DIV;
6346 #if (defined(CONFIG_2G_CGCS_RX_DIVERSITY))
6347 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
6348 PHYDM_DBG(dm, DBG_ANT_DIV,
6349 "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
6350 #elif (defined(CONFIG_2G_CG_TRX_DIVERSITY))
6351 dm->ant_div_type = CG_TRX_HW_ANTDIV;
6352 PHYDM_DBG(dm, DBG_ANT_DIV,
6353 "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
6354 #elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
6355 dm->ant_div_type = CG_TRX_SMART_ANTDIV;
6356 PHYDM_DBG(dm, DBG_ANT_DIV,
6357 "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n");
6358 #elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY))
6359 dm->ant_div_type = S0S1_SW_ANTDIV;
6360 PHYDM_DBG(dm, DBG_ANT_DIV,
6361 "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n");
6362 #endif
6363 } else if (*dm->band_type == ODM_BAND_5G) {
6364 PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 5G ant_div_type\n");
6365 dm->support_ability &= ~(ODM_BB_ANT_DIV);
6366 }
6367 #endif
6368
6369 if (!(dm->support_ic_type & ODM_ANTDIV_SUPPORT_IC)) {
6370 fat_tab->ant_div_2g_5g = 0;
6371 dm->support_ability &= ~(ODM_BB_ANT_DIV);
6372 }
6373 #endif
6374
6375 PHYDM_DBG(dm, DBG_ANT_DIV,
6376 "[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\n",
6377 ((dm->support_ability & ODM_BB_ANT_DIV) ? 1 : 0));
6378 PHYDM_DBG(dm, DBG_ANT_DIV,
6379 "[AntDiv Config Info] be_fix_tx_ant = ((%d))\n",
6380 dm->dm_fat_table.b_fix_tx_ant);
6381 }
6382
odm_ant_div_timers(void * dm_void,u8 state)6383 void odm_ant_div_timers(void *dm_void, u8 state)
6384 {
6385 struct dm_struct *dm = (struct dm_struct *)dm_void;
6386 if (state == INIT_ANTDIV_TIMMER) {
6387 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
6388 odm_initialize_timer(dm,
6389 &dm->dm_swat_table.sw_antdiv_timer,
6390 (void *)odm_sw_antdiv_callback, NULL,
6391 "sw_antdiv_timer");
6392 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
6393 (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
6394 odm_initialize_timer(dm, &dm->fast_ant_training_timer,
6395 (void *)odm_fast_ant_training_callback,
6396 NULL, "fast_ant_training_timer");
6397 #endif
6398
6399 #ifdef ODM_EVM_ENHANCE_ANTDIV
6400 odm_initialize_timer(dm, &dm->evm_fast_ant_training_timer,
6401 (void *)phydm_evm_antdiv_callback, NULL,
6402 "evm_fast_ant_training_timer");
6403 #endif
6404 } else if (state == CANCEL_ANTDIV_TIMMER) {
6405 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
6406 odm_cancel_timer(dm,
6407 &dm->dm_swat_table.sw_antdiv_timer);
6408 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
6409 (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
6410 odm_cancel_timer(dm, &dm->fast_ant_training_timer);
6411 #endif
6412
6413 #ifdef ODM_EVM_ENHANCE_ANTDIV
6414 odm_cancel_timer(dm, &dm->evm_fast_ant_training_timer);
6415 #endif
6416 } else if (state == RELEASE_ANTDIV_TIMMER) {
6417 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
6418 odm_release_timer(dm,
6419 &dm->dm_swat_table.sw_antdiv_timer);
6420 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
6421 (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
6422 odm_release_timer(dm, &dm->fast_ant_training_timer);
6423 #endif
6424
6425 #ifdef ODM_EVM_ENHANCE_ANTDIV
6426 odm_release_timer(dm, &dm->evm_fast_ant_training_timer);
6427 #endif
6428 }
6429 }
6430
phydm_antdiv_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)6431 void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used,
6432 char *output, u32 *_out_len)
6433 {
6434 struct dm_struct *dm = (struct dm_struct *)dm_void;
6435 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
6436 u32 used = *_used;
6437 u32 out_len = *_out_len;
6438 u32 dm_value[10] = {0};
6439 char help[] = "-h";
6440 u8 i, input_idx = 0;
6441
6442 for (i = 0; i < 5; i++) {
6443 if (input[i + 1]) {
6444 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
6445 input_idx++;
6446 }
6447 }
6448
6449 if (input_idx == 0)
6450 return;
6451
6452 if ((strcmp(input[1], help) == 0)) {
6453 PDM_SNPF(out_len, used, output + used, out_len - used,
6454 "{1} {0:auto, 1:fix main, 2:fix auto}\n");
6455 PDM_SNPF(out_len, used, output + used, out_len - used,
6456 "{2} {antdiv_period}\n");
6457 #if (RTL8821C_SUPPORT == 1)
6458 PDM_SNPF(out_len, used, output + used, out_len - used,
6459 "{3} {en} {0:Default, 1:HW_Div, 2:SW_Div}\n");
6460 #endif
6461
6462 } else if (dm_value[0] == 1) {
6463 /*@fixed or auto antenna*/
6464 if (dm_value[1] == 0) {
6465 dm->ant_type = ODM_AUTO_ANT;
6466 PDM_SNPF(out_len, used, output + used, out_len - used,
6467 "AntDiv: Auto\n");
6468 } else if (dm_value[1] == 1) {
6469 dm->ant_type = ODM_FIX_MAIN_ANT;
6470
6471 #if (RTL8710C_SUPPORT == 1)
6472 dm->antdiv_select = 1;
6473 #endif
6474
6475 PDM_SNPF(out_len, used, output + used, out_len - used,
6476 "AntDiv: Fix Main\n");
6477 } else if (dm_value[1] == 2) {
6478 dm->ant_type = ODM_FIX_AUX_ANT;
6479
6480 #if (RTL8710C_SUPPORT == 1)
6481 dm->antdiv_select = 2;
6482 #endif
6483
6484 PDM_SNPF(out_len, used, output + used, out_len - used,
6485 "AntDiv: Fix Aux\n");
6486 }
6487
6488 if (dm->ant_type != ODM_AUTO_ANT) {
6489 odm_stop_antenna_switch_dm(dm);
6490 if (dm->ant_type == ODM_FIX_MAIN_ANT)
6491 odm_update_rx_idle_ant(dm, MAIN_ANT);
6492 else if (dm->ant_type == ODM_FIX_AUX_ANT)
6493 odm_update_rx_idle_ant(dm, AUX_ANT);
6494 } else {
6495 phydm_enable_antenna_diversity(dm);
6496 }
6497 dm->pre_ant_type = dm->ant_type;
6498 } else if (dm_value[0] == 2) {
6499 /*@dynamic period for AntDiv*/
6500 dm->antdiv_period = (u8)dm_value[1];
6501 PDM_SNPF(out_len, used, output + used, out_len - used,
6502 "AntDiv_period=((%d))\n", dm->antdiv_period);
6503 }
6504 #if (RTL8821C_SUPPORT == 1)
6505 else if (dm_value[0] == 3 &&
6506 dm->support_ic_type == ODM_RTL8821C) {
6507 /*Only for 8821C*/
6508 if (dm_value[1] == 0) {
6509 fat_tab->force_antdiv_type = false;
6510 PDM_SNPF(out_len, used, output + used, out_len - used,
6511 "[8821C] AntDiv: Default\n");
6512 } else if (dm_value[1] == 1) {
6513 fat_tab->force_antdiv_type = true;
6514 fat_tab->antdiv_type_dbg = CG_TRX_HW_ANTDIV;
6515 PDM_SNPF(out_len, used, output + used, out_len - used,
6516 "[8821C] AntDiv: HW diversity\n");
6517 } else if (dm_value[1] == 2) {
6518 fat_tab->force_antdiv_type = true;
6519 fat_tab->antdiv_type_dbg = S0S1_SW_ANTDIV;
6520 PDM_SNPF(out_len, used, output + used, out_len - used,
6521 "[8821C] AntDiv: SW diversity\n");
6522 }
6523 }
6524 #endif
6525 #ifdef ODM_EVM_ENHANCE_ANTDIV
6526 else if (dm_value[0] == 4) {
6527 if (dm_value[1] == 0) {
6528 /*@init parameters for EVM AntDiv*/
6529 phydm_evm_sw_antdiv_init(dm);
6530 PDM_SNPF(out_len, used, output + used, out_len - used,
6531 "init evm antdiv parameters\n");
6532 } else if (dm_value[1] == 1) {
6533 /*training number for EVM AntDiv*/
6534 dm->antdiv_train_num = (u8)dm_value[2];
6535 PDM_SNPF(out_len, used, output + used, out_len - used,
6536 "antdiv_train_num = ((%d))\n",
6537 dm->antdiv_train_num);
6538 } else if (dm_value[1] == 2) {
6539 /*training interval for EVM AntDiv*/
6540 dm->antdiv_intvl = (u8)dm_value[2];
6541 PDM_SNPF(out_len, used, output + used, out_len - used,
6542 "antdiv_intvl = ((%d))\n",
6543 dm->antdiv_intvl);
6544 } else if (dm_value[1] == 3) {
6545 /*@function period for EVM AntDiv*/
6546 dm->evm_antdiv_period = (u8)dm_value[2];
6547 PDM_SNPF(out_len, used, output + used, out_len - used,
6548 "evm_antdiv_period = ((%d))\n",
6549 dm->evm_antdiv_period);
6550 } else if (dm_value[1] == 100) {/*show parameters*/
6551 PDM_SNPF(out_len, used, output + used, out_len - used,
6552 "ant_type = ((%d))\n", dm->ant_type);
6553 PDM_SNPF(out_len, used, output + used, out_len - used,
6554 "antdiv_train_num = ((%d))\n",
6555 dm->antdiv_train_num);
6556 PDM_SNPF(out_len, used, output + used, out_len - used,
6557 "antdiv_intvl = ((%d))\n",
6558 dm->antdiv_intvl);
6559 PDM_SNPF(out_len, used, output + used, out_len - used,
6560 "evm_antdiv_period = ((%d))\n",
6561 dm->evm_antdiv_period);
6562 }
6563 }
6564 #ifdef CONFIG_2T4R_ANTENNA
6565 else if (dm_value[0] == 5) { /*Only for 8822B 2T4R case*/
6566
6567 if (dm_value[1] == 0) {
6568 dm->ant_type2 = ODM_AUTO_ANT;
6569 PDM_SNPF(out_len, used, output + used, out_len - used,
6570 "AntDiv: PathB Auto\n");
6571 } else if (dm_value[1] == 1) {
6572 dm->ant_type2 = ODM_FIX_MAIN_ANT;
6573 PDM_SNPF(out_len, used, output + used, out_len - used,
6574 "AntDiv: PathB Fix Main\n");
6575 } else if (dm_value[1] == 2) {
6576 dm->ant_type2 = ODM_FIX_AUX_ANT;
6577 PDM_SNPF(out_len, used, output + used, out_len - used,
6578 "AntDiv: PathB Fix Aux\n");
6579 }
6580
6581 if (dm->ant_type2 != ODM_AUTO_ANT) {
6582 odm_stop_antenna_switch_dm(dm);
6583 if (dm->ant_type2 == ODM_FIX_MAIN_ANT)
6584 phydm_update_rx_idle_ant_pathb(dm, MAIN_ANT);
6585 else if (dm->ant_type2 == ODM_FIX_AUX_ANT)
6586 phydm_update_rx_idle_ant_pathb(dm, AUX_ANT);
6587 } else {
6588 phydm_enable_antenna_diversity(dm);
6589 }
6590 dm->pre_ant_type2 = dm->ant_type2;
6591 }
6592 #endif
6593 #endif
6594 *_used = used;
6595 *_out_len = out_len;
6596 }
6597
odm_ant_div_reset(void * dm_void)6598 void odm_ant_div_reset(void *dm_void)
6599 {
6600 struct dm_struct *dm = (struct dm_struct *)dm_void;
6601
6602 if (!(dm->support_ability & ODM_BB_ANT_DIV))
6603 return;
6604
6605 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
6606 if (dm->ant_div_type == S0S1_SW_ANTDIV)
6607 odm_s0s1_sw_ant_div_reset(dm);
6608 #endif
6609 }
6610
odm_antenna_diversity_init(void * dm_void)6611 void odm_antenna_diversity_init(void *dm_void)
6612 {
6613 struct dm_struct *dm = (struct dm_struct *)dm_void;
6614
6615 odm_ant_div_config(dm);
6616 odm_ant_div_init(dm);
6617 }
6618
odm_antenna_diversity(void * dm_void)6619 void odm_antenna_diversity(void *dm_void)
6620 {
6621 struct dm_struct *dm = (struct dm_struct *)dm_void;
6622
6623 if (*dm->mp_mode)
6624 return;
6625
6626 if (!(dm->support_ability & ODM_BB_ANT_DIV)) {
6627 PHYDM_DBG(dm, DBG_ANT_DIV,
6628 "[Return!!!] Not Support Antenna Diversity Function\n");
6629 return;
6630 }
6631
6632 if (dm->pause_ability & ODM_BB_ANT_DIV) {
6633 PHYDM_DBG(dm, DBG_ANT_DIV, "Return: Pause AntDIv in LV=%d\n",
6634 dm->pause_lv_table.lv_antdiv);
6635 return;
6636 }
6637
6638 odm_ant_div(dm);
6639 }
6640 #endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/
6641