1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 /*@
34 * ODM IO Relative API.
35 */
36
odm_read_1byte(struct dm_struct * dm,u32 reg_addr)37 u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr)
38 {
39 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
40 struct rtl8192cd_priv *priv = dm->priv;
41 return RTL_R8(reg_addr);
42 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
43 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
44
45 return rtl_read_byte(rtlpriv, reg_addr);
46 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
47 struct rtw_dev *rtwdev = dm->adapter;
48
49 return rtw_read8(rtwdev, reg_addr);
50 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
51 void *adapter = dm->adapter;
52 return rtw_read8(adapter, reg_addr);
53 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
54 void *adapter = dm->adapter;
55 return PlatformEFIORead1Byte(adapter, reg_addr);
56 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
57 void *adapter = dm->adapter;
58
59 return rtw_read8(adapter, reg_addr);
60 #endif
61 }
62
odm_read_2byte(struct dm_struct * dm,u32 reg_addr)63 u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr)
64 {
65 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
66 struct rtl8192cd_priv *priv = dm->priv;
67 return RTL_R16(reg_addr);
68 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
69 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
70
71 return rtl_read_word(rtlpriv, reg_addr);
72 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
73 struct rtw_dev *rtwdev = dm->adapter;
74
75 return rtw_read16(rtwdev, reg_addr);
76 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
77 void *adapter = dm->adapter;
78 return rtw_read16(adapter, reg_addr);
79 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
80 void *adapter = dm->adapter;
81 return PlatformEFIORead2Byte(adapter, reg_addr);
82 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
83 void *adapter = dm->adapter;
84
85 return rtw_read16(adapter, reg_addr);
86 #endif
87 }
88
odm_read_4byte(struct dm_struct * dm,u32 reg_addr)89 u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr)
90 {
91 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
92 struct rtl8192cd_priv *priv = dm->priv;
93 return RTL_R32(reg_addr);
94 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
95 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
96
97 return rtl_read_dword(rtlpriv, reg_addr);
98 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
99 struct rtw_dev *rtwdev = dm->adapter;
100
101 return rtw_read32(rtwdev, reg_addr);
102 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
103 void *adapter = dm->adapter;
104 return rtw_read32(adapter, reg_addr);
105 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
106 void *adapter = dm->adapter;
107 return PlatformEFIORead4Byte(adapter, reg_addr);
108 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
109 void *adapter = dm->adapter;
110
111 return rtw_read32(adapter, reg_addr);
112 #endif
113 }
114
odm_write_1byte(struct dm_struct * dm,u32 reg_addr,u8 data)115 void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data)
116 {
117 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
118 struct rtl8192cd_priv *priv = dm->priv;
119 RTL_W8(reg_addr, data);
120 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
121 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
122
123 rtl_write_byte(rtlpriv, reg_addr, data);
124 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
125 struct rtw_dev *rtwdev = dm->adapter;
126
127 rtw_write8(rtwdev, reg_addr, data);
128 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
129 void *adapter = dm->adapter;
130 rtw_write8(adapter, reg_addr, data);
131 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
132 void *adapter = dm->adapter;
133 PlatformEFIOWrite1Byte(adapter, reg_addr, data);
134 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
135 void *adapter = dm->adapter;
136
137 rtw_write8(adapter, reg_addr, data);
138 #endif
139
140 if (dm->en_reg_mntr_byte)
141 pr_debug("1byte:addr=0x%x, data=0x%x\n", reg_addr, data);
142 }
143
odm_write_2byte(struct dm_struct * dm,u32 reg_addr,u16 data)144 void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data)
145 {
146 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
147 struct rtl8192cd_priv *priv = dm->priv;
148 RTL_W16(reg_addr, data);
149 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
150 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
151
152 rtl_write_word(rtlpriv, reg_addr, data);
153 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
154 struct rtw_dev *rtwdev = dm->adapter;
155
156 rtw_write16(rtwdev, reg_addr, data);
157 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
158 void *adapter = dm->adapter;
159 rtw_write16(adapter, reg_addr, data);
160 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
161 void *adapter = dm->adapter;
162 PlatformEFIOWrite2Byte(adapter, reg_addr, data);
163 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
164 void *adapter = dm->adapter;
165
166 rtw_write16(adapter, reg_addr, data);
167 #endif
168
169 if (dm->en_reg_mntr_byte)
170 pr_debug("2byte:addr=0x%x, data=0x%x\n", reg_addr, data);
171 }
172
odm_write_4byte(struct dm_struct * dm,u32 reg_addr,u32 data)173 void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data)
174 {
175 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
176 struct rtl8192cd_priv *priv = dm->priv;
177 RTL_W32(reg_addr, data);
178 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
179 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
180
181 rtl_write_dword(rtlpriv, reg_addr, data);
182 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
183 struct rtw_dev *rtwdev = dm->adapter;
184
185 rtw_write32(rtwdev, reg_addr, data);
186 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
187 void *adapter = dm->adapter;
188 rtw_write32(adapter, reg_addr, data);
189 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
190 void *adapter = dm->adapter;
191 PlatformEFIOWrite4Byte(adapter, reg_addr, data);
192 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
193 void *adapter = dm->adapter;
194
195 rtw_write32(adapter, reg_addr, data);
196 #endif
197
198 if (dm->en_reg_mntr_byte)
199 pr_debug("4byte:addr=0x%x, data=0x%x\n", reg_addr, data);
200 }
201
odm_set_mac_reg(struct dm_struct * dm,u32 reg_addr,u32 bit_mask,u32 data)202 void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data)
203 {
204 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
205 phy_set_bb_reg(dm->priv, reg_addr, bit_mask, data);
206 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
207 void *adapter = dm->adapter;
208 PHY_SetBBReg(adapter, reg_addr, bit_mask, data);
209 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
210 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
211
212 rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data);
213 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
214 struct rtw_dev *rtwdev = dm->adapter;
215
216 rtw_set_reg_with_mask(rtwdev, reg_addr, bit_mask, data);
217 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
218 phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
219 #else
220 phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
221 #endif
222
223 if (dm->en_reg_mntr_mac)
224 pr_debug("MAC:addr=0x%x, mask=0x%x, data=0x%x\n",
225 reg_addr, bit_mask, data);
226 }
227
odm_get_mac_reg(struct dm_struct * dm,u32 reg_addr,u32 bit_mask)228 u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask)
229 {
230 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
231 return phy_query_bb_reg(dm->priv, reg_addr, bit_mask);
232 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
233 return PHY_QueryMacReg(dm->adapter, reg_addr, bit_mask);
234 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
235 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
236
237 return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask);
238 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
239 struct rtw_dev *rtwdev = dm->adapter;
240
241 return rtw_get_reg_with_mask(rtwdev, reg_addr, bit_mask);
242 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
243 return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);
244 #else
245 return phy_query_mac_reg(dm->adapter, reg_addr, bit_mask);
246 #endif
247 }
248
odm_set_bb_reg(struct dm_struct * dm,u32 reg_addr,u32 bit_mask,u32 data)249 void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data)
250 {
251 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
252 phy_set_bb_reg(dm->priv, reg_addr, bit_mask, data);
253 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
254 void *adapter = dm->adapter;
255 PHY_SetBBReg(adapter, reg_addr, bit_mask, data);
256 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
257 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
258
259 rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data);
260 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
261 struct rtw_dev *rtwdev = dm->adapter;
262
263 rtw_set_reg_with_mask(rtwdev, reg_addr, bit_mask, data);
264 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
265 phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
266 #else
267 phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
268 #endif
269
270 if (dm->en_reg_mntr_bb)
271 pr_debug("BB:addr=0x%x, mask=0x%x, data=0x%x\n",
272 reg_addr, bit_mask, data);
273 }
274
odm_get_bb_reg(struct dm_struct * dm,u32 reg_addr,u32 bit_mask)275 u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask)
276 {
277 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
278 return phy_query_bb_reg(dm->priv, reg_addr, bit_mask);
279 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
280 void *adapter = dm->adapter;
281 return PHY_QueryBBReg(adapter, reg_addr, bit_mask);
282 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
283 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
284
285 return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask);
286 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
287 struct rtw_dev *rtwdev = dm->adapter;
288
289 return rtw_get_reg_with_mask(rtwdev, reg_addr, bit_mask);
290 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
291 return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);
292 #else
293 return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);
294 #endif
295 }
296
odm_set_rf_reg(struct dm_struct * dm,u8 e_rf_path,u32 reg_addr,u32 bit_mask,u32 data)297 void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
298 u32 bit_mask, u32 data)
299 {
300 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
301 phy_set_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, data);
302 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
303 void *adapter = dm->adapter;
304 PHY_SetRFReg(adapter, e_rf_path, reg_addr, bit_mask, data);
305 ODM_delay_us(2);
306
307 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
308 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
309
310 rtl_set_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask, data);
311 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
312 struct rtw_dev *rtwdev = dm->adapter;
313
314 rtw_write_rf(rtwdev, e_rf_path, reg_addr, bit_mask, data);
315 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
316 phy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data);
317 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
318 phy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data);
319 ODM_delay_us(2);
320 #endif
321
322 if (dm->en_reg_mntr_rf)
323 pr_debug("RF:path=0x%x, addr=0x%x, mask=0x%x, data=0x%x\n",
324 e_rf_path, reg_addr, bit_mask, data);
325 }
326
odm_get_rf_reg(struct dm_struct * dm,u8 e_rf_path,u32 reg_addr,u32 bit_mask)327 u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
328 u32 bit_mask)
329 {
330 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
331 return phy_query_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, 1);
332 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
333 void *adapter = dm->adapter;
334 return PHY_QueryRFReg(adapter, e_rf_path, reg_addr, bit_mask);
335 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
336 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
337
338 return rtl_get_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask);
339 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
340 struct rtw_dev *rtwdev = dm->adapter;
341
342 return rtw_read_rf(rtwdev, e_rf_path, reg_addr, bit_mask);
343 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
344 return phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask);
345 #else
346 return phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask);
347 #endif
348 }
349
350 enum hal_status
phydm_set_reg_by_fw(struct dm_struct * dm,enum phydm_halmac_param config_type,u32 offset,u32 data,u32 mask,enum rf_path e_rf_path,u32 delay_time)351 phydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type,
352 u32 offset, u32 data, u32 mask, enum rf_path e_rf_path,
353 u32 delay_time)
354 {
355 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
356 return HAL_MAC_Config_PHY_WriteNByte(dm,
357 config_type,
358 offset,
359 data,
360 mask,
361 e_rf_path,
362 delay_time);
363 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
364 #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
365 PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
366 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
367 return -ENOTSUPP;
368 #else
369 return rtw_phydm_cfg_phy_para(dm,
370 config_type,
371 offset,
372 data,
373 mask,
374 e_rf_path,
375 delay_time);
376 #endif
377 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
378 PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
379 #endif
380 }
381
382 /*@
383 * ODM Memory relative API.
384 */
odm_allocate_memory(struct dm_struct * dm,void ** ptr,u32 length)385 void odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length)
386 {
387 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
388 *ptr = kmalloc(length, GFP_ATOMIC);
389 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
390 *ptr = kmalloc(length, GFP_ATOMIC);
391 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
392 *ptr = kmalloc(length, GFP_ATOMIC);
393 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
394 *ptr = rtw_zvmalloc(length);
395 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
396 void *adapter = dm->adapter;
397 PlatformAllocateMemory(adapter, ptr, length);
398 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
399 *ptr = rtw_zvmalloc(length);
400 #endif
401 }
402
403 /* @length could be ignored, used to detect memory leakage. */
odm_free_memory(struct dm_struct * dm,void * ptr,u32 length)404 void odm_free_memory(struct dm_struct *dm, void *ptr, u32 length)
405 {
406 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
407 kfree(ptr);
408 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
409 kfree(ptr);
410 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
411 kfree(ptr);
412 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
413 rtw_vmfree(ptr, length);
414 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
415 /* struct void* adapter = dm->adapter; */
416 PlatformFreeMemory(ptr, length);
417 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
418 rtw_vmfree(ptr, length);
419 #endif
420 }
421
odm_move_memory(struct dm_struct * dm,void * dest,void * src,u32 length)422 void odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length)
423 {
424 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
425 memcpy(dest, src, length);
426 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
427 memcpy(dest, src, length);
428 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
429 memcpy(dest, src, length);
430 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
431 _rtw_memcpy(dest, src, length);
432 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
433 PlatformMoveMemory(dest, src, length);
434 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
435 rtw_memcpy(dest, src, length);
436 #endif
437 }
438
odm_convert_to_le16(u16 value)439 u16 odm_convert_to_le16(u16 value)
440 {
441 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
442 return cpu_to_le16(value);
443 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
444 return cpu_to_le16(value);
445 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
446 return cpu_to_le16(value);
447 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
448 return cpu_to_le16(value);
449 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
450 return value;
451 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
452 return cpu_to_le16(value);
453 #else
454 return value;
455 #endif
456 }
457
odm_convert_to_le32(u32 value)458 u32 odm_convert_to_le32(u32 value)
459 {
460 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
461 return cpu_to_le32(value);
462 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
463 return cpu_to_le32(value);
464 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
465 return cpu_to_le32(value);
466 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
467 return cpu_to_le32(value);
468 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
469 return value;
470 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
471 return cpu_to_le32(value);
472 #else
473 return value;
474 #endif
475 }
476
odm_memory_set(struct dm_struct * dm,void * pbuf,s8 value,u32 length)477 void odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length)
478 {
479 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
480 memset(pbuf, value, length);
481 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
482 memset(pbuf, value, length);
483 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
484 memset(pbuf, value, length);
485 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
486 _rtw_memset(pbuf, value, length);
487 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
488 PlatformFillMemory(pbuf, length, value);
489 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
490 rtw_memset(pbuf, value, length);
491 #endif
492 }
493
odm_compare_memory(struct dm_struct * dm,void * buf1,void * buf2,u32 length)494 s32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2, u32 length)
495 {
496 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
497 return memcmp(buf1, buf2, length);
498 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
499 return memcmp(buf1, buf2, length);
500 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
501 return memcmp(buf1, buf2, length);
502 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
503 return _rtw_memcmp(buf1, buf2, length);
504 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
505 return PlatformCompareMemory(buf1, buf2, length);
506 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
507 return rtw_memcmp(buf1, buf2, length);
508 #endif
509 }
510
511 /*@
512 * ODM MISC relative API.
513 */
odm_acquire_spin_lock(struct dm_struct * dm,enum rt_spinlock_type type)514 void odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type)
515 {
516 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
517
518 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
519 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
520
521 rtl_odm_acquirespinlock(rtlpriv, type);
522 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
523 struct rtw_dev *rtwdev = dm->adapter;
524
525 spin_lock(&rtwdev->hal.dm_lock);
526 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
527 void *adapter = dm->adapter;
528 rtw_odm_acquirespinlock(adapter, type);
529 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
530 void *adapter = dm->adapter;
531 PlatformAcquireSpinLock(adapter, type);
532 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
533 void *adapter = dm->adapter;
534
535 rtw_odm_acquirespinlock(adapter, type);
536 #endif
537 }
538
odm_release_spin_lock(struct dm_struct * dm,enum rt_spinlock_type type)539 void odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type)
540 {
541 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
542
543 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
544 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
545
546 rtl_odm_releasespinlock(rtlpriv, type);
547 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
548 struct rtw_dev *rtwdev = dm->adapter;
549
550 spin_unlock(&rtwdev->hal.dm_lock);
551 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
552 void *adapter = dm->adapter;
553 rtw_odm_releasespinlock(adapter, type);
554 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
555 void *adapter = dm->adapter;
556 PlatformReleaseSpinLock(adapter, type);
557 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
558 void *adapter = dm->adapter;
559
560 rtw_odm_releasespinlock(adapter, type);
561 #endif
562 }
563
564 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
565 /*@
566 * Work item relative API. FOr MP driver only~!
567 * */
odm_initialize_work_item(struct dm_struct * dm,PRT_WORK_ITEM work_item,RT_WORKITEM_CALL_BACK callback,void * context,const char * id)568 void odm_initialize_work_item(
569 struct dm_struct *dm,
570 PRT_WORK_ITEM work_item,
571 RT_WORKITEM_CALL_BACK callback,
572 void *context,
573 const char *id)
574 {
575 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
576
577 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
578
579 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
580 void *adapter = dm->adapter;
581 PlatformInitializeWorkItem(adapter, work_item, callback, context, id);
582 #endif
583 }
584
odm_start_work_item(PRT_WORK_ITEM p_rt_work_item)585 void odm_start_work_item(
586 PRT_WORK_ITEM p_rt_work_item)
587 {
588 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
589
590 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
591
592 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
593 PlatformStartWorkItem(p_rt_work_item);
594 #endif
595 }
596
odm_stop_work_item(PRT_WORK_ITEM p_rt_work_item)597 void odm_stop_work_item(
598 PRT_WORK_ITEM p_rt_work_item)
599 {
600 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
601
602 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
603
604 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
605 PlatformStopWorkItem(p_rt_work_item);
606 #endif
607 }
608
odm_free_work_item(PRT_WORK_ITEM p_rt_work_item)609 void odm_free_work_item(
610 PRT_WORK_ITEM p_rt_work_item)
611 {
612 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
613
614 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
615
616 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
617 PlatformFreeWorkItem(p_rt_work_item);
618 #endif
619 }
620
odm_schedule_work_item(PRT_WORK_ITEM p_rt_work_item)621 void odm_schedule_work_item(
622 PRT_WORK_ITEM p_rt_work_item)
623 {
624 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
625
626 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
627
628 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
629 PlatformScheduleWorkItem(p_rt_work_item);
630 #endif
631 }
632
633 boolean
odm_is_work_item_scheduled(PRT_WORK_ITEM p_rt_work_item)634 odm_is_work_item_scheduled(
635 PRT_WORK_ITEM p_rt_work_item)
636 {
637 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
638
639 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
640
641 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
642 return PlatformIsWorkItemScheduled(p_rt_work_item);
643 #endif
644 }
645 #endif
646
647 /*@
648 * ODM Timer relative API.
649 */
650
ODM_delay_ms(u32 ms)651 void ODM_delay_ms(u32 ms)
652 {
653 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
654 delay_ms(ms);
655 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
656 mdelay(ms);
657 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
658 mdelay(ms);
659 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
660 rtw_mdelay_os(ms);
661 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
662 delay_ms(ms);
663 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
664 rtw_mdelay_os(ms);
665 #endif
666 }
667
ODM_delay_us(u32 us)668 void ODM_delay_us(u32 us)
669 {
670 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
671 delay_us(us);
672 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
673 udelay(us);
674 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
675 udelay(us);
676 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
677 rtw_udelay_os(us);
678 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
679 PlatformStallExecution(us);
680 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
681 rtw_udelay_os(us);
682 #endif
683 }
684
ODM_sleep_ms(u32 ms)685 void ODM_sleep_ms(u32 ms)
686 {
687 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
688 delay_ms(ms);
689 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
690 msleep(ms);
691 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
692 msleep(ms);
693 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
694 rtw_msleep_os(ms);
695 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
696 delay_ms(ms);
697 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
698 rtw_msleep_os(ms);
699 #endif
700 }
701
ODM_sleep_us(u32 us)702 void ODM_sleep_us(u32 us)
703 {
704 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
705 delay_us(us);
706 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
707 usleep_range(us, us + 1);
708 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
709 usleep_range(us, us + 1);
710 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
711 rtw_usleep_os(us);
712 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
713 PlatformStallExecution(us);
714 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
715 rtw_usleep_os(us);
716 #endif
717 }
718
odm_set_timer(struct dm_struct * dm,struct phydm_timer_list * timer,u32 ms_delay)719 void odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
720 u32 ms_delay)
721 {
722 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
723 mod_timer(timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(ms_delay));
724 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
725 mod_timer(timer, jiffies + msecs_to_jiffies(ms_delay));
726 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
727 mod_timer(&timer->timer, jiffies + msecs_to_jiffies(ms_delay));
728 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
729 _set_timer(timer, ms_delay); /* @ms */
730 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
731 void *adapter = dm->adapter;
732 PlatformSetTimer(adapter, timer, ms_delay);
733 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
734 rtw_set_timer(timer, ms_delay); /* @ms */
735 #endif
736 }
737
odm_initialize_timer(struct dm_struct * dm,struct phydm_timer_list * timer,void * call_back_func,void * context,const char * sz_id)738 void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
739 void *call_back_func, void *context,
740 const char *sz_id)
741 {
742 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
743 init_timer(timer);
744 timer->function = call_back_func;
745 timer->data = (unsigned long)dm;
746 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
747 timer_setup(timer, call_back_func, 0);
748 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
749 struct _ADAPTER *adapter = dm->adapter;
750
751 _init_timer(timer, adapter->pnetdev, call_back_func, dm);
752 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
753 void *adapter = dm->adapter;
754
755 PlatformInitializeTimer(adapter, timer, (RT_TIMER_CALL_BACK)call_back_func, context, sz_id);
756 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
757 struct _ADAPTER *adapter = dm->adapter;
758
759 rtw_init_timer(timer, adapter->pnetdev, (TIMER_FUN)call_back_func, dm, NULL);
760 #endif
761 }
762
odm_cancel_timer(struct dm_struct * dm,struct phydm_timer_list * timer)763 void odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer)
764 {
765 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
766 del_timer(timer);
767 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
768 del_timer(timer);
769 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
770 del_timer(&timer->timer);
771 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
772 _cancel_timer_ex(timer);
773 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
774 void *adapter = dm->adapter;
775 PlatformCancelTimer(adapter, timer);
776 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
777 rtw_cancel_timer(timer);
778 #endif
779 }
780
odm_release_timer(struct dm_struct * dm,struct phydm_timer_list * timer)781 void odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer)
782 {
783 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
784
785 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
786
787 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
788
789 void *adapter = dm->adapter;
790
791 /* @<20120301, Kordan> If the initilization fails,
792 * InitializeAdapterXxx will return regardless of InitHalDm.
793 * Hence, uninitialized timers cause BSOD when the driver
794 * releases resources since the init fail.
795 */
796 if (timer == 0) {
797 PHYDM_DBG(dm, ODM_COMP_INIT,
798 "[%s] Timer is NULL! Please check!\n", __func__);
799 return;
800 }
801
802 PlatformReleaseTimer(adapter, timer);
803 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
804 rtw_del_timer(timer);
805 #endif
806 }
807
phydm_trans_h2c_id(struct dm_struct * dm,u8 phydm_h2c_id)808 u8 phydm_trans_h2c_id(struct dm_struct *dm, u8 phydm_h2c_id)
809 {
810 u8 platform_h2c_id = phydm_h2c_id;
811
812 switch (phydm_h2c_id) {
813 /* @1 [0] */
814 case ODM_H2C_RSSI_REPORT:
815
816 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
817 #if (RTL8188E_SUPPORT == 1)
818 if (dm->support_ic_type == ODM_RTL8188E)
819 platform_h2c_id = H2C_88E_RSSI_REPORT;
820 else
821 #endif
822 platform_h2c_id = H2C_RSSI_REPORT;
823
824 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
825 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
826 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
827 platform_h2c_id = H2C_RSSI_SETTING;
828
829 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
830 #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
831 if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8192F | PHYDM_IC_3081_SERIES))
832 platform_h2c_id = H2C_88XX_RSSI_REPORT;
833 else
834 #endif
835 #if (RTL8812A_SUPPORT == 1)
836 if (dm->support_ic_type == ODM_RTL8812)
837 platform_h2c_id = H2C_8812_RSSI_REPORT;
838 else
839 #endif
840 {
841 }
842 #endif
843
844 break;
845
846 /* @1 [3] */
847 case ODM_H2C_WIFI_CALIBRATION:
848 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
849 platform_h2c_id = H2C_WIFI_CALIBRATION;
850
851 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
852 #if (RTL8723B_SUPPORT == 1)
853 platform_h2c_id = H2C_8723B_BT_WLAN_CALIBRATION;
854 #endif
855
856 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
857 #endif
858 break;
859
860 /* @1 [4] */
861 case ODM_H2C_IQ_CALIBRATION:
862 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
863 platform_h2c_id = H2C_IQ_CALIBRATION;
864
865 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
866 #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
867 platform_h2c_id = H2C_8812_IQ_CALIBRATION;
868 #endif
869 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
870 #endif
871
872 break;
873 /* @1 [5] */
874 case ODM_H2C_RA_PARA_ADJUST:
875
876 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
877 platform_h2c_id = H2C_RA_PARA_ADJUST;
878 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
879 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
880 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
881 #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
882 platform_h2c_id = H2C_8812_RA_PARA_ADJUST;
883 #elif ((RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1))
884 platform_h2c_id = H2C_RA_PARA_ADJUST;
885 #elif (RTL8192E_SUPPORT == 1)
886 platform_h2c_id = H2C_8192E_RA_PARA_ADJUST;
887 #elif (RTL8723B_SUPPORT == 1)
888 platform_h2c_id = H2C_8723B_RA_PARA_ADJUST;
889 #endif
890
891 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
892 #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
893 if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8192F | PHYDM_IC_3081_SERIES))
894 platform_h2c_id = H2C_88XX_RA_PARA_ADJUST;
895 else
896 #endif
897 #if (RTL8812A_SUPPORT == 1)
898 if (dm->support_ic_type == ODM_RTL8812)
899 platform_h2c_id = H2C_8812_RA_PARA_ADJUST;
900 else
901 #endif
902 {
903 }
904 #endif
905
906 break;
907
908 /* @1 [6] */
909 case PHYDM_H2C_DYNAMIC_TX_PATH:
910
911 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
912 #if (RTL8814A_SUPPORT == 1)
913 if (dm->support_ic_type == ODM_RTL8814A)
914 platform_h2c_id = H2C_8814A_DYNAMIC_TX_PATH;
915 #endif
916 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
917 #if (RTL8814A_SUPPORT == 1)
918 if (dm->support_ic_type == ODM_RTL8814A)
919 platform_h2c_id = H2C_DYNAMIC_TX_PATH;
920 #endif
921 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
922 #if (RTL8814A_SUPPORT == 1)
923 if (dm->support_ic_type == ODM_RTL8814A)
924 platform_h2c_id = H2C_88XX_DYNAMIC_TX_PATH;
925 #endif
926
927 #endif
928
929 break;
930
931 /* @[7]*/
932 case PHYDM_H2C_FW_TRACE_EN:
933
934 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
935
936 platform_h2c_id = H2C_FW_TRACE_EN;
937
938 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
939
940 platform_h2c_id = 0x49;
941
942 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
943 #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
944 if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8192F | PHYDM_IC_3081_SERIES))
945 platform_h2c_id = H2C_88XX_FW_TRACE_EN;
946 else
947 #endif
948 #if (RTL8812A_SUPPORT == 1)
949 if (dm->support_ic_type == ODM_RTL8812)
950 platform_h2c_id = H2C_8812_FW_TRACE_EN;
951 else
952 #endif
953 {
954 }
955
956 #endif
957
958 break;
959
960 case PHYDM_H2C_TXBF:
961 #if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1))
962 if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812))
963 platform_h2c_id = 0x41; /*@H2C_TxBF*/
964 #endif
965 break;
966
967 case PHYDM_H2C_MU:
968 #if (RTL8822B_SUPPORT == 1)
969 platform_h2c_id = 0x4a; /*@H2C_MU*/
970 #endif
971 break;
972
973 default:
974 platform_h2c_id = phydm_h2c_id;
975 break;
976 }
977
978 return platform_h2c_id;
979 }
980
981 /*@ODM FW relative API.*/
982
odm_fill_h2c_cmd(struct dm_struct * dm,u8 phydm_h2c_id,u32 cmd_len,u8 * cmd_buf)983 void odm_fill_h2c_cmd(struct dm_struct *dm, u8 phydm_h2c_id, u32 cmd_len,
984 u8 *cmd_buf)
985 {
986 #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
987 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
988 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
989 struct rtw_dev *rtwdev = dm->adapter;
990 u8 cmd_id, cmd_class;
991 u8 h2c_pkt[8];
992 #else
993 void *adapter = dm->adapter;
994 #endif
995 u8 h2c_id = phydm_trans_h2c_id(dm, phydm_h2c_id);
996
997 PHYDM_DBG(dm, DBG_RA, "[H2C] h2c_id=((0x%x))\n", h2c_id);
998
999 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1000 if (dm->support_ic_type == ODM_RTL8188E) {
1001 if (!dm->ra_support88e)
1002 FillH2CCmd88E(adapter, h2c_id, cmd_len, cmd_buf);
1003 } else if (dm->support_ic_type == ODM_RTL8814A)
1004 FillH2CCmd8814A(adapter, h2c_id, cmd_len, cmd_buf);
1005 else if (dm->support_ic_type == ODM_RTL8822B)
1006 FillH2CCmd8822B(adapter, h2c_id, cmd_len, cmd_buf);
1007 else
1008 FillH2CCmd(adapter, h2c_id, cmd_len, cmd_buf);
1009
1010 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1011
1012 #ifdef DM_ODM_CE_MAC80211
1013 rtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->hw, h2c_id, cmd_len, cmd_buf);
1014 #elif defined(DM_ODM_CE_MAC80211_V2)
1015 cmd_id = phydm_h2c_id & 0x1f;
1016 cmd_class = (phydm_h2c_id >> RTW_H2C_CLASS_OFFSET) & 0x7;
1017 memcpy(h2c_pkt + 1, cmd_buf, 7);
1018 h2c_pkt[0] = phydm_h2c_id;
1019 rtw_fw_send_h2c_packet(rtwdev, h2c_pkt, cmd_id, cmd_class);
1020 /* TODO: implement fill h2c command for rtwlan */
1021 #else
1022 rtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buf);
1023 #endif
1024
1025 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
1026
1027 #if (RTL8812A_SUPPORT == 1)
1028 if (dm->support_ic_type == ODM_RTL8812) {
1029 fill_h2c_cmd8812(dm->priv, h2c_id, cmd_len, cmd_buf);
1030 } else
1031 #endif
1032 {
1033 GET_HAL_INTERFACE(dm->priv)->fill_h2c_cmd_handler(dm->priv, h2c_id, cmd_len, cmd_buf);
1034 }
1035
1036 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
1037 rtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buf);
1038
1039 #endif
1040 }
1041
phydm_c2H_content_parsing(void * dm_void,u8 c2h_cmd_id,u8 c2h_cmd_len,u8 * tmp_buf)1042 u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,
1043 u8 *tmp_buf)
1044 {
1045 struct dm_struct *dm = (struct dm_struct *)dm_void;
1046 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1047 void *adapter = dm->adapter;
1048 #endif
1049 u8 extend_c2h_sub_id = 0;
1050 u8 find_c2h_cmd = true;
1051
1052 if (c2h_cmd_len > 12 || c2h_cmd_len == 0) {
1053 pr_debug("[Warning] Error C2H ID=%d, len=%d\n",
1054 c2h_cmd_id, c2h_cmd_len);
1055
1056 find_c2h_cmd = false;
1057 return find_c2h_cmd;
1058 }
1059
1060 switch (c2h_cmd_id) {
1061 case PHYDM_C2H_DBG:
1062 phydm_fw_trace_handler(dm, tmp_buf, c2h_cmd_len);
1063 break;
1064
1065 case PHYDM_C2H_RA_RPT:
1066 phydm_c2h_ra_report_handler(dm, tmp_buf, c2h_cmd_len);
1067 break;
1068
1069 case PHYDM_C2H_RA_PARA_RPT:
1070 odm_c2h_ra_para_report_handler(dm, tmp_buf, c2h_cmd_len);
1071 break;
1072 #ifdef CONFIG_PATH_DIVERSITY
1073 case PHYDM_C2H_DYNAMIC_TX_PATH_RPT:
1074 if (dm->support_ic_type & (ODM_RTL8814A))
1075 phydm_c2h_dtp_handler(dm, tmp_buf, c2h_cmd_len);
1076 break;
1077 #endif
1078
1079 case PHYDM_C2H_IQK_FINISH:
1080 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1081
1082 if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) {
1083 RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Finish ==\n"));
1084 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1085 dm->rf_calibrate_info.is_iqk_in_progress = false;
1086 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1087 dm->rf_calibrate_info.iqk_progressing_time = 0;
1088 dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time);
1089 }
1090
1091 #endif
1092 break;
1093
1094 case PHYDM_C2H_CLM_MONITOR:
1095 phydm_clm_c2h_report_handler(dm, tmp_buf, c2h_cmd_len);
1096 break;
1097
1098 case PHYDM_C2H_DBG_CODE:
1099 phydm_fw_trace_handler_code(dm, tmp_buf, c2h_cmd_len);
1100 break;
1101
1102 case PHYDM_C2H_EXTEND:
1103 extend_c2h_sub_id = tmp_buf[0];
1104 if (extend_c2h_sub_id == PHYDM_EXTEND_C2H_DBG_PRINT)
1105 phydm_fw_trace_handler_8051(dm, tmp_buf, c2h_cmd_len);
1106
1107 break;
1108
1109 default:
1110 find_c2h_cmd = false;
1111 break;
1112 }
1113
1114 return find_c2h_cmd;
1115 }
1116
odm_get_current_time(struct dm_struct * dm)1117 u64 odm_get_current_time(struct dm_struct *dm)
1118 {
1119 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1120 return (u64)rtw_get_current_time();
1121 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1122 return jiffies;
1123 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
1124 return jiffies;
1125 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1126 return rtw_get_current_time();
1127 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1128 return PlatformGetCurrentTime();
1129 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
1130 return rtw_get_current_time();
1131 #endif
1132 }
1133
odm_get_progressing_time(struct dm_struct * dm,u64 start_time)1134 u64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time)
1135 {
1136 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1137 return rtw_get_passing_time_ms((u32)start_time);
1138 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1139 return jiffies_to_msecs(jiffies - start_time);
1140 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
1141 return jiffies_to_msecs(jiffies - start_time);
1142 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1143 return rtw_get_passing_time_ms((systime)start_time);
1144 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1145 return ((PlatformGetCurrentTime() - start_time) >> 10);
1146 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
1147 return rtw_get_passing_time_ms(start_time);
1148 #endif
1149 }
1150
1151 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \
1152 (!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
1153
phydm_set_hw_reg_handler_interface(struct dm_struct * dm,u8 RegName,u8 * val)1154 void phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 RegName,
1155 u8 *val)
1156 {
1157 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1158 struct _ADAPTER *adapter = dm->adapter;
1159
1160 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1161 ((PADAPTER)adapter)->HalFunc.SetHwRegHandler(adapter, RegName, val);
1162 #else
1163 adapter->hal_func.set_hw_reg_handler(adapter, RegName, val);
1164 #endif
1165
1166 #endif
1167 }
1168
phydm_get_hal_def_var_handler_interface(struct dm_struct * dm,enum _HAL_DEF_VARIABLE e_variable,void * value)1169 void phydm_get_hal_def_var_handler_interface(struct dm_struct *dm,
1170 enum _HAL_DEF_VARIABLE e_variable,
1171 void *value)
1172 {
1173 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1174 struct _ADAPTER *adapter = dm->adapter;
1175
1176 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1177 ((PADAPTER)adapter)->HalFunc.GetHalDefVarHandler(adapter, e_variable, value);
1178 #else
1179 adapter->hal_func.get_hal_def_var_handler(adapter, e_variable, value);
1180 #endif
1181
1182 #endif
1183 }
1184
1185 #endif
1186
odm_set_tx_power_index_by_rate_section(struct dm_struct * dm,enum rf_path path,u8 ch,u8 section)1187 void odm_set_tx_power_index_by_rate_section(struct dm_struct *dm,
1188 enum rf_path path, u8 ch,
1189 u8 section)
1190 {
1191 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1192 void *adapter = dm->adapter;
1193 PHY_SetTxPowerIndexByRateSection(adapter, path, ch, section);
1194 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
1195 void *adapter = dm->adapter;
1196
1197 phy_set_tx_power_index_by_rs(adapter, ch, path, section);
1198 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
1199 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1200 phy_set_tx_power_index_by_rate_section(dm->adapter, path, ch, section);
1201 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
1202 void *adapter = dm->adapter;
1203
1204 PHY_SetTxPowerIndexByRateSection(adapter, path, ch, section);
1205 #endif
1206 }
1207
odm_get_tx_power_index(struct dm_struct * dm,enum rf_path path,u8 rate,u8 bw,u8 ch)1208 u8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 rate,
1209 u8 bw, u8 ch)
1210 {
1211 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1212 void *adapter = dm->adapter;
1213
1214 return PHY_GetTxPowerIndex(dm->adapter, path, rate, (CHANNEL_WIDTH)bw, ch);
1215 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1216 void *adapter = dm->adapter;
1217
1218 return phy_get_tx_power_index(adapter, path, rate, bw, ch);
1219 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
1220 void *adapter = dm->adapter;
1221
1222 return phy_get_tx_power_index(adapter, path, rate, bw, ch);
1223 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1224 return phy_get_tx_power_index(dm->adapter, path, rate, bw, ch);
1225 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
1226 void *adapter = dm->adapter;
1227
1228 return PHY_GetTxPowerIndex(dm->adapter, path, rate, bw, ch);
1229 #endif
1230 }
1231
odm_efuse_one_byte_read(struct dm_struct * dm,u16 addr,u8 * data,boolean b_pseu_do_test)1232 u8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data,
1233 boolean b_pseu_do_test)
1234 {
1235 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1236 void *adapter = dm->adapter;
1237
1238 return (u8)EFUSE_OneByteRead(adapter, addr, data, b_pseu_do_test);
1239 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1240 void *adapter = dm->adapter;
1241
1242 return rtl_efuse_onebyte_read(adapter, addr, data, b_pseu_do_test);
1243 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
1244 return -1;
1245 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1246 return efuse_onebyte_read(dm->adapter, addr, data, b_pseu_do_test);
1247 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
1248 return Efuse_OneByteRead(dm, addr, data);
1249 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
1250 void *adapter = dm->adapter;
1251
1252 return (u8)efuse_OneByteRead(adapter, addr, data, b_pseu_do_test);
1253 #endif
1254 }
1255
odm_efuse_logical_map_read(struct dm_struct * dm,u8 type,u16 offset,u32 * data)1256 void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset,
1257 u32 *data)
1258 {
1259 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1260 void *adapter = dm->adapter;
1261
1262 EFUSE_ShadowRead(adapter, type, offset, data);
1263 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1264 void *adapter = dm->adapter;
1265
1266 rtl_efuse_logical_map_read(adapter, type, offset, data);
1267 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
1268 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1269 efuse_logical_map_read(dm->adapter, type, offset, data);
1270 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
1271 void *adapter = dm->adapter;
1272
1273 EFUSE_ShadowRead(adapter, type, offset, data);
1274 #endif
1275 }
1276
1277 enum hal_status
odm_iq_calibrate_by_fw(struct dm_struct * dm,u8 clear,u8 segment)1278 odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment)
1279 {
1280 enum hal_status iqk_result = HAL_STATUS_FAILURE;
1281
1282 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1283 struct _ADAPTER *adapter = dm->adapter;
1284
1285 if (HAL_MAC_FWIQK_Trigger(&GET_HAL_MAC_INFO(adapter), clear, segment) == 0)
1286 iqk_result = HAL_STATUS_SUCCESS;
1287 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1288 #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1289 void *adapter = dm->adapter;
1290
1291 iqk_result = rtl_phydm_fw_iqk(adapter, clear, segment);
1292 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
1293 #else
1294 iqk_result = rtw_phydm_fw_iqk(dm, clear, segment);
1295 #endif
1296 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
1297 iqk_result = rtw_phydm_fw_iqk(dm, clear, segment);
1298 #endif
1299 return iqk_result;
1300 }
1301
1302 enum hal_status
odm_dpk_by_fw(struct dm_struct * dm)1303 odm_dpk_by_fw(struct dm_struct *dm)
1304 {
1305 enum hal_status dpk_result = HAL_STATUS_FAILURE;
1306 #if 0
1307
1308 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1309 struct _ADAPTER *adapter = dm->adapter;
1310
1311 if (hal_mac_fwdpk_trigger(&GET_HAL_MAC_INFO(adapter)) == 0)
1312 dpk_result = HAL_STATUS_SUCCESS;
1313 #else
1314 dpk_result = rtw_phydm_fw_dpk(dm);
1315 #endif
1316
1317 #endif
1318 return dpk_result;
1319 }
1320
phydm_cmn_sta_info_hook(struct dm_struct * dm,u8 mac_id,struct cmn_sta_info * pcmn_sta_info)1321 void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 mac_id,
1322 struct cmn_sta_info *pcmn_sta_info)
1323 {
1324 dm->phydm_sta_info[mac_id] = pcmn_sta_info;
1325
1326 if (is_sta_active(pcmn_sta_info))
1327 dm->phydm_macid_table[pcmn_sta_info->mac_id] = mac_id;
1328 }
1329
phydm_macid2sta_idx_table(struct dm_struct * dm,u8 entry_idx,struct cmn_sta_info * pcmn_sta_info)1330 void phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx,
1331 struct cmn_sta_info *pcmn_sta_info)
1332 {
1333 if (is_sta_active(pcmn_sta_info))
1334 dm->phydm_macid_table[pcmn_sta_info->mac_id] = entry_idx;
1335 }
1336
phydm_add_interrupt_mask_handler(struct dm_struct * dm,u8 interrupt_type)1337 void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type)
1338 {
1339 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1340 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
1341
1342 struct rtl8192cd_priv *priv = dm->priv;
1343
1344 #if IS_EXIST_PCI || IS_EXIST_EMBEDDED
1345 if (dm->support_interface == ODM_ITRF_PCIE)
1346 GET_HAL_INTERFACE(priv)->AddInterruptMaskHandler(priv,
1347 interrupt_type)
1348 ;
1349 #endif
1350
1351 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1352 #endif
1353 }
1354
phydm_enable_rx_related_interrupt_handler(struct dm_struct * dm)1355 void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm)
1356 {
1357 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1358 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
1359
1360 struct rtl8192cd_priv *priv = dm->priv;
1361
1362 #if IS_EXIST_PCI || IS_EXIST_EMBEDDED
1363 if (dm->support_interface == ODM_ITRF_PCIE)
1364 GET_HAL_INTERFACE(priv)->EnableRxRelatedInterruptHandler(priv);
1365 #endif
1366
1367 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1368 #endif
1369 }
1370
phydm_iqk_wait(struct dm_struct * dm,u32 timeout)1371 void phydm_iqk_wait(struct dm_struct *dm, u32 timeout)
1372 {
1373 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1374 #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1375 PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
1376 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
1377 #else
1378 void *adapter = dm->adapter;
1379
1380 rtl8812_iqk_wait(adapter, timeout);
1381 #endif
1382 #endif
1383 }
1384
phydm_get_hwrate_to_mrate(struct dm_struct * dm,u8 rate)1385 u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate)
1386 {
1387 #if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
1388 return HwRateToMRate(rate);
1389 #endif
1390 return 0;
1391 }
1392
phydm_set_crystalcap(struct dm_struct * dm,u8 crystal_cap)1393 void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap)
1394 {
1395 #if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
1396 ROM_odm_SetCrystalCap(dm, crystal_cap);
1397 #endif
1398 }
1399
phydm_run_in_thread_cmd(struct dm_struct * dm,void (* func)(void *),void * context)1400 void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *),
1401 void *context)
1402 {
1403 #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1404 PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
1405 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1406 void *adapter = dm->adapter;
1407
1408 rtw_run_in_thread_cmd(adapter, func, context);
1409 #endif
1410 }
1411
phydm_get_tx_rate(struct dm_struct * dm)1412 u8 phydm_get_tx_rate(struct dm_struct *dm)
1413 {
1414 struct _hal_rf_ *rf = &dm->rf_table;
1415 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1416 struct _ADAPTER *adapter = dm->adapter;
1417 #endif
1418 u8 tx_rate = 0xff;
1419 u8 mpt_rate_index = 0;
1420
1421 if (*dm->mp_mode == 1) {
1422 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1423 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1424 #if (MP_DRIVER == 1)
1425 PMPT_CONTEXT p_mpt_ctx = &adapter->MptCtx;
1426
1427 tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
1428 #endif
1429 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1430 #ifdef CONFIG_MP_INCLUDED
1431 if (rf->mp_rate_index)
1432 mpt_rate_index = *rf->mp_rate_index;
1433
1434 tx_rate = mpt_to_mgnt_rate(mpt_rate_index);
1435 #endif
1436 #endif
1437 #endif
1438 } else {
1439 u16 rate = *dm->forced_data_rate;
1440
1441 if (!rate) { /*auto rate*/
1442 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1443 struct _ADAPTER *adapter = dm->adapter;
1444
1445 tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
1446 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1447 tx_rate = dm->tx_rate;
1448 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1449 if (dm->number_linked_client != 0)
1450 tx_rate = hw_rate_to_m_rate(dm->tx_rate);
1451 else
1452 tx_rate = rf->p_rate_index;
1453 #endif
1454 } else { /*force rate*/
1455 tx_rate = (u8)rate;
1456 }
1457 }
1458
1459 return tx_rate;
1460 }
1461
phydm_get_tx_power_dbm(struct dm_struct * dm,u8 rf_path,u8 rate,u8 bandwidth,u8 channel)1462 u8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path,
1463 u8 rate, u8 bandwidth, u8 channel)
1464 {
1465 u8 tx_power_dbm = 0;
1466 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1467 struct _ADAPTER *adapter = dm->adapter;
1468 tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValue(adapter, rf_path, rate, bandwidth, channel);
1469 #endif
1470
1471 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1472 tx_power_dbm = phy_get_tx_power_final_absolute_value(dm->adapter, rf_path, rate, bandwidth, channel);
1473 #endif
1474
1475 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1476 tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValue(dm, rf_path, rate, bandwidth, channel);
1477 #endif
1478 return tx_power_dbm;
1479 }
1480
phydm_get_tx_power_mdbm(struct dm_struct * dm,u8 rf_path,u8 rate,u8 bandwidth,u8 channel)1481 s16 phydm_get_tx_power_mdbm(struct dm_struct *dm, u8 rf_path,
1482 u8 rate, u8 bandwidth, u8 channel)
1483 {
1484 s16 tx_power_dbm = 0;
1485 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1486 struct _ADAPTER *adapter = dm->adapter;
1487 tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValuemdBm(adapter, rf_path, rate, bandwidth, channel);
1488 #endif
1489
1490 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1491 tx_power_dbm = rtw_odm_get_tx_power_mbm(dm, rf_path, rate, bandwidth, channel);
1492 #endif
1493
1494 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1495 tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValuembm(dm, rf_path, rate, bandwidth, channel);
1496 #endif
1497 return tx_power_dbm;
1498 }
1499
phydm_rfe_ctrl_gpio(struct dm_struct * dm,u8 gpio_num)1500 u32 phydm_rfe_ctrl_gpio(struct dm_struct *dm, u8 gpio_num)
1501 {
1502 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1503 return rtw_phydm_rfe_ctrl_gpio(dm->adapter, gpio_num);
1504 #endif
1505 return 0;
1506 }
1507
phydm_division64(u64 x,u64 y)1508 u64 phydm_division64(u64 x, u64 y)
1509 {
1510 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1511 do_div(x, y);
1512 return x;
1513 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1514 return x / y;
1515 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1516 return rtw_division64(x, y);
1517 #endif
1518 }
1519