1 /* 2 * Copyright (c) 2022 ASR Microelectronics (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #include "duet_pinmux.h" 17 duet_pinmux_config(Pad_Num_Type pad_num,Pad_Func_Type pad_func)18Pad_Config_State duet_pinmux_config(Pad_Num_Type pad_num, Pad_Func_Type pad_func) 19 { 20 uint32_t pad_reg_addr = PINMUX_REG_BASE + 4 * (pad_num >> 3); // pinmux register address of pad pad_num 21 uint32_t reg_offset = (pad_num % 8) * 4; // offset from pad_reg_addr in bits 22 Pad_Config_State config_state = Config_Success; 23 uint32_t pad_func_value = 0; 24 switch (pad_num) { 25 case PAD0: 26 switch (pad_func) { 27 case PF_GPIO0: 28 pad_func_value = 0; 29 break; 30 case PF_UART0: 31 pad_func_value = 1; 32 break; 33 case PF_SWD: 34 pad_func_value = 2; 35 break; 36 case PF_SPI1: 37 pad_func_value = 3; 38 break; 39 case PF_PWM5: 40 pad_func_value = 4; 41 break; 42 default: 43 config_state = Config_Fail; 44 break; 45 } 46 break; 47 case PAD1: 48 switch (pad_func) { 49 case PF_GPIO1: 50 pad_func_value = 0; 51 break; 52 case PF_UART0: 53 pad_func_value = 1; 54 break; 55 case PF_SWD: 56 pad_func_value = 2; 57 break; 58 case PF_SPI1: 59 pad_func_value = 3; 60 break; 61 case PF_PWM7: 62 pad_func_value = 4; 63 break; 64 default: 65 config_state = Config_Fail; 66 break; 67 } 68 break; 69 case PAD2: 70 switch (pad_func) { 71 case PF_GPIO2: 72 pad_func_value = 0; 73 break; 74 case PF_UART1: 75 pad_func_value = 1; 76 break; 77 case PF_SPI1: 78 pad_func_value = 3; 79 break; 80 case PF_I2C0: 81 pad_func_value = 4; 82 break; 83 default: 84 config_state = Config_Fail; 85 break; 86 } 87 break; 88 case PAD3: 89 switch (pad_func) { 90 case PF_GPIO3: 91 pad_func_value = 0; 92 break; 93 case PF_UART1: 94 pad_func_value = 1; 95 break; 96 case PF_SPI1: 97 pad_func_value = 3; 98 break; 99 case PF_I2C0: 100 pad_func_value = 4; 101 break; 102 default: 103 config_state = Config_Fail; 104 break; 105 } 106 break; 107 case PAD4: 108 switch (pad_func) { 109 case PF_SWD: 110 pad_func_value = 0; 111 break; 112 case PF_GPIO4: 113 pad_func_value = 1; 114 break; 115 case PF_SDIO0: 116 pad_func_value = 2; 117 break; 118 case PF_UART0: 119 pad_func_value = 3; 120 break; 121 case PF_PWM0: 122 pad_func_value = 4; 123 break; 124 case PF_PSRAM: 125 pad_func_value = 7; 126 break; 127 default: 128 config_state = Config_Fail; 129 break; 130 } 131 break; 132 case PAD5: 133 switch (pad_func) { 134 case PF_SWD: 135 pad_func_value = 0; 136 break; 137 case PF_GPIO5: 138 pad_func_value = 1; 139 break; 140 case PF_SDIO0: 141 pad_func_value = 2; 142 break; 143 case PF_UART0: 144 pad_func_value = 3; 145 break; 146 case PF_PWM2: 147 pad_func_value = 4; 148 break; 149 case PF_PSRAM: 150 pad_func_value = 7; 151 break; 152 default: 153 config_state = Config_Fail; 154 break; 155 } 156 break; 157 case PAD6: 158 switch (pad_func) { 159 case PF_GPIO6: 160 pad_func_value = 0; 161 break; 162 case PF_SPI0: 163 pad_func_value = 1; 164 break; 165 case PF_SDIO0: 166 pad_func_value = 2; 167 break; 168 case PF_UART0: 169 pad_func_value = 3; 170 break; 171 case PF_PWM4: 172 pad_func_value = 4; 173 break; 174 case PF_PSRAM: 175 pad_func_value = 7; 176 break; 177 default: 178 config_state = Config_Fail; 179 break; 180 } 181 break; 182 case PAD7: 183 switch (pad_func) { 184 case PF_GPIO7: 185 pad_func_value = 0; 186 break; 187 case PF_SPI0: 188 pad_func_value = 1; 189 break; 190 case PF_SDIO0: 191 pad_func_value = 2; 192 break; 193 case PF_UART0: 194 pad_func_value = 3; 195 break; 196 case PF_PWM6: 197 pad_func_value = 4; 198 break; 199 case PF_I2S: 200 pad_func_value = 6; 201 break; 202 case PF_PSRAM: 203 pad_func_value = 7; 204 break; 205 default: 206 config_state = Config_Fail; 207 break; 208 } 209 break; 210 case PAD8: 211 switch (pad_func) { 212 case PF_GPIO8: 213 pad_func_value = 0; 214 break; 215 case PF_SPI0: 216 pad_func_value = 1; 217 break; 218 case PF_SDIO0: 219 pad_func_value = 2; 220 break; 221 case PF_I2C1: 222 pad_func_value = 3; 223 break; 224 case PF_UART1: 225 pad_func_value = 4; 226 break; 227 case PF_I2S: 228 pad_func_value = 6; 229 break; 230 case PF_PSRAM: 231 pad_func_value = 7; 232 break; 233 default: 234 config_state = Config_Fail; 235 break; 236 } 237 break; 238 case PAD9: 239 switch (pad_func) { 240 case PF_GPIO9: 241 pad_func_value = 0; 242 break; 243 case PF_SPI0: 244 pad_func_value = 1; 245 break; 246 case PF_SDIO0: 247 pad_func_value = 2; 248 break; 249 case PF_I2C1: 250 pad_func_value = 3; 251 break; 252 case PF_UART1: 253 pad_func_value = 4; 254 break; 255 case PF_I2S: 256 pad_func_value = 6; 257 break; 258 case PF_PSRAM: 259 pad_func_value = 7; 260 break; 261 default: 262 config_state = Config_Fail; 263 break; 264 } 265 break; 266 case PAD10: 267 switch (pad_func) { 268 269 case PF_PWM1: 270 pad_func_value = 1; 271 break; 272 case PF_GPIO10: 273 pad_func_value = 2; 274 break; 275 case PF_UART2: 276 pad_func_value = 3; 277 break; 278 case PF_SPI2: 279 pad_func_value = 4; 280 break; 281 case PF_I2S: 282 pad_func_value = 6; 283 break; 284 default: 285 config_state = Config_Fail; 286 break; 287 } 288 break; 289 case PAD11: 290 switch (pad_func) { 291 case PF_GPIO11: 292 pad_func_value = 0; 293 break; 294 case PF_PWM3: 295 pad_func_value = 1; 296 break; 297 case PF_SDIO0: 298 pad_func_value = 2; 299 break; 300 case PF_UART2: 301 pad_func_value = 3; 302 break; 303 case PF_SPI2: 304 pad_func_value = 4; 305 break; 306 case PF_I2S: 307 pad_func_value = 6; 308 break; 309 default: 310 config_state = Config_Fail; 311 break; 312 } 313 break; 314 case PAD12: 315 switch (pad_func) { 316 case PF_GPIO12: 317 pad_func_value = 0; 318 break; 319 case PF_SPI2: 320 pad_func_value = 2; 321 break; 322 case PF_UART2: 323 pad_func_value = 3; 324 break; 325 case PF_I2S: 326 pad_func_value = 6; 327 break; 328 default: 329 config_state = Config_Fail; 330 break; 331 } 332 break; 333 case PAD13: 334 switch (pad_func) { 335 case PF_GPIO13: 336 pad_func_value = 0; 337 break; 338 case PF_SPI2: 339 pad_func_value = 2; 340 break; 341 case PF_UART2: 342 pad_func_value = 3; 343 break; 344 default: 345 config_state = Config_Fail; 346 break; 347 } 348 break; 349 case PAD14: 350 switch (pad_func) { 351 case PF_PWM0: 352 pad_func_value = 1; 353 break; 354 case PF_SPI2: 355 pad_func_value = 2; 356 break; 357 case PF_UART1: 358 pad_func_value = 3; 359 break; 360 case PF_GPIO14: 361 pad_func_value = 4; 362 break; 363 default: 364 config_state = Config_Fail; 365 break; 366 } 367 break; 368 case PAD15: 369 switch (pad_func) { 370 case PF_PWM2: 371 pad_func_value = 1; 372 break; 373 case PF_SPI2: 374 pad_func_value = 2; 375 break; 376 case PF_UART1: 377 pad_func_value = 3; 378 break; 379 case PF_GPIO15: 380 pad_func_value = 4; 381 break; 382 default: 383 config_state = Config_Fail; 384 break; 385 } 386 break; 387 case PAD16: 388 switch (pad_func) { 389 case PF_GPIO16: 390 pad_func_value = 0; 391 break; 392 case PF_UART0: 393 pad_func_value = 1; 394 break; 395 case PF_SDIO0: 396 pad_func_value = 2; 397 break; 398 case PF_SPI1: 399 pad_func_value = 3; 400 break; 401 case PF_PSRAM: 402 pad_func_value = 6; 403 break; 404 default: 405 config_state = Config_Fail; 406 break; 407 } 408 break; 409 case PAD17: 410 switch (pad_func) { 411 case PF_GPIO17: 412 pad_func_value = 0; 413 break; 414 case PF_UART0: 415 pad_func_value = 1; 416 break; 417 case PF_SDIO0: 418 pad_func_value = 2; 419 break; 420 case PF_SPI1: 421 pad_func_value = 3; 422 break; 423 case PF_PSRAM: 424 pad_func_value = 6; 425 break; 426 default: 427 config_state = Config_Fail; 428 break; 429 } 430 break; 431 case PAD18: 432 switch (pad_func) { 433 case PF_GPIO18: 434 pad_func_value = 0; 435 break; 436 case PF_UART1: 437 pad_func_value = 1; 438 break; 439 case PF_SDIO0: 440 pad_func_value = 2; 441 break; 442 case PF_SPI1: 443 pad_func_value = 3; 444 break; 445 case PF_PSRAM: 446 pad_func_value = 6; 447 break; 448 default: 449 config_state = Config_Fail; 450 break; 451 } 452 break; 453 case PAD19: 454 switch (pad_func) { 455 case PF_GPIO19: 456 pad_func_value = 0; 457 break; 458 case PF_UART1: 459 pad_func_value = 1; 460 break; 461 case PF_SDIO0: 462 pad_func_value = 2; 463 break; 464 case PF_SPI1: 465 pad_func_value = 3; 466 break; 467 case PF_PSRAM: 468 pad_func_value = 6; 469 break; 470 default: 471 config_state = Config_Fail; 472 break; 473 } 474 break; 475 case PAD20: 476 switch (pad_func) { 477 case PF_GPIO20: 478 pad_func_value = 0; 479 break; 480 case PF_I2C0: 481 pad_func_value = 1; 482 break; 483 case PF_SDIO0: 484 pad_func_value = 2; 485 break; 486 case PF_UART0: 487 pad_func_value = 3; 488 break; 489 case PF_PSRAM: 490 pad_func_value = 6; 491 break; 492 default: 493 config_state = Config_Fail; 494 break; 495 } 496 break; 497 case PAD21: 498 switch (pad_func) { 499 case PF_GPIO21: 500 pad_func_value = 0; 501 break; 502 case PF_I2C0: 503 pad_func_value = 1; 504 break; 505 case PF_SDIO0: 506 pad_func_value = 2; 507 break; 508 case PF_UART0: 509 pad_func_value = 3; 510 break; 511 case PF_PSRAM: 512 pad_func_value = 6; 513 break; 514 default: 515 config_state = Config_Fail; 516 break; 517 } 518 break; 519 case PAD22: 520 switch (pad_func) { 521 case PF_GPIO22: 522 pad_func_value = 0; 523 break; 524 case PF_I2C1: 525 pad_func_value = 1; 526 break; 527 case PF_SDIO0: 528 pad_func_value = 2; 529 break; 530 case PF_UART2: 531 pad_func_value = 3; 532 break; 533 case PF_PSRAM: 534 pad_func_value = 6; 535 break; 536 default: 537 config_state = Config_Fail; 538 break; 539 } 540 break; 541 case PAD23: 542 switch (pad_func) { 543 case PF_GPIO23: 544 pad_func_value = 0; 545 break; 546 case PF_I2C1: 547 pad_func_value = 1; 548 break; 549 case PF_UART2: 550 pad_func_value = 3; 551 break; 552 default: 553 config_state = Config_Fail; 554 break; 555 } 556 break; 557 default: 558 config_state = Config_Fail; 559 break; 560 } 561 562 *(volatile uint32_t *)(pad_reg_addr) &= ~(0xf << reg_offset); // mask 563 *(volatile uint32_t *)(pad_reg_addr) |= (pad_func_value << reg_offset); // set pinmux value 564 return config_state; 565 } 566 duet_pad_config(Pad_Num_Type pad_num,Pad_Pull_Type pull_type)567void duet_pad_config(Pad_Num_Type pad_num, Pad_Pull_Type pull_type) 568 { 569 /* assert params */ 570 // to-do 571 switch (pull_type) { 572 case PULL_UP: 573 *(volatile uint32_t *)(HW_CTRL_PE_PS) &= ~(0x1 << (pad_num)); 574 *(volatile uint32_t *)(PAD_PE_REG) |= (0x1 << (pad_num)); 575 *(volatile uint32_t *)(PAD_PS_REG) |= (0x1 << (pad_num)); 576 break; 577 case PULL_DOWN: 578 *(volatile uint32_t *)(HW_CTRL_PE_PS) &= ~(0x1 << (pad_num)); 579 *(volatile uint32_t *)(PAD_PE_REG) |= (0x1 << (pad_num)); 580 *(volatile uint32_t *)(PAD_PS_REG) &= ~(0x1 << (pad_num)); 581 break; 582 case PULL_NONE: 583 *(volatile uint32_t *)(HW_CTRL_PE_PS) &= ~(0x1 << (pad_num)); 584 *(volatile uint32_t *)(PAD_PE_REG) &= ~(0x1 << (pad_num)); 585 break; 586 default: 587 break; 588 } 589 } 590 591