1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 1999 - 2010 Intel Corporation.
4 * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD.
5 *
6 * This code was derived from the Intel e1000e Linux driver.
7 */
8
9 #include "pch_gbe.h"
10 #include "pch_gbe_phy.h"
11 #include <linux/module.h>
12 #include <linux/net_tstamp.h>
13 #include <linux/ptp_classify.h>
14 #include <linux/gpio.h>
15
16 #define DRV_VERSION "1.01"
17 const char pch_driver_version[] = DRV_VERSION;
18
19 #define PCH_GBE_MAR_ENTRIES 16
20 #define PCH_GBE_SHORT_PKT 64
21 #define DSC_INIT16 0xC000
22 #define PCH_GBE_DMA_ALIGN 0
23 #define PCH_GBE_DMA_PADDING 2
24 #define PCH_GBE_WATCHDOG_PERIOD (5 * HZ) /* watchdog time */
25 #define PCH_GBE_PCI_BAR 1
26 #define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */
27
28 #define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802
29
30 #define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
31 #define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802
32
33 #define PCH_GBE_TX_WEIGHT 64
34 #define PCH_GBE_RX_WEIGHT 64
35 #define PCH_GBE_RX_BUFFER_WRITE 16
36
37 /* Initialize the wake-on-LAN settings */
38 #define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP)
39
40 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
41 PCH_GBE_CHIP_TYPE_INTERNAL | \
42 PCH_GBE_RGMII_MODE_RGMII \
43 )
44
45 /* Ethertype field values */
46 #define PCH_GBE_MAX_RX_BUFFER_SIZE 0x2880
47 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318
48 #define PCH_GBE_FRAME_SIZE_2048 2048
49 #define PCH_GBE_FRAME_SIZE_4096 4096
50 #define PCH_GBE_FRAME_SIZE_8192 8192
51
52 #define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
53 #define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
54 #define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
55 #define PCH_GBE_DESC_UNUSED(R) \
56 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
57 (R)->next_to_clean - (R)->next_to_use - 1)
58
59 /* Pause packet value */
60 #define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001
61 #define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100
62 #define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888
63 #define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF
64
65
66 /* This defines the bits that are set in the Interrupt Mask
67 * Set/Read Register. Each bit is documented below:
68 * o RXT0 = Receiver Timer Interrupt (ring 0)
69 * o TXDW = Transmit Descriptor Written Back
70 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
71 * o RXSEQ = Receive Sequence Error
72 * o LSC = Link Status Change
73 */
74 #define PCH_GBE_INT_ENABLE_MASK ( \
75 PCH_GBE_INT_RX_DMA_CMPLT | \
76 PCH_GBE_INT_RX_DSC_EMP | \
77 PCH_GBE_INT_RX_FIFO_ERR | \
78 PCH_GBE_INT_WOL_DET | \
79 PCH_GBE_INT_TX_CMPLT \
80 )
81
82 #define PCH_GBE_INT_DISABLE_ALL 0
83
84 /* Macros for ieee1588 */
85 /* 0x40 Time Synchronization Channel Control Register Bits */
86 #define MASTER_MODE (1<<0)
87 #define SLAVE_MODE (0)
88 #define V2_MODE (1<<31)
89 #define CAP_MODE0 (0)
90 #define CAP_MODE2 (1<<17)
91
92 /* 0x44 Time Synchronization Channel Event Register Bits */
93 #define TX_SNAPSHOT_LOCKED (1<<0)
94 #define RX_SNAPSHOT_LOCKED (1<<1)
95
96 #define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81"
97 #define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00"
98
99 #define MINNOW_PHY_RESET_GPIO 13
100
101 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
102 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
103 int data);
104 static void pch_gbe_set_multi(struct net_device *netdev);
105
pch_ptp_match(struct sk_buff * skb,u16 uid_hi,u32 uid_lo,u16 seqid)106 static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
107 {
108 u8 *data = skb->data;
109 unsigned int offset;
110 u16 hi, id;
111 u32 lo;
112
113 if (ptp_classify_raw(skb) == PTP_CLASS_NONE)
114 return 0;
115
116 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
117
118 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
119 return 0;
120
121 hi = get_unaligned_be16(data + offset + OFF_PTP_SOURCE_UUID + 0);
122 lo = get_unaligned_be32(data + offset + OFF_PTP_SOURCE_UUID + 2);
123 id = get_unaligned_be16(data + offset + OFF_PTP_SEQUENCE_ID);
124
125 return (uid_hi == hi && uid_lo == lo && seqid == id);
126 }
127
128 static void
pch_rx_timestamp(struct pch_gbe_adapter * adapter,struct sk_buff * skb)129 pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
130 {
131 struct skb_shared_hwtstamps *shhwtstamps;
132 struct pci_dev *pdev;
133 u64 ns;
134 u32 hi, lo, val;
135
136 if (!adapter->hwts_rx_en)
137 return;
138
139 /* Get ieee1588's dev information */
140 pdev = adapter->ptp_pdev;
141
142 val = pch_ch_event_read(pdev);
143
144 if (!(val & RX_SNAPSHOT_LOCKED))
145 return;
146
147 lo = pch_src_uuid_lo_read(pdev);
148 hi = pch_src_uuid_hi_read(pdev);
149
150 if (!pch_ptp_match(skb, hi, lo, hi >> 16))
151 goto out;
152
153 ns = pch_rx_snap_read(pdev);
154
155 shhwtstamps = skb_hwtstamps(skb);
156 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
157 shhwtstamps->hwtstamp = ns_to_ktime(ns);
158 out:
159 pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED);
160 }
161
162 static void
pch_tx_timestamp(struct pch_gbe_adapter * adapter,struct sk_buff * skb)163 pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
164 {
165 struct skb_shared_hwtstamps shhwtstamps;
166 struct pci_dev *pdev;
167 struct skb_shared_info *shtx;
168 u64 ns;
169 u32 cnt, val;
170
171 shtx = skb_shinfo(skb);
172 if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en)))
173 return;
174
175 shtx->tx_flags |= SKBTX_IN_PROGRESS;
176
177 /* Get ieee1588's dev information */
178 pdev = adapter->ptp_pdev;
179
180 /*
181 * This really stinks, but we have to poll for the Tx time stamp.
182 */
183 for (cnt = 0; cnt < 100; cnt++) {
184 val = pch_ch_event_read(pdev);
185 if (val & TX_SNAPSHOT_LOCKED)
186 break;
187 udelay(1);
188 }
189 if (!(val & TX_SNAPSHOT_LOCKED)) {
190 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
191 return;
192 }
193
194 ns = pch_tx_snap_read(pdev);
195
196 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
197 shhwtstamps.hwtstamp = ns_to_ktime(ns);
198 skb_tstamp_tx(skb, &shhwtstamps);
199
200 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED);
201 }
202
hwtstamp_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)203 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
204 {
205 struct hwtstamp_config cfg;
206 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
207 struct pci_dev *pdev;
208 u8 station[20];
209
210 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
211 return -EFAULT;
212
213 if (cfg.flags) /* reserved for future extensions */
214 return -EINVAL;
215
216 /* Get ieee1588's dev information */
217 pdev = adapter->ptp_pdev;
218
219 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
220 return -ERANGE;
221
222 switch (cfg.rx_filter) {
223 case HWTSTAMP_FILTER_NONE:
224 adapter->hwts_rx_en = 0;
225 break;
226 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
227 adapter->hwts_rx_en = 0;
228 pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0);
229 break;
230 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
231 adapter->hwts_rx_en = 1;
232 pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0);
233 break;
234 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
235 adapter->hwts_rx_en = 1;
236 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
237 strcpy(station, PTP_L4_MULTICAST_SA);
238 pch_set_station_address(station, pdev);
239 break;
240 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
241 adapter->hwts_rx_en = 1;
242 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
243 strcpy(station, PTP_L2_MULTICAST_SA);
244 pch_set_station_address(station, pdev);
245 break;
246 default:
247 return -ERANGE;
248 }
249
250 adapter->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
251
252 /* Clear out any old time stamps. */
253 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED);
254
255 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
256 }
257
pch_gbe_mac_load_mac_addr(struct pch_gbe_hw * hw)258 static inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
259 {
260 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
261 }
262
263 /**
264 * pch_gbe_mac_read_mac_addr - Read MAC address
265 * @hw: Pointer to the HW structure
266 * Returns:
267 * 0: Successful.
268 */
pch_gbe_mac_read_mac_addr(struct pch_gbe_hw * hw)269 static s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
270 {
271 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
272 u32 adr1a, adr1b;
273
274 adr1a = ioread32(&hw->reg->mac_adr[0].high);
275 adr1b = ioread32(&hw->reg->mac_adr[0].low);
276
277 hw->mac.addr[0] = (u8)(adr1a & 0xFF);
278 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
279 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
280 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
281 hw->mac.addr[4] = (u8)(adr1b & 0xFF);
282 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
283
284 netdev_dbg(adapter->netdev, "hw->mac.addr : %pM\n", hw->mac.addr);
285 return 0;
286 }
287
288 /**
289 * pch_gbe_wait_clr_bit - Wait to clear a bit
290 * @reg: Pointer of register
291 * @bit: Busy bit
292 */
pch_gbe_wait_clr_bit(void * reg,u32 bit)293 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
294 {
295 u32 tmp;
296
297 /* wait busy */
298 tmp = 1000;
299 while ((ioread32(reg) & bit) && --tmp)
300 cpu_relax();
301 if (!tmp)
302 pr_err("Error: busy bit is not cleared\n");
303 }
304
305 /**
306 * pch_gbe_mac_mar_set - Set MAC address register
307 * @hw: Pointer to the HW structure
308 * @addr: Pointer to the MAC address
309 * @index: MAC address array register
310 */
pch_gbe_mac_mar_set(struct pch_gbe_hw * hw,u8 * addr,u32 index)311 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
312 {
313 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
314 u32 mar_low, mar_high, adrmask;
315
316 netdev_dbg(adapter->netdev, "index : 0x%x\n", index);
317
318 /*
319 * HW expects these in little endian so we reverse the byte order
320 * from network order (big endian) to little endian
321 */
322 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
323 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
324 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
325 /* Stop the MAC Address of index. */
326 adrmask = ioread32(&hw->reg->ADDR_MASK);
327 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
328 /* wait busy */
329 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
330 /* Set the MAC address to the MAC address 1A/1B register */
331 iowrite32(mar_high, &hw->reg->mac_adr[index].high);
332 iowrite32(mar_low, &hw->reg->mac_adr[index].low);
333 /* Start the MAC address of index */
334 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
335 /* wait busy */
336 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
337 }
338
339 /**
340 * pch_gbe_mac_reset_hw - Reset hardware
341 * @hw: Pointer to the HW structure
342 */
pch_gbe_mac_reset_hw(struct pch_gbe_hw * hw)343 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
344 {
345 /* Read the MAC address. and store to the private data */
346 pch_gbe_mac_read_mac_addr(hw);
347 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
348 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
349 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
350 /* Setup the receive addresses */
351 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
352 return;
353 }
354
pch_gbe_disable_mac_rx(struct pch_gbe_hw * hw)355 static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw)
356 {
357 u32 rctl;
358 /* Disables Receive MAC */
359 rctl = ioread32(&hw->reg->MAC_RX_EN);
360 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
361 }
362
pch_gbe_enable_mac_rx(struct pch_gbe_hw * hw)363 static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw)
364 {
365 u32 rctl;
366 /* Enables Receive MAC */
367 rctl = ioread32(&hw->reg->MAC_RX_EN);
368 iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
369 }
370
371 /**
372 * pch_gbe_mac_init_rx_addrs - Initialize receive address's
373 * @hw: Pointer to the HW structure
374 * @mar_count: Receive address registers
375 */
pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw * hw,u16 mar_count)376 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
377 {
378 u32 i;
379
380 /* Setup the receive address */
381 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
382
383 /* Zero out the other receive addresses */
384 for (i = 1; i < mar_count; i++) {
385 iowrite32(0, &hw->reg->mac_adr[i].high);
386 iowrite32(0, &hw->reg->mac_adr[i].low);
387 }
388 iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
389 /* wait busy */
390 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
391 }
392
393 /**
394 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
395 * @hw: Pointer to the HW structure
396 * Returns:
397 * 0: Successful.
398 * Negative value: Failed.
399 */
pch_gbe_mac_force_mac_fc(struct pch_gbe_hw * hw)400 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
401 {
402 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
403 struct pch_gbe_mac_info *mac = &hw->mac;
404 u32 rx_fctrl;
405
406 netdev_dbg(adapter->netdev, "mac->fc = %u\n", mac->fc);
407
408 rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
409
410 switch (mac->fc) {
411 case PCH_GBE_FC_NONE:
412 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
413 mac->tx_fc_enable = false;
414 break;
415 case PCH_GBE_FC_RX_PAUSE:
416 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
417 mac->tx_fc_enable = false;
418 break;
419 case PCH_GBE_FC_TX_PAUSE:
420 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
421 mac->tx_fc_enable = true;
422 break;
423 case PCH_GBE_FC_FULL:
424 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
425 mac->tx_fc_enable = true;
426 break;
427 default:
428 netdev_err(adapter->netdev,
429 "Flow control param set incorrectly\n");
430 return -EINVAL;
431 }
432 if (mac->link_duplex == DUPLEX_HALF)
433 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
434 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
435 netdev_dbg(adapter->netdev,
436 "RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n",
437 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
438 return 0;
439 }
440
441 /**
442 * pch_gbe_mac_set_wol_event - Set wake-on-lan event
443 * @hw: Pointer to the HW structure
444 * @wu_evt: Wake up event
445 */
pch_gbe_mac_set_wol_event(struct pch_gbe_hw * hw,u32 wu_evt)446 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
447 {
448 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
449 u32 addr_mask;
450
451 netdev_dbg(adapter->netdev, "wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n",
452 wu_evt, ioread32(&hw->reg->ADDR_MASK));
453
454 if (wu_evt) {
455 /* Set Wake-On-Lan address mask */
456 addr_mask = ioread32(&hw->reg->ADDR_MASK);
457 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
458 /* wait busy */
459 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
460 iowrite32(0, &hw->reg->WOL_ST);
461 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
462 iowrite32(0x02, &hw->reg->TCPIP_ACC);
463 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
464 } else {
465 iowrite32(0, &hw->reg->WOL_CTRL);
466 iowrite32(0, &hw->reg->WOL_ST);
467 }
468 return;
469 }
470
471 /**
472 * pch_gbe_mac_ctrl_miim - Control MIIM interface
473 * @hw: Pointer to the HW structure
474 * @addr: Address of PHY
475 * @dir: Operetion. (Write or Read)
476 * @reg: Access register of PHY
477 * @data: Write data.
478 *
479 * Returns: Read date.
480 */
pch_gbe_mac_ctrl_miim(struct pch_gbe_hw * hw,u32 addr,u32 dir,u32 reg,u16 data)481 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
482 u16 data)
483 {
484 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
485 u32 data_out = 0;
486 unsigned int i;
487 unsigned long flags;
488
489 spin_lock_irqsave(&hw->miim_lock, flags);
490
491 for (i = 100; i; --i) {
492 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
493 break;
494 udelay(20);
495 }
496 if (i == 0) {
497 netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n");
498 spin_unlock_irqrestore(&hw->miim_lock, flags);
499 return 0; /* No way to indicate timeout error */
500 }
501 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
502 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
503 dir | data), &hw->reg->MIIM);
504 for (i = 0; i < 100; i++) {
505 udelay(20);
506 data_out = ioread32(&hw->reg->MIIM);
507 if ((data_out & PCH_GBE_MIIM_OPER_READY))
508 break;
509 }
510 spin_unlock_irqrestore(&hw->miim_lock, flags);
511
512 netdev_dbg(adapter->netdev, "PHY %s: reg=%d, data=0x%04X\n",
513 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
514 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
515 return (u16) data_out;
516 }
517
518 /**
519 * pch_gbe_mac_set_pause_packet - Set pause packet
520 * @hw: Pointer to the HW structure
521 */
pch_gbe_mac_set_pause_packet(struct pch_gbe_hw * hw)522 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
523 {
524 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
525 unsigned long tmp2, tmp3;
526
527 /* Set Pause packet */
528 tmp2 = hw->mac.addr[1];
529 tmp2 = (tmp2 << 8) | hw->mac.addr[0];
530 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
531
532 tmp3 = hw->mac.addr[5];
533 tmp3 = (tmp3 << 8) | hw->mac.addr[4];
534 tmp3 = (tmp3 << 8) | hw->mac.addr[3];
535 tmp3 = (tmp3 << 8) | hw->mac.addr[2];
536
537 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
538 iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
539 iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
540 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
541 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
542
543 /* Transmit Pause Packet */
544 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
545
546 netdev_dbg(adapter->netdev,
547 "PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
548 ioread32(&hw->reg->PAUSE_PKT1),
549 ioread32(&hw->reg->PAUSE_PKT2),
550 ioread32(&hw->reg->PAUSE_PKT3),
551 ioread32(&hw->reg->PAUSE_PKT4),
552 ioread32(&hw->reg->PAUSE_PKT5));
553
554 return;
555 }
556
557
558 /**
559 * pch_gbe_alloc_queues - Allocate memory for all rings
560 * @adapter: Board private structure to initialize
561 * Returns:
562 * 0: Successfully
563 * Negative value: Failed
564 */
pch_gbe_alloc_queues(struct pch_gbe_adapter * adapter)565 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
566 {
567 adapter->tx_ring = devm_kzalloc(&adapter->pdev->dev,
568 sizeof(*adapter->tx_ring), GFP_KERNEL);
569 if (!adapter->tx_ring)
570 return -ENOMEM;
571
572 adapter->rx_ring = devm_kzalloc(&adapter->pdev->dev,
573 sizeof(*adapter->rx_ring), GFP_KERNEL);
574 if (!adapter->rx_ring)
575 return -ENOMEM;
576 return 0;
577 }
578
579 /**
580 * pch_gbe_init_stats - Initialize status
581 * @adapter: Board private structure to initialize
582 */
pch_gbe_init_stats(struct pch_gbe_adapter * adapter)583 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
584 {
585 memset(&adapter->stats, 0, sizeof(adapter->stats));
586 return;
587 }
588
589 /**
590 * pch_gbe_init_phy - Initialize PHY
591 * @adapter: Board private structure to initialize
592 * Returns:
593 * 0: Successfully
594 * Negative value: Failed
595 */
pch_gbe_init_phy(struct pch_gbe_adapter * adapter)596 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
597 {
598 struct net_device *netdev = adapter->netdev;
599 u32 addr;
600 u16 bmcr, stat;
601
602 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
603 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
604 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
605 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
606 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
607 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
608 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
609 break;
610 }
611 adapter->hw.phy.addr = adapter->mii.phy_id;
612 netdev_dbg(netdev, "phy_addr = %d\n", adapter->mii.phy_id);
613 if (addr == PCH_GBE_PHY_REGS_LEN)
614 return -EAGAIN;
615 /* Selected the phy and isolate the rest */
616 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
617 if (addr != adapter->mii.phy_id) {
618 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
619 BMCR_ISOLATE);
620 } else {
621 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
622 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
623 bmcr & ~BMCR_ISOLATE);
624 }
625 }
626
627 /* MII setup */
628 adapter->mii.phy_id_mask = 0x1F;
629 adapter->mii.reg_num_mask = 0x1F;
630 adapter->mii.dev = adapter->netdev;
631 adapter->mii.mdio_read = pch_gbe_mdio_read;
632 adapter->mii.mdio_write = pch_gbe_mdio_write;
633 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
634 return 0;
635 }
636
637 /**
638 * pch_gbe_mdio_read - The read function for mii
639 * @netdev: Network interface device structure
640 * @addr: Phy ID
641 * @reg: Access location
642 * Returns:
643 * 0: Successfully
644 * Negative value: Failed
645 */
pch_gbe_mdio_read(struct net_device * netdev,int addr,int reg)646 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
647 {
648 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
649 struct pch_gbe_hw *hw = &adapter->hw;
650
651 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
652 (u16) 0);
653 }
654
655 /**
656 * pch_gbe_mdio_write - The write function for mii
657 * @netdev: Network interface device structure
658 * @addr: Phy ID (not used)
659 * @reg: Access location
660 * @data: Write data
661 */
pch_gbe_mdio_write(struct net_device * netdev,int addr,int reg,int data)662 static void pch_gbe_mdio_write(struct net_device *netdev,
663 int addr, int reg, int data)
664 {
665 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
666 struct pch_gbe_hw *hw = &adapter->hw;
667
668 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
669 }
670
671 /**
672 * pch_gbe_reset_task - Reset processing at the time of transmission timeout
673 * @work: Pointer of board private structure
674 */
pch_gbe_reset_task(struct work_struct * work)675 static void pch_gbe_reset_task(struct work_struct *work)
676 {
677 struct pch_gbe_adapter *adapter;
678 adapter = container_of(work, struct pch_gbe_adapter, reset_task);
679
680 rtnl_lock();
681 pch_gbe_reinit_locked(adapter);
682 rtnl_unlock();
683 }
684
685 /**
686 * pch_gbe_reinit_locked- Re-initialization
687 * @adapter: Board private structure
688 */
pch_gbe_reinit_locked(struct pch_gbe_adapter * adapter)689 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
690 {
691 pch_gbe_down(adapter);
692 pch_gbe_up(adapter);
693 }
694
695 /**
696 * pch_gbe_reset - Reset GbE
697 * @adapter: Board private structure
698 */
pch_gbe_reset(struct pch_gbe_adapter * adapter)699 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
700 {
701 struct net_device *netdev = adapter->netdev;
702 struct pch_gbe_hw *hw = &adapter->hw;
703 s32 ret_val;
704
705 pch_gbe_mac_reset_hw(hw);
706 /* reprogram multicast address register after reset */
707 pch_gbe_set_multi(netdev);
708 /* Setup the receive address. */
709 pch_gbe_mac_init_rx_addrs(hw, PCH_GBE_MAR_ENTRIES);
710
711 ret_val = pch_gbe_phy_get_id(hw);
712 if (ret_val) {
713 netdev_err(adapter->netdev, "pch_gbe_phy_get_id error\n");
714 return;
715 }
716 pch_gbe_phy_init_setting(hw);
717 /* Setup Mac interface option RGMII */
718 pch_gbe_phy_set_rgmii(hw);
719 }
720
721 /**
722 * pch_gbe_free_irq - Free an interrupt
723 * @adapter: Board private structure
724 */
pch_gbe_free_irq(struct pch_gbe_adapter * adapter)725 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
726 {
727 struct net_device *netdev = adapter->netdev;
728
729 free_irq(adapter->irq, netdev);
730 pci_free_irq_vectors(adapter->pdev);
731 }
732
733 /**
734 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
735 * @adapter: Board private structure
736 */
pch_gbe_irq_disable(struct pch_gbe_adapter * adapter)737 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
738 {
739 struct pch_gbe_hw *hw = &adapter->hw;
740
741 atomic_inc(&adapter->irq_sem);
742 iowrite32(0, &hw->reg->INT_EN);
743 ioread32(&hw->reg->INT_ST);
744 synchronize_irq(adapter->irq);
745
746 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
747 ioread32(&hw->reg->INT_EN));
748 }
749
750 /**
751 * pch_gbe_irq_enable - Enable default interrupt generation settings
752 * @adapter: Board private structure
753 */
pch_gbe_irq_enable(struct pch_gbe_adapter * adapter)754 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
755 {
756 struct pch_gbe_hw *hw = &adapter->hw;
757
758 if (likely(atomic_dec_and_test(&adapter->irq_sem)))
759 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
760 ioread32(&hw->reg->INT_ST);
761 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
762 ioread32(&hw->reg->INT_EN));
763 }
764
765
766
767 /**
768 * pch_gbe_setup_tctl - configure the Transmit control registers
769 * @adapter: Board private structure
770 */
pch_gbe_setup_tctl(struct pch_gbe_adapter * adapter)771 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
772 {
773 struct pch_gbe_hw *hw = &adapter->hw;
774 u32 tx_mode, tcpip;
775
776 tx_mode = PCH_GBE_TM_LONG_PKT |
777 PCH_GBE_TM_ST_AND_FD |
778 PCH_GBE_TM_SHORT_PKT |
779 PCH_GBE_TM_TH_TX_STRT_8 |
780 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
781
782 iowrite32(tx_mode, &hw->reg->TX_MODE);
783
784 tcpip = ioread32(&hw->reg->TCPIP_ACC);
785 tcpip |= PCH_GBE_TX_TCPIPACC_EN;
786 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
787 return;
788 }
789
790 /**
791 * pch_gbe_configure_tx - Configure Transmit Unit after Reset
792 * @adapter: Board private structure
793 */
pch_gbe_configure_tx(struct pch_gbe_adapter * adapter)794 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
795 {
796 struct pch_gbe_hw *hw = &adapter->hw;
797 u32 tdba, tdlen, dctrl;
798
799 netdev_dbg(adapter->netdev, "dma addr = 0x%08llx size = 0x%08x\n",
800 (unsigned long long)adapter->tx_ring->dma,
801 adapter->tx_ring->size);
802
803 /* Setup the HW Tx Head and Tail descriptor pointers */
804 tdba = adapter->tx_ring->dma;
805 tdlen = adapter->tx_ring->size - 0x10;
806 iowrite32(tdba, &hw->reg->TX_DSC_BASE);
807 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
808 iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
809
810 /* Enables Transmission DMA */
811 dctrl = ioread32(&hw->reg->DMA_CTRL);
812 dctrl |= PCH_GBE_TX_DMA_EN;
813 iowrite32(dctrl, &hw->reg->DMA_CTRL);
814 }
815
816 /**
817 * pch_gbe_setup_rctl - Configure the receive control registers
818 * @adapter: Board private structure
819 */
pch_gbe_setup_rctl(struct pch_gbe_adapter * adapter)820 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
821 {
822 struct pch_gbe_hw *hw = &adapter->hw;
823 u32 rx_mode, tcpip;
824
825 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
826 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
827
828 iowrite32(rx_mode, &hw->reg->RX_MODE);
829
830 tcpip = ioread32(&hw->reg->TCPIP_ACC);
831
832 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
833 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
834 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
835 return;
836 }
837
838 /**
839 * pch_gbe_configure_rx - Configure Receive Unit after Reset
840 * @adapter: Board private structure
841 */
pch_gbe_configure_rx(struct pch_gbe_adapter * adapter)842 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
843 {
844 struct pch_gbe_hw *hw = &adapter->hw;
845 u32 rdba, rdlen, rxdma;
846
847 netdev_dbg(adapter->netdev, "dma adr = 0x%08llx size = 0x%08x\n",
848 (unsigned long long)adapter->rx_ring->dma,
849 adapter->rx_ring->size);
850
851 pch_gbe_mac_force_mac_fc(hw);
852
853 pch_gbe_disable_mac_rx(hw);
854
855 /* Disables Receive DMA */
856 rxdma = ioread32(&hw->reg->DMA_CTRL);
857 rxdma &= ~PCH_GBE_RX_DMA_EN;
858 iowrite32(rxdma, &hw->reg->DMA_CTRL);
859
860 netdev_dbg(adapter->netdev,
861 "MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n",
862 ioread32(&hw->reg->MAC_RX_EN),
863 ioread32(&hw->reg->DMA_CTRL));
864
865 /* Setup the HW Rx Head and Tail Descriptor Pointers and
866 * the Base and Length of the Rx Descriptor Ring */
867 rdba = adapter->rx_ring->dma;
868 rdlen = adapter->rx_ring->size - 0x10;
869 iowrite32(rdba, &hw->reg->RX_DSC_BASE);
870 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
871 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
872 }
873
874 /**
875 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
876 * @adapter: Board private structure
877 * @buffer_info: Buffer information structure
878 */
pch_gbe_unmap_and_free_tx_resource(struct pch_gbe_adapter * adapter,struct pch_gbe_buffer * buffer_info)879 static void pch_gbe_unmap_and_free_tx_resource(
880 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
881 {
882 if (buffer_info->mapped) {
883 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
884 buffer_info->length, DMA_TO_DEVICE);
885 buffer_info->mapped = false;
886 }
887 if (buffer_info->skb) {
888 dev_kfree_skb_any(buffer_info->skb);
889 buffer_info->skb = NULL;
890 }
891 }
892
893 /**
894 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
895 * @adapter: Board private structure
896 * @buffer_info: Buffer information structure
897 */
pch_gbe_unmap_and_free_rx_resource(struct pch_gbe_adapter * adapter,struct pch_gbe_buffer * buffer_info)898 static void pch_gbe_unmap_and_free_rx_resource(
899 struct pch_gbe_adapter *adapter,
900 struct pch_gbe_buffer *buffer_info)
901 {
902 if (buffer_info->mapped) {
903 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
904 buffer_info->length, DMA_FROM_DEVICE);
905 buffer_info->mapped = false;
906 }
907 if (buffer_info->skb) {
908 dev_kfree_skb_any(buffer_info->skb);
909 buffer_info->skb = NULL;
910 }
911 }
912
913 /**
914 * pch_gbe_clean_tx_ring - Free Tx Buffers
915 * @adapter: Board private structure
916 * @tx_ring: Ring to be cleaned
917 */
pch_gbe_clean_tx_ring(struct pch_gbe_adapter * adapter,struct pch_gbe_tx_ring * tx_ring)918 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
919 struct pch_gbe_tx_ring *tx_ring)
920 {
921 struct pch_gbe_hw *hw = &adapter->hw;
922 struct pch_gbe_buffer *buffer_info;
923 unsigned long size;
924 unsigned int i;
925
926 /* Free all the Tx ring sk_buffs */
927 for (i = 0; i < tx_ring->count; i++) {
928 buffer_info = &tx_ring->buffer_info[i];
929 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
930 }
931 netdev_dbg(adapter->netdev,
932 "call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
933
934 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
935 memset(tx_ring->buffer_info, 0, size);
936
937 /* Zero out the descriptor ring */
938 memset(tx_ring->desc, 0, tx_ring->size);
939 tx_ring->next_to_use = 0;
940 tx_ring->next_to_clean = 0;
941 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
942 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
943 }
944
945 /**
946 * pch_gbe_clean_rx_ring - Free Rx Buffers
947 * @adapter: Board private structure
948 * @rx_ring: Ring to free buffers from
949 */
950 static void
pch_gbe_clean_rx_ring(struct pch_gbe_adapter * adapter,struct pch_gbe_rx_ring * rx_ring)951 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
952 struct pch_gbe_rx_ring *rx_ring)
953 {
954 struct pch_gbe_hw *hw = &adapter->hw;
955 struct pch_gbe_buffer *buffer_info;
956 unsigned long size;
957 unsigned int i;
958
959 /* Free all the Rx ring sk_buffs */
960 for (i = 0; i < rx_ring->count; i++) {
961 buffer_info = &rx_ring->buffer_info[i];
962 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
963 }
964 netdev_dbg(adapter->netdev,
965 "call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
966 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
967 memset(rx_ring->buffer_info, 0, size);
968
969 /* Zero out the descriptor ring */
970 memset(rx_ring->desc, 0, rx_ring->size);
971 rx_ring->next_to_clean = 0;
972 rx_ring->next_to_use = 0;
973 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
974 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
975 }
976
pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter * adapter,u16 speed,u16 duplex)977 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
978 u16 duplex)
979 {
980 struct pch_gbe_hw *hw = &adapter->hw;
981 unsigned long rgmii = 0;
982
983 /* Set the RGMII control. */
984 switch (speed) {
985 case SPEED_10:
986 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
987 PCH_GBE_MAC_RGMII_CTRL_SETTING);
988 break;
989 case SPEED_100:
990 rgmii = (PCH_GBE_RGMII_RATE_25M |
991 PCH_GBE_MAC_RGMII_CTRL_SETTING);
992 break;
993 case SPEED_1000:
994 rgmii = (PCH_GBE_RGMII_RATE_125M |
995 PCH_GBE_MAC_RGMII_CTRL_SETTING);
996 break;
997 }
998 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
999 }
pch_gbe_set_mode(struct pch_gbe_adapter * adapter,u16 speed,u16 duplex)1000 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
1001 u16 duplex)
1002 {
1003 struct net_device *netdev = adapter->netdev;
1004 struct pch_gbe_hw *hw = &adapter->hw;
1005 unsigned long mode = 0;
1006
1007 /* Set the communication mode */
1008 switch (speed) {
1009 case SPEED_10:
1010 mode = PCH_GBE_MODE_MII_ETHER;
1011 netdev->tx_queue_len = 10;
1012 break;
1013 case SPEED_100:
1014 mode = PCH_GBE_MODE_MII_ETHER;
1015 netdev->tx_queue_len = 100;
1016 break;
1017 case SPEED_1000:
1018 mode = PCH_GBE_MODE_GMII_ETHER;
1019 break;
1020 }
1021 if (duplex == DUPLEX_FULL)
1022 mode |= PCH_GBE_MODE_FULL_DUPLEX;
1023 else
1024 mode |= PCH_GBE_MODE_HALF_DUPLEX;
1025 iowrite32(mode, &hw->reg->MODE);
1026 }
1027
1028 /**
1029 * pch_gbe_watchdog - Watchdog process
1030 * @t: timer list containing a Board private structure
1031 */
pch_gbe_watchdog(struct timer_list * t)1032 static void pch_gbe_watchdog(struct timer_list *t)
1033 {
1034 struct pch_gbe_adapter *adapter = from_timer(adapter, t,
1035 watchdog_timer);
1036 struct net_device *netdev = adapter->netdev;
1037 struct pch_gbe_hw *hw = &adapter->hw;
1038
1039 netdev_dbg(netdev, "right now = %ld\n", jiffies);
1040
1041 pch_gbe_update_stats(adapter);
1042 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
1043 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1044 netdev->tx_queue_len = adapter->tx_queue_len;
1045 /* mii library handles link maintenance tasks */
1046 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
1047 netdev_err(netdev, "ethtool get setting Error\n");
1048 mod_timer(&adapter->watchdog_timer,
1049 round_jiffies(jiffies +
1050 PCH_GBE_WATCHDOG_PERIOD));
1051 return;
1052 }
1053 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
1054 hw->mac.link_duplex = cmd.duplex;
1055 /* Set the RGMII control. */
1056 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
1057 hw->mac.link_duplex);
1058 /* Set the communication mode */
1059 pch_gbe_set_mode(adapter, hw->mac.link_speed,
1060 hw->mac.link_duplex);
1061 netdev_dbg(netdev,
1062 "Link is Up %d Mbps %s-Duplex\n",
1063 hw->mac.link_speed,
1064 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1065 netif_carrier_on(netdev);
1066 netif_wake_queue(netdev);
1067 } else if ((!mii_link_ok(&adapter->mii)) &&
1068 (netif_carrier_ok(netdev))) {
1069 netdev_dbg(netdev, "NIC Link is Down\n");
1070 hw->mac.link_speed = SPEED_10;
1071 hw->mac.link_duplex = DUPLEX_HALF;
1072 netif_carrier_off(netdev);
1073 netif_stop_queue(netdev);
1074 }
1075 mod_timer(&adapter->watchdog_timer,
1076 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
1077 }
1078
1079 /**
1080 * pch_gbe_tx_queue - Carry out queuing of the transmission data
1081 * @adapter: Board private structure
1082 * @tx_ring: Tx descriptor ring structure
1083 * @skb: Sockt buffer structure
1084 */
pch_gbe_tx_queue(struct pch_gbe_adapter * adapter,struct pch_gbe_tx_ring * tx_ring,struct sk_buff * skb)1085 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
1086 struct pch_gbe_tx_ring *tx_ring,
1087 struct sk_buff *skb)
1088 {
1089 struct pch_gbe_hw *hw = &adapter->hw;
1090 struct pch_gbe_tx_desc *tx_desc;
1091 struct pch_gbe_buffer *buffer_info;
1092 struct sk_buff *tmp_skb;
1093 unsigned int frame_ctrl;
1094 unsigned int ring_num;
1095
1096 /*-- Set frame control --*/
1097 frame_ctrl = 0;
1098 if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
1099 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
1100 if (skb->ip_summed == CHECKSUM_NONE)
1101 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1102
1103 /* Performs checksum processing */
1104 /*
1105 * It is because the hardware accelerator does not support a checksum,
1106 * when the received data size is less than 64 bytes.
1107 */
1108 if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
1109 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
1110 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1111 if (skb->protocol == htons(ETH_P_IP)) {
1112 struct iphdr *iph = ip_hdr(skb);
1113 unsigned int offset;
1114 offset = skb_transport_offset(skb);
1115 if (iph->protocol == IPPROTO_TCP) {
1116 skb->csum = 0;
1117 tcp_hdr(skb)->check = 0;
1118 skb->csum = skb_checksum(skb, offset,
1119 skb->len - offset, 0);
1120 tcp_hdr(skb)->check =
1121 csum_tcpudp_magic(iph->saddr,
1122 iph->daddr,
1123 skb->len - offset,
1124 IPPROTO_TCP,
1125 skb->csum);
1126 } else if (iph->protocol == IPPROTO_UDP) {
1127 skb->csum = 0;
1128 udp_hdr(skb)->check = 0;
1129 skb->csum =
1130 skb_checksum(skb, offset,
1131 skb->len - offset, 0);
1132 udp_hdr(skb)->check =
1133 csum_tcpudp_magic(iph->saddr,
1134 iph->daddr,
1135 skb->len - offset,
1136 IPPROTO_UDP,
1137 skb->csum);
1138 }
1139 }
1140 }
1141
1142 ring_num = tx_ring->next_to_use;
1143 if (unlikely((ring_num + 1) == tx_ring->count))
1144 tx_ring->next_to_use = 0;
1145 else
1146 tx_ring->next_to_use = ring_num + 1;
1147
1148
1149 buffer_info = &tx_ring->buffer_info[ring_num];
1150 tmp_skb = buffer_info->skb;
1151
1152 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */
1153 memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1154 tmp_skb->data[ETH_HLEN] = 0x00;
1155 tmp_skb->data[ETH_HLEN + 1] = 0x00;
1156 tmp_skb->len = skb->len;
1157 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1158 (skb->len - ETH_HLEN));
1159 /*-- Set Buffer information --*/
1160 buffer_info->length = tmp_skb->len;
1161 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1162 buffer_info->length,
1163 DMA_TO_DEVICE);
1164 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1165 netdev_err(adapter->netdev, "TX DMA map failed\n");
1166 buffer_info->dma = 0;
1167 buffer_info->time_stamp = 0;
1168 tx_ring->next_to_use = ring_num;
1169 dev_kfree_skb_any(skb);
1170 return;
1171 }
1172 buffer_info->mapped = true;
1173 buffer_info->time_stamp = jiffies;
1174
1175 /*-- Set Tx descriptor --*/
1176 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1177 tx_desc->buffer_addr = (buffer_info->dma);
1178 tx_desc->length = (tmp_skb->len);
1179 tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1180 tx_desc->tx_frame_ctrl = (frame_ctrl);
1181 tx_desc->gbec_status = (DSC_INIT16);
1182
1183 if (unlikely(++ring_num == tx_ring->count))
1184 ring_num = 0;
1185
1186 /* Update software pointer of TX descriptor */
1187 iowrite32(tx_ring->dma +
1188 (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1189 &hw->reg->TX_DSC_SW_P);
1190
1191 pch_tx_timestamp(adapter, skb);
1192
1193 dev_kfree_skb_any(skb);
1194 }
1195
1196 /**
1197 * pch_gbe_update_stats - Update the board statistics counters
1198 * @adapter: Board private structure
1199 */
pch_gbe_update_stats(struct pch_gbe_adapter * adapter)1200 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1201 {
1202 struct net_device *netdev = adapter->netdev;
1203 struct pci_dev *pdev = adapter->pdev;
1204 struct pch_gbe_hw_stats *stats = &adapter->stats;
1205 unsigned long flags;
1206
1207 /*
1208 * Prevent stats update while adapter is being reset, or if the pci
1209 * connection is down.
1210 */
1211 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1212 return;
1213
1214 spin_lock_irqsave(&adapter->stats_lock, flags);
1215
1216 /* Update device status "adapter->stats" */
1217 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1218 stats->tx_errors = stats->tx_length_errors +
1219 stats->tx_aborted_errors +
1220 stats->tx_carrier_errors + stats->tx_timeout_count;
1221
1222 /* Update network device status "adapter->net_stats" */
1223 netdev->stats.rx_packets = stats->rx_packets;
1224 netdev->stats.rx_bytes = stats->rx_bytes;
1225 netdev->stats.rx_dropped = stats->rx_dropped;
1226 netdev->stats.tx_packets = stats->tx_packets;
1227 netdev->stats.tx_bytes = stats->tx_bytes;
1228 netdev->stats.tx_dropped = stats->tx_dropped;
1229 /* Fill out the OS statistics structure */
1230 netdev->stats.multicast = stats->multicast;
1231 netdev->stats.collisions = stats->collisions;
1232 /* Rx Errors */
1233 netdev->stats.rx_errors = stats->rx_errors;
1234 netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1235 netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1236 /* Tx Errors */
1237 netdev->stats.tx_errors = stats->tx_errors;
1238 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1239 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1240
1241 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1242 }
1243
pch_gbe_disable_dma_rx(struct pch_gbe_hw * hw)1244 static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw)
1245 {
1246 u32 rxdma;
1247
1248 /* Disable Receive DMA */
1249 rxdma = ioread32(&hw->reg->DMA_CTRL);
1250 rxdma &= ~PCH_GBE_RX_DMA_EN;
1251 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1252 }
1253
pch_gbe_enable_dma_rx(struct pch_gbe_hw * hw)1254 static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
1255 {
1256 u32 rxdma;
1257
1258 /* Enables Receive DMA */
1259 rxdma = ioread32(&hw->reg->DMA_CTRL);
1260 rxdma |= PCH_GBE_RX_DMA_EN;
1261 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1262 }
1263
1264 /**
1265 * pch_gbe_intr - Interrupt Handler
1266 * @irq: Interrupt number
1267 * @data: Pointer to a network interface device structure
1268 * Returns:
1269 * - IRQ_HANDLED: Our interrupt
1270 * - IRQ_NONE: Not our interrupt
1271 */
pch_gbe_intr(int irq,void * data)1272 static irqreturn_t pch_gbe_intr(int irq, void *data)
1273 {
1274 struct net_device *netdev = data;
1275 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1276 struct pch_gbe_hw *hw = &adapter->hw;
1277 u32 int_st;
1278 u32 int_en;
1279
1280 /* Check request status */
1281 int_st = ioread32(&hw->reg->INT_ST);
1282 int_st = int_st & ioread32(&hw->reg->INT_EN);
1283 /* When request status is no interruption factor */
1284 if (unlikely(!int_st))
1285 return IRQ_NONE; /* Not our interrupt. End processing. */
1286 netdev_dbg(netdev, "%s occur int_st = 0x%08x\n", __func__, int_st);
1287 if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1288 adapter->stats.intr_rx_frame_err_count++;
1289 if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1290 if (!adapter->rx_stop_flag) {
1291 adapter->stats.intr_rx_fifo_err_count++;
1292 netdev_dbg(netdev, "Rx fifo over run\n");
1293 adapter->rx_stop_flag = true;
1294 int_en = ioread32(&hw->reg->INT_EN);
1295 iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
1296 &hw->reg->INT_EN);
1297 pch_gbe_disable_dma_rx(&adapter->hw);
1298 int_st |= ioread32(&hw->reg->INT_ST);
1299 int_st = int_st & ioread32(&hw->reg->INT_EN);
1300 }
1301 if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1302 adapter->stats.intr_rx_dma_err_count++;
1303 if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1304 adapter->stats.intr_tx_fifo_err_count++;
1305 if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1306 adapter->stats.intr_tx_dma_err_count++;
1307 if (int_st & PCH_GBE_INT_TCPIP_ERR)
1308 adapter->stats.intr_tcpip_err_count++;
1309 /* When Rx descriptor is empty */
1310 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1311 adapter->stats.intr_rx_dsc_empty_count++;
1312 netdev_dbg(netdev, "Rx descriptor is empty\n");
1313 int_en = ioread32(&hw->reg->INT_EN);
1314 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1315 if (hw->mac.tx_fc_enable) {
1316 /* Set Pause packet */
1317 pch_gbe_mac_set_pause_packet(hw);
1318 }
1319 }
1320
1321 /* When request status is Receive interruption */
1322 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) ||
1323 (adapter->rx_stop_flag)) {
1324 if (likely(napi_schedule_prep(&adapter->napi))) {
1325 /* Enable only Rx Descriptor empty */
1326 atomic_inc(&adapter->irq_sem);
1327 int_en = ioread32(&hw->reg->INT_EN);
1328 int_en &=
1329 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1330 iowrite32(int_en, &hw->reg->INT_EN);
1331 /* Start polling for NAPI */
1332 __napi_schedule(&adapter->napi);
1333 }
1334 }
1335 netdev_dbg(netdev, "return = 0x%08x INT_EN reg = 0x%08x\n",
1336 IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1337 return IRQ_HANDLED;
1338 }
1339
1340 /**
1341 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1342 * @adapter: Board private structure
1343 * @rx_ring: Rx descriptor ring
1344 * @cleaned_count: Cleaned count
1345 */
1346 static void
pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter * adapter,struct pch_gbe_rx_ring * rx_ring,int cleaned_count)1347 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1348 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1349 {
1350 struct net_device *netdev = adapter->netdev;
1351 struct pci_dev *pdev = adapter->pdev;
1352 struct pch_gbe_hw *hw = &adapter->hw;
1353 struct pch_gbe_rx_desc *rx_desc;
1354 struct pch_gbe_buffer *buffer_info;
1355 struct sk_buff *skb;
1356 unsigned int i;
1357 unsigned int bufsz;
1358
1359 bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1360 i = rx_ring->next_to_use;
1361
1362 while ((cleaned_count--)) {
1363 buffer_info = &rx_ring->buffer_info[i];
1364 skb = netdev_alloc_skb(netdev, bufsz);
1365 if (unlikely(!skb)) {
1366 /* Better luck next round */
1367 adapter->stats.rx_alloc_buff_failed++;
1368 break;
1369 }
1370 /* align */
1371 skb_reserve(skb, NET_IP_ALIGN);
1372 buffer_info->skb = skb;
1373
1374 buffer_info->dma = dma_map_single(&pdev->dev,
1375 buffer_info->rx_buffer,
1376 buffer_info->length,
1377 DMA_FROM_DEVICE);
1378 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1379 dev_kfree_skb(skb);
1380 buffer_info->skb = NULL;
1381 buffer_info->dma = 0;
1382 adapter->stats.rx_alloc_buff_failed++;
1383 break; /* while !buffer_info->skb */
1384 }
1385 buffer_info->mapped = true;
1386 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1387 rx_desc->buffer_addr = (buffer_info->dma);
1388 rx_desc->gbec_status = DSC_INIT16;
1389
1390 netdev_dbg(netdev,
1391 "i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n",
1392 i, (unsigned long long)buffer_info->dma,
1393 buffer_info->length);
1394
1395 if (unlikely(++i == rx_ring->count))
1396 i = 0;
1397 }
1398 if (likely(rx_ring->next_to_use != i)) {
1399 rx_ring->next_to_use = i;
1400 if (unlikely(i-- == 0))
1401 i = (rx_ring->count - 1);
1402 iowrite32(rx_ring->dma +
1403 (int)sizeof(struct pch_gbe_rx_desc) * i,
1404 &hw->reg->RX_DSC_SW_P);
1405 }
1406 return;
1407 }
1408
1409 static int
pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter * adapter,struct pch_gbe_rx_ring * rx_ring,int cleaned_count)1410 pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter,
1411 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1412 {
1413 struct pci_dev *pdev = adapter->pdev;
1414 struct pch_gbe_buffer *buffer_info;
1415 unsigned int i;
1416 unsigned int bufsz;
1417 unsigned int size;
1418
1419 bufsz = adapter->rx_buffer_len;
1420
1421 size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY;
1422 rx_ring->rx_buff_pool =
1423 dma_alloc_coherent(&pdev->dev, size,
1424 &rx_ring->rx_buff_pool_logic, GFP_KERNEL);
1425 if (!rx_ring->rx_buff_pool)
1426 return -ENOMEM;
1427
1428 rx_ring->rx_buff_pool_size = size;
1429 for (i = 0; i < rx_ring->count; i++) {
1430 buffer_info = &rx_ring->buffer_info[i];
1431 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i;
1432 buffer_info->length = bufsz;
1433 }
1434 return 0;
1435 }
1436
1437 /**
1438 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1439 * @adapter: Board private structure
1440 * @tx_ring: Tx descriptor ring
1441 */
pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter * adapter,struct pch_gbe_tx_ring * tx_ring)1442 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1443 struct pch_gbe_tx_ring *tx_ring)
1444 {
1445 struct pch_gbe_buffer *buffer_info;
1446 struct sk_buff *skb;
1447 unsigned int i;
1448 unsigned int bufsz;
1449 struct pch_gbe_tx_desc *tx_desc;
1450
1451 bufsz =
1452 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1453
1454 for (i = 0; i < tx_ring->count; i++) {
1455 buffer_info = &tx_ring->buffer_info[i];
1456 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1457 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1458 buffer_info->skb = skb;
1459 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1460 tx_desc->gbec_status = (DSC_INIT16);
1461 }
1462 return;
1463 }
1464
1465 /**
1466 * pch_gbe_clean_tx - Reclaim resources after transmit completes
1467 * @adapter: Board private structure
1468 * @tx_ring: Tx descriptor ring
1469 * Returns:
1470 * true: Cleaned the descriptor
1471 * false: Not cleaned the descriptor
1472 */
1473 static bool
pch_gbe_clean_tx(struct pch_gbe_adapter * adapter,struct pch_gbe_tx_ring * tx_ring)1474 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1475 struct pch_gbe_tx_ring *tx_ring)
1476 {
1477 struct pch_gbe_tx_desc *tx_desc;
1478 struct pch_gbe_buffer *buffer_info;
1479 struct sk_buff *skb;
1480 unsigned int i;
1481 unsigned int cleaned_count = 0;
1482 bool cleaned = false;
1483 int unused, thresh;
1484
1485 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1486 tx_ring->next_to_clean);
1487
1488 i = tx_ring->next_to_clean;
1489 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1490 netdev_dbg(adapter->netdev, "gbec_status:0x%04x dma_status:0x%04x\n",
1491 tx_desc->gbec_status, tx_desc->dma_status);
1492
1493 unused = PCH_GBE_DESC_UNUSED(tx_ring);
1494 thresh = tx_ring->count - PCH_GBE_TX_WEIGHT;
1495 if ((tx_desc->gbec_status == DSC_INIT16) && (unused < thresh))
1496 { /* current marked clean, tx queue filling up, do extra clean */
1497 int j, k;
1498 if (unused < 8) { /* tx queue nearly full */
1499 netdev_dbg(adapter->netdev,
1500 "clean_tx: transmit queue warning (%x,%x) unused=%d\n",
1501 tx_ring->next_to_clean, tx_ring->next_to_use,
1502 unused);
1503 }
1504
1505 /* current marked clean, scan for more that need cleaning. */
1506 k = i;
1507 for (j = 0; j < PCH_GBE_TX_WEIGHT; j++)
1508 {
1509 tx_desc = PCH_GBE_TX_DESC(*tx_ring, k);
1510 if (tx_desc->gbec_status != DSC_INIT16) break; /*found*/
1511 if (++k >= tx_ring->count) k = 0; /*increment, wrap*/
1512 }
1513 if (j < PCH_GBE_TX_WEIGHT) {
1514 netdev_dbg(adapter->netdev,
1515 "clean_tx: unused=%d loops=%d found tx_desc[%x,%x:%x].gbec_status=%04x\n",
1516 unused, j, i, k, tx_ring->next_to_use,
1517 tx_desc->gbec_status);
1518 i = k; /*found one to clean, usu gbec_status==2000.*/
1519 }
1520 }
1521
1522 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1523 netdev_dbg(adapter->netdev, "gbec_status:0x%04x\n",
1524 tx_desc->gbec_status);
1525 buffer_info = &tx_ring->buffer_info[i];
1526 skb = buffer_info->skb;
1527 cleaned = true;
1528
1529 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1530 adapter->stats.tx_aborted_errors++;
1531 netdev_err(adapter->netdev, "Transfer Abort Error\n");
1532 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1533 ) {
1534 adapter->stats.tx_carrier_errors++;
1535 netdev_err(adapter->netdev,
1536 "Transfer Carrier Sense Error\n");
1537 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1538 ) {
1539 adapter->stats.tx_aborted_errors++;
1540 netdev_err(adapter->netdev,
1541 "Transfer Collision Abort Error\n");
1542 } else if ((tx_desc->gbec_status &
1543 (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1544 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1545 adapter->stats.collisions++;
1546 adapter->stats.tx_packets++;
1547 adapter->stats.tx_bytes += skb->len;
1548 netdev_dbg(adapter->netdev, "Transfer Collision\n");
1549 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1550 ) {
1551 adapter->stats.tx_packets++;
1552 adapter->stats.tx_bytes += skb->len;
1553 }
1554 if (buffer_info->mapped) {
1555 netdev_dbg(adapter->netdev,
1556 "unmap buffer_info->dma : %d\n", i);
1557 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1558 buffer_info->length, DMA_TO_DEVICE);
1559 buffer_info->mapped = false;
1560 }
1561 if (buffer_info->skb) {
1562 netdev_dbg(adapter->netdev,
1563 "trim buffer_info->skb : %d\n", i);
1564 skb_trim(buffer_info->skb, 0);
1565 }
1566 tx_desc->gbec_status = DSC_INIT16;
1567 if (unlikely(++i == tx_ring->count))
1568 i = 0;
1569 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1570
1571 /* weight of a sort for tx, to avoid endless transmit cleanup */
1572 if (cleaned_count++ == PCH_GBE_TX_WEIGHT) {
1573 cleaned = false;
1574 break;
1575 }
1576 }
1577 netdev_dbg(adapter->netdev,
1578 "called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1579 cleaned_count);
1580 if (cleaned_count > 0) { /*skip this if nothing cleaned*/
1581 /* Recover from running out of Tx resources in xmit_frame */
1582 netif_tx_lock(adapter->netdev);
1583 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev))))
1584 {
1585 netif_wake_queue(adapter->netdev);
1586 adapter->stats.tx_restart_count++;
1587 netdev_dbg(adapter->netdev, "Tx wake queue\n");
1588 }
1589
1590 tx_ring->next_to_clean = i;
1591
1592 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1593 tx_ring->next_to_clean);
1594 netif_tx_unlock(adapter->netdev);
1595 }
1596 return cleaned;
1597 }
1598
1599 /**
1600 * pch_gbe_clean_rx - Send received data up the network stack; legacy
1601 * @adapter: Board private structure
1602 * @rx_ring: Rx descriptor ring
1603 * @work_done: Completed count
1604 * @work_to_do: Request count
1605 * Returns:
1606 * true: Cleaned the descriptor
1607 * false: Not cleaned the descriptor
1608 */
1609 static bool
pch_gbe_clean_rx(struct pch_gbe_adapter * adapter,struct pch_gbe_rx_ring * rx_ring,int * work_done,int work_to_do)1610 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1611 struct pch_gbe_rx_ring *rx_ring,
1612 int *work_done, int work_to_do)
1613 {
1614 struct net_device *netdev = adapter->netdev;
1615 struct pci_dev *pdev = adapter->pdev;
1616 struct pch_gbe_buffer *buffer_info;
1617 struct pch_gbe_rx_desc *rx_desc;
1618 u32 length;
1619 unsigned int i;
1620 unsigned int cleaned_count = 0;
1621 bool cleaned = false;
1622 struct sk_buff *skb;
1623 u8 dma_status;
1624 u16 gbec_status;
1625 u32 tcp_ip_status;
1626
1627 i = rx_ring->next_to_clean;
1628
1629 while (*work_done < work_to_do) {
1630 /* Check Rx descriptor status */
1631 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1632 if (rx_desc->gbec_status == DSC_INIT16)
1633 break;
1634 cleaned = true;
1635 cleaned_count++;
1636
1637 dma_status = rx_desc->dma_status;
1638 gbec_status = rx_desc->gbec_status;
1639 tcp_ip_status = rx_desc->tcp_ip_status;
1640 rx_desc->gbec_status = DSC_INIT16;
1641 buffer_info = &rx_ring->buffer_info[i];
1642 skb = buffer_info->skb;
1643 buffer_info->skb = NULL;
1644
1645 /* unmap dma */
1646 dma_unmap_single(&pdev->dev, buffer_info->dma,
1647 buffer_info->length, DMA_FROM_DEVICE);
1648 buffer_info->mapped = false;
1649
1650 netdev_dbg(netdev,
1651 "RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x TCP:0x%08x] BufInf = 0x%p\n",
1652 i, dma_status, gbec_status, tcp_ip_status,
1653 buffer_info);
1654 /* Error check */
1655 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1656 adapter->stats.rx_frame_errors++;
1657 netdev_err(netdev, "Receive Not Octal Error\n");
1658 } else if (unlikely(gbec_status &
1659 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1660 adapter->stats.rx_frame_errors++;
1661 netdev_err(netdev, "Receive Nibble Error\n");
1662 } else if (unlikely(gbec_status &
1663 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1664 adapter->stats.rx_crc_errors++;
1665 netdev_err(netdev, "Receive CRC Error\n");
1666 } else {
1667 /* get receive length */
1668 /* length convert[-3], length includes FCS length */
1669 length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN;
1670 if (rx_desc->rx_words_eob & 0x02)
1671 length = length - 4;
1672 /*
1673 * buffer_info->rx_buffer: [Header:14][payload]
1674 * skb->data: [Reserve:2][Header:14][payload]
1675 */
1676 memcpy(skb->data, buffer_info->rx_buffer, length);
1677
1678 /* update status of driver */
1679 adapter->stats.rx_bytes += length;
1680 adapter->stats.rx_packets++;
1681 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1682 adapter->stats.multicast++;
1683 /* Write meta date of skb */
1684 skb_put(skb, length);
1685
1686 pch_rx_timestamp(adapter, skb);
1687
1688 skb->protocol = eth_type_trans(skb, netdev);
1689 if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
1690 skb->ip_summed = CHECKSUM_UNNECESSARY;
1691 else
1692 skb->ip_summed = CHECKSUM_NONE;
1693
1694 napi_gro_receive(&adapter->napi, skb);
1695 (*work_done)++;
1696 netdev_dbg(netdev,
1697 "Receive skb->ip_summed: %d length: %d\n",
1698 skb->ip_summed, length);
1699 }
1700 /* return some buffers to hardware, one at a time is too slow */
1701 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1702 pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1703 cleaned_count);
1704 cleaned_count = 0;
1705 }
1706 if (++i == rx_ring->count)
1707 i = 0;
1708 }
1709 rx_ring->next_to_clean = i;
1710 if (cleaned_count)
1711 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1712 return cleaned;
1713 }
1714
1715 /**
1716 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1717 * @adapter: Board private structure
1718 * @tx_ring: Tx descriptor ring (for a specific queue) to setup
1719 * Returns:
1720 * 0: Successfully
1721 * Negative value: Failed
1722 */
pch_gbe_setup_tx_resources(struct pch_gbe_adapter * adapter,struct pch_gbe_tx_ring * tx_ring)1723 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1724 struct pch_gbe_tx_ring *tx_ring)
1725 {
1726 struct pci_dev *pdev = adapter->pdev;
1727 struct pch_gbe_tx_desc *tx_desc;
1728 int size;
1729 int desNo;
1730
1731 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1732 tx_ring->buffer_info = vzalloc(size);
1733 if (!tx_ring->buffer_info)
1734 return -ENOMEM;
1735
1736 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1737
1738 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1739 &tx_ring->dma, GFP_KERNEL);
1740 if (!tx_ring->desc) {
1741 vfree(tx_ring->buffer_info);
1742 return -ENOMEM;
1743 }
1744
1745 tx_ring->next_to_use = 0;
1746 tx_ring->next_to_clean = 0;
1747
1748 for (desNo = 0; desNo < tx_ring->count; desNo++) {
1749 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1750 tx_desc->gbec_status = DSC_INIT16;
1751 }
1752 netdev_dbg(adapter->netdev,
1753 "tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1754 tx_ring->desc, (unsigned long long)tx_ring->dma,
1755 tx_ring->next_to_clean, tx_ring->next_to_use);
1756 return 0;
1757 }
1758
1759 /**
1760 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1761 * @adapter: Board private structure
1762 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1763 * Returns:
1764 * 0: Successfully
1765 * Negative value: Failed
1766 */
pch_gbe_setup_rx_resources(struct pch_gbe_adapter * adapter,struct pch_gbe_rx_ring * rx_ring)1767 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1768 struct pch_gbe_rx_ring *rx_ring)
1769 {
1770 struct pci_dev *pdev = adapter->pdev;
1771 struct pch_gbe_rx_desc *rx_desc;
1772 int size;
1773 int desNo;
1774
1775 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1776 rx_ring->buffer_info = vzalloc(size);
1777 if (!rx_ring->buffer_info)
1778 return -ENOMEM;
1779
1780 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1781 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1782 &rx_ring->dma, GFP_KERNEL);
1783 if (!rx_ring->desc) {
1784 vfree(rx_ring->buffer_info);
1785 return -ENOMEM;
1786 }
1787 rx_ring->next_to_clean = 0;
1788 rx_ring->next_to_use = 0;
1789 for (desNo = 0; desNo < rx_ring->count; desNo++) {
1790 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1791 rx_desc->gbec_status = DSC_INIT16;
1792 }
1793 netdev_dbg(adapter->netdev,
1794 "rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1795 rx_ring->desc, (unsigned long long)rx_ring->dma,
1796 rx_ring->next_to_clean, rx_ring->next_to_use);
1797 return 0;
1798 }
1799
1800 /**
1801 * pch_gbe_free_tx_resources - Free Tx Resources
1802 * @adapter: Board private structure
1803 * @tx_ring: Tx descriptor ring for a specific queue
1804 */
pch_gbe_free_tx_resources(struct pch_gbe_adapter * adapter,struct pch_gbe_tx_ring * tx_ring)1805 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1806 struct pch_gbe_tx_ring *tx_ring)
1807 {
1808 struct pci_dev *pdev = adapter->pdev;
1809
1810 pch_gbe_clean_tx_ring(adapter, tx_ring);
1811 vfree(tx_ring->buffer_info);
1812 tx_ring->buffer_info = NULL;
1813 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1814 tx_ring->desc = NULL;
1815 }
1816
1817 /**
1818 * pch_gbe_free_rx_resources - Free Rx Resources
1819 * @adapter: Board private structure
1820 * @rx_ring: Ring to clean the resources from
1821 */
pch_gbe_free_rx_resources(struct pch_gbe_adapter * adapter,struct pch_gbe_rx_ring * rx_ring)1822 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1823 struct pch_gbe_rx_ring *rx_ring)
1824 {
1825 struct pci_dev *pdev = adapter->pdev;
1826
1827 pch_gbe_clean_rx_ring(adapter, rx_ring);
1828 vfree(rx_ring->buffer_info);
1829 rx_ring->buffer_info = NULL;
1830 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1831 rx_ring->desc = NULL;
1832 }
1833
1834 /**
1835 * pch_gbe_request_irq - Allocate an interrupt line
1836 * @adapter: Board private structure
1837 * Returns:
1838 * 0: Successfully
1839 * Negative value: Failed
1840 */
pch_gbe_request_irq(struct pch_gbe_adapter * adapter)1841 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1842 {
1843 struct net_device *netdev = adapter->netdev;
1844 int err;
1845
1846 err = pci_alloc_irq_vectors(adapter->pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1847 if (err < 0)
1848 return err;
1849
1850 adapter->irq = pci_irq_vector(adapter->pdev, 0);
1851
1852 err = request_irq(adapter->irq, &pch_gbe_intr, IRQF_SHARED,
1853 netdev->name, netdev);
1854 if (err)
1855 netdev_err(netdev, "Unable to allocate interrupt Error: %d\n",
1856 err);
1857 netdev_dbg(netdev, "have_msi : %d return : 0x%04x\n",
1858 pci_dev_msi_enabled(adapter->pdev), err);
1859 return err;
1860 }
1861
1862 /**
1863 * pch_gbe_up - Up GbE network device
1864 * @adapter: Board private structure
1865 * Returns:
1866 * 0: Successfully
1867 * Negative value: Failed
1868 */
pch_gbe_up(struct pch_gbe_adapter * adapter)1869 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1870 {
1871 struct net_device *netdev = adapter->netdev;
1872 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1873 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1874 int err = -EINVAL;
1875
1876 /* Ensure we have a valid MAC */
1877 if (!is_valid_ether_addr(adapter->hw.mac.addr)) {
1878 netdev_err(netdev, "Error: Invalid MAC address\n");
1879 goto out;
1880 }
1881
1882 /* hardware has been reset, we need to reload some things */
1883 pch_gbe_set_multi(netdev);
1884
1885 pch_gbe_setup_tctl(adapter);
1886 pch_gbe_configure_tx(adapter);
1887 pch_gbe_setup_rctl(adapter);
1888 pch_gbe_configure_rx(adapter);
1889
1890 err = pch_gbe_request_irq(adapter);
1891 if (err) {
1892 netdev_err(netdev,
1893 "Error: can't bring device up - irq request failed\n");
1894 goto out;
1895 }
1896 err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count);
1897 if (err) {
1898 netdev_err(netdev,
1899 "Error: can't bring device up - alloc rx buffers pool failed\n");
1900 goto freeirq;
1901 }
1902 pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1903 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1904 adapter->tx_queue_len = netdev->tx_queue_len;
1905 pch_gbe_enable_dma_rx(&adapter->hw);
1906 pch_gbe_enable_mac_rx(&adapter->hw);
1907
1908 mod_timer(&adapter->watchdog_timer, jiffies);
1909
1910 napi_enable(&adapter->napi);
1911 pch_gbe_irq_enable(adapter);
1912 netif_start_queue(adapter->netdev);
1913
1914 return 0;
1915
1916 freeirq:
1917 pch_gbe_free_irq(adapter);
1918 out:
1919 return err;
1920 }
1921
1922 /**
1923 * pch_gbe_down - Down GbE network device
1924 * @adapter: Board private structure
1925 */
pch_gbe_down(struct pch_gbe_adapter * adapter)1926 void pch_gbe_down(struct pch_gbe_adapter *adapter)
1927 {
1928 struct net_device *netdev = adapter->netdev;
1929 struct pci_dev *pdev = adapter->pdev;
1930 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1931
1932 /* signal that we're down so the interrupt handler does not
1933 * reschedule our watchdog timer */
1934 napi_disable(&adapter->napi);
1935 atomic_set(&adapter->irq_sem, 0);
1936
1937 pch_gbe_irq_disable(adapter);
1938 pch_gbe_free_irq(adapter);
1939
1940 del_timer_sync(&adapter->watchdog_timer);
1941
1942 netdev->tx_queue_len = adapter->tx_queue_len;
1943 netif_carrier_off(netdev);
1944 netif_stop_queue(netdev);
1945
1946 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1947 pch_gbe_reset(adapter);
1948 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
1949 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
1950
1951 pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size,
1952 rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic);
1953 rx_ring->rx_buff_pool_logic = 0;
1954 rx_ring->rx_buff_pool_size = 0;
1955 rx_ring->rx_buff_pool = NULL;
1956 }
1957
1958 /**
1959 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
1960 * @adapter: Board private structure to initialize
1961 * Returns:
1962 * 0: Successfully
1963 * Negative value: Failed
1964 */
pch_gbe_sw_init(struct pch_gbe_adapter * adapter)1965 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
1966 {
1967 struct pch_gbe_hw *hw = &adapter->hw;
1968 struct net_device *netdev = adapter->netdev;
1969
1970 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1971 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1972 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1973 hw->phy.reset_delay_us = PCH_GBE_PHY_RESET_DELAY_US;
1974
1975 if (pch_gbe_alloc_queues(adapter)) {
1976 netdev_err(netdev, "Unable to allocate memory for queues\n");
1977 return -ENOMEM;
1978 }
1979 spin_lock_init(&adapter->hw.miim_lock);
1980 spin_lock_init(&adapter->stats_lock);
1981 spin_lock_init(&adapter->ethtool_lock);
1982 atomic_set(&adapter->irq_sem, 0);
1983 pch_gbe_irq_disable(adapter);
1984
1985 pch_gbe_init_stats(adapter);
1986
1987 netdev_dbg(netdev,
1988 "rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n",
1989 (u32) adapter->rx_buffer_len,
1990 hw->mac.min_frame_size, hw->mac.max_frame_size);
1991 return 0;
1992 }
1993
1994 /**
1995 * pch_gbe_open - Called when a network interface is made active
1996 * @netdev: Network interface device structure
1997 * Returns:
1998 * 0: Successfully
1999 * Negative value: Failed
2000 */
pch_gbe_open(struct net_device * netdev)2001 static int pch_gbe_open(struct net_device *netdev)
2002 {
2003 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2004 struct pch_gbe_hw *hw = &adapter->hw;
2005 int err;
2006
2007 /* allocate transmit descriptors */
2008 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
2009 if (err)
2010 goto err_setup_tx;
2011 /* allocate receive descriptors */
2012 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
2013 if (err)
2014 goto err_setup_rx;
2015 pch_gbe_phy_power_up(hw);
2016 err = pch_gbe_up(adapter);
2017 if (err)
2018 goto err_up;
2019 netdev_dbg(netdev, "Success End\n");
2020 return 0;
2021
2022 err_up:
2023 if (!adapter->wake_up_evt)
2024 pch_gbe_phy_power_down(hw);
2025 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2026 err_setup_rx:
2027 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2028 err_setup_tx:
2029 pch_gbe_reset(adapter);
2030 netdev_err(netdev, "Error End\n");
2031 return err;
2032 }
2033
2034 /**
2035 * pch_gbe_stop - Disables a network interface
2036 * @netdev: Network interface device structure
2037 * Returns:
2038 * 0: Successfully
2039 */
pch_gbe_stop(struct net_device * netdev)2040 static int pch_gbe_stop(struct net_device *netdev)
2041 {
2042 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2043 struct pch_gbe_hw *hw = &adapter->hw;
2044
2045 pch_gbe_down(adapter);
2046 if (!adapter->wake_up_evt)
2047 pch_gbe_phy_power_down(hw);
2048 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2049 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2050 return 0;
2051 }
2052
2053 /**
2054 * pch_gbe_xmit_frame - Packet transmitting start
2055 * @skb: Socket buffer structure
2056 * @netdev: Network interface device structure
2057 * Returns:
2058 * - NETDEV_TX_OK: Normal end
2059 * - NETDEV_TX_BUSY: Error end
2060 */
pch_gbe_xmit_frame(struct sk_buff * skb,struct net_device * netdev)2061 static netdev_tx_t pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2062 {
2063 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2064 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
2065
2066 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
2067 netif_stop_queue(netdev);
2068 netdev_dbg(netdev,
2069 "Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n",
2070 tx_ring->next_to_use, tx_ring->next_to_clean);
2071 return NETDEV_TX_BUSY;
2072 }
2073
2074 /* CRC,ITAG no support */
2075 pch_gbe_tx_queue(adapter, tx_ring, skb);
2076 return NETDEV_TX_OK;
2077 }
2078
2079 /**
2080 * pch_gbe_set_multi - Multicast and Promiscuous mode set
2081 * @netdev: Network interface device structure
2082 */
pch_gbe_set_multi(struct net_device * netdev)2083 static void pch_gbe_set_multi(struct net_device *netdev)
2084 {
2085 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2086 struct pch_gbe_hw *hw = &adapter->hw;
2087 struct netdev_hw_addr *ha;
2088 u32 rctl, adrmask;
2089 int mc_count, i;
2090
2091 netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags);
2092
2093 /* By default enable address & multicast filtering */
2094 rctl = ioread32(&hw->reg->RX_MODE);
2095 rctl |= PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN;
2096
2097 /* Promiscuous mode disables all hardware address filtering */
2098 if (netdev->flags & IFF_PROMISC)
2099 rctl &= ~(PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
2100
2101 /* If we want to monitor more multicast addresses than the hardware can
2102 * support then disable hardware multicast filtering.
2103 */
2104 mc_count = netdev_mc_count(netdev);
2105 if ((netdev->flags & IFF_ALLMULTI) || mc_count >= PCH_GBE_MAR_ENTRIES)
2106 rctl &= ~PCH_GBE_MLT_FIL_EN;
2107
2108 iowrite32(rctl, &hw->reg->RX_MODE);
2109
2110 /* If we're not using multicast filtering then there's no point
2111 * configuring the unused MAC address registers.
2112 */
2113 if (!(rctl & PCH_GBE_MLT_FIL_EN))
2114 return;
2115
2116 /* Load the first set of multicast addresses into MAC address registers
2117 * for use by hardware filtering.
2118 */
2119 i = 1;
2120 netdev_for_each_mc_addr(ha, netdev)
2121 pch_gbe_mac_mar_set(hw, ha->addr, i++);
2122
2123 /* If there are spare MAC registers, mask & clear them */
2124 for (; i < PCH_GBE_MAR_ENTRIES; i++) {
2125 /* Clear MAC address mask */
2126 adrmask = ioread32(&hw->reg->ADDR_MASK);
2127 iowrite32(adrmask | BIT(i), &hw->reg->ADDR_MASK);
2128 /* wait busy */
2129 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
2130 /* Clear MAC address */
2131 iowrite32(0, &hw->reg->mac_adr[i].high);
2132 iowrite32(0, &hw->reg->mac_adr[i].low);
2133 }
2134
2135 netdev_dbg(netdev,
2136 "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n",
2137 ioread32(&hw->reg->RX_MODE), mc_count);
2138 }
2139
2140 /**
2141 * pch_gbe_set_mac - Change the Ethernet Address of the NIC
2142 * @netdev: Network interface device structure
2143 * @addr: Pointer to an address structure
2144 * Returns:
2145 * 0: Successfully
2146 * -EADDRNOTAVAIL: Failed
2147 */
pch_gbe_set_mac(struct net_device * netdev,void * addr)2148 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
2149 {
2150 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2151 struct sockaddr *skaddr = addr;
2152 int ret_val;
2153
2154 if (!is_valid_ether_addr(skaddr->sa_data)) {
2155 ret_val = -EADDRNOTAVAIL;
2156 } else {
2157 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
2158 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
2159 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2160 ret_val = 0;
2161 }
2162 netdev_dbg(netdev, "ret_val : 0x%08x\n", ret_val);
2163 netdev_dbg(netdev, "dev_addr : %pM\n", netdev->dev_addr);
2164 netdev_dbg(netdev, "mac_addr : %pM\n", adapter->hw.mac.addr);
2165 netdev_dbg(netdev, "MAC_ADR1AB reg : 0x%08x 0x%08x\n",
2166 ioread32(&adapter->hw.reg->mac_adr[0].high),
2167 ioread32(&adapter->hw.reg->mac_adr[0].low));
2168 return ret_val;
2169 }
2170
2171 /**
2172 * pch_gbe_change_mtu - Change the Maximum Transfer Unit
2173 * @netdev: Network interface device structure
2174 * @new_mtu: New value for maximum frame size
2175 * Returns:
2176 * 0: Successfully
2177 * -EINVAL: Failed
2178 */
pch_gbe_change_mtu(struct net_device * netdev,int new_mtu)2179 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2180 {
2181 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2182 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2183 unsigned long old_rx_buffer_len = adapter->rx_buffer_len;
2184 int err;
2185
2186 if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2187 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2188 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2189 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2190 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2191 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2192 else
2193 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE;
2194
2195 if (netif_running(netdev)) {
2196 pch_gbe_down(adapter);
2197 err = pch_gbe_up(adapter);
2198 if (err) {
2199 adapter->rx_buffer_len = old_rx_buffer_len;
2200 pch_gbe_up(adapter);
2201 return err;
2202 } else {
2203 netdev->mtu = new_mtu;
2204 adapter->hw.mac.max_frame_size = max_frame;
2205 }
2206 } else {
2207 pch_gbe_reset(adapter);
2208 netdev->mtu = new_mtu;
2209 adapter->hw.mac.max_frame_size = max_frame;
2210 }
2211
2212 netdev_dbg(netdev,
2213 "max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n",
2214 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2215 adapter->hw.mac.max_frame_size);
2216 return 0;
2217 }
2218
2219 /**
2220 * pch_gbe_set_features - Reset device after features changed
2221 * @netdev: Network interface device structure
2222 * @features: New features
2223 * Returns:
2224 * 0: HW state updated successfully
2225 */
pch_gbe_set_features(struct net_device * netdev,netdev_features_t features)2226 static int pch_gbe_set_features(struct net_device *netdev,
2227 netdev_features_t features)
2228 {
2229 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2230 netdev_features_t changed = features ^ netdev->features;
2231
2232 if (!(changed & NETIF_F_RXCSUM))
2233 return 0;
2234
2235 if (netif_running(netdev))
2236 pch_gbe_reinit_locked(adapter);
2237 else
2238 pch_gbe_reset(adapter);
2239
2240 return 0;
2241 }
2242
2243 /**
2244 * pch_gbe_ioctl - Controls register through a MII interface
2245 * @netdev: Network interface device structure
2246 * @ifr: Pointer to ifr structure
2247 * @cmd: Control command
2248 * Returns:
2249 * 0: Successfully
2250 * Negative value: Failed
2251 */
pch_gbe_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)2252 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2253 {
2254 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2255
2256 netdev_dbg(netdev, "cmd : 0x%04x\n", cmd);
2257
2258 if (cmd == SIOCSHWTSTAMP)
2259 return hwtstamp_ioctl(netdev, ifr, cmd);
2260
2261 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2262 }
2263
2264 /**
2265 * pch_gbe_tx_timeout - Respond to a Tx Hang
2266 * @netdev: Network interface device structure
2267 * @txqueue: index of hanging queue
2268 */
pch_gbe_tx_timeout(struct net_device * netdev,unsigned int txqueue)2269 static void pch_gbe_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2270 {
2271 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2272
2273 /* Do the reset outside of interrupt context */
2274 adapter->stats.tx_timeout_count++;
2275 schedule_work(&adapter->reset_task);
2276 }
2277
2278 /**
2279 * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2280 * @napi: Pointer of polling device struct
2281 * @budget: The maximum number of a packet
2282 * Returns:
2283 * false: Exit the polling mode
2284 * true: Continue the polling mode
2285 */
pch_gbe_napi_poll(struct napi_struct * napi,int budget)2286 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2287 {
2288 struct pch_gbe_adapter *adapter =
2289 container_of(napi, struct pch_gbe_adapter, napi);
2290 int work_done = 0;
2291 bool poll_end_flag = false;
2292 bool cleaned = false;
2293
2294 netdev_dbg(adapter->netdev, "budget : %d\n", budget);
2295
2296 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2297 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2298
2299 if (cleaned)
2300 work_done = budget;
2301 /* If no Tx and not enough Rx work done,
2302 * exit the polling mode
2303 */
2304 if (work_done < budget)
2305 poll_end_flag = true;
2306
2307 if (poll_end_flag) {
2308 napi_complete_done(napi, work_done);
2309 pch_gbe_irq_enable(adapter);
2310 }
2311
2312 if (adapter->rx_stop_flag) {
2313 adapter->rx_stop_flag = false;
2314 pch_gbe_enable_dma_rx(&adapter->hw);
2315 }
2316
2317 netdev_dbg(adapter->netdev,
2318 "poll_end_flag : %d work_done : %d budget : %d\n",
2319 poll_end_flag, work_done, budget);
2320
2321 return work_done;
2322 }
2323
2324 #ifdef CONFIG_NET_POLL_CONTROLLER
2325 /**
2326 * pch_gbe_netpoll - Used by things like netconsole to send skbs
2327 * @netdev: Network interface device structure
2328 */
pch_gbe_netpoll(struct net_device * netdev)2329 static void pch_gbe_netpoll(struct net_device *netdev)
2330 {
2331 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2332
2333 disable_irq(adapter->irq);
2334 pch_gbe_intr(adapter->irq, netdev);
2335 enable_irq(adapter->irq);
2336 }
2337 #endif
2338
2339 static const struct net_device_ops pch_gbe_netdev_ops = {
2340 .ndo_open = pch_gbe_open,
2341 .ndo_stop = pch_gbe_stop,
2342 .ndo_start_xmit = pch_gbe_xmit_frame,
2343 .ndo_set_mac_address = pch_gbe_set_mac,
2344 .ndo_tx_timeout = pch_gbe_tx_timeout,
2345 .ndo_change_mtu = pch_gbe_change_mtu,
2346 .ndo_set_features = pch_gbe_set_features,
2347 .ndo_do_ioctl = pch_gbe_ioctl,
2348 .ndo_set_rx_mode = pch_gbe_set_multi,
2349 #ifdef CONFIG_NET_POLL_CONTROLLER
2350 .ndo_poll_controller = pch_gbe_netpoll,
2351 #endif
2352 };
2353
pch_gbe_io_error_detected(struct pci_dev * pdev,pci_channel_state_t state)2354 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2355 pci_channel_state_t state)
2356 {
2357 struct net_device *netdev = pci_get_drvdata(pdev);
2358 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2359
2360 netif_device_detach(netdev);
2361 if (netif_running(netdev))
2362 pch_gbe_down(adapter);
2363 pci_disable_device(pdev);
2364 /* Request a slot slot reset. */
2365 return PCI_ERS_RESULT_NEED_RESET;
2366 }
2367
pch_gbe_io_slot_reset(struct pci_dev * pdev)2368 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2369 {
2370 struct net_device *netdev = pci_get_drvdata(pdev);
2371 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2372 struct pch_gbe_hw *hw = &adapter->hw;
2373
2374 if (pci_enable_device(pdev)) {
2375 netdev_err(netdev, "Cannot re-enable PCI device after reset\n");
2376 return PCI_ERS_RESULT_DISCONNECT;
2377 }
2378 pci_set_master(pdev);
2379 pci_enable_wake(pdev, PCI_D0, 0);
2380 pch_gbe_phy_power_up(hw);
2381 pch_gbe_reset(adapter);
2382 /* Clear wake up status */
2383 pch_gbe_mac_set_wol_event(hw, 0);
2384
2385 return PCI_ERS_RESULT_RECOVERED;
2386 }
2387
pch_gbe_io_resume(struct pci_dev * pdev)2388 static void pch_gbe_io_resume(struct pci_dev *pdev)
2389 {
2390 struct net_device *netdev = pci_get_drvdata(pdev);
2391 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2392
2393 if (netif_running(netdev)) {
2394 if (pch_gbe_up(adapter)) {
2395 netdev_dbg(netdev,
2396 "can't bring device back up after reset\n");
2397 return;
2398 }
2399 }
2400 netif_device_attach(netdev);
2401 }
2402
__pch_gbe_suspend(struct pci_dev * pdev)2403 static int __pch_gbe_suspend(struct pci_dev *pdev)
2404 {
2405 struct net_device *netdev = pci_get_drvdata(pdev);
2406 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2407 struct pch_gbe_hw *hw = &adapter->hw;
2408 u32 wufc = adapter->wake_up_evt;
2409 int retval = 0;
2410
2411 netif_device_detach(netdev);
2412 if (netif_running(netdev))
2413 pch_gbe_down(adapter);
2414 if (wufc) {
2415 pch_gbe_set_multi(netdev);
2416 pch_gbe_setup_rctl(adapter);
2417 pch_gbe_configure_rx(adapter);
2418 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2419 hw->mac.link_duplex);
2420 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2421 hw->mac.link_duplex);
2422 pch_gbe_mac_set_wol_event(hw, wufc);
2423 pci_disable_device(pdev);
2424 } else {
2425 pch_gbe_phy_power_down(hw);
2426 pch_gbe_mac_set_wol_event(hw, wufc);
2427 pci_disable_device(pdev);
2428 }
2429 return retval;
2430 }
2431
2432 #ifdef CONFIG_PM
pch_gbe_suspend(struct device * device)2433 static int pch_gbe_suspend(struct device *device)
2434 {
2435 struct pci_dev *pdev = to_pci_dev(device);
2436
2437 return __pch_gbe_suspend(pdev);
2438 }
2439
pch_gbe_resume(struct device * device)2440 static int pch_gbe_resume(struct device *device)
2441 {
2442 struct pci_dev *pdev = to_pci_dev(device);
2443 struct net_device *netdev = pci_get_drvdata(pdev);
2444 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2445 struct pch_gbe_hw *hw = &adapter->hw;
2446 u32 err;
2447
2448 err = pci_enable_device(pdev);
2449 if (err) {
2450 netdev_err(netdev, "Cannot enable PCI device from suspend\n");
2451 return err;
2452 }
2453 pci_set_master(pdev);
2454 pch_gbe_phy_power_up(hw);
2455 pch_gbe_reset(adapter);
2456 /* Clear wake on lan control and status */
2457 pch_gbe_mac_set_wol_event(hw, 0);
2458
2459 if (netif_running(netdev))
2460 pch_gbe_up(adapter);
2461 netif_device_attach(netdev);
2462
2463 return 0;
2464 }
2465 #endif /* CONFIG_PM */
2466
pch_gbe_shutdown(struct pci_dev * pdev)2467 static void pch_gbe_shutdown(struct pci_dev *pdev)
2468 {
2469 __pch_gbe_suspend(pdev);
2470 if (system_state == SYSTEM_POWER_OFF) {
2471 pci_wake_from_d3(pdev, true);
2472 pci_set_power_state(pdev, PCI_D3hot);
2473 }
2474 }
2475
pch_gbe_remove(struct pci_dev * pdev)2476 static void pch_gbe_remove(struct pci_dev *pdev)
2477 {
2478 struct net_device *netdev = pci_get_drvdata(pdev);
2479 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2480
2481 cancel_work_sync(&adapter->reset_task);
2482 unregister_netdev(netdev);
2483
2484 pch_gbe_phy_hw_reset(&adapter->hw);
2485 pci_dev_put(adapter->ptp_pdev);
2486
2487 free_netdev(netdev);
2488 }
2489
pch_gbe_probe(struct pci_dev * pdev,const struct pci_device_id * pci_id)2490 static int pch_gbe_probe(struct pci_dev *pdev,
2491 const struct pci_device_id *pci_id)
2492 {
2493 struct net_device *netdev;
2494 struct pch_gbe_adapter *adapter;
2495 int ret;
2496
2497 ret = pcim_enable_device(pdev);
2498 if (ret)
2499 return ret;
2500
2501 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2502 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2503 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2504 if (ret) {
2505 ret = pci_set_consistent_dma_mask(pdev,
2506 DMA_BIT_MASK(32));
2507 if (ret) {
2508 dev_err(&pdev->dev, "ERR: No usable DMA "
2509 "configuration, aborting\n");
2510 return ret;
2511 }
2512 }
2513 }
2514
2515 ret = pcim_iomap_regions(pdev, 1 << PCH_GBE_PCI_BAR, pci_name(pdev));
2516 if (ret) {
2517 dev_err(&pdev->dev,
2518 "ERR: Can't reserve PCI I/O and memory resources\n");
2519 return ret;
2520 }
2521 pci_set_master(pdev);
2522
2523 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2524 if (!netdev)
2525 return -ENOMEM;
2526 SET_NETDEV_DEV(netdev, &pdev->dev);
2527
2528 pci_set_drvdata(pdev, netdev);
2529 adapter = netdev_priv(netdev);
2530 adapter->netdev = netdev;
2531 adapter->pdev = pdev;
2532 adapter->hw.back = adapter;
2533 adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
2534
2535 adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
2536 if (adapter->pdata && adapter->pdata->platform_init) {
2537 ret = adapter->pdata->platform_init(pdev);
2538 if (ret)
2539 goto err_free_netdev;
2540 }
2541
2542 adapter->ptp_pdev =
2543 pci_get_domain_bus_and_slot(pci_domain_nr(adapter->pdev->bus),
2544 adapter->pdev->bus->number,
2545 PCI_DEVFN(12, 4));
2546
2547 netdev->netdev_ops = &pch_gbe_netdev_ops;
2548 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2549 netif_napi_add(netdev, &adapter->napi,
2550 pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2551 netdev->hw_features = NETIF_F_RXCSUM |
2552 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2553 netdev->features = netdev->hw_features;
2554 pch_gbe_set_ethtool_ops(netdev);
2555
2556 /* MTU range: 46 - 10300 */
2557 netdev->min_mtu = ETH_ZLEN - ETH_HLEN;
2558 netdev->max_mtu = PCH_GBE_MAX_JUMBO_FRAME_SIZE -
2559 (ETH_HLEN + ETH_FCS_LEN);
2560
2561 pch_gbe_mac_load_mac_addr(&adapter->hw);
2562 pch_gbe_mac_reset_hw(&adapter->hw);
2563
2564 /* setup the private structure */
2565 ret = pch_gbe_sw_init(adapter);
2566 if (ret)
2567 goto err_put_dev;
2568
2569 /* Initialize PHY */
2570 ret = pch_gbe_init_phy(adapter);
2571 if (ret) {
2572 dev_err(&pdev->dev, "PHY initialize error\n");
2573 goto err_free_adapter;
2574 }
2575
2576 /* Read the MAC address. and store to the private data */
2577 ret = pch_gbe_mac_read_mac_addr(&adapter->hw);
2578 if (ret) {
2579 dev_err(&pdev->dev, "MAC address Read Error\n");
2580 goto err_free_adapter;
2581 }
2582
2583 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2584 if (!is_valid_ether_addr(netdev->dev_addr)) {
2585 /*
2586 * If the MAC is invalid (or just missing), display a warning
2587 * but do not abort setting up the device. pch_gbe_up will
2588 * prevent the interface from being brought up until a valid MAC
2589 * is set.
2590 */
2591 dev_err(&pdev->dev, "Invalid MAC address, "
2592 "interface disabled.\n");
2593 }
2594 timer_setup(&adapter->watchdog_timer, pch_gbe_watchdog, 0);
2595
2596 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2597
2598 pch_gbe_check_options(adapter);
2599
2600 /* initialize the wol settings based on the eeprom settings */
2601 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2602 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2603
2604 /* reset the hardware with the new settings */
2605 pch_gbe_reset(adapter);
2606
2607 ret = register_netdev(netdev);
2608 if (ret)
2609 goto err_free_adapter;
2610 /* tell the stack to leave us alone until pch_gbe_open() is called */
2611 netif_carrier_off(netdev);
2612 netif_stop_queue(netdev);
2613
2614 dev_dbg(&pdev->dev, "PCH Network Connection\n");
2615
2616 /* Disable hibernation on certain platforms */
2617 if (adapter->pdata && adapter->pdata->phy_disable_hibernate)
2618 pch_gbe_phy_disable_hibernate(&adapter->hw);
2619
2620 device_set_wakeup_enable(&pdev->dev, 1);
2621 return 0;
2622
2623 err_free_adapter:
2624 pch_gbe_phy_hw_reset(&adapter->hw);
2625 err_put_dev:
2626 pci_dev_put(adapter->ptp_pdev);
2627 err_free_netdev:
2628 free_netdev(netdev);
2629 return ret;
2630 }
2631
2632 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
2633 * ensure it is awake for probe and init. Request the line and reset the PHY.
2634 */
pch_gbe_minnow_platform_init(struct pci_dev * pdev)2635 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
2636 {
2637 unsigned long flags = GPIOF_OUT_INIT_HIGH;
2638 unsigned gpio = MINNOW_PHY_RESET_GPIO;
2639 int ret;
2640
2641 ret = devm_gpio_request_one(&pdev->dev, gpio, flags,
2642 "minnow_phy_reset");
2643 if (ret) {
2644 dev_err(&pdev->dev,
2645 "ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
2646 return ret;
2647 }
2648
2649 gpio_set_value(gpio, 0);
2650 usleep_range(1250, 1500);
2651 gpio_set_value(gpio, 1);
2652 usleep_range(1250, 1500);
2653
2654 return ret;
2655 }
2656
2657 static struct pch_gbe_privdata pch_gbe_minnow_privdata = {
2658 .phy_tx_clk_delay = true,
2659 .phy_disable_hibernate = true,
2660 .platform_init = pch_gbe_minnow_platform_init,
2661 };
2662
2663 static const struct pci_device_id pch_gbe_pcidev_id[] = {
2664 {.vendor = PCI_VENDOR_ID_INTEL,
2665 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2666 .subvendor = PCI_VENDOR_ID_CIRCUITCO,
2667 .subdevice = PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD,
2668 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2669 .class_mask = (0xFFFF00),
2670 .driver_data = (kernel_ulong_t)&pch_gbe_minnow_privdata
2671 },
2672 {.vendor = PCI_VENDOR_ID_INTEL,
2673 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2674 .subvendor = PCI_ANY_ID,
2675 .subdevice = PCI_ANY_ID,
2676 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2677 .class_mask = (0xFFFF00)
2678 },
2679 {.vendor = PCI_VENDOR_ID_ROHM,
2680 .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2681 .subvendor = PCI_ANY_ID,
2682 .subdevice = PCI_ANY_ID,
2683 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2684 .class_mask = (0xFFFF00)
2685 },
2686 {.vendor = PCI_VENDOR_ID_ROHM,
2687 .device = PCI_DEVICE_ID_ROHM_ML7831_GBE,
2688 .subvendor = PCI_ANY_ID,
2689 .subdevice = PCI_ANY_ID,
2690 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2691 .class_mask = (0xFFFF00)
2692 },
2693 /* required last entry */
2694 {0}
2695 };
2696
2697 #ifdef CONFIG_PM
2698 static const struct dev_pm_ops pch_gbe_pm_ops = {
2699 .suspend = pch_gbe_suspend,
2700 .resume = pch_gbe_resume,
2701 .freeze = pch_gbe_suspend,
2702 .thaw = pch_gbe_resume,
2703 .poweroff = pch_gbe_suspend,
2704 .restore = pch_gbe_resume,
2705 };
2706 #endif
2707
2708 static const struct pci_error_handlers pch_gbe_err_handler = {
2709 .error_detected = pch_gbe_io_error_detected,
2710 .slot_reset = pch_gbe_io_slot_reset,
2711 .resume = pch_gbe_io_resume
2712 };
2713
2714 static struct pci_driver pch_gbe_driver = {
2715 .name = KBUILD_MODNAME,
2716 .id_table = pch_gbe_pcidev_id,
2717 .probe = pch_gbe_probe,
2718 .remove = pch_gbe_remove,
2719 #ifdef CONFIG_PM
2720 .driver.pm = &pch_gbe_pm_ops,
2721 #endif
2722 .shutdown = pch_gbe_shutdown,
2723 .err_handler = &pch_gbe_err_handler
2724 };
2725 module_pci_driver(pch_gbe_driver);
2726
2727 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2728 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
2729 MODULE_LICENSE("GPL");
2730 MODULE_VERSION(DRV_VERSION);
2731 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2732
2733 /* pch_gbe_main.c */
2734