1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 #ifndef __DRV_HDMI_COMMON_H_ 19 #define __DRV_HDMI_COMMON_H_ 20 21 #include "hi_type.h" 22 #include "drv_hdmi_infoframe.h" 23 #include "hdmi_ext.h" 24 #include "securec.h" 25 #include "hi_comm_hdmi.h" 26 27 #define HDMI_VER_MAJOR 2 28 #define HDMI_VER_MINOR 0 29 #define HDMI_VER_REVISE 0 30 #define HDMI_VER_DATE 20201202 31 #define HDMI_VER_TIMES 0 32 33 #define make_ver_bit(x) #x 34 #define make_macro2str(exp) make_ver_bit(exp) 35 #define MAKE_VERSION \ 36 make_macro2str(HDMI_VER_MAJOR) "." \ 37 make_macro2str(HDMI_VER_MINOR) "." \ 38 make_macro2str(HDMI_VER_REVISE) "." \ 39 make_macro2str(HDMI_VER_DATE) "." \ 40 make_macro2str(HDMI_VER_TIMES) 41 42 #define MAX_FRL_RATE 6 43 #define HDMI_FRL_LANE_MAX_NUM 4 44 #define CEA_VIDEO_CODE_MAX 44 45 #define VESA_VIDEO_CODE_MAX 31 46 #define CEA861_F_VIDEO_CODES_MAX_4K 4 47 #define HDMI_INFO_FRAME_MAX_SIZE 31 48 #define SCDC_TMDS_BIT_CLK_RATIO_10X 10 49 #define SCDC_TMDS_BIT_CLK_RATIO_40X 40 50 #ifdef CONFIG_HI_PLATFORM_H8 51 #define HI_ERR_NULL_PTR HI_ERR_HDMI_NULL_PTR 52 #else 53 #define HI_ERR_NULL_PTR HI_ERR_HDMI_NUL_PTR 54 #endif 55 #define HDMI_DECIMAL 10 56 #define HDMI_HUNDRED 100 57 #define HDMI_THOUSAND 1000 58 #define FMT_PIX_CLK_13400 13400 59 #define FMT_PIX_CLK_74250 74250 60 #define FMT_PIX_CLK_165000 165000 61 #define FMT_PIX_CLK_190000 190000 62 #define FMT_PIX_CLK_297000 297000 63 #define FMT_PIX_CLK_340000 340000 64 #define ZERO_DRMIF_SEND_TIME 2000 /* unit: ms */ 65 #define HDRMODE_CHANGE_TIME 500 /* unit: ms */ 66 #define HDMI_EDID_BLOCK_SIZE 128 67 #define HDMI_EDID_TOTAL_BLOCKS 4 68 #define HDMI_EDID_SIZE (HDMI_EDID_BLOCK_SIZE * HDMI_EDID_TOTAL_BLOCKS) 69 #define HDMI_REGISTER_SIZE 4 70 #define hdmi_array_size(a) (sizeof(a) / sizeof(a[0])) 71 #ifdef HDMI_FPGA_SUPPORT 72 #define FPGA_SUPPORT HI_TRUE 73 #else 74 #define FPGA_SUPPORT HI_FALSE 75 #endif 76 #define FRL_CTRL_TYPE_COMPRESS_ALL 0x00 77 #define FRL_CTRL_TYPE_COMPRESS_HW 0x01 78 #define FRL_CTRL_TYPE_COMPRESS_NON 0x03 79 #define HDMI_FRL_COMPRESS_DEBUG_MASK 0x4 80 81 /* AVI InfoFrame Packet byte offset define */ 82 #define AVI_OFFSET_TYPE 0 83 #define AVI_OFFSET_VERSION 1 84 #define AVI_OFFSET_LENGTH 2 85 #define AVI_OFFSET_CHECKSUM 3 86 87 #define hdmi_unequal_eok_return(ret, err_code) \ 88 do { \ 89 if ((ret) != EOK) { \ 90 hdmi_err("secure function error:%d\n", (ret)); \ 91 return (err_code); \ 92 } \ 93 } while (0) 94 95 #define hdmi_unequal_eok_return_void(ret) \ 96 do { \ 97 if ((ret) != EOK) { \ 98 hdmi_err("secure function error:%d\n", (ret)); \ 99 return; \ 100 } \ 101 } while (0) 102 103 #define hdmi_unlock_unequal_eok_return(ret, mutex, err_code) \ 104 do { \ 105 if ((ret) != EOK) { \ 106 hdmi_err("secure function error:%d\n", (ret)); \ 107 hdmi_mutex_unlock((mutex)); \ 108 return (err_code); \ 109 } \ 110 } while (0) 111 112 #define hdmi_unlock_if_null_return(p, mutex, err_code) \ 113 do { \ 114 if ((p) == HI_NULL) { \ 115 hdmi_err("This is null pointer!\n"); \ 116 hdmi_mutex_unlock((mutex)); \ 117 return (err_code); \ 118 } \ 119 } while (0) 120 121 #define hdmi_if_null_return(p, ret) \ 122 do { \ 123 if ((p) == HI_NULL) { \ 124 hdmi_err("%s is null pointer!\n", #p); \ 125 return (ret); \ 126 } \ 127 } while (0) 128 129 #define hdmi_if_null_return_void(p) \ 130 do { \ 131 if ((p) == HI_NULL) { \ 132 hdmi_err("%s is null pointer!\n", #p); \ 133 return; \ 134 } \ 135 } while (0) 136 137 #define hdmi_if_null_warn_return(p, ret) \ 138 do { \ 139 if ((p) == HI_NULL) { \ 140 hdmi_warn("%s is null pointer!\n", #p); \ 141 return (ret); \ 142 } \ 143 } while (0) 144 145 #define hdmi_if_null_warn_return_void(p) \ 146 do { \ 147 if ((p) == HI_NULL) { \ 148 hdmi_warn("%s is null pointer!\n", #p); \ 149 return; \ 150 } \ 151 } while (0) 152 153 #define hdmi_if_false_return_void(b) \ 154 do { \ 155 if ((b) != HI_TRUE) { \ 156 hdmi_err("%s is FALSE!\n", #b); \ 157 return; \ 158 } \ 159 } while (0) 160 161 #define hdmi_if_false_return(tmp, ret) \ 162 do { \ 163 if ((tmp) != HI_TRUE) { \ 164 hdmi_err("%s is FALSE!\n", #tmp); \ 165 return (ret); \ 166 } \ 167 } while (0) 168 169 #define hdmi_if_false_warn_return(tmp, ret) \ 170 do { \ 171 if ((tmp) != HI_TRUE) { \ 172 hdmi_warn("%s is FALSE!\n", #tmp); \ 173 return (ret); \ 174 } \ 175 } while (0) 176 177 #define hdmi_if_false_warn_return_void(tmp) \ 178 do { \ 179 if ((tmp) != HI_TRUE) { \ 180 hdmi_warn("%s is FALSE!\n", #tmp); \ 181 return; \ 182 } \ 183 } while (0) 184 185 #define hdmi_check_is_change_return(tmp0, tmp1, ret) \ 186 do { \ 187 if ((tmp0) != (tmp1)) { \ 188 hdmi_info("%s change, old(%u)->new(%u) \n", #tmp0, (hi_u32)(tmp0), (hi_u32)(tmp1)); \ 189 return (ret); \ 190 } \ 191 } while (0) 192 193 #define hdmi_check_max_return(value, max, ret) \ 194 do { \ 195 if ((value) > (max)) { \ 196 hdmi_warn("value %u exceed max!\n", (hi_u32)(value)); \ 197 return (ret); \ 198 } \ 199 } while (0) 200 201 #define hdmi_if_failure_return(tmp, ret) \ 202 do { \ 203 if ((tmp) != HI_SUCCESS) { \ 204 hdmi_err("%s is failure!\n", #tmp); \ 205 return (ret); \ 206 } \ 207 } while (0) 208 209 #define hdmi_if_failure_return_void(tmp) \ 210 do { \ 211 if ((tmp) != HI_SUCCESS) { \ 212 hdmi_err("%s is failure!\n", #tmp); \ 213 return; \ 214 } \ 215 } while (0) 216 #define hdmi_if_failure_warn_return_void(tmp) \ 217 do { \ 218 if ((tmp) != HI_SUCCESS) { \ 219 hdmi_warn("%s is failure!\n", #tmp); \ 220 return; \ 221 } \ 222 } while (0) 223 224 #define hdmi_set_bit(var, bit) \ 225 do { \ 226 (var) |= 1 << (bit); \ 227 } while (0) 228 229 #define hdmi_clr_bit(var, bit) \ 230 do { \ 231 (var) &= ~(1 << (bit)); \ 232 } while (0) 233 234 #define hdmi_if_fpga_return(ret) \ 235 do { \ 236 if (FPGA_SUPPORT) { \ 237 hdmi_warn("FPGA CFG!\n"); \ 238 return(ret); \ 239 } \ 240 } while (0) 241 242 #define hdmi_if_fpga_return_void() \ 243 do { \ 244 if (FPGA_SUPPORT) { \ 245 hdmi_warn("FPGA CFG!\n"); \ 246 return; \ 247 } \ 248 } while (0) 249 250 #define is_bit_set(var, bit) ({ (var) & (0x1 << (bit)) ? HI_TRUE : HI_FALSE; }) 251 252 #ifdef HDMI_LITEOS_SUPPORT 253 #define max(a, b) (((a) < (b)) ? (b) : (a)) 254 #define min(a, b) (((a) > (b)) ? (b) : (a)) 255 #endif 256 257 #define hal_call_ret(ret, func, param...) \ 258 do { \ 259 if (hdmi_dev != HI_NULL && hdmi_dev->hal != HI_NULL && \ 260 hdmi_dev->hal->func != HI_NULL) { \ 261 ret = hdmi_dev->hal->func(param); \ 262 } else { \ 263 ret = HI_ERR_NULL_PTR; \ 264 } \ 265 } while (0) 266 267 #define hal_call_void(func, param...) \ 268 do { \ 269 if (hdmi_dev != HI_NULL && hdmi_dev->hal != HI_NULL && \ 270 hdmi_dev->hal->func != HI_NULL) { \ 271 hdmi_dev->hal->func(param); \ 272 } else { \ 273 hdmi_warn("null pointer! \n"); \ 274 } \ 275 } while (0) 276 277 #define hdmi_if_zero_return_void(x) \ 278 do { \ 279 if ((x) == 0) { \ 280 hdmi_err("%s is zero!\n", #x); \ 281 return; \ 282 } \ 283 } while (0) 284 285 typedef enum { 286 CHIP_HI3559AV100, 287 CHIP_HI3516CV500, 288 CHIP_HI3519AV100, 289 CHIP_HI3531DV200, 290 CHIP_BUTT 291 } hdmi_chip_type; 292 293 typedef enum { 294 HDMI_DEVICE_ID0, 295 HDMI_DEVICE_ID_BUTT 296 } hdmi_device_id; 297 298 typedef enum { 299 HDMI_THREAD_STATE_RUN, 300 HDMI_THREAD_STATE_STOP 301 } hdmi_thread_state; 302 303 typedef enum { 304 HDMI_EVENT_HOTPLUG = 0x10, 305 HDMI_EVENT_HOTUNPLUG, 306 HDMI_EVENT_EDID_FAIL, 307 HDMI_EVENT_HDCP_FAIL, 308 HDMI_EVENT_HDCP_SUCCESS, 309 HDMI_EVENT_RSEN_CONNECT, 310 HDMI_EVENT_RSEN_DISCONNECT, 311 HDMI_EVENT_HDCP_USERSETTING, 312 HDMI_EVENT_HDCP_OFF, 313 HDMI_EVENT_SCRAMBLE_FAIL, 314 HDMI_EVENT_SCRAMBLE_SUCCESS, 315 HDMI_EVENT_ZERO_DRMIF_TIMEOUT, 316 HDMI_EVENT_SWITCH_TO_HDRMODE_TIMEOUT, 317 HDMI_EVENT_BUTT 318 } hdmi_event; 319 320 typedef enum { 321 HDMI_INT_TYPE_NONE, 322 HDMI_INT_TYPE_HPD_RSEN, 323 HDMI_INT_TYPE_HDCP, 324 HDMI_INT_TYPE_HDCP2X, 325 HDMI_INT_TYPE_CEC 326 } hdmi_int_type; 327 328 typedef hi_s32 (*hdmi_callback)(hi_void *, hdmi_event); 329 330 typedef struct { 331 hi_void *event_data; 332 hdmi_callback event_callback; 333 hi_u32 hdmi_dev_id; 334 hi_char *base_addr; 335 hi_char *phy_addr; 336 } hdmi_hal_init; 337 338 typedef struct { 339 hdmi_colorimetry colorimetry; 340 hdmi_quant_range quantization; 341 hdmi_pixel_encoding pixel_encoding; 342 } hdmi_csc_attr; 343 344 typedef struct { 345 hi_u8 edid_valid; 346 hi_u32 edid_len; 347 hi_u8 edid[HDMI_EDID_SIZE]; 348 } hdmi_edid_raw_data; 349 350 typedef struct { 351 hi_u8 *input_encrypted_key_addr; 352 hi_u32 key_length; 353 } hdmi_load_key; 354 355 typedef struct { 356 hi_u32 input_encrypted_key_addr; 357 hi_u32 key_length; 358 } hdmi_compat_load_key; 359 360 typedef enum { 361 HDMI_HDCP_VERSION_NONE, 362 HDMI_HDCP_VERSION_1_4, 363 HDMI_HDCP_VERSION_2_2, 364 HDMI_HDCP_VERSION_BUTT 365 } hdmi_hdcp_version; 366 367 typedef struct { 368 hi_bool connected; 369 hi_bool sink_power_on; 370 hi_bool authed; 371 hi_u8 bksv[5]; 372 hdmi_hdcp_version hdcp_version; 373 } hdmi_status; 374 375 typedef struct { 376 hi_u32 i_de_main_clk; 377 hi_u32 i_de_main_data; 378 hi_u32 i_main_clk; 379 hi_u32 i_main_data; 380 hi_u32 ft_cap_clk; 381 hi_u32 ft_cap_data; 382 } hdmi_hw_param; 383 384 typedef struct { 385 hdmi_hw_param hw_param[4]; 386 } hdmi_hw_spec; 387 388 typedef struct { 389 hdmi_hw_spec hwspec_user; 390 hdmi_hw_spec hwspec_def; 391 hdmi_hw_param hwparam_cur; 392 } hdmi_hwspec; 393 394 /* HDMI deep color mode */ 395 typedef enum { 396 HDMI_DEEP_COLOR_24BIT, 397 HDMI_DEEP_COLOR_30BIT, 398 HDMI_DEEP_COLOR_36BIT, 399 HDMI_DEEP_COLOR_48BIT, 400 HDMI_DEEP_COLOR_OFF = 0xff, 401 HDMI_DEEP_COLOR_BUTT 402 } hdmi_deep_color; 403 404 typedef enum { 405 HDMI_VIDEO_BITDEPTH_8, 406 HDMI_VIDEO_BITDEPTH_10, 407 HDMI_VIDEO_BITDEPTH_12, 408 HDMI_VIDEO_BITDEPTH_16, 409 HDMI_VIDEO_BITDEPTH_OFF, 410 HDMI_VIDEO_BITDEPTH_BUTT 411 } hdmi_video_bit_depth; 412 413 typedef enum { 414 HDMI_HV_SYNC_POL_HPVP, 415 HDMI_HV_SYNC_POL_HPVN, 416 HDMI_HV_SYNC_POL_HNVP, 417 HDMI_HV_SYNC_POL_HNVN, 418 HDMI_HV_SYNC_POL_BUTT 419 } hdmi_hvsync_polarity; 420 421 typedef enum { 422 HDMI_PICTURE_NON_UNIFORM__SCALING, 423 HDMI_PICTURE_SCALING__H, 424 HDMI_PICTURE_SCALING__V, 425 HDMI_PICTURE_SCALING__HV 426 } hdmi_picture_scaling; 427 428 typedef struct { 429 hi_u32 clk_fs; /* VDP setting(in) */ 430 hi_u32 tmds_clk; 431 hi_u32 hdmi_adapt_pix_clk; /* HDMI adapt setting(out) */ 432 hi_u32 pixel_repeat; 433 hi_bool v_sync_pol; 434 hi_bool h_sync_pol; 435 hi_bool de_pol; 436 hdmi_video_timing video_timing; 437 hdmi_3d_mode stereo_mode; 438 hdmi_colorspace in_color_space; 439 hdmi_colormetry colorimetry; 440 hdmi_extended_colormetry extended_colorimetry; 441 hdmi_quantization_range rgb_quantization; 442 hdmi_ycc_quantization_range ycc_quantization; 443 hdmi_picture_aspect picture_aspect; 444 hdmi_active_aspect active_aspect; 445 hdmi_picture_scaling picture_scaling; 446 hdmi_video_bit_depth in_bit_depth; 447 hdmi_disp_format disp_fmt; 448 } hdmi_vo_attr; 449 450 typedef enum { 451 HDMI_AUDIO_FORMAT_2CH = 0x02, 452 HDMI_AUDIO_FORMAT_3CH, 453 HDMI_AUDIO_FORMAT_4CH, 454 HDMI_AUDIO_FORMAT_5CH, 455 HDMI_AUDIO_FORMAT_6CH, 456 HDMI_AUDIO_FORMAT_7CH, 457 HDMI_AUDIO_FORMAT_8CH, 458 HDMI_AUDIO_FORMAT_BUTT 459 } hdmi_audio_ch; 460 461 typedef enum { 462 HDMI_AUDIO_INTF_I2S, 463 HDMI_AUDIO_INTF_SPDIF, 464 HDMI_AUDIO_INTF_HBRA, 465 HDMI_AUDIO_INTF_BUTT 466 } hdmi_audio_interface; 467 468 typedef enum { 469 HDMI_AUDIO_BIT_DEPTH_UNKNOWN, 470 HDMI_AUDIO_BIT_DEPTH_8 = 8, 471 HDMI_AUDIO_BIT_DEPTH_16 = 16, 472 HDMI_AUDIO_BIT_DEPTH_18 = 18, 473 HDMI_AUDIO_BIT_DEPTH_20 = 20, 474 HDMI_AUDIO_BIT_DEPTH_24 = 24, 475 HDMI_AUDIO_BIT_DEPTH_32 = 32, 476 HDMI_AUDIO_BIT_DEPTH_BUTT 477 } hdmi_audio_bit_depth; 478 479 typedef enum { 480 HDMI_SAMPLE_RATE_UNKNOWN, 481 HDMI_SAMPLE_RATE_8K = 8000, 482 HDMI_SAMPLE_RATE_11K = 11025, 483 HDMI_SAMPLE_RATE_12K = 12000, 484 HDMI_SAMPLE_RATE_16K = 16000, 485 HDMI_SAMPLE_RATE_22K = 22050, 486 HDMI_SAMPLE_RATE_24K = 24000, 487 HDMI_SAMPLE_RATE_32K = 32000, 488 HDMI_SAMPLE_RATE_44K = 44100, 489 HDMI_SAMPLE_RATE_48K = 48000, 490 HDMI_SAMPLE_RATE_88K = 88200, 491 HDMI_SAMPLE_RATE_96K = 96000, 492 HDMI_SAMPLE_RATE_176K = 176400, 493 HDMI_SAMPLE_RATE_192K = 192000, 494 HDMI_SAMPLE_RATE_768K = 768000, 495 HDMI_SAMPLE_RATE_BUTT 496 } hdmi_sample_rate; 497 498 typedef struct { 499 hi_bool down_sample; 500 hdmi_sample_rate sample_fs; 501 hdmi_audio_ch channels; 502 hdmi_audio_interface sound_intf; 503 hdmi_audio_bit_depth sample_depth; 504 hdmi_audio_format_code audio_code; 505 } hdmi_ao_attr; 506 507 typedef enum { 508 HDMI_TMDS_MODE_NONE, 509 HDMI_TMDS_MODE_DVI, 510 HDMI_TMDS_MODE_HDMI_1_4, 511 HDMI_TMDS_MODE_HDMI_2_0, 512 HDMI_TMDS_MODE_AUTO, 513 HDMI_TMDS_MODE_HDMI_2_1, 514 HDMI_TMDS_MODE_BUTT 515 } hdmi_tmds_mode; 516 517 typedef enum { 518 HDMI_HDCP_MODE_AUTO, 519 HDMI_HDCP_MODE_1_4, 520 HDMI_HDCP_MODE_2_2, 521 HDMI_HDCP_MODE_BUTT 522 } hdmi_hdcp_mode; 523 524 typedef enum { 525 HDMI_DEFAULT_ACTION_NULL, 526 HDMI_DEFAULT_ACTION_HDMI, 527 HDMI_DEFAULT_ACTION_DVI, 528 HDMI_DEFAULT_ACTION_BUTT 529 } hdmi_default_action; 530 531 typedef enum { 532 HDMI_VIDEO_DITHER_12_10, 533 HDMI_VIDEO_DITHER_12_8, 534 HDMI_VIDEO_DITHER_10_8, 535 HDMI_VIDEO_DITHER_DISABLE 536 } hdmi_video_dither; 537 538 typedef struct { 539 hi_bool enable_hdmi; 540 hi_bool enable_video; 541 hi_bool enable_audio; 542 hdmi_colorspace out_color_space; 543 hdmi_quantization_range out_csc_quantization; 544 hdmi_deep_color deep_color_mode; 545 hi_bool xvycc_mode; 546 hi_bool enable_avi_infoframe; 547 hi_bool enable_spd_infoframe; 548 hi_bool enable_mpeg_infoframe; 549 hi_bool enable_aud_infoframe; 550 hi_u32 debug_flag; 551 hi_bool hdcp_enable; 552 hdmi_default_action hdmi_action; 553 hi_bool enable_clr_space_adapt; 554 hi_bool enable_deep_clr_adapt; 555 hi_bool auth_mode; 556 hi_bool enable_drm_infoframe; 557 hdmi_hdcp_mode hdcp_mode; 558 hi_bool enable_vsif_dolby; 559 } hdmi_app_attr; 560 561 typedef enum { 562 HDMI_HDR_COLORIMETRY_NONE, 563 HDMI_HDR_COLORIMETRY_ITU_601, 564 HDMI_HDR_COLORIMETRY_ITU_709, 565 HDMI_HDR_COLORIMETRY_EXTENDED, 566 HDMI_HDR_EXTENDED_COLORIMETRY_XV_YCC_601, 567 HDMI_HDR_EXTENDED_COLORIMETRY_XV_YCC_709, 568 HDMI_HDR_EXTENDED_COLORIMETRY_S_YCC_601, 569 HDMI_HDR_EXTENDED_COLORIMETRY_ADOBE_YCC_601, 570 HDMI_HDR_EXTENDED_COLORIMETRY_ADOBE_RGB, 571 HDMI_HDR_EXTENDED_COLORIMETRY_2020_CONST_LUMINOUS, /* BT2020 c_ycc */ 572 HDMI_HDR_EXTENDED_COLORIMETRY_2020_NON_CONST_LUMINOUW 573 } hdmi_hdr_colormetry; 574 575 typedef enum { 576 HDMI_HDR_MODE_DISABLE, /* HDR & dolby mode disable */ 577 HDMI_HDR_MODE_DOLBY_NORMAL, /* dolby normal(ycbcr422-12bit) mode enable */ 578 HDMI_HDR_MODE_DOLBY_TUNNELING, /* dolby tunneling(RGB-8bit) mode enable */ 579 HDMI_HDR_MODE_CEA_861_3, /* HDR standard mode enable(according to <CEA-861-3.2015>) */ 580 HDMI_HDR_MODE_CEA_861_3_AUTHEN, /* HDR authen mode */ 581 HDMI_HDR_MODE_BUTT 582 } drv_hdmi_hdr_mode; 583 584 typedef enum { 585 HDMI_HDR_USERMODE_SDR, 586 HDMI_HDR_USERMODE_HDR10, 587 HDMI_HDR_USERMODE_DOLBY, 588 HDMI_HDR_USERMODE_BUTT 589 } drv_hdmi_hdr_user_mode; 590 591 typedef struct { 592 drv_hdmi_hdr_mode hdr_mode; /* HDR mode */ 593 drv_hdmi_hdr_user_mode user_hdr_mode; /* user HDR mode */ 594 hdmi_eotf_type eotf_type; /* EOTF type. when hdr_mode==HI_UNF_HDMI_HDR_MODE_CEA_861_3 valid */ 595 /* metadata descriptor type(ID). when hdr_mode==HI_UNF_HDMI_HDR_MODE_CEA_861_3 valid */ 596 hdmi_static_meta_type_id metadata_id; 597 /* static metadata descriptor type. when hdr_mode==HI_UNF_HDMI_HDR_MODE_CEA_861_3 valid */ 598 hdmi_meta_descriptor un_descriptor; 599 hdmi_hdr_colormetry colorimetry; /* colorimetry. when hdr_mode==HI_UNF_HDMI_HDR_MODE_CEA_861_3 valid */ 600 } drv_hdmi_hdr_attr; 601 602 typedef struct { 603 hi_bool enable_hdmi; 604 hi_bool enable_video; 605 hdmi_disp_format disp_fmt; 606 hdmi_video_timing video_timing; 607 hi_u32 pix_clk; 608 hdmi_colorspace in_color_space; 609 hdmi_colorspace out_color_space; 610 hdmi_deep_color deep_color_mode; 611 hdmi_quantization_range out_csc_quantization; 612 hi_bool enable_audio; 613 hdmi_sample_rate sample_rate; 614 hdmi_audio_bit_depth bit_depth; 615 hi_bool enable_avi_infoframe; 616 hi_bool enable_aud_infoframe; 617 hdmi_default_action hdmi_action; 618 hi_bool enable_vid_mode_adapt; 619 hi_bool enable_deep_clr_adapt; 620 hi_bool auth_mode; 621 } hdmi_property; 622 623 typedef struct { 624 hdmi_ao_attr ao_attr; 625 hdmi_vo_attr vo_attr; 626 hdmi_app_attr app_attr; 627 #ifdef HDMI_HDR_SUPPORT 628 drv_hdmi_hdr_attr hdr_attr; 629 #endif 630 } hdmi_attr; 631 632 typedef enum { 633 HDMI_CEC_LOGICALADD_TV, 634 HDMI_CEC_LOGICALADD_RECORDDEV_1, 635 HDMI_CEC_LOGICALADD_RECORDDEV_2, 636 HDMI_CEC_LOGICALADD_TUNER_1, 637 HDMI_CEC_LOGICALADD_PLAYDEV_1, 638 HDMI_CEC_LOGICALADD_AUDIOSYSTEM, 639 HDMI_CEC_LOGICALADD_TUNER_2, 640 HDMI_CEC_LOGICALADD_TUNER_3, 641 HDMI_CEC_LOGICALADD_PLAYDEV_2, 642 HDMI_CEC_LOGICALADD_RECORDDEV_3, 643 HDMI_CEC_LOGICALADD_TUNER_4, 644 HDMI_CEC_LOGICALADD_PLAYDEV_3, 645 HDMI_CEC_LOGICALADD_RESERVED_1, 646 HDMI_CEC_LOGICALADD_RESERVED_2, 647 HDMI_CEC_LOGICALADD_SPECIALUSE, 648 HDMI_CEC_LOGICALADD_BROADCAST, 649 HDMI_CEC_LOGICALADD_BUTT 650 } hdmi_cec_logical_addr; 651 652 typedef enum { 653 HDMI_CEC_UICMD_SELECT, 654 HDMI_CEC_UICMD_UP, 655 HDMI_CEC_UICMD_DOWN, 656 HDMI_CEC_UICMD_LEFT, 657 HDMI_CEC_UICMD_RIGHT, 658 HDMI_CEC_UICMD_RIGHT_UP, 659 HDMI_CEC_UICMD_RIGHT_DOWN, 660 HDMI_CEC_UICMD_LEFT_UP, 661 HDMI_CEC_UICMD_LEFT_DOWN, 662 HDMI_CEC_UICMD_ROOT_MENU, 663 HDMI_CEC_UICMD_SETUP_MENU, 664 HDMI_CEC_UICMD_CONTENTS_MENU, 665 HDMI_CEC_UICMD_FAVORITE_MENU, 666 HDMI_CEC_UICMD_EXIT, 667 HDMI_CEC_UICMD_NUM_0 = 0x20, 668 HDMI_CEC_UICMD_NUM_1, 669 HDMI_CEC_UICMD_NUM_2, 670 HDMI_CEC_UICMD_NUM_3, 671 HDMI_CEC_UICMD_NUM_4, 672 HDMI_CEC_UICMD_NUM_5, 673 HDMI_CEC_UICMD_NUM_6, 674 HDMI_CEC_UICMD_NUM_7, 675 HDMI_CEC_UICMD_NUM_8, 676 HDMI_CEC_UICMD_NUM_9, 677 HDMI_CEC_UICMD_DOT, 678 HDMI_CEC_UICMD_ENTER, 679 HDMI_CEC_UICMD_CLEAR, 680 HDMI_CEC_UICMD_NEXT_FAVORITE = 0x2F, 681 HDMI_CEC_UICMD_CHANNEL_UP, 682 HDMI_CEC_UICMD_CHANNEL_DOWN, 683 HDMI_CEC_UICMD_PREVIOUS_CHANNEL, 684 HDMI_CEC_UICMD_SOUND_SELECT, 685 HDMI_CEC_UICMD_INPUT_SELECT, 686 HDMI_CEC_UICMD_DISPLAY_INFORMATION, 687 HDMI_CEC_UICMD_HELP, 688 HDMI_CEC_UICMD_PAGE_UP, 689 HDMI_CEC_UICMD_PAGE_DOWN, 690 HDMI_CEC_UICMD_POWER = 0x40, 691 HDMI_CEC_UICMD_VOLUME_UP, 692 HDMI_CEC_UICMD_VOLUME_DOWN, 693 HDMI_CEC_UICMD_MUTE, 694 HDMI_CEC_UICMD_PLAY, 695 HDMI_CEC_UICMD_STOP, 696 HDMI_CEC_UICMD_PAUSE, 697 HDMI_CEC_UICMD_RECORD, 698 HDMI_CEC_UICMD_REWIND, 699 HDMI_CEC_UICMD_FAST_FORWARD, 700 HDMI_CEC_UICMD_EJECT, 701 HDMI_CEC_UICMD_FORWARD, 702 HDMI_CEC_UICMD_BACKWARD, 703 HDMI_CEC_UICMD_STOP_RECORD, 704 HDMI_CEC_UICMD_PAUSE_RECORD, 705 HDMI_CEC_UICMD_ANGLE = 0x50, 706 HDMI_CEC_UICMD_SUBPICTURE, 707 HDMI_CEC_UICMD_VIDEO_ON_DEMAND, 708 HDMI_CEC_UICMD_ELECTRONIC_PROGRAM_GUIDE, 709 HDMI_CEC_UICMD_TIMER_PROGRAMMING, 710 HDMI_CEC_UICMD_INITIAL_CONFIGURATION, 711 HDMI_CEC_UICMD_PLAY_FUNCTION = 0x60, 712 HDMI_CEC_UICMD_PAUSE_PLAY_FUNCTION, 713 HDMI_CEC_UICMD_RECORD_FUNCTION, 714 HDMI_CEC_UICMD_PAUSE_RECORD_FUNCTION, 715 HDMI_CEC_UICMD_STOP_FUNCTION, 716 HDMI_CEC_UICMD_MUTE_FUNCTION, 717 HDMI_CEC_UICMD_RESTORE_VOLUME_FUNCTION, 718 HDMI_CEC_UICMD_TUNE_FUNCTION, 719 HDMI_CEC_UICMD_SELECT_MEDIA_FUNCTION, 720 HDMI_CEC_UICMD_SELECT_AV_INPUT_FUNCTION, 721 HDMI_CEC_UICMD_SELECT_AUDIO_INPUT_FUNCTION, 722 HDMI_CEC_UICMD_POWER_TOGGLE_FUNCTION, 723 HDMI_CEC_UICMD_POWER_OFF_FUNCTION, 724 HDMI_CEC_UICMD_POWER_ON_FUNCTION, 725 HDMI_CEC_UICMD_F1_BLUE = 0x71, 726 HDMI_CEC_UICMD_F2_RED, 727 HDMI_CEC_UICMD_F3_GREEN, 728 HDMI_CEC_UICMD_F4_YELLOW, 729 HDMI_CEC_UICMD_F5, 730 HDMI_CEC_UICMD_DATA, 731 HDMI_CEC_UICMD_REPORT_PHYADDR = 0x84 732 } hdmi_cec_ui_cmd; 733 734 typedef struct { 735 hi_u8 length; 736 hi_u8 data[15]; 737 } hdmi_cec_raw_data; 738 739 typedef struct { 740 hi_u8 opcode; 741 hdmi_cec_logical_addr src_addr; 742 hdmi_cec_logical_addr dst_addr; 743 hdmi_cec_raw_data raw_data; 744 } hdmi_cec_cmd; 745 746 typedef struct { 747 hi_bool cec_enable; 748 hi_u8 physical_addr[4]; 749 hi_u32 recieve_cnt; /* receive message count */ 750 hi_bool net_valid; /* logical_addr & au8_network valid flag */ 751 hi_u8 logical_addr; 752 hi_u8 network[HDMI_CEC_LOGICALADD_BUTT]; 753 } hdmi_cec_info; 754 755 typedef enum { 756 HDMI_TRANSITION_NONE, 757 HDMI_TRANSITION_BOOT_MCE, 758 HDMI_TRANSITION_MCE_APP, 759 HDMI_TRANSITION_BOOT_APP = 0x4 760 } hdmi_transition_state; 761 762 typedef enum { 763 HDMI_RUN_STATE_NONE, 764 HDMI_RUN_STATE_INIT, 765 HDMI_RUN_STATE_OPEN, 766 HDMI_RUN_STATE_START = 0x04, 767 HDMI_RUN_STATE_STOP = 0x08, 768 HDMI_RUN_STATE_CLOSE = 0x10, 769 HDMI_RUN_STATE_DEINIT = 0x20 770 } hdmi_run_state; 771 772 typedef struct { 773 hi_u16 length; 774 hi_u8 *list; 775 hi_u8 *list_start; 776 } hdmi_hdcp_ksv_list; 777 778 typedef enum { 779 HDMI_HDCP_SINK_UNKNOWN, 780 HDMI_HDCP_SINK_SUPPORT, 781 HDMI_HDCP_SINK_NOSUPPORT 782 } hdmi_hdcp_support; 783 784 typedef struct { 785 hi_bool hdcp_is_on; 786 hi_bool hdcp_was_on; 787 hi_bool hdcp1_prep; 788 hi_bool hdcp2_prep; 789 hi_bool hdcp_auth_suc; 790 hdmi_hdcp_support hdcp14_support; 791 hdmi_hdcp_support hdcp22_support; 792 hdmi_hdcp_mode hdcp_mode; 793 } hdmi_hdcp_info; 794 795 typedef enum { 796 HDMI_TX_SUPPORT_HDMI1_4 = 0x1, 797 HDMI_TX_SUPPORT_HDMI2_0 = 0x2, 798 HDMI_TX_SUPPORT_HDCP1_4 = 0x4, 799 HDMI_TX_SUPPORT_HDCP2_2 = 0x8, 800 HDMI_TX_SUPPORT_YUV420 = 0x10, 801 HDMI_TX_SUPPORT_YUV420_422 = 0x20, 802 HDMI_TX_SUPPORT_YUV422_444 = 0x40, 803 HDMI_TX_SUPPORT_YUV444_422 = 0x80, 804 HDMI_TX_SUPPORT_YUV422_420 = 0x100, 805 HDMI_TX_SUPPORT_YUV2RGB = 0x200, 806 HDMI_TX_SUPPORT_RGB2YUV = 0x400, 807 HDMI_TX_SUPPORT_SCRAMBLE = 0x800 808 } hdmi_tx_capability; 809 810 typedef struct { 811 hi_bool tx_hdmi_14; 812 hi_bool tx_hdmi_20; 813 hi_bool tx_hdmi_21; 814 hi_bool tx_hdcp_14; 815 hi_bool tx_hdcp_22; 816 hi_bool tx_rgb444; 817 hi_bool tx_ycbcr444; 818 hi_bool tx_ycbcr422; 819 hi_bool tx_ycbcr420; 820 hi_bool tx_deep_clr10_bit; 821 hi_bool tx_deep_clr12_bit; 822 hi_bool tx_deep_clr16_bit; 823 hi_bool tx_rgb_ycbcr444; 824 hi_bool tx_ycbcr444_422; 825 hi_bool tx_ycbcr422_420; 826 hi_bool tx_ycbcr420_422; 827 hi_bool tx_ycbcr422_444; 828 hi_bool tx_ycbcr444_rgb; 829 hi_bool tx_scdc; 830 hi_u32 tx_max_tmds_clk; 831 hi_u32 tx_max_frl_rate; 832 } hdmi_tx_capability_data; 833 834 typedef enum { 835 HDMI_CONV_STD_BT_709, 836 HDMI_CONV_STD_BT_601, 837 HDMI_CONV_STD_BT_2020_NON_CONST_LUMINOUS, 838 HDMI_CONV_STD_BT_2020_CONST_LUMINOUS, 839 HDMI_CONV_STD_BUTT 840 } hdmi_conversion_stb; 841 842 typedef struct { 843 hdmi_video_timing timing; 844 hi_u32 pixel_clk; 845 hi_u32 tmds_clk; 846 hi_bool v_sync_pol; 847 hi_bool h_sync_pol; 848 hi_bool de_pol; 849 hdmi_conversion_stb conv_std; 850 hdmi_quantization_range quantization; 851 hdmi_colorspace in_color_space; 852 hdmi_colorspace out_color_space; 853 hdmi_deep_color deep_color; 854 hdmi_video_bit_depth in_bit_depth; 855 hdmi_quantization_range out_csc_quantization; 856 hi_bool emi_enable; 857 } hdmi_video_config; 858 859 typedef struct { 860 hi_bool enable_audio; 861 hi_bool down_sample; 862 hi_u32 tmds_clk; 863 hi_u32 pixel_repeat; 864 hdmi_sample_rate sample_fs; 865 hdmi_audio_ch layout; 866 hdmi_audio_interface sound_intf; 867 hdmi_audio_bit_depth sample_depth; 868 } hdmi_audio_config; 869 870 typedef enum { 871 HDMI_FRL_MODE_TMDS, 872 HDMI_FRL_MODE_FRL, 873 HDMI_FRL_MODE_BUTT 874 } hdmi_frl_mode; 875 876 typedef struct { 877 hdmi_sample_rate sample_rate; 878 hdmi_frl_mode hdmi_mode; 879 hi_u8 frl_rate; 880 hi_u32 pixel_clk; 881 } hdmi_audio_ncts; 882 883 typedef struct { 884 hi_bool phy_oe; 885 hi_bool phy_power_on; 886 hdmi_video_bit_depth deep_color; 887 } hdmi_phy_status; 888 889 typedef struct { 890 hi_bool sw_emi_enable; 891 hi_bool hw_emi_enable; 892 hi_bool debug_enable; 893 } hdmi_emi_status; 894 895 typedef struct { 896 hi_bool video_mute; 897 hi_bool ycbcr2rgb; 898 hi_bool rgb2ycbcr; 899 hi_bool ycbcr444_422; 900 hi_bool ycbcr422_420; 901 hi_bool ycbcr420_422; 902 hi_bool ycbcr422_444; 903 hi_bool in420_ydemux; 904 hi_bool out420_ydemux; 905 hdmi_video_dither dither; 906 hi_bool v_sync_pol; 907 hi_bool h_sync_pol; 908 hi_bool sync_pol; 909 hi_bool de_pol; 910 hi_bool swap_hs_cs; 911 hdmi_colorspace in_color_space; 912 hdmi_colorspace out_color_space; 913 hdmi_video_bit_depth out_bit_depth; 914 hdmi_hvsync_polarity hv_sync_pol; 915 hdmi_quantization_range out_csc_quantization; 916 #if defined(HDMI_SUPPORT_LOGIC_HISIV100) 917 /* detect timing */ 918 hi_bool sync_sw_enable; 919 hi_bool vsync_polarity; /* when sync_sw_enable==0,indicates hw;or ,indicates sw */ 920 hi_bool hsync_polarity; /* when sync_sw_enable==0,indicates hw;or ,indicates sw */ 921 hi_bool progressive; 922 hi_u32 hsync_total; 923 hi_u32 hactive_cnt; 924 hi_u32 vsync_total; 925 hi_u32 vactive_cnt; 926 #endif 927 } hdmi_video_status; 928 929 typedef struct { 930 hi_bool hdcp14_support; 931 hi_bool hdcp22_support; 932 } hdmi_hdcp_capability; 933 934 typedef struct { 935 hi_bool audio_mute; 936 hi_bool audio_enable; 937 hi_bool down_sample; 938 hdmi_sample_rate sample_fs; 939 hdmi_audio_ch layout; 940 hdmi_audio_interface sound_intf; 941 hdmi_audio_bit_depth sample_depth; 942 hi_u32 ref_n; 943 hi_u32 reg_n; 944 hi_u32 ref_cts; 945 hi_u32 reg_cts; 946 } hdmi_audio_status; 947 948 typedef struct { 949 hi_bool hotplug; 950 hi_bool rsen; 951 hi_bool avmute; 952 hdmi_tmds_mode tmds_mode; 953 } hdmi_common_status; 954 955 typedef struct { 956 hi_bool source_scramble_on; 957 hi_bool sink_scramble_on; 958 hi_u8 tmds_bit_clk_ratio; 959 #if defined(HDMI_SUPPORT_LOGIC_HISIV100) 960 hi_bool sink_read_quest; 961 /* in unit of ms.for [0,200], force to default 200; or, set the value cfg(>200). */ 962 hi_u32 scramble_timeout; 963 /* in unit of ms, range[20,200). for [0,20] or >=200, force to default 20; or, set the value cfg[20,200). */ 964 hi_u32 scramble_interval; 965 #endif 966 } hdmi_scdc_status; 967 968 typedef struct { 969 hi_bool avi_enable; 970 hi_bool audio_enable; 971 hi_bool vsif_enable; 972 hi_bool spd_enable; 973 hi_bool mpeg_enable; 974 hi_bool gbd_enable; 975 hi_u8 avi[HDMI_INFO_FRAME_MAX_SIZE]; 976 hi_u8 audio[HDMI_INFO_FRAME_MAX_SIZE]; 977 hi_u8 vsif[HDMI_INFO_FRAME_MAX_SIZE]; 978 hi_u8 spd[HDMI_INFO_FRAME_MAX_SIZE]; 979 hi_u8 mpeg[HDMI_INFO_FRAME_MAX_SIZE]; 980 hi_u8 gdb[HDMI_INFO_FRAME_MAX_SIZE]; 981 hi_bool drm_enable; 982 hi_u8 drm[HDMI_INFO_FRAME_MAX_SIZE]; 983 } hdmi_infoframe_status; 984 985 typedef struct { 986 hi_bool hdcp22_enable; 987 hi_bool hdcp14_enable; 988 hi_bool repeater_on; 989 hi_u8 bksv[5]; 990 hi_u8 aksv[5]; 991 hi_u8 hdcp_status; 992 } hdmi_hdcp_status; 993 994 typedef enum { 995 FRL_WORK_MODE_NONE, 996 FRL_WORK_MODE_3L3G, 997 FRL_WORK_MODE_3L6G, 998 FRL_WORK_MODE_4L6G, 999 FRL_WORK_MODE_4L8G, 1000 FRL_WORK_MODE_4L10G, 1001 FRL_WORK_MODE_4L12G, 1002 FRL_WORK_MODE_BUTT 1003 } hdmi_work_mode; 1004 1005 typedef struct { 1006 hi_bool frl_start; 1007 hi_bool work_en; 1008 hdmi_work_mode work_mode; 1009 } hdmi_frl_status; 1010 1011 typedef enum { 1012 FRL_TXFFE_MODE_0, 1013 FRL_TXFFE_MODE_1, 1014 FRL_TXFFE_MODE_2, 1015 FRL_TXFFE_MODE_3, 1016 FRL_TXFFE_MODE_BUTT 1017 } hdmi_txfff_mode; 1018 1019 typedef struct { 1020 hdmi_common_status common_status; 1021 hdmi_phy_status phy_status; 1022 hdmi_video_status video_status; 1023 hdmi_audio_status audio_status; 1024 hdmi_infoframe_status info_frame_status; 1025 hdmi_hdcp_status hdcp_status; 1026 hdmi_hwspec phy_hwspec; 1027 #ifdef HDMI_FRL_SUPPORT 1028 hdmi_frl_status frl_status; 1029 #endif 1030 } hdmi_hardware_status; 1031 1032 typedef struct { 1033 hi_u32 max_tmds_character_rate; 1034 hi_bool scdc_present; 1035 hi_bool rr_capable; 1036 hi_bool lte340_mcsc_scramble; 1037 hi_bool _3d_osd_disparity; 1038 hi_bool dual_view; 1039 hi_bool independent_view; 1040 hi_bool dc30bit420; 1041 hi_bool dc36bit420; 1042 hi_bool dc48bit420; 1043 hi_bool scdc_enable; 1044 } hdmi_scdc_config; 1045 1046 typedef struct { 1047 hi_u32 mute_delay; /* delay for avmute */ 1048 hi_u32 fmt_delay; /* delay for setformat */ 1049 hi_bool force_fmt_delay; /* force setformat delay mode */ 1050 hi_bool force_mute_delay; /* force avmute delay mode */ 1051 } hdmi_delay; 1052 1053 typedef enum { 1054 HDMI_VIDEO_UNKNOWN, 1055 HDMI_VIDEO_PROGRESSIVE, 1056 HDMI_VIDEO_INTERLACE, 1057 HDMI_VIDEO_BUTT 1058 } hdmi_video_format_type; 1059 1060 typedef struct { 1061 hdmi_video_code_vic video_code; 1062 hi_u32 pixclk; 1063 hi_u32 rate; 1064 hi_u32 hactive; 1065 hi_u32 vactive; 1066 hi_u32 hblank; 1067 hi_u32 vblank; 1068 hi_u32 hfront; 1069 hi_u32 hsync; 1070 hi_u32 hback; 1071 hi_u32 vfront; 1072 hi_u32 vsync; 1073 hi_u32 vback; 1074 hdmi_picture_aspect aspect_ratio; 1075 hdmi_video_timing timing; 1076 hdmi_video_format_type pi_type; 1077 hi_char *fmt_str; 1078 } hdmi_video_def; 1079 1080 typedef struct { 1081 hdmi_vsif_vic hdmi_vic; 1082 hdmi_video_code_vic equivalent_video_code; // real vic 1083 hi_u32 pixclk; 1084 hi_u32 rate; 1085 hi_u32 hactive; 1086 hi_u32 vactive; 1087 hdmi_picture_aspect aspect_ratio; 1088 hdmi_video_timing timing; 1089 hdmi_video_format_type pi_type; 1090 hi_char *fmt_str; 1091 } hdmi_video_4k_def; 1092 1093 typedef struct { 1094 hi_u32 attach_in_time; 1095 hi_u32 attach_out_time; 1096 hi_u32 de_attach_in_time; 1097 hi_u32 de_attach_out_time; 1098 hi_u32 preformat_in_time; 1099 hi_u32 preformat_out_time; 1100 hi_u32 setformat_in_time; 1101 hi_u32 setformat_out_time; 1102 hi_u32 suspend_in_time; 1103 hi_u32 suspend_out_time; 1104 hi_u32 resume_in_time; 1105 hi_u32 resume_out_time; 1106 } hdmi_intf_status; 1107 1108 typedef struct { 1109 hi_bool black_enable; 1110 hi_u8 in_color_space; 1111 hi_u8 in_bit_depth; 1112 hi_u8 in_quantization; 1113 } hdmi_black_frame_info; 1114 1115 typedef struct { 1116 hi_u32 stop_delay; 1117 hdmi_intf_status intf_status; 1118 } hdmi_debug; 1119 1120 typedef enum { 1121 HDMI_TIMER_ZERO_DRMIF, 1122 HDMI_TIMER_SDR_TO_HDR10, 1123 HDMI_TIMER_TYPE_BUTT 1124 } hdmi_timer_type; 1125 1126 typedef struct { 1127 hdmi_timer_type timer_type; 1128 hi_bool timer_start; 1129 hi_u32 time; 1130 } hdmi_timer_config; 1131 1132 typedef enum { 1133 HDMI_HDR_DEBUG_MODE_NONE, /* HDR mode change, SDR->HDR10 don't change anything */ 1134 HDMI_HDR_DEBUG_MODE_OE, /* HDR mode change, SDR->HDR10 output disable and enable */ 1135 HDMI_HDR_DEBUG_MODE_AVMUTE, /* HDR mode change, SDR->HDR10 send avmute */ 1136 HDMI_HDR_DEBUG_MODE_BUTT 1137 } hdmi_hdr_debug_mode; 1138 1139 typedef struct { 1140 /* HDR debug mode. to solve the problem of some TV can not switch smoothly from non-HDR10 to HDR10. */ 1141 hdmi_hdr_debug_mode hdr_debug_mode; 1142 /* should send zero DRM infoframe when the HDR mode from HDR10 to non-HDR10. */ 1143 hdmi_timer_config zero_drm_if_timer; 1144 hdmi_timer_config hdr_mode_chn_timer; /* HDR debug timer. */ 1145 } drv_hdmi_hdr_info; 1146 1147 typedef struct { 1148 hi_bool mute_pkg_en; 1149 hi_bool mute_set; 1150 hi_bool mute_clr; 1151 hi_bool mute_rpt_en; 1152 hi_u32 rpt_cnt; 1153 } hdmi_avmute_cfg; 1154 1155 typedef enum { 1156 HDMI_FRL_SCDC_TYPE_SINK_VERSION, 1157 HDMI_FRL_SCDC_TYPE_SOURCE_VERSION, 1158 HDMI_FRL_SCDC_TYPE_UPDATE_FLAGS, 1159 HDMI_FRL_SCDC_TYPE_STATUS_FLAGS, 1160 HDMI_FRL_SCDC_TYPE_CONFIG, 1161 HDMI_FRL_SCDC_TYPE_TXFFE_REQ, 1162 HDMI_FRL_FLAGS_TYPE_BUTT 1163 } hdmi_frl_scdc_type; 1164 1165 typedef enum { 1166 HDMI_FRL_TRAIN_PATTERN_NONE, 1167 HDMI_FRL_TRAIN_PATTERN_LP1, 1168 HDMI_FRL_TRAIN_PATTERN_LP2, 1169 HDMI_FRL_TRAIN_PATTERN_LP3, 1170 HDMI_FRL_TRAIN_PATTERN_LP4, 1171 HDMI_FRL_TRAIN_PATTERN_LP5, 1172 HDMI_FRL_TRAIN_PATTERN_LP6, 1173 HDMI_FRL_TRAIN_PATTERN_LP7, 1174 HDMI_FRL_TRAIN_PATTERN_LP8, 1175 HDMI_FRL_TRAIN_PATTERN_RESERVED, 1176 HDMI_FRL_TRAIN_PATTERN_0E = 0xE, 1177 HDMI_FRL_TRAIN_PATTERN_0F = 0xF, 1178 HDMI_FRL_TRAIN_PATTERN_BUTT 1179 } hdmi_frl_train_pattern; 1180 1181 typedef enum { 1182 HDMI_FRL_TRAIN_NONE, 1183 HDMI_FRL_TRAIN_FAIL, 1184 HDMI_FRL_TRAIN_SUCCESS, 1185 HDMI_FRL_TRAIN_BUSY, 1186 HDMI_FRL_TRAIN_BUTT 1187 } hdmi_frl_train_status; 1188 1189 typedef enum { 1190 HDMI_FRL_TRAIN_FAIL_NORMAL, 1191 HDMI_FRL_TRAIN_FAIL_FLTTIMEOUT, 1192 HDMI_FRL_TRAIN_FAIL_FLTSTEPTIMEOUT, 1193 HDMI_FRL_TRAIN_FAIL_RATECHANGE, 1194 HDMI_FRL_TRAIN_FAIL_FFECHANGE, 1195 HDMI_FRL_TRAIN_FAIL_BUTT 1196 } hdmi_frl_train_fail_code; 1197 1198 typedef enum { 1199 HDMI_FRL_TRAIN_SEL_SW, 1200 HDMI_FRL_TRAIN_SEL_HW, 1201 HDMI_FRL_TRAIN_SEL_BUTT 1202 } hdmi_frl_train_sel; 1203 1204 typedef enum { 1205 FRL_DEBUG_RATE, 1206 FRL_DEBUG_SW_TRAIN_SEL, 1207 FRL_DEBUG_LTP_PATTERN, 1208 FRL_DEBUG_SELECT_CHANNEL, 1209 FRL_DEBUG_LTS3_INTERVAL, 1210 FRL_DEBUG_LTS3_TIMEOUT, 1211 FRL_DEBUG_TRAINING_BREAK, 1212 FRL_DEBUG_LM_TABLE_GET, 1213 FRL_DEBUG_CTRL_TYPE_CONFIG, 1214 FRL_DEBUG_BUTT 1215 } frl_debug_cmd; 1216 1217 typedef enum { 1218 FRL_SW_TRAIN_DELAY, 1219 FRL_SW_TRAIN_TIMER, 1220 FRL_SW_TRAIN_BUTT 1221 } frl_sw_train_mode; 1222 1223 typedef enum { 1224 FRL_CHL_SEL_NORMAL, 1225 FRL_CHL_SEL_RX_TMDS, 1226 FRL_CHL_SEL_BUTT 1227 } frl_channel_sel; 1228 1229 typedef struct { 1230 hdmi_frl_train_status frl_train_status; 1231 hdmi_frl_train_pattern train_pattern[HDMI_FRL_LANE_MAX_NUM]; 1232 hdmi_frl_train_fail_code train_fail_res; 1233 } hdmi_frl_train; 1234 1235 typedef enum { 1236 HDMI_FRL_MACH_MODE_STEP, 1237 HDMI_FRL_MACH_MODE_TIMEOUT, 1238 HDMI_FRL_MACH_MODE_BUTT 1239 } hdmi_frl_mach_mode; 1240 1241 typedef struct { 1242 hi_bool frl_no_timeout; 1243 hi_u8 frl_rate; 1244 hi_u8 ffe_levels; 1245 hi_u32 train_timeout; 1246 hdmi_frl_mach_mode mach_mode; 1247 frl_sw_train_mode sw_train_mode; 1248 hi_u8 ctl_type_config; 1249 } hdmi_frl_train_config; 1250 1251 typedef struct { 1252 frl_debug_cmd debug_cmd; 1253 hi_u8 rate; 1254 hi_u8 ltp; 1255 hi_u8 lane_idx; 1256 hi_u8 training_break; 1257 frl_sw_train_mode sw_train_mode; 1258 frl_channel_sel channel_sel; 1259 hi_u32 lts3_interval; 1260 hi_u32 lts3_timeout; 1261 hi_u8 crtl_type_config; 1262 hi_u8 avi_send_by_gen5; 1263 } frl_debug; 1264 1265 typedef enum { 1266 SCDC_CMD_SET_SOURCE_VER, 1267 SCDC_CMD_GET_SOURCE_VER, 1268 SCDC_CMD_GET_SINK_VER, 1269 SCDC_CMD_SET_FLT_UPDATE, 1270 SCDC_CMD_GET_FLT_UPDATE, 1271 SCDC_CMD_SET_FLT_UPDATE_TRIM, 1272 SCDC_CMD_GET_FLT_UPDATE_TRIM, 1273 SCDC_CMD_SET_FRL_START, 1274 SCDC_CMD_GET_FRL_START, 1275 SCDC_CMD_SET_CONFIG1, 1276 SCDC_CMD_GET_CONFIG1, 1277 SCDC_CMD_GET_TEST_CONFIG, 1278 SCDC_CMD_GET_FLT_READY, 1279 SCDC_CMD_GET_LTP_REQ, 1280 SCDC_CMD_BUTT 1281 } scdc_cmd; 1282 1283 typedef struct { 1284 hi_u8 frl_rate; 1285 hi_u8 ffe_levels; 1286 } scdc_config1; 1287 1288 typedef struct { 1289 hi_bool pre_shoot_only; 1290 hi_bool de_emphasis_only; 1291 hi_bool no_ffe; 1292 hi_bool flt_no_timeout; 1293 hi_bool dsc_frl_max; 1294 hi_bool frl_max; 1295 } scdc_test_config; 1296 1297 typedef struct { 1298 hi_u8 ln0_ltp; 1299 hi_u8 ln1_ltp; 1300 hi_u8 ln2_ltp; 1301 hi_u8 ln3_ltp; 1302 } scdc_ltp_req; 1303 1304 typedef enum { 1305 HDMI_PHY_MODE_CFG_TMDS, 1306 HDMI_PHY_MODE_CFG_FRL, 1307 HDMI_PHY_MODE_CFG_TXFFE 1308 } hdmi_phy_mode_cfg; 1309 1310 typedef enum { 1311 HDMI_TRACE_LEN_0, /* 1.0 inch */ 1312 HDMI_TRACE_LEN_1, /* 1.5 inch */ 1313 HDMI_TRACE_LEN_2, /* 2.0 inch */ 1314 HDMI_TRACE_LEN_3, /* 2.5 inch */ 1315 HDMI_TRACE_LEN_4, /* 3.0 inch */ 1316 HDMI_TRACE_LEN_5, /* 3.5 inch */ 1317 HDMI_TRACE_LEN_6, /* 4.0 inch */ 1318 HDMI_TRACE_LEN_7, /* 4.5 inch */ 1319 HDMI_TRACE_LEN_8, /* 5.0 inch */ 1320 HDMI_TRACE_BUTT 1321 } hdmi_trace_len; 1322 1323 typedef struct { 1324 hdmi_trace_len trace_len; 1325 } hdmi_mode_param; 1326 1327 typedef struct { 1328 hi_u32 pixel_clk; 1329 hi_u32 tmds_clk; /* TMDS colck,in k_hz */ 1330 hi_bool emi_enable; 1331 hdmi_deep_color deep_color; /* deep color(color depth) */ 1332 hdmi_phy_mode_cfg mode_cfg; /* TMDS/FRL/tx_ffe */ 1333 hdmi_trace_len trace_len; 1334 #ifdef HDMI_FRL_SUPPORT 1335 hdmi_colorspace color_space; 1336 hdmi_work_mode rate; /* lane and rate */ 1337 hdmi_txfff_mode aen_tx_ffe[4]; /* tx_ffe */ 1338 #endif 1339 } hdmi_phy_cfg; 1340 1341 hdmi_video_code_vic drv_hdmi_vic_search(hdmi_video_timing, hdmi_picture_aspect, hi_bool); 1342 1343 hi_void hdmi_reg_write(volatile hi_void *reg_addr, hi_u32 value); 1344 1345 hi_u32 hdmi_reg_read(volatile hi_void *reg_addr); 1346 1347 hi_void drv_hdmi_milli_delay(hi_u32 m_sec); 1348 1349 hi_u32 drv_hdmi_vic_to_index(hi_u32 vic); 1350 1351 hdmi_video_timing drv_hdmi_video_timing_get(hdmi_video_code_vic vic, hdmi_picture_aspect aspect); 1352 1353 hdmi_video_timing drv_hdmi_vsif_video_timing_get(hdmi_vsif_vic vic); 1354 1355 hdmi_video_4k_def *drv_hdmi_video_codes_4k_get(hi_u32 cnt); 1356 1357 hdmi_video_def *drv_hdmi_comm_format_param_get(hdmi_video_code_vic vic); 1358 1359 #ifdef HDMI_FRL_SUPPORT 1360 hdmi_video_def *drv_hdmi_vesa_format_param_get(hdmi_video_timing timing); 1361 #endif 1362 1363 #endif /* __DRV_HDMI_COMMON_H_ */ 1364 1365