1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 * ************************************************************
29 */
30
31 #include "mp_precomp.h"
32 #include "phydm_precomp.h"
33
phydm_rxsc_2_bw(void * dm_void,u8 rxsc)34 enum channel_width phydm_rxsc_2_bw(void *dm_void, u8 rxsc)
35 {
36 struct dm_struct *dm = (struct dm_struct *)dm_void;
37 enum channel_width bw = 0;
38
39 /* @Check RX bandwidth */
40 if (rxsc == 0)
41 bw = *dm->band_width; /*@full bw*/
42 else if (rxsc >= 1 && rxsc <= 8)
43 bw = CHANNEL_WIDTH_20;
44 else if (rxsc >= 9 && rxsc <= 12)
45 bw = CHANNEL_WIDTH_40;
46 else /*if (rxsc >= 13)*/
47 bw = CHANNEL_WIDTH_80;
48
49 return bw;
50 }
51
phydm_reset_bb_hw_cnt(void * dm_void)52 void phydm_reset_bb_hw_cnt(void *dm_void)
53 {
54 struct dm_struct *dm = (struct dm_struct *)dm_void;
55
56 /*@ Reset all counter when 1 */
57 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
58 #if (RTL8723F_SUPPORT)
59 if (dm->support_ic_type & ODM_RTL8723F) {
60 odm_set_bb_reg(dm, R_0x2a44, BIT(21), 0);
61 odm_set_bb_reg(dm, R_0x2a44, BIT(21), 1);
62 }
63 #endif
64 odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 1);
65 odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 0);
66 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
67 /*@ Reset all counter when 1 (including PMAC and PHY)*/
68 /* Reset Page F counter*/
69 odm_set_bb_reg(dm, R_0xb58, BIT(0), 1);
70 odm_set_bb_reg(dm, R_0xb58, BIT(0), 0);
71 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
72 odm_set_bb_reg(dm, R_0xf14, BIT(16), 0x1);
73 odm_set_bb_reg(dm, R_0xf14, BIT(16), 0x0);
74 }
75 }
76
phydm_dynamic_ant_weighting(void * dm_void)77 void phydm_dynamic_ant_weighting(void *dm_void)
78 {
79 struct dm_struct *dm = (struct dm_struct *)dm_void;
80
81 #ifdef DYN_ANT_WEIGHTING_SUPPORT
82 #if (RTL8197F_SUPPORT)
83 if (dm->support_ic_type & (ODM_RTL8197F))
84 phydm_dynamic_ant_weighting_8197f(dm);
85 #endif
86
87 #if (RTL8812A_SUPPORT)
88 if (dm->support_ic_type & (ODM_RTL8812)) {
89 phydm_dynamic_ant_weighting_8812a(dm);
90 }
91 #endif
92
93 #if (RTL8822B_SUPPORT)
94 if (dm->support_ic_type & (ODM_RTL8822B))
95 phydm_dynamic_ant_weighting_8822b(dm);
96 #endif
97 #endif
98 }
99
100 #ifdef DYN_ANT_WEIGHTING_SUPPORT
phydm_ant_weight_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)101 void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used,
102 char *output, u32 *_out_len)
103 {
104 struct dm_struct *dm = (struct dm_struct *)dm_void;
105 char help[] = "-h";
106 u32 var1[10] = {0};
107 u32 used = *_used;
108 u32 out_len = *_out_len;
109
110 if (!(dm->support_ic_type &
111 (ODM_RTL8192F | ODM_RTL8822B | ODM_RTL8812 | ODM_RTL8197F))) {
112 return;
113 }
114
115 if ((strcmp(input[1], help) == 0)) {
116 PDM_SNPF(out_len, used, output + used, out_len - used,
117 "echo dis_dym_ant_weighting {0/1}\n");
118
119 } else {
120 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
121
122 if (var1[0] == 1) {
123 dm->is_disable_dym_ant_weighting = 1;
124 PDM_SNPF(out_len, used, output + used, out_len - used,
125 "Disable dyn-ant-weighting\n");
126 } else {
127 dm->is_disable_dym_ant_weighting = 0;
128 PDM_SNPF(out_len, used, output + used, out_len - used,
129 "Enable dyn-ant-weighting\n");
130 }
131 }
132 *_used = used;
133 *_out_len = out_len;
134 }
135 #endif
136
phydm_trx_antenna_setting_init(void * dm_void,u8 num_rf_path)137 void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path)
138 {
139 struct dm_struct *dm = (struct dm_struct *)dm_void;
140 u8 rx_ant = 0, tx_ant = 0;
141 u8 path_bitmap = 1;
142
143 path_bitmap = (u8)phydm_gen_bitmask(num_rf_path);
144
145 /*PHYDM_DBG(dm, ODM_COMP_INIT, "path_bitmap=0x%x\n", path_bitmap);*/
146
147 dm->tx_ant_status = path_bitmap;
148 dm->rx_ant_status = path_bitmap;
149
150 if (num_rf_path == PDM_1SS)
151 return;
152
153 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
154 if (dm->support_ic_type &
155 (ODM_RTL8192F | ODM_RTL8192E | ODM_RTL8197F)) {
156 dm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0xc04, 0x3);
157 dm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x90c, 0x3);
158 } else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8814A)) {
159 dm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0x808, 0xf);
160 dm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x80c, 0xf);
161 }
162 #endif
163 /* @trx_ant_status are already updated in trx mode API in JGR3 ICs */
164
165 PHYDM_DBG(dm, ODM_COMP_INIT, "[%s]ant_status{tx,rx}={0x%x, 0x%x}\n",
166 __func__, dm->tx_ant_status, dm->rx_ant_status);
167 }
168
phydm_config_ofdm_tx_path(void * dm_void,enum bb_path path)169 void phydm_config_ofdm_tx_path(void *dm_void, enum bb_path path)
170 {
171 #if (RTL8192E_SUPPORT || RTL8192F_SUPPORT || RTL8812A_SUPPORT)
172 struct dm_struct *dm = (struct dm_struct *)dm_void;
173 u8 ofdm_tx_path = 0x33;
174
175 if (dm->num_rf_path == PDM_1SS)
176 return;
177
178 switch (dm->support_ic_type) {
179 #if (RTL8192E_SUPPORT || RTL8192F_SUPPORT)
180 case ODM_RTL8192E:
181 case ODM_RTL8192F:
182 if (path == BB_PATH_A)
183 odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121313);
184 else if (path == BB_PATH_B)
185 odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x82221323);
186 else if (path == BB_PATH_AB)
187 odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333);
188
189 break;
190 #endif
191
192 #if (RTL8812A_SUPPORT)
193 case ODM_RTL8812:
194 if (path == BB_PATH_A)
195 ofdm_tx_path = 0x11;
196 else if (path == BB_PATH_B)
197 ofdm_tx_path = 0x22;
198 else if (path == BB_PATH_AB)
199 ofdm_tx_path = 0x33;
200
201 odm_set_bb_reg(dm, R_0x80c, 0xff00, ofdm_tx_path);
202
203 break;
204 #endif
205
206 default:
207 break;
208 }
209 #endif
210 }
211
phydm_config_ofdm_rx_path(void * dm_void,enum bb_path path)212 void phydm_config_ofdm_rx_path(void *dm_void, enum bb_path path)
213 {
214 struct dm_struct *dm = (struct dm_struct *)dm_void;
215 u8 val = 0;
216
217 if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8192F)) {
218 #if (RTL8192E_SUPPORT || RTL8192F_SUPPORT)
219 if (path == BB_PATH_A)
220 val = 1;
221 else if (path == BB_PATH_B)
222 val = 2;
223 else if (path == BB_PATH_AB)
224 val = 3;
225
226 odm_set_bb_reg(dm, R_0xc04, 0xff, ((val << 4) | val));
227 odm_set_bb_reg(dm, R_0xd04, 0xf, val);
228 #endif
229 }
230 #if (RTL8812A_SUPPORT || RTL8822B_SUPPORT)
231 else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) {
232 if (path == BB_PATH_A)
233 val = 1;
234 else if (path == BB_PATH_B)
235 val = 2;
236 else if (path == BB_PATH_AB)
237 val = 3;
238
239 odm_set_bb_reg(dm, R_0x808, MASKBYTE0, ((val << 4) | val));
240 }
241 #endif
242 }
243
phydm_config_cck_rx_antenna_init(void * dm_void)244 void phydm_config_cck_rx_antenna_init(void *dm_void)
245 {
246 struct dm_struct *dm = (struct dm_struct *)dm_void;
247
248 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
249 if (dm->support_ic_type & ODM_IC_1SS)
250 return;
251
252 /*@CCK 2R CCA parameters*/
253 odm_set_bb_reg(dm, R_0xa00, BIT(15), 0x0); /*@Disable Ant diversity*/
254 odm_set_bb_reg(dm, R_0xa70, BIT(7), 0); /*@Concurrent CCA at LSB & USB*/
255 odm_set_bb_reg(dm, R_0xa74, BIT(8), 0); /*RX path diversity enable*/
256 odm_set_bb_reg(dm, R_0xa14, BIT(7), 0); /*r_en_mrc_antsel*/
257 odm_set_bb_reg(dm, R_0xa20, (BIT(5) | BIT(4)), 1); /*@MBC weighting*/
258
259 if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F))
260 odm_set_bb_reg(dm, R_0xa08, BIT(28), 1); /*r_cck_2nd_sel_eco*/
261 else if (dm->support_ic_type & ODM_RTL8814A)
262 odm_set_bb_reg(dm, R_0xa84, BIT(28), 1); /*@2R CCA only*/
263 #endif
264 }
265
phydm_config_cck_rx_path(void * dm_void,enum bb_path path)266 void phydm_config_cck_rx_path(void *dm_void, enum bb_path path)
267 {
268 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
269 struct dm_struct *dm = (struct dm_struct *)dm_void;
270 u8 path_div_select = 0;
271 u8 cck_path[2] = {0};
272 u8 en_2R_path = 0;
273 u8 en_2R_mrc = 0;
274 u8 i = 0, j = 0;
275 u8 num_enable_path = 0;
276 u8 cck_mrc_max_path = 2;
277
278 if (dm->support_ic_type & ODM_IC_1SS)
279 return;
280
281 for (i = 0; i < 4; i++) {
282 if (path & BIT(i)) { /*@ex: PHYDM_ABCD*/
283 num_enable_path++;
284 cck_path[j] = i;
285 j++;
286 }
287 if (num_enable_path >= cck_mrc_max_path)
288 break;
289 }
290
291 if (num_enable_path > 1) {
292 path_div_select = 1;
293 en_2R_path = 1;
294 en_2R_mrc = 1;
295 } else {
296 path_div_select = 0;
297 en_2R_path = 0;
298 en_2R_mrc = 0;
299 }
300 /*@CCK_1 input signal path*/
301 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), cck_path[0]);
302 /*@CCK_2 input signal path*/
303 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), cck_path[1]);
304 /*@enable Rx path diversity*/
305 odm_set_bb_reg(dm, R_0xa74, BIT(8), path_div_select);
306 /*@enable 2R Rx path*/
307 odm_set_bb_reg(dm, R_0xa2c, BIT(18), en_2R_path);
308 /*@enable 2R MRC*/
309 odm_set_bb_reg(dm, R_0xa2c, BIT(22), en_2R_mrc);
310 if (dm->support_ic_type & (ODM_RTL8192F | ODM_RTL8197F)) {
311 if (path == BB_PATH_A) {
312 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
313 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 0);
314 odm_set_bb_reg(dm, R_0xa74, BIT(8), 0);
315 odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0);
316 odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0);
317 } else if (path == BB_PATH_B) {/*@for DC cancellation*/
318 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 1);
319 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
320 odm_set_bb_reg(dm, R_0xa74, BIT(8), 0);
321 odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0);
322 odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0);
323 } else if (path == BB_PATH_AB) {
324 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
325 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
326 odm_set_bb_reg(dm, R_0xa74, BIT(8), 1);
327 odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 1);
328 odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 1);
329 }
330 } else if (dm->support_ic_type & ODM_RTL8822B) {
331 if (path == BB_PATH_A) {
332 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
333 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 0);
334 } else {
335 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 1);
336 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
337 }
338 }
339
340 #endif
341 }
342
phydm_config_cck_tx_path(void * dm_void,enum bb_path path)343 void phydm_config_cck_tx_path(void *dm_void, enum bb_path path)
344 {
345 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
346 struct dm_struct *dm = (struct dm_struct *)dm_void;
347
348 if (path == BB_PATH_A)
349 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x8);
350 else if (path == BB_PATH_B)
351 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x4);
352 else /*if (path == BB_PATH_AB)*/
353 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc);
354 #endif
355 }
356
phydm_config_trx_path_v2(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)357 void phydm_config_trx_path_v2(void *dm_void, char input[][16], u32 *_used,
358 char *output, u32 *_out_len)
359 {
360 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\
361 RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT ||\
362 RTL8812F_SUPPORT || RTL8198F_SUPPORT)
363 struct dm_struct *dm = (struct dm_struct *)dm_void;
364 u32 used = *_used;
365 u32 out_len = *_out_len;
366 u32 val[10] = {0};
367 char help[] = "-h";
368 u8 i = 0, input_idx = 0;
369 enum bb_path tx_path, rx_path, tx_path_ctrl;
370 boolean dbg_mode_en;
371
372 if (!(dm->support_ic_type &
373 (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8822C |
374 ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8197G | ODM_RTL8198F |
375 ODM_RTL8814C)))
376 return;
377
378 for (i = 0; i < 5; i++) {
379 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
380 input_idx++;
381 }
382
383 if (input_idx == 0)
384 return;
385
386 dbg_mode_en = (boolean)val[0];
387 tx_path = (enum bb_path)val[1];
388 rx_path = (enum bb_path)val[2];
389 tx_path_ctrl = (enum bb_path)val[3];
390
391 if ((strcmp(input[1], help) == 0)) {
392 if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8822B |
393 ODM_RTL8192F)) {
394 PDM_SNPF(out_len, used, output + used, out_len - used,
395 "{en} {tx_path} {rx_path} {ff:auto, else:1ss_tx_path}\n"
396 );
397 } else {
398 PDM_SNPF(out_len, used, output + used, out_len - used,
399 "{en} {tx_path} {rx_path} {is_tx_2_path}\n");
400 }
401
402 } else if (dbg_mode_en) {
403 dm->is_disable_phy_api = false;
404 phydm_api_trx_mode(dm, tx_path, rx_path, tx_path_ctrl);
405 dm->is_disable_phy_api = true;
406 PDM_SNPF(out_len, used, output + used, out_len - used,
407 "T/RX path = 0x%x/0x%x, tx_path_ctrl=%d\n",
408 tx_path, rx_path, tx_path_ctrl);
409 PDM_SNPF(out_len, used, output + used, out_len - used,
410 "T/RX path_en={0x%x, 0x%x}, tx_1ss=%d\n",
411 dm->tx_ant_status, dm->rx_ant_status,
412 dm->tx_1ss_status);
413 } else {
414 dm->is_disable_phy_api = false;
415 PDM_SNPF(out_len, used, output + used, out_len - used,
416 "Disable API debug mode\n");
417 }
418 #endif
419 }
420
phydm_config_trx_path_v1(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)421 void phydm_config_trx_path_v1(void *dm_void, char input[][16], u32 *_used,
422 char *output, u32 *_out_len)
423 {
424 #if (RTL8192E_SUPPORT || RTL8812A_SUPPORT)
425 struct dm_struct *dm = (struct dm_struct *)dm_void;
426 u32 used = *_used;
427 u32 out_len = *_out_len;
428 u32 val[10] = {0};
429 char help[] = "-h";
430 u8 i = 0, input_idx = 0;
431
432 if (!(dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)))
433 return;
434
435 for (i = 0; i < 5; i++) {
436 if (input[i + 1]) {
437 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
438 input_idx++;
439 }
440 }
441
442 if (input_idx == 0)
443 return;
444
445 if ((strcmp(input[1], help) == 0)) {
446 PDM_SNPF(out_len, used, output + used, out_len - used,
447 "{0:CCK, 1:OFDM} {1:TX, 2:RX} {1:path_A, 2:path_B, 3:path_AB}\n");
448
449 *_used = used;
450 *_out_len = out_len;
451 return;
452
453 } else if (val[0] == 0) {
454 /* @CCK */
455 if (val[1] == 1) { /*TX*/
456 if (val[2] == 1)
457 phydm_config_cck_tx_path(dm, BB_PATH_A);
458 else if (val[2] == 2)
459 phydm_config_cck_tx_path(dm, BB_PATH_B);
460 else if (val[2] == 3)
461 phydm_config_cck_tx_path(dm, BB_PATH_AB);
462 } else if (val[1] == 2) { /*RX*/
463
464 phydm_config_cck_rx_antenna_init(dm);
465
466 if (val[2] == 1)
467 phydm_config_cck_rx_path(dm, BB_PATH_A);
468 else if (val[2] == 2)
469 phydm_config_cck_rx_path(dm, BB_PATH_B);
470 else if (val[2] == 3)
471 phydm_config_cck_rx_path(dm, BB_PATH_AB);
472 }
473 }
474 /* OFDM */
475 else if (val[0] == 1) {
476 if (val[1] == 1) /*TX*/
477 phydm_config_ofdm_tx_path(dm, val[2]);
478 else if (val[1] == 2) /*RX*/
479 phydm_config_ofdm_rx_path(dm, val[2]);
480 }
481
482 PDM_SNPF(out_len, used, output + used, out_len - used,
483 "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n",
484 (val[0] == 1) ? "OFDM" : "CCK",
485 (val[1] == 1) ? "TX" : "RX",
486 (val[2] & 0x1) ? "A" : "", (val[2] & 0x2) ? "B" : "",
487 (val[2] & 0x4) ? "C" : "",
488 (val[2] & 0x8) ? "D" : "");
489
490 *_used = used;
491 *_out_len = out_len;
492 #endif
493 }
494
phydm_config_trx_path(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)495 void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used,
496 char *output, u32 *_out_len)
497 {
498 struct dm_struct *dm = (struct dm_struct *)dm_void;
499
500 if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) {
501 #if (RTL8192E_SUPPORT || RTL8812A_SUPPORT)
502 phydm_config_trx_path_v1(dm, input, _used, output, _out_len);
503 #endif
504 } else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F |
505 ODM_RTL8192F | ODM_RTL8822C | ODM_RTL8812F |
506 ODM_RTL8197G | ODM_RTL8814B | ODM_RTL8198F |
507 ODM_RTL8814C)) {
508 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT ||\
509 RTL8192F_SUPPORT || RTL8822C_SUPPORT ||\
510 RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
511 RTL8197G_SUPPORT || RTL8198F_SUPPORT)
512 phydm_config_trx_path_v2(dm, input, _used, output, _out_len);
513 #endif
514 }
515 }
516
phydm_tx_2path(void * dm_void)517 void phydm_tx_2path(void *dm_void)
518 {
519 #if (defined(PHYDM_COMPILE_IC_2SS))
520 struct dm_struct *dm = (struct dm_struct *)dm_void;
521 enum bb_path rx_path = (enum bb_path)dm->rx_ant_status;
522
523 PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
524
525
526 if (!(dm->support_ic_type & ODM_IC_2SS))
527 return;
528
529 #if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8197F_SUPPORT ||\
530 RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
531 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |
532 ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G))
533 phydm_api_trx_mode(dm, BB_PATH_AB, rx_path, BB_PATH_AB);
534 #endif
535
536 #if (RTL8812A_SUPPORT || RTL8192E_SUPPORT)
537 if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) {
538 phydm_config_cck_tx_path(dm, BB_PATH_AB);
539 phydm_config_ofdm_tx_path(dm, BB_PATH_AB);
540 }
541 #endif
542 #endif
543 }
544
phydm_stop_3_wire(void * dm_void,u8 set_type)545 void phydm_stop_3_wire(void *dm_void, u8 set_type)
546 {
547 struct dm_struct *dm = (struct dm_struct *)dm_void;
548
549 if (set_type == PHYDM_SET) {
550 /*@[Stop 3-wires]*/
551 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
552 odm_set_bb_reg(dm, R_0x180c, 0x3, 0x0);
553 odm_set_bb_reg(dm, R_0x180c, BIT(28), 0x1);
554
555 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
556 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
557 odm_set_bb_reg(dm, R_0x410c, 0x3, 0x0);
558 odm_set_bb_reg(dm, R_0x410c, BIT(28), 0x1);
559 }
560 #endif
561
562 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
563 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
564 odm_set_bb_reg(dm, R_0x520c, 0x3, 0x0);
565 odm_set_bb_reg(dm, R_0x520c, BIT(28), 0x1);
566 odm_set_bb_reg(dm, R_0x530c, 0x3, 0x0);
567 odm_set_bb_reg(dm, R_0x530c, BIT(28), 0x1);
568 }
569 #endif
570 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
571 odm_set_bb_reg(dm, R_0xc00, 0xf, 0x4);
572 odm_set_bb_reg(dm, R_0xe00, 0xf, 0x4);
573 } else {
574 odm_set_bb_reg(dm, R_0x88c, 0xf00000, 0xf);
575 }
576
577 } else { /*@if (set_type == PHYDM_REVERT)*/
578
579 /*@[Start 3-wires]*/
580 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
581 odm_set_bb_reg(dm, R_0x180c, 0x3, 0x3);
582 odm_set_bb_reg(dm, R_0x180c, BIT(28), 0x1);
583
584 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
585 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
586 odm_set_bb_reg(dm, R_0x410c, 0x3, 0x3);
587 odm_set_bb_reg(dm, R_0x410c, BIT(28), 0x1);
588 }
589 #endif
590
591 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
592 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
593 odm_set_bb_reg(dm, R_0x520c, 0x3, 0x3);
594 odm_set_bb_reg(dm, R_0x520c, BIT(28), 0x1);
595 odm_set_bb_reg(dm, R_0x530c, 0x3, 0x3);
596 odm_set_bb_reg(dm, R_0x530c, BIT(28), 0x1);
597 }
598 #endif
599 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
600 odm_set_bb_reg(dm, R_0xc00, 0xf, 0x7);
601 odm_set_bb_reg(dm, R_0xe00, 0xf, 0x7);
602 } else {
603 odm_set_bb_reg(dm, R_0x88c, 0xf00000, 0x0);
604 }
605 }
606 }
607
phydm_stop_ic_trx(void * dm_void,u8 set_type)608 u8 phydm_stop_ic_trx(void *dm_void, u8 set_type)
609 {
610 struct dm_struct *dm = (struct dm_struct *)dm_void;
611 struct phydm_api_stuc *api = &dm->api_table;
612 u8 i = 0;
613 boolean trx_idle_success = false;
614 u32 dbg_port_value = 0;
615
616 if (set_type == PHYDM_SET) {
617 /*[Stop TRX]---------------------------------------------------------*/
618 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
619 #if (RTL8723F_SUPPORT)
620 /*Judy 2020-0515*/
621 /*set debug port to 0x0*/
622 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0x0))
623 return PHYDM_SET_FAIL;
624 #endif
625 for (i = 0; i < 100; i++) {
626 dbg_port_value = odm_get_bb_reg(dm, R_0x2db4,
627 MASKDWORD);
628 /* BB idle */
629 if ((dbg_port_value & 0x1FFEFF3F) == 0 &&
630 (dbg_port_value & 0xC0010000) ==
631 0xC0010000) {
632 PHYDM_DBG(dm, ODM_COMP_API,
633 "Stop trx wait for (%d) times\n",
634 i);
635
636 trx_idle_success = true;
637 break;
638 }
639 }
640 } else {
641 /*set debug port to 0x0*/
642 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0x0))
643 return PHYDM_SET_FAIL;
644 for (i = 0; i < 100; i++) {
645 dbg_port_value = phydm_get_bb_dbg_port_val(dm);
646 /* PHYTXON && CCA_all */
647 if (dm->support_ic_type & (ODM_RTL8721D |
648 ODM_RTL8710B | ODM_RTL8710C |
649 ODM_RTL8188F | ODM_RTL8723D)) {
650 if ((dbg_port_value &
651 (BIT(20) | BIT(15))) == 0) {
652 PHYDM_DBG(dm, ODM_COMP_API,
653 "Stop trx wait for (%d) times\n",
654 i);
655
656 trx_idle_success = true;
657 break;
658 }
659 } else {
660 if ((dbg_port_value &
661 (BIT(17) | BIT(3))) == 0) {
662 PHYDM_DBG(dm, ODM_COMP_API,
663 "Stop trx wait for (%d) times\n",
664 i);
665
666 trx_idle_success = true;
667 break;
668 }
669 }
670 ODM_delay_ms(1);
671 }
672 phydm_release_bb_dbg_port(dm);
673 }
674
675 if (trx_idle_success) {
676 api->tx_queue_bitmap = odm_read_1byte(dm, R_0x522);
677
678 /*pause all TX queue*/
679 odm_set_mac_reg(dm, R_0x520, 0xff0000, 0xff);
680
681 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
682 /*disable OFDM RX CCA*/
683 odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff);
684 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
685 /*disable OFDM RX CCA*/
686 odm_set_bb_reg(dm, R_0x838, BIT(1), 1);
687 } else {
688 api->rxiqc_reg1 = odm_read_4byte(dm, R_0xc14);
689 api->rxiqc_reg2 = odm_read_4byte(dm, R_0xc1c);
690 /* [ Set IQK Matrix = 0 ]
691 * equivalent to [ Turn off CCA]
692 */
693 odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0);
694 odm_set_bb_reg(dm, R_0xc1c, MASKDWORD, 0x0);
695 }
696 phydm_dis_cck_trx(dm, PHYDM_SET);
697 } else {
698 return PHYDM_SET_FAIL;
699 }
700
701 return PHYDM_SET_SUCCESS;
702
703 } else { /*@if (set_type == PHYDM_REVERT)*/
704 /*Release all TX queue*/
705 odm_write_1byte(dm, R_0x522, api->tx_queue_bitmap);
706
707 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
708 /*@enable OFDM RX CCA*/
709 odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x0);
710 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
711 /*@enable OFDM RX CCA*/
712 odm_set_bb_reg(dm, R_0x838, BIT(1), 0);
713 } else {
714 /* @[Set IQK Matrix = 0] equivalent to [ Turn off CCA]*/
715 odm_write_4byte(dm, R_0xc14, api->rxiqc_reg1);
716 odm_write_4byte(dm, R_0xc1c, api->rxiqc_reg2);
717 }
718 phydm_dis_cck_trx(dm, PHYDM_REVERT);
719 return PHYDM_SET_SUCCESS;
720 }
721 }
722
phydm_dis_cck_trx(void * dm_void,u8 set_type)723 void phydm_dis_cck_trx(void *dm_void, u8 set_type)
724 {
725 struct dm_struct *dm = (struct dm_struct *)dm_void;
726 struct phydm_api_stuc *api = &dm->api_table;
727
728 if (set_type == PHYDM_SET) {
729 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
730 if(dm->support_ic_type & ODM_RTL8723F) {
731 api->ccktx_path = 1;
732 /* @disable CCK CCA */
733 odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x1);
734 /* @disable CCK Tx */
735 odm_set_bb_reg(dm, R_0x2a00, BIT(1), 0x1);
736 } else {
737 api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0x1a04,
738 0xf0000000);
739 /* @CCK RxIQ weighting = [0,0] */
740 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
741 /* @disable CCK Tx */
742 odm_set_bb_reg(dm, R_0x1a04, 0xf0000000, 0x0);
743 }
744 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
745 api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0xa04,
746 0xf0000000);
747 /* @disable CCK block */
748 odm_set_bb_reg(dm, R_0x808, BIT(28), 0);
749 /* @disable CCK Tx */
750 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x0);
751 } else {
752 api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0xa04,
753 0xf0000000);
754 /* @disable whole CCK block */
755 odm_set_bb_reg(dm, R_0x800, BIT(24), 0);
756 /* @disable CCK Tx */
757 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x0);
758 }
759 } else if (set_type == PHYDM_REVERT) {
760 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
761 if(dm->support_ic_type & ODM_RTL8723F) {
762 /* @enable CCK CCA */
763 odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x0);
764 /* @enable CCK Tx */
765 odm_set_bb_reg(dm, R_0x2a00, BIT(1), 0x0);
766 } else {
767 /* @CCK RxIQ weighting = [1,1] */
768 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
769 /* @enable CCK Tx */
770 odm_set_bb_reg(dm, R_0x1a04, 0xf0000000,
771 api->ccktx_path);
772 }
773 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
774 /* @enable CCK block */
775 odm_set_bb_reg(dm, R_0x808, BIT(28), 1);
776 /* @enable CCK Tx */
777 odm_set_bb_reg(dm, R_0xa04, 0xf0000000,
778 api->ccktx_path);
779 } else {
780 /* @enable whole CCK block */
781 odm_set_bb_reg(dm, R_0x800, BIT(24), 1);
782 /* @enable CCK Tx */
783 odm_set_bb_reg(dm, R_0xa04, 0xf0000000,
784 api->ccktx_path);
785 }
786 }
787 }
788
phydm_bw_fixed_enable(void * dm_void,u8 enable)789 void phydm_bw_fixed_enable(void *dm_void, u8 enable)
790 {
791 #ifdef CONFIG_BW_INDICATION
792 struct dm_struct *dm = (struct dm_struct *)dm_void;
793 boolean val = (enable == FUNC_ENABLE) ? 1 : 0;
794
795 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8195B))
796 odm_set_bb_reg(dm, R_0x840, BIT(4), val);
797 else if (dm->support_ic_type & ODM_RTL8822C)
798 odm_set_bb_reg(dm, R_0x878, BIT(28), val);
799 #endif
800 }
801
phydm_bw_fixed_setting(void * dm_void)802 void phydm_bw_fixed_setting(void *dm_void)
803 {
804 #ifdef CONFIG_BW_INDICATION
805 struct dm_struct *dm = (struct dm_struct *)dm_void;
806 struct phydm_api_stuc *api = &dm->api_table;
807 u8 bw = *dm->band_width;
808 u32 reg = 0, reg_mask = 0, reg_value = 0;
809
810 if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT))
811 return;
812
813 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B |
814 ODM_RTL8195B)) {
815 reg = R_0x840;
816 reg_mask = 0xf;
817 reg_value = api->pri_ch_idx;
818 } else if (dm->support_ic_type & ODM_RTL8822C) {
819 reg = R_0x878;
820 reg_mask = 0xc0000000;
821 reg_value = 0x0;
822 }
823
824 switch (bw) {
825 case CHANNEL_WIDTH_80:
826 odm_set_bb_reg(dm, reg, reg_mask, reg_value);
827 break;
828 case CHANNEL_WIDTH_40:
829 odm_set_bb_reg(dm, reg, reg_mask, reg_value);
830 break;
831 default:
832 odm_set_bb_reg(dm, reg, reg_mask, 0x0);
833 }
834
835 phydm_bw_fixed_enable(dm, FUNC_ENABLE);
836 #endif
837 }
838
phydm_set_ext_switch(void * dm_void,u32 ext_ant_switch)839 void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch)
840 {
841 #if (RTL8821A_SUPPORT || RTL8881A_SUPPORT)
842 struct dm_struct *dm = (struct dm_struct *)dm_void;
843
844 if (!(dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)))
845 return;
846
847 /*Output Pin Settings*/
848
849 /*select DPDT_P and DPDT_N as output pin*/
850 odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
851
852 /*@by WLAN control*/
853 odm_set_mac_reg(dm, R_0x4c, BIT(24), 1);
854
855 /*@DPDT_N = 1b'0*/ /*@DPDT_P = 1b'0*/
856 odm_set_bb_reg(dm, R_0xcb4, 0xFF, 77);
857
858 if (ext_ant_switch == 1) { /*@2b'01*/
859 odm_set_bb_reg(dm, R_0xcb4, (BIT(29) | BIT(28)), 1);
860 PHYDM_DBG(dm, ODM_COMP_API, "8821A ant swh=2b'01\n");
861 } else if (ext_ant_switch == 2) { /*@2b'10*/
862 odm_set_bb_reg(dm, R_0xcb4, BIT(29) | BIT(28), 2);
863 PHYDM_DBG(dm, ODM_COMP_API, "*8821A ant swh=2b'10\n");
864 }
865 #endif
866 }
867
phydm_csi_mask_enable(void * dm_void,u32 enable)868 void phydm_csi_mask_enable(void *dm_void, u32 enable)
869 {
870 struct dm_struct *dm = (struct dm_struct *)dm_void;
871 boolean en = false;
872
873 en = (enable == FUNC_ENABLE) ? true : false;
874
875 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
876 odm_set_bb_reg(dm, R_0xd2c, BIT(28), en);
877 PHYDM_DBG(dm, ODM_COMP_API,
878 "Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n", en);
879 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
880 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
881 odm_set_bb_reg(dm, R_0xc0c, BIT(3), en);
882 PHYDM_DBG(dm, ODM_COMP_API,
883 "Enable CSI Mask: Reg 0xc0c[3] = ((0x%x))\n", en);
884 #endif
885 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
886 odm_set_bb_reg(dm, R_0x874, BIT(0), en);
887 PHYDM_DBG(dm, ODM_COMP_API,
888 "Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n", en);
889 }
890 }
891
phydm_clean_all_csi_mask(void * dm_void)892 void phydm_clean_all_csi_mask(void *dm_void)
893 {
894 struct dm_struct *dm = (struct dm_struct *)dm_void;
895
896 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
897 odm_set_bb_reg(dm, R_0xd40, MASKDWORD, 0);
898 odm_set_bb_reg(dm, R_0xd44, MASKDWORD, 0);
899 odm_set_bb_reg(dm, R_0xd48, MASKDWORD, 0);
900 odm_set_bb_reg(dm, R_0xd4c, MASKDWORD, 0);
901 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
902 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
903 u8 i = 0, idx_lmt = 0;
904
905 if (dm->support_ic_type &
906 (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G))
907 idx_lmt = 127;
908 else /*@for IC supporting 80 + 80*/
909 idx_lmt = 255;
910
911 odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3);
912 odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1);
913 for (i = 0; i < idx_lmt; i++) {
914 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, i);
915 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE0, 0x0);
916 }
917 odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0);
918 #endif
919 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
920 odm_set_bb_reg(dm, R_0x880, MASKDWORD, 0);
921 odm_set_bb_reg(dm, R_0x884, MASKDWORD, 0);
922 odm_set_bb_reg(dm, R_0x888, MASKDWORD, 0);
923 odm_set_bb_reg(dm, R_0x88c, MASKDWORD, 0);
924 odm_set_bb_reg(dm, R_0x890, MASKDWORD, 0);
925 odm_set_bb_reg(dm, R_0x894, MASKDWORD, 0);
926 odm_set_bb_reg(dm, R_0x898, MASKDWORD, 0);
927 odm_set_bb_reg(dm, R_0x89c, MASKDWORD, 0);
928 }
929 }
930
phydm_set_csi_mask(void * dm_void,u32 tone_idx_tmp,u8 tone_direction)931 void phydm_set_csi_mask(void *dm_void, u32 tone_idx_tmp, u8 tone_direction)
932 {
933 struct dm_struct *dm = (struct dm_struct *)dm_void;
934 u8 byte_offset = 0, bit_offset = 0;
935 u32 target_reg = 0;
936 u8 reg_tmp_value = 0;
937 u32 tone_num = 64;
938 u32 tone_num_shift = 0;
939 u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0;
940
941 /* @calculate real tone idx*/
942 if ((tone_idx_tmp % 10) >= 5)
943 tone_idx_tmp += 10;
944
945 tone_idx_tmp = (tone_idx_tmp / 10);
946
947 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
948 tone_num = 64;
949 csi_mask_reg_p = 0xD40;
950 csi_mask_reg_n = 0xD48;
951
952 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
953 tone_num = 128;
954 csi_mask_reg_p = 0x880;
955 csi_mask_reg_n = 0x890;
956 }
957
958 if (tone_direction == FREQ_POSITIVE) {
959 if (tone_idx_tmp >= (tone_num - 1))
960 tone_idx_tmp = (tone_num - 1);
961
962 byte_offset = (u8)(tone_idx_tmp >> 3);
963 bit_offset = (u8)(tone_idx_tmp & 0x7);
964 target_reg = csi_mask_reg_p + byte_offset;
965
966 } else {
967 tone_num_shift = tone_num;
968
969 if (tone_idx_tmp >= tone_num)
970 tone_idx_tmp = tone_num;
971
972 tone_idx_tmp = tone_num - tone_idx_tmp;
973
974 byte_offset = (u8)(tone_idx_tmp >> 3);
975 bit_offset = (u8)(tone_idx_tmp & 0x7);
976 target_reg = csi_mask_reg_n + byte_offset;
977 }
978
979 reg_tmp_value = odm_read_1byte(dm, target_reg);
980 PHYDM_DBG(dm, ODM_COMP_API,
981 "Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n",
982 (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value);
983 reg_tmp_value |= BIT(bit_offset);
984 odm_write_1byte(dm, target_reg, reg_tmp_value);
985 PHYDM_DBG(dm, ODM_COMP_API,
986 "New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n",
987 (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value);
988 }
989
phydm_set_nbi_reg(void * dm_void,u32 tone_idx_tmp,u32 bw)990 void phydm_set_nbi_reg(void *dm_void, u32 tone_idx_tmp, u32 bw)
991 {
992 struct dm_struct *dm = (struct dm_struct *)dm_void;
993 /*tone_idx X 10*/
994 u32 nbi_128[NBI_128TONE] = {25, 55, 85, 115, 135,
995 155, 185, 205, 225, 245,
996 265, 285, 305, 335, 355,
997 375, 395, 415, 435, 455,
998 485, 505, 525, 555, 585, 615, 635};
999 /*tone_idx X 10*/
1000 u32 nbi_256[NBI_256TONE] = {25, 55, 85, 115, 135,
1001 155, 175, 195, 225, 245,
1002 265, 285, 305, 325, 345,
1003 365, 385, 405, 425, 445,
1004 465, 485, 505, 525, 545,
1005 565, 585, 605, 625, 645,
1006 665, 695, 715, 735, 755,
1007 775, 795, 815, 835, 855,
1008 875, 895, 915, 935, 955,
1009 975, 995, 1015, 1035, 1055,
1010 1085, 1105, 1125, 1145, 1175,
1011 1195, 1225, 1255, 1275};
1012 u32 reg_idx = 0;
1013 u32 i;
1014 u8 nbi_table_idx = FFT_128_TYPE;
1015
1016 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1017 nbi_table_idx = FFT_128_TYPE;
1018 } else if (dm->support_ic_type & ODM_IC_11AC_1_SERIES) {
1019 nbi_table_idx = FFT_256_TYPE;
1020 } else if (dm->support_ic_type & ODM_IC_11AC_2_SERIES) {
1021 if (bw == 80)
1022 nbi_table_idx = FFT_256_TYPE;
1023 else /*@20M, 40M*/
1024 nbi_table_idx = FFT_128_TYPE;
1025 }
1026
1027 if (nbi_table_idx == FFT_128_TYPE) {
1028 for (i = 0; i < NBI_128TONE; i++) {
1029 if (tone_idx_tmp < nbi_128[i]) {
1030 reg_idx = i + 1;
1031 break;
1032 }
1033 }
1034
1035 } else if (nbi_table_idx == FFT_256_TYPE) {
1036 for (i = 0; i < NBI_256TONE; i++) {
1037 if (tone_idx_tmp < nbi_256[i]) {
1038 reg_idx = i + 1;
1039 break;
1040 }
1041 }
1042 }
1043
1044 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1045 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, reg_idx);
1046 PHYDM_DBG(dm, ODM_COMP_API,
1047 "Set tone idx: Reg0xC40[28:24] = ((0x%x))\n",
1048 reg_idx);
1049 } else {
1050 odm_set_bb_reg(dm, R_0x87c, 0xfc000, reg_idx);
1051 PHYDM_DBG(dm, ODM_COMP_API,
1052 "Set tone idx: Reg0x87C[19:14] = ((0x%x))\n",
1053 reg_idx);
1054 }
1055 }
1056
phydm_nbi_enable(void * dm_void,u32 enable)1057 void phydm_nbi_enable(void *dm_void, u32 enable)
1058 {
1059 struct dm_struct *dm = (struct dm_struct *)dm_void;
1060 u32 val = 0;
1061
1062 val = (enable == FUNC_ENABLE) ? 1 : 0;
1063
1064 PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI=%d\n", val);
1065
1066 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1067 if (dm->support_ic_type & (ODM_RTL8192F | ODM_RTL8197F)) {
1068 val = (enable == FUNC_ENABLE) ? 0xf : 0;
1069 odm_set_bb_reg(dm, R_0xc50, 0xf000000, val);
1070 } else {
1071 odm_set_bb_reg(dm, R_0xc40, BIT(9), val);
1072 }
1073 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1074 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C |
1075 ODM_RTL8195B)) {
1076 odm_set_bb_reg(dm, R_0x87c, BIT(13), val);
1077 odm_set_bb_reg(dm, R_0xc20, BIT(28), val);
1078 if (dm->rf_type > RF_1T1R)
1079 odm_set_bb_reg(dm, R_0xe20, BIT(28), val);
1080 } else {
1081 odm_set_bb_reg(dm, R_0x87c, BIT(13), val);
1082 }
1083 }
1084 }
1085
phydm_find_fc(void * dm_void,u32 channel,u32 bw,u32 second_ch,u32 * fc_in)1086 u8 phydm_find_fc(void *dm_void, u32 channel, u32 bw, u32 second_ch, u32 *fc_in)
1087 {
1088 struct dm_struct *dm = (struct dm_struct *)dm_void;
1089 u32 fc = *fc_in;
1090 u32 start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100,
1091 108, 116, 124, 132, 140,
1092 149, 157, 165, 173};
1093 u32 start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132,
1094 149, 165};
1095 u32 *start_ch = &start_ch_per_40m[0];
1096 u32 num_start_channel = NUM_START_CH_40M;
1097 u32 channel_offset = 0;
1098 u32 i;
1099
1100 /*@2.4G*/
1101 if (channel <= 14 && channel > 0) {
1102 if (bw == 80)
1103 return PHYDM_SET_FAIL;
1104
1105 fc = 2412 + (channel - 1) * 5;
1106
1107 if (bw == 40 && second_ch == PHYDM_ABOVE) {
1108 if (channel >= 10) {
1109 PHYDM_DBG(dm, ODM_COMP_API,
1110 "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
1111 channel, second_ch);
1112 return PHYDM_SET_FAIL;
1113 }
1114 fc += 10;
1115 } else if (bw == 40 && (second_ch == PHYDM_BELOW)) {
1116 if (channel <= 2) {
1117 PHYDM_DBG(dm, ODM_COMP_API,
1118 "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
1119 channel, second_ch);
1120 return PHYDM_SET_FAIL;
1121 }
1122 fc -= 10;
1123 }
1124 }
1125 /*@5G*/
1126 else if (channel >= 36 && channel <= 177) {
1127 if (bw != 20) {
1128 if (bw == 40) {
1129 num_start_channel = NUM_START_CH_40M;
1130 start_ch = &start_ch_per_40m[0];
1131 channel_offset = CH_OFFSET_40M;
1132 } else if (bw == 80) {
1133 num_start_channel = NUM_START_CH_80M;
1134 start_ch = &start_ch_per_80m[0];
1135 channel_offset = CH_OFFSET_80M;
1136 }
1137
1138 for (i = 0; i < (num_start_channel - 1); i++) {
1139 if (channel < start_ch[i + 1]) {
1140 channel = start_ch[i] + channel_offset;
1141 break;
1142 }
1143 }
1144 PHYDM_DBG(dm, ODM_COMP_API, "Mod_CH = ((%d))\n",
1145 channel);
1146 }
1147
1148 fc = 5180 + (channel - 36) * 5;
1149
1150 } else {
1151 PHYDM_DBG(dm, ODM_COMP_API, "CH = ((%d)) Error setting\n",
1152 channel);
1153 return PHYDM_SET_FAIL;
1154 }
1155
1156 *fc_in = fc;
1157
1158 return PHYDM_SET_SUCCESS;
1159 }
1160
phydm_find_intf_distance(void * dm_void,u32 bw,u32 fc,u32 f_interference,u32 * tone_idx_tmp_in)1161 u8 phydm_find_intf_distance(void *dm_void, u32 bw, u32 fc, u32 f_interference,
1162 u32 *tone_idx_tmp_in)
1163 {
1164 struct dm_struct *dm = (struct dm_struct *)dm_void;
1165 u32 bw_up = 0, bw_low = 0;
1166 u32 int_distance = 0;
1167 u32 tone_idx_tmp = 0;
1168 u8 set_result = PHYDM_SET_NO_NEED;
1169
1170 bw_up = fc + bw / 2;
1171 bw_low = fc - bw / 2;
1172
1173 PHYDM_DBG(dm, ODM_COMP_API,
1174 "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low,
1175 fc, bw_up, f_interference);
1176
1177 if (f_interference >= bw_low && f_interference <= bw_up) {
1178 int_distance = DIFF_2(fc, f_interference);
1179 /*@10*(int_distance /0.3125)*/
1180 tone_idx_tmp = (int_distance << 5);
1181 PHYDM_DBG(dm, ODM_COMP_API,
1182 "int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n",
1183 int_distance, tone_idx_tmp / 10,
1184 tone_idx_tmp % 10);
1185 *tone_idx_tmp_in = tone_idx_tmp;
1186 set_result = PHYDM_SET_SUCCESS;
1187 }
1188
1189 return set_result;
1190 }
1191
phydm_csi_mask_setting(void * dm_void,u32 enable,u32 ch,u32 bw,u32 f_intf,u32 sec_ch)1192 u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw,
1193 u32 f_intf, u32 sec_ch)
1194 {
1195 struct dm_struct *dm = (struct dm_struct *)dm_void;
1196 u32 fc = 2412;
1197 u8 direction = FREQ_POSITIVE;
1198 u32 tone_idx = 0;
1199 u8 set_result = PHYDM_SET_SUCCESS;
1200 u8 rpt = 0;
1201
1202 if (enable == FUNC_DISABLE) {
1203 set_result = PHYDM_SET_SUCCESS;
1204 phydm_clean_all_csi_mask(dm);
1205
1206 } else {
1207 PHYDM_DBG(dm, ODM_COMP_API,
1208 "[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
1209 ch, bw, f_intf,
1210 (((bw == 20) || (ch > 14)) ? "Don't care" :
1211 (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
1212
1213 /*@calculate fc*/
1214 if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
1215 set_result = PHYDM_SET_FAIL;
1216 } else {
1217 /*@calculate interference distance*/
1218 rpt = phydm_find_intf_distance(dm, bw, fc, f_intf,
1219 &tone_idx);
1220 if (rpt == PHYDM_SET_SUCCESS) {
1221 if (f_intf >= fc)
1222 direction = FREQ_POSITIVE;
1223 else
1224 direction = FREQ_NEGATIVE;
1225
1226 phydm_set_csi_mask(dm, tone_idx, direction);
1227 set_result = PHYDM_SET_SUCCESS;
1228 } else {
1229 set_result = PHYDM_SET_NO_NEED;
1230 }
1231 }
1232 }
1233
1234 if (set_result == PHYDM_SET_SUCCESS)
1235 phydm_csi_mask_enable(dm, enable);
1236 else
1237 phydm_csi_mask_enable(dm, FUNC_DISABLE);
1238
1239 return set_result;
1240 }
1241
phydm_spur_case_mapping(void * dm_void)1242 boolean phydm_spur_case_mapping(void *dm_void)
1243 {
1244 struct dm_struct *dm = (struct dm_struct *)dm_void;
1245 u8 channel = *dm->channel, bw = *dm->band_width;
1246 boolean mapping_result = false;
1247 #if (RTL8814B_SUPPORT == 1)
1248 if (channel == 153 && bw == CHANNEL_WIDTH_20)
1249 mapping_result = true;
1250 else if (channel == 151 && bw == CHANNEL_WIDTH_40)
1251 mapping_result = true;
1252 else if (channel == 155 && bw == CHANNEL_WIDTH_80)
1253 mapping_result = true;
1254 #endif
1255 return mapping_result;
1256 }
1257
phydm_ch_to_rf_band(void * dm_void,u8 central_ch)1258 enum odm_rf_band phydm_ch_to_rf_band(void *dm_void, u8 central_ch)
1259 {
1260 struct dm_struct *dm = (struct dm_struct *)dm_void;
1261 enum odm_rf_band rf_band = ODM_RF_BAND_5G_LOW;
1262
1263 if (central_ch <= 14)
1264 rf_band = ODM_RF_BAND_2G;
1265 else if (central_ch >= 36 && central_ch <= 64)
1266 rf_band = ODM_RF_BAND_5G_LOW;
1267 else if ((central_ch >= 100) && (central_ch <= 144))
1268 rf_band = ODM_RF_BAND_5G_MID;
1269 else if (central_ch >= 149)
1270 rf_band = ODM_RF_BAND_5G_HIGH;
1271 else
1272 PHYDM_DBG(dm, ODM_COMP_API, "mapping channel to band fail\n");
1273
1274 return rf_band;
1275 }
1276
1277 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
phydm_rf_psd_jgr3(void * dm_void,u8 path,u32 tone_idx)1278 u32 phydm_rf_psd_jgr3(void *dm_void, u8 path, u32 tone_idx)
1279 {
1280 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
1281 struct dm_struct *dm = (struct dm_struct *)dm_void;
1282 u32 reg_1b04 = 0, reg_1b08 = 0, reg_1b0c_11_10 = 0;
1283 u32 reg_1b14 = 0, reg_1b18 = 0, reg_1b1c = 0;
1284 u32 reg_1b28 = 0;
1285 u32 reg_1bcc_5_0 = 0;
1286 u32 reg_1b2c_27_16 = 0, reg_1b34 = 0, reg_1bd4 = 0;
1287 u32 reg_180c = 0, reg_410c = 0, reg_520c = 0, reg_530c = 0;
1288 u32 igi = 0;
1289 u32 i = 0;
1290 u32 psd_val = 0, psd_val_msb = 0, psd_val_lsb = 0, psd_max = 0;
1291 u32 psd_status_temp = 0;
1292 u16 poll_cnt = 0;
1293
1294 /*read and record the ori. value*/
1295 reg_1b04 = odm_get_bb_reg(dm, R_0x1b04, MASKDWORD);
1296 reg_1b08 = odm_get_bb_reg(dm, R_0x1b08, MASKDWORD);
1297 reg_1b0c_11_10 = odm_get_bb_reg(dm, R_0x1b0c, 0xc00);
1298 reg_1b14 = odm_get_bb_reg(dm, R_0x1b14, MASKDWORD);
1299 reg_1b18 = odm_get_bb_reg(dm, R_0x1b18, MASKDWORD);
1300 reg_1b1c = odm_get_bb_reg(dm, R_0x1b1c, MASKDWORD);
1301 reg_1b28 = odm_get_bb_reg(dm, R_0x1b28, MASKDWORD);
1302 reg_1bcc_5_0 = odm_get_bb_reg(dm, R_0x1bcc, 0x3f);
1303 reg_1b2c_27_16 = odm_get_bb_reg(dm, R_0x1b2c, 0xfff0000);
1304 reg_1b34 = odm_get_bb_reg(dm, R_0x1b34, MASKDWORD);
1305 reg_1bd4 = odm_get_bb_reg(dm, R_0x1bd4, MASKDWORD);
1306 igi = odm_get_bb_reg(dm, R_0x1d70, MASKDWORD);
1307 reg_180c = odm_get_bb_reg(dm, R_0x180c, 0x3);
1308 reg_410c = odm_get_bb_reg(dm, R_0x410c, 0x3);
1309 reg_520c = odm_get_bb_reg(dm, R_0x520c, 0x3);
1310 reg_530c = odm_get_bb_reg(dm, R_0x530c, 0x3);
1311
1312 /*rf psd reg setting*/
1313 odm_set_bb_reg(dm, R_0x1b00, 0x6, path); /*path is RF_path*/
1314 odm_set_bb_reg(dm, R_0x1b04, MASKDWORD, 0x0);
1315 odm_set_bb_reg(dm, R_0x1b08, MASKDWORD, 0x80);
1316 odm_set_bb_reg(dm, R_0x1b0c, 0xc00, 0x3);
1317 odm_set_bb_reg(dm, R_0x1b14, MASKDWORD, 0x0);
1318 odm_set_bb_reg(dm, R_0x1b18, MASKDWORD, 0x1);
1319 /*#if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/
1320 odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, 0x82103D21);
1321 /*#else*/
1322 /*odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, 0x821A3D21);*/
1323 /*#endif*/
1324 odm_set_bb_reg(dm, R_0x1b28, MASKDWORD, 0x0);
1325 odm_set_bb_reg(dm, R_0x1bcc, 0x3f, 0x3f);
1326 odm_set_bb_reg(dm, R_0x8a0, 0xf, 0x0); /* AGC off */
1327 odm_set_bb_reg(dm, R_0x1d70, MASKDWORD, 0x20202020);
1328
1329 for (i = tone_idx - 1; i <= tone_idx + 1; i++) {
1330 /*set psd tone_idx for detection*/
1331 odm_set_bb_reg(dm, R_0x1b2c, 0xfff0000, i);
1332 /*one shot for RXIQK psd*/
1333 odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x1);
1334 odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x0);
1335
1336 if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C))
1337 for (poll_cnt = 0; poll_cnt < 20; poll_cnt++) {
1338 odm_set_bb_reg(dm, R_0x1bd4, 0x3f0000, 0x2b);
1339 psd_status_temp = odm_get_bb_reg(dm, R_0x1bfc,
1340 BIT(1));
1341 if (!psd_status_temp)
1342 ODM_delay_us(10);
1343 else
1344 break;
1345 }
1346 else
1347 ODM_delay_us(250);
1348
1349 /*read RxIQK power*/
1350 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);
1351 if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C))
1352 psd_val_msb = odm_get_bb_reg(dm, R_0x1bfc, 0x7ff0000);
1353 else if (dm->support_ic_type & ODM_RTL8198F)
1354 psd_val_msb = odm_get_bb_reg(dm, R_0x1bfc, 0x1f0000);
1355
1356 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001);
1357 psd_val_lsb = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
1358 if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C))
1359 psd_val = (psd_val_msb << 21) + (psd_val_lsb >> 11);
1360 else if (dm->support_ic_type & ODM_RTL8198F)
1361 psd_val = (psd_val_msb << 27) + (psd_val_lsb >> 5);
1362
1363 if (psd_val > psd_max)
1364 psd_max = psd_val;
1365 }
1366
1367 /*refill the ori. value*/
1368 odm_set_bb_reg(dm, R_0x1b00, 0x6, path);
1369 odm_set_bb_reg(dm, R_0x1b04, MASKDWORD, reg_1b04);
1370 odm_set_bb_reg(dm, R_0x1b08, MASKDWORD, reg_1b08);
1371 odm_set_bb_reg(dm, R_0x1b0c, 0xc00, reg_1b0c_11_10);
1372 odm_set_bb_reg(dm, R_0x1b14, MASKDWORD, reg_1b14);
1373 odm_set_bb_reg(dm, R_0x1b18, MASKDWORD, reg_1b18);
1374 odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, reg_1b1c);
1375 odm_set_bb_reg(dm, R_0x1b28, MASKDWORD, reg_1b28);
1376 odm_set_bb_reg(dm, R_0x1bcc, 0x3f, reg_1bcc_5_0);
1377 odm_set_bb_reg(dm, R_0x1b2c, 0xfff0000, reg_1b2c_27_16);
1378 odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, reg_1b34);
1379 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, reg_1bd4);
1380 odm_set_bb_reg(dm, R_0x8a0, 0xf, 0xf); /* AGC on */
1381 odm_set_bb_reg(dm, R_0x1d70, MASKDWORD, igi);
1382 PHYDM_DBG(dm, ODM_COMP_API, "psd_max %d\n", psd_max);
1383
1384 return psd_max;
1385 #else
1386 return 0;
1387 #endif
1388 }
1389
phydm_find_intf_distance_jgr3(void * dm_void,u32 bw,u32 fc,u32 f_interference,u32 * tone_idx_tmp_in)1390 u8 phydm_find_intf_distance_jgr3(void *dm_void, u32 bw, u32 fc,
1391 u32 f_interference, u32 *tone_idx_tmp_in)
1392 {
1393 struct dm_struct *dm = (struct dm_struct *)dm_void;
1394 u32 bw_up = 0, bw_low = 0;
1395 u32 int_distance = 0;
1396 u32 tone_idx_tmp = 0;
1397 u8 set_result = PHYDM_SET_NO_NEED;
1398 u8 channel = *dm->channel;
1399
1400 bw_up = 1000 * (fc + bw / 2);
1401 bw_low = 1000 * (fc - bw / 2);
1402 fc = 1000 * fc;
1403
1404 PHYDM_DBG(dm, ODM_COMP_API,
1405 "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low,
1406 fc, bw_up, f_interference);
1407
1408 if (f_interference >= bw_low && f_interference <= bw_up) {
1409 int_distance = DIFF_2(fc, f_interference);
1410 /*@10*(int_distance /0.3125)*/
1411 if (channel < 15 &&
1412 (dm->support_ic_type &
1413 (ODM_RTL8814B | ODM_RTL8198F | ODM_RTL8814C)))
1414 tone_idx_tmp = int_distance / 312;
1415 else
1416 tone_idx_tmp = ((int_distance + 156) / 312);
1417 PHYDM_DBG(dm, ODM_COMP_API,
1418 "int_distance = ((%d)) , tone_idx_tmp = ((%d))\n",
1419 int_distance, tone_idx_tmp);
1420 *tone_idx_tmp_in = tone_idx_tmp;
1421 set_result = PHYDM_SET_SUCCESS;
1422 }
1423
1424 return set_result;
1425 }
1426
phydm_csi_mask_setting_jgr3(void * dm_void,u32 enable,u32 ch,u32 bw,u32 f_intf,u32 sec_ch,u8 wgt)1427 u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw,
1428 u32 f_intf, u32 sec_ch, u8 wgt)
1429 {
1430 struct dm_struct *dm = (struct dm_struct *)dm_void;
1431 u32 fc = 2412;
1432 u8 direction = FREQ_POSITIVE;
1433 u32 tone_idx = 0;
1434 u8 set_result = PHYDM_SET_SUCCESS;
1435 u8 rpt = 0;
1436
1437 if (enable == FUNC_DISABLE) {
1438 phydm_csi_mask_enable(dm, FUNC_ENABLE);
1439 phydm_clean_all_csi_mask(dm);
1440 phydm_csi_mask_enable(dm, FUNC_DISABLE);
1441 set_result = PHYDM_SET_SUCCESS;
1442 } else {
1443 PHYDM_DBG(dm, ODM_COMP_API,
1444 "[Set CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s)), wgt = ((%d))\n",
1445 ch, bw, f_intf,
1446 (((bw == 20) || (ch > 14)) ? "Don't care" :
1447 (sec_ch == PHYDM_ABOVE) ? "H" : "L"), wgt);
1448
1449 /*@calculate fc*/
1450 if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
1451 set_result = PHYDM_SET_FAIL;
1452 } else {
1453 /*@calculate interference distance*/
1454 rpt = phydm_find_intf_distance_jgr3(dm, bw, fc, f_intf,
1455 &tone_idx);
1456 if (rpt == PHYDM_SET_SUCCESS) {
1457 if (f_intf >= 1000 * fc)
1458 direction = FREQ_POSITIVE;
1459 else
1460 direction = FREQ_NEGATIVE;
1461
1462 phydm_csi_mask_enable(dm, FUNC_ENABLE);
1463 phydm_set_csi_mask_jgr3(dm, tone_idx, direction,
1464 wgt);
1465 set_result = PHYDM_SET_SUCCESS;
1466 } else {
1467 set_result = PHYDM_SET_NO_NEED;
1468 }
1469 }
1470 if (!(set_result == PHYDM_SET_SUCCESS))
1471 phydm_csi_mask_enable(dm, FUNC_DISABLE);
1472 }
1473
1474 return set_result;
1475 }
1476
phydm_set_csi_mask_jgr3(void * dm_void,u32 tone_idx_tmp,u8 tone_direction,u8 wgt)1477 void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
1478 u8 wgt)
1479 {
1480 struct dm_struct *dm = (struct dm_struct *)dm_void;
1481 u32 multi_tone_idx_tmp = 0;
1482 u32 reg_tmp = 0;
1483 u32 tone_num = 64;
1484 u32 table_addr = 0;
1485 u32 addr = 0;
1486 u8 rf_bw = 0;
1487 u8 value = 0;
1488 u8 channel = *dm->channel;
1489
1490 rf_bw = odm_read_1byte(dm, R_0x9b0);
1491 if (((rf_bw & 0xc) >> 2) == 0x2)
1492 tone_num = 128; /* @RF80 : tone(-1) at tone_idx=255 */
1493 else
1494 tone_num = 64; /* @RF20/40 : tone(-1) at tone_idx=127 */
1495
1496 if (tone_direction == FREQ_POSITIVE) {
1497 if (tone_idx_tmp >= (tone_num - 1))
1498 tone_idx_tmp = (tone_num - 1);
1499 } else {
1500 if (tone_idx_tmp >= tone_num)
1501 tone_idx_tmp = tone_num;
1502
1503 tone_idx_tmp = (tone_num << 1) - tone_idx_tmp;
1504 }
1505 table_addr = tone_idx_tmp >> 1;
1506
1507 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1508 PHYDM_DBG(dm, ODM_COMP_API,
1509 "Pre Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
1510 tone_idx_tmp, reg_tmp);
1511 odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3);
1512 odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1);
1513
1514 if (channel < 15 &&
1515 (dm->support_ic_type &
1516 (ODM_RTL8814B | ODM_RTL8198F | ODM_RTL8814C))) {
1517 if (tone_idx_tmp % 2 == 1) {
1518 if (tone_direction == FREQ_POSITIVE) {
1519 /*===Tone 1===*/
1520 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1521 (table_addr & 0xff));
1522 value = (BIT(3) | (wgt & 0x7)) << 4;
1523 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1524 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1525 PHYDM_DBG(dm, ODM_COMP_API,
1526 "New Mask tone 1 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1527 tone_idx_tmp, reg_tmp);
1528 /*===Tone 2===*/
1529 value = 0;
1530 multi_tone_idx_tmp = tone_idx_tmp + 1;
1531 table_addr = multi_tone_idx_tmp >> 1;
1532 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1533 (table_addr & 0xff));
1534 value = (BIT(3) | (wgt & 0x7));
1535 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1536 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1537 PHYDM_DBG(dm, ODM_COMP_API,
1538 "New Mask tone 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1539 tone_idx_tmp, reg_tmp);
1540 } else {
1541 /*===Tone 1 & 2===*/
1542 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1543 (table_addr & 0xff));
1544 value = ((BIT(3) | (wgt & 0x7)) << 4) |
1545 (BIT(3) | (wgt & 0x7));
1546 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1547 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1548 PHYDM_DBG(dm, ODM_COMP_API,
1549 "New Mask tone 1 & 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1550 tone_idx_tmp, reg_tmp);
1551 }
1552 } else {
1553 if (tone_direction == FREQ_POSITIVE) {
1554 /*===Tone 1 & 2===*/
1555 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1556 (table_addr & 0xff));
1557 value = ((BIT(3) | (wgt & 0x7)) << 4) |
1558 (BIT(3) | (wgt & 0x7));
1559 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1560 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1561 PHYDM_DBG(dm, ODM_COMP_API,
1562 "New Mask tone 1 & 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1563 tone_idx_tmp, reg_tmp);
1564 } else {
1565 /*===Tone 1===*/
1566 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1567 (table_addr & 0xff));
1568 value = (BIT(3) | (wgt & 0x7));
1569 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1570 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1571 PHYDM_DBG(dm, ODM_COMP_API,
1572 "New Mask tone 1 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1573 tone_idx_tmp, reg_tmp);
1574
1575 /*===Tone 2===*/
1576 value = 0;
1577 multi_tone_idx_tmp = tone_idx_tmp - 1;
1578 table_addr = multi_tone_idx_tmp >> 1;
1579 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1580 (table_addr & 0xff));
1581 value = (BIT(3) | (wgt & 0x7)) << 4;
1582 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1583 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1584 PHYDM_DBG(dm, ODM_COMP_API,
1585 "New Mask tone 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1586 tone_idx_tmp, reg_tmp);
1587 }
1588 }
1589 } else {
1590 if ((dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) &&
1591 phydm_spur_case_mapping(dm)) {
1592 if (!(tone_idx_tmp % 2)) {
1593 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1594 (table_addr & 0xff));
1595 value = ((BIT(3) | (((wgt + 4) <= 7 ? (wgt +
1596 4) : 7) & 0x7)) << 4) | (BIT(3) |
1597 (wgt & 0x7));
1598 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1599 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1600 PHYDM_DBG(dm, ODM_COMP_API,
1601 "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
1602 tone_idx_tmp, reg_tmp);
1603 if (tone_idx_tmp == 0)
1604 table_addr = tone_num - 1;
1605 else
1606 table_addr = table_addr - 1;
1607 if (tone_idx_tmp != tone_num) {
1608 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1609 (table_addr & 0xff));
1610 value = (BIT(3) | (((wgt + 4) <= 7 ?
1611 (wgt + 4) : 7) & 0x7)) << 4;
1612 odm_set_bb_reg(dm, R_0x1d94, 0xff,
1613 value);
1614 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1615 PHYDM_DBG(dm, ODM_COMP_API,
1616 "New Mask Reg0x1d94 = ((0x%x))\n",
1617 reg_tmp);
1618 }
1619 } else {
1620 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1621 (table_addr & 0xff));
1622 value = ((BIT(3) | (wgt & 0x7)) << 4) |
1623 (BIT(3) | (((wgt + 4) <= 7 ? (wgt +
1624 4) : 7) & 0x7));
1625 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1626 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1627 PHYDM_DBG(dm, ODM_COMP_API,
1628 "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
1629 tone_idx_tmp, reg_tmp);
1630 if (tone_idx_tmp == (tone_num << 1) - 1)
1631 table_addr = 0;
1632 else
1633 table_addr = table_addr + 1;
1634 if (tone_idx_tmp != tone_num - 1) {
1635 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1636 (table_addr & 0xff));
1637 value = (BIT(3) | (((wgt + 4) <= 7 ?
1638 (wgt + 4) : 7) & 0x7));
1639 odm_set_bb_reg(dm, R_0x1d94, 0xff,
1640 value);
1641 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1642 PHYDM_DBG(dm, ODM_COMP_API,
1643 "New Mask Reg0x1d94 = ((0x%x))\n",
1644 reg_tmp);
1645 }
1646 }
1647 } else {
1648 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, (table_addr &
1649 0xff));
1650 if (tone_idx_tmp % 2)
1651 value = (BIT(3) | (wgt & 0x7)) << 4;
1652 else
1653 value = BIT(3) | (wgt & 0x7);
1654
1655 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1656 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1657 PHYDM_DBG(dm, ODM_COMP_API,
1658 "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
1659 tone_idx_tmp, reg_tmp);
1660 }
1661 }
1662 odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0);
1663 }
1664
phydm_nbi_reset_jgr3(void * dm_void)1665 void phydm_nbi_reset_jgr3(void *dm_void)
1666 {
1667 struct dm_struct *dm = (struct dm_struct *)dm_void;
1668
1669 odm_set_bb_reg(dm, R_0x818, BIT(3), 1);
1670 odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0);
1671 odm_set_bb_reg(dm, R_0x818, BIT(3), 0);
1672 odm_set_bb_reg(dm, R_0x818, BIT(11), 0);
1673 #if RTL8814B_SUPPORT
1674 if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) {
1675 odm_set_bb_reg(dm, R_0x1944, 0x300, 0x3);
1676 odm_set_bb_reg(dm, R_0x4044, 0x300, 0x3);
1677 odm_set_bb_reg(dm, R_0x5044, 0x300, 0x3);
1678 odm_set_bb_reg(dm, R_0x5144, 0x300, 0x3);
1679 odm_set_bb_reg(dm, R_0x810, 0xf, 0x0);
1680 odm_set_bb_reg(dm, R_0x810, 0xf0000, 0x0);
1681 odm_set_bb_reg(dm, R_0xc24, MASKDWORD, 0x406000ff);
1682 }
1683 #endif
1684 }
1685
phydm_nbi_setting_jgr3(void * dm_void,u32 enable,u32 ch,u32 bw,u32 f_intf,u32 sec_ch,u8 path)1686 u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
1687 u32 sec_ch, u8 path)
1688 {
1689 struct dm_struct *dm = (struct dm_struct *)dm_void;
1690 u32 fc = 2412;
1691 u8 direction = FREQ_POSITIVE;
1692 u32 tone_idx = 0;
1693 u8 set_result = PHYDM_SET_SUCCESS;
1694 u8 rpt = 0;
1695
1696 if (enable == FUNC_DISABLE) {
1697 phydm_nbi_reset_jgr3(dm);
1698 set_result = PHYDM_SET_SUCCESS;
1699 } else {
1700 PHYDM_DBG(dm, ODM_COMP_API,
1701 "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
1702 ch, bw, f_intf,
1703 (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) ||
1704 (ch > 14)) ? "Don't care" :
1705 (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
1706
1707 /*@calculate fc*/
1708 if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
1709 set_result = PHYDM_SET_FAIL;
1710 } else {
1711 /*@calculate interference distance*/
1712 rpt = phydm_find_intf_distance_jgr3(dm, bw, fc, f_intf,
1713 &tone_idx);
1714 if (rpt == PHYDM_SET_SUCCESS) {
1715 if (f_intf >= 1000 * fc)
1716 direction = FREQ_POSITIVE;
1717 else
1718 direction = FREQ_NEGATIVE;
1719
1720 phydm_set_nbi_reg_jgr3(dm, tone_idx, direction,
1721 path);
1722 set_result = PHYDM_SET_SUCCESS;
1723 } else {
1724 set_result = PHYDM_SET_NO_NEED;
1725 }
1726 }
1727 }
1728
1729 if (set_result == PHYDM_SET_SUCCESS)
1730 phydm_nbi_enable_jgr3(dm, enable, path);
1731 else
1732 phydm_nbi_enable_jgr3(dm, FUNC_DISABLE, path);
1733
1734 if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C))
1735 odm_set_bb_reg(dm, R_0x1d3c, BIT(19), 0);
1736
1737 return set_result;
1738 }
1739
phydm_set_nbi_reg_jgr3(void * dm_void,u32 tone_idx_tmp,u8 tone_direction,u8 path)1740 void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
1741 u8 path)
1742 {
1743 struct dm_struct *dm = (struct dm_struct *)dm_void;
1744 u32 reg_tmp_value = 0;
1745 u32 tone_num = 64;
1746 u32 addr = 0;
1747 u8 rf_bw = 0;
1748
1749 rf_bw = odm_read_1byte(dm, R_0x9b0);
1750 if (((rf_bw & 0xc) >> 2) == 0x2)
1751 tone_num = 128; /* RF80 : tone-1 at tone_idx=255 */
1752 else
1753 tone_num = 64; /* RF20/40 : tone-1 at tone_idx=127 */
1754
1755 if (tone_direction == FREQ_POSITIVE) {
1756 if (tone_idx_tmp >= (tone_num - 1))
1757 tone_idx_tmp = (tone_num - 1);
1758 } else {
1759 if (tone_idx_tmp >= tone_num)
1760 tone_idx_tmp = tone_num;
1761
1762 tone_idx_tmp = (tone_num << 1) - tone_idx_tmp;
1763 }
1764 /*Mark the tone idx for Packet detection*/
1765 #if RTL8814B_SUPPORT
1766 if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) {
1767 odm_set_bb_reg(dm, R_0xc24, 0xff, 0xff);
1768 if ((*dm->channel == 5) &&
1769 (*dm->band_width == CHANNEL_WIDTH_40))
1770 odm_set_bb_reg(dm, R_0xc24, 0xff00, 0x1a);
1771 else
1772 odm_set_bb_reg(dm, R_0xc24, 0xff00, tone_idx_tmp);
1773 }
1774 #endif
1775 switch (path) {
1776 case RF_PATH_A:
1777 odm_set_bb_reg(dm, R_0x1944, 0x001FF000, tone_idx_tmp);
1778 PHYDM_DBG(dm, ODM_COMP_API,
1779 "Set tone idx[%d]:PATH-A = ((0x%x))\n",
1780 tone_idx_tmp, tone_idx_tmp);
1781 break;
1782 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
1783 case RF_PATH_B:
1784 odm_set_bb_reg(dm, R_0x4044, 0x001FF000, tone_idx_tmp);
1785 PHYDM_DBG(dm, ODM_COMP_API,
1786 "Set tone idx[%d]:PATH-B = ((0x%x))\n",
1787 tone_idx_tmp, tone_idx_tmp);
1788 break;
1789 #endif
1790 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
1791 case RF_PATH_C:
1792 odm_set_bb_reg(dm, R_0x5044, 0x001FF000, tone_idx_tmp);
1793 PHYDM_DBG(dm, ODM_COMP_API,
1794 "Set tone idx[%d]:PATH-C = ((0x%x))\n",
1795 tone_idx_tmp, tone_idx_tmp);
1796 break;
1797 #endif
1798 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
1799 case RF_PATH_D:
1800 odm_set_bb_reg(dm, R_0x5144, 0x001FF000, tone_idx_tmp);
1801 PHYDM_DBG(dm, ODM_COMP_API,
1802 "Set tone idx[%d]:PATH-D = ((0x%x))\n",
1803 tone_idx_tmp, tone_idx_tmp);
1804 break;
1805 #endif
1806 default:
1807 break;
1808 }
1809 }
1810
phydm_nbi_enable_jgr3(void * dm_void,u32 enable,u8 path)1811 void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path)
1812 {
1813 struct dm_struct *dm = (struct dm_struct *)dm_void;
1814 boolean val = false;
1815
1816 val = (enable == FUNC_ENABLE) ? true : false;
1817
1818 PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI=%d\n", val);
1819
1820 if (dm->support_ic_type & ODM_RTL8814B) {
1821 odm_set_bb_reg(dm, R_0x1d3c, BIT(19), val);
1822 odm_set_bb_reg(dm, R_0x818, BIT(3), val);
1823 } else if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
1824 odm_set_bb_reg(dm, R_0x818, BIT(3), !val);
1825 }
1826 odm_set_bb_reg(dm, R_0x818, BIT(11), val);
1827 odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0xf);
1828
1829 if (enable == FUNC_ENABLE) {
1830 switch (path) {
1831 case RF_PATH_A:
1832 odm_set_bb_reg(dm, R_0x1940, BIT(31), val);
1833 break;
1834 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
1835 case RF_PATH_B:
1836 odm_set_bb_reg(dm, R_0x4040, BIT(31), val);
1837 break;
1838 #endif
1839 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
1840 case RF_PATH_C:
1841 odm_set_bb_reg(dm, R_0x5040, BIT(31), val);
1842 break;
1843 #endif
1844 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
1845 case RF_PATH_D:
1846 odm_set_bb_reg(dm, R_0x5140, BIT(31), val);
1847 break;
1848 #endif
1849 default:
1850 break;
1851 }
1852 } else {
1853 odm_set_bb_reg(dm, R_0x1940, BIT(31), val);
1854 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
1855 odm_set_bb_reg(dm, R_0x4040, BIT(31), val);
1856 #endif
1857 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
1858 odm_set_bb_reg(dm, R_0x5040, BIT(31), val);
1859 #endif
1860 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
1861 odm_set_bb_reg(dm, R_0x5140, BIT(31), val);
1862 #endif
1863 #if RTL8812F_SUPPORT
1864 if (dm->support_ic_type & ODM_RTL8812F) {
1865 odm_set_bb_reg(dm, R_0x818, BIT(3), val);
1866 odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0x0);
1867 }
1868 #endif
1869 }
1870 }
1871
phydm_phystat_rpt_jgr3(void * dm_void,enum phystat_rpt info,enum rf_path ant_path)1872 u8 phydm_phystat_rpt_jgr3(void *dm_void, enum phystat_rpt info,
1873 enum rf_path ant_path)
1874 {
1875 struct dm_struct *dm = (struct dm_struct *)dm_void;
1876 s8 evm_org, cfo_org, rxsnr_org;
1877 u8 i, return_info = 0, tmp_lsb = 0, tmp_msb = 0, tmp_info = 0;
1878
1879 /* Update the status for each pkt */
1880 odm_set_bb_reg(dm, R_0x8c4, 0xfff000, 0x448);
1881 odm_set_bb_reg(dm, R_0x8c0, MASKLWORD, 0x4001);
1882 /* PHY status Page1 */
1883 odm_set_bb_reg(dm, R_0x8c0, 0x3C00000, 0x1);
1884 /*choose debug port for phystatus */
1885 odm_set_bb_reg(dm, R_0x1c3c, 0xFFF00, 0x380);
1886
1887 if (info == PHY_PWDB) {
1888 /* Choose the report of the diff path */
1889 if (ant_path == RF_PATH_A)
1890 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1);
1891 else if (ant_path == RF_PATH_B)
1892 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x2);
1893 else if (ant_path == RF_PATH_C)
1894 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x3);
1895 else if (ant_path == RF_PATH_D)
1896 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x4);
1897 } else if (info == PHY_EVM) {
1898 /* Choose the report of the diff path */
1899 if (ant_path == RF_PATH_A)
1900 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x10);
1901 else if (ant_path == RF_PATH_B)
1902 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x11);
1903 else if (ant_path == RF_PATH_C)
1904 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x12);
1905 else if (ant_path == RF_PATH_D)
1906 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x13);
1907 return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
1908 } else if (info == PHY_CFO) {
1909 /* Choose the report of the diff path */
1910 if (ant_path == RF_PATH_A)
1911 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x14);
1912 else if (ant_path == RF_PATH_B)
1913 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x15);
1914 else if (ant_path == RF_PATH_C)
1915 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x16);
1916 else if (ant_path == RF_PATH_D)
1917 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x17);
1918 return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
1919 } else if (info == PHY_RXSNR) {
1920 /* Choose the report of the diff path */
1921 if (ant_path == RF_PATH_A)
1922 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x18);
1923 else if (ant_path == RF_PATH_B)
1924 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x19);
1925 else if (ant_path == RF_PATH_C)
1926 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1a);
1927 else if (ant_path == RF_PATH_D)
1928 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1b);
1929 return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
1930 } else if (info == PHY_LGAIN) {
1931 /* choose page */
1932 odm_set_bb_reg(dm, R_0x8c0, 0x3c00000, 0x2);
1933 /* Choose the report of the diff path */
1934 if (ant_path == RF_PATH_A) {
1935 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xd);
1936 tmp_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3f);
1937 return_info = tmp_info;
1938 } else if (ant_path == RF_PATH_B) {
1939 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xd);
1940 tmp_lsb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xc0);
1941 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xe);
1942 tmp_msb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xf);
1943 tmp_info |= (tmp_msb << 2) | tmp_lsb;
1944 return_info = tmp_info;
1945 } else if (ant_path == RF_PATH_C) {
1946 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xe);
1947 tmp_lsb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xf0);
1948 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xf);
1949 tmp_msb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3);
1950 tmp_info |= (tmp_msb << 4) | tmp_lsb;
1951 return_info = tmp_info;
1952 } else if (ant_path == RF_PATH_D) {
1953 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x10);
1954 tmp_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3f);
1955 return_info = tmp_info;
1956 }
1957 } else if (info == PHY_HT_AAGC_GAIN) {
1958 /* choose page */
1959 odm_set_bb_reg(dm, R_0x8c0, 0x3c00000, 0x2);
1960 /* Choose the report of the diff path */
1961 if (ant_path == RF_PATH_A)
1962 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x12);
1963 else if (ant_path == RF_PATH_B)
1964 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x13);
1965 else if (ant_path == RF_PATH_C)
1966 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x14);
1967 else if (ant_path == RF_PATH_D)
1968 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x15);
1969 return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
1970 }
1971 return return_info;
1972 }
1973
phydm_ex_hal8814b_wifi_only_hw_config(void * dm_void)1974 void phydm_ex_hal8814b_wifi_only_hw_config(void *dm_void)
1975 {
1976 /*BB control*/
1977 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2);*/
1978 /*SW control*/
1979 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0xff, 0x77);*/
1980 /*antenna mux switch */
1981 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x974, 0x300, 0x3);*/
1982
1983 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1990, 0x300, 0x0);*/
1984
1985 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x80000, 0x0);*/
1986 /*switch to WL side controller and gnt_wl gnt_bt debug signal */
1987 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0xff000000, 0x0e);*/
1988 /*gnt_wl=1 , gnt_bt=0*/
1989 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff,
1990 * 0x7700);
1991 */
1992 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff,
1993 * 0xc00f0038);
1994 */
1995 }
1996
phydm_user_position_for_sniffer(void * dm_void,u8 user_position)1997 void phydm_user_position_for_sniffer(void *dm_void, u8 user_position)
1998 {
1999 struct dm_struct *dm = (struct dm_struct *)dm_void;
2000
2001 /* user position valid */
2002 odm_set_bb_reg(dm, R_0xa68, BIT(17), 1);
2003 /* Select user seat from pmac */
2004 odm_set_bb_reg(dm, R_0xa68, BIT(16), 1);
2005 /*user seat*/
2006 odm_set_bb_reg(dm, R_0xa68, (BIT(19) | BIT(18)), user_position);
2007 }
2008
2009 boolean
phydm_bb_ctrl_txagc_ofst_jgr3(void * dm_void,s8 pw_offset,u8 add_half_db)2010 phydm_bb_ctrl_txagc_ofst_jgr3(void *dm_void, s8 pw_offset, /*@(unit: dB)*/
2011 u8 add_half_db /*@(+0.5 dB)*/)
2012 {
2013 struct dm_struct *dm = (struct dm_struct *)dm_void;
2014 s8 pw_idx = pw_offset * 4; /*@ 7Bit, 0.25dB unit*/
2015
2016 if (pw_offset < -16 || pw_offset > 15) {
2017 pr_debug("[Warning][%s]Ofst error=%d", __func__, pw_offset);
2018 return false;
2019 }
2020
2021 if (add_half_db)
2022 pw_idx += 2;
2023
2024 PHYDM_DBG(dm, ODM_COMP_API, "Pw_ofst=0x%x\n", pw_idx);
2025
2026 odm_set_bb_reg(dm, R_0x18a0, 0x3f, pw_idx);
2027
2028 if (dm->num_rf_path >= 2)
2029 odm_set_bb_reg(dm, R_0x41a0, 0x3f, pw_idx);
2030
2031 if (dm->num_rf_path >= 3)
2032 odm_set_bb_reg(dm, R_0x52a0, 0x3f, pw_idx);
2033
2034 if (dm->num_rf_path >= 4)
2035 odm_set_bb_reg(dm, R_0x53a0, 0x3f, pw_idx);
2036
2037 return true;
2038 }
2039
2040 #endif
phydm_nbi_setting(void * dm_void,u32 enable,u32 ch,u32 bw,u32 f_intf,u32 sec_ch)2041 u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
2042 u32 sec_ch)
2043 {
2044 struct dm_struct *dm = (struct dm_struct *)dm_void;
2045 u32 fc = 2412;
2046 u8 direction = FREQ_POSITIVE;
2047 u32 tone_idx = 0;
2048 u8 set_result = PHYDM_SET_SUCCESS;
2049 u8 rpt = 0;
2050
2051 if (enable == FUNC_DISABLE) {
2052 set_result = PHYDM_SET_SUCCESS;
2053 } else {
2054 PHYDM_DBG(dm, ODM_COMP_API,
2055 "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
2056 ch, bw, f_intf,
2057 (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) ||
2058 (ch > 14)) ? "Don't care" :
2059 (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
2060
2061 /*@calculate fc*/
2062 if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
2063 set_result = PHYDM_SET_FAIL;
2064 } else {
2065 /*@calculate interference distance*/
2066 rpt = phydm_find_intf_distance(dm, bw, fc, f_intf,
2067 &tone_idx);
2068 if (rpt == PHYDM_SET_SUCCESS) {
2069 if (f_intf >= fc)
2070 direction = FREQ_POSITIVE;
2071 else
2072 direction = FREQ_NEGATIVE;
2073
2074 phydm_set_nbi_reg(dm, tone_idx, bw);
2075
2076 set_result = PHYDM_SET_SUCCESS;
2077 } else {
2078 set_result = PHYDM_SET_NO_NEED;
2079 }
2080 }
2081 }
2082
2083 if (set_result == PHYDM_SET_SUCCESS)
2084 phydm_nbi_enable(dm, enable);
2085 else
2086 phydm_nbi_enable(dm, FUNC_DISABLE);
2087
2088 return set_result;
2089 }
2090
phydm_nbi_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2091 void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used, char *output,
2092 u32 *_out_len)
2093 {
2094 struct dm_struct *dm = (struct dm_struct *)dm_void;
2095 u32 used = *_used;
2096 u32 out_len = *_out_len;
2097 u32 val[10] = {0};
2098 char help[] = "-h";
2099 u8 i = 0, input_idx = 0, idx_lmt = 0;
2100 u32 enable = 0; /*@function enable*/
2101 u32 ch = 0;
2102 u32 bw = 0;
2103 u32 f_int = 0; /*@interference frequency*/
2104 u32 sec_ch = 0; /*secondary channel*/
2105 u8 rpt = 0;
2106 u8 path = 0;
2107
2108 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2109 idx_lmt = 6;
2110 else
2111 idx_lmt = 5;
2112 for (i = 0; i < idx_lmt; i++) {
2113 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
2114 input_idx++;
2115 }
2116
2117 if (input_idx == 0)
2118 return;
2119
2120 enable = val[0];
2121 ch = val[1];
2122 bw = val[2];
2123 f_int = val[3];
2124 sec_ch = val[4];
2125 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2126 path = (u8)val[5];
2127 #endif
2128
2129 if ((strcmp(input[1], help) == 0)) {
2130 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2131 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2132 PDM_SNPF(out_len, used, output + used, out_len - used,
2133 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(khz)} {Scnd_CH(L=1, H=2)} {Path:A~D(0~3)}\n");
2134 else
2135 #endif
2136 PDM_SNPF(out_len, used, output + used, out_len - used,
2137 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(khz)} {Scnd_CH(L=1, H=2)}\n");
2138 *_used = used;
2139 *_out_len = out_len;
2140 return;
2141 } else if (val[0] == FUNC_ENABLE) {
2142 PDM_SNPF(out_len, used, output + used, out_len - used,
2143 "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
2144 ch, bw, f_int,
2145 ((sec_ch == PHYDM_DONT_CARE) ||
2146 (bw == 20) || (ch > 14)) ? "Don't care" :
2147 ((sec_ch == PHYDM_ABOVE) ? "H" : "L"));
2148 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2149 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2150 rpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int,
2151 sec_ch, path);
2152 else
2153 #endif
2154 rpt = phydm_nbi_setting(dm, enable, ch, bw, f_int,
2155 sec_ch);
2156 } else if (val[0] == FUNC_DISABLE) {
2157 PDM_SNPF(out_len, used, output + used, out_len - used,
2158 "[Disable NBI]\n");
2159 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2160 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2161 rpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int,
2162 sec_ch, path);
2163 else
2164 #endif
2165 rpt = phydm_nbi_setting(dm, enable, ch, bw, f_int,
2166 sec_ch);
2167 } else {
2168 rpt = PHYDM_SET_FAIL;
2169 }
2170
2171 PDM_SNPF(out_len, used, output + used, out_len - used,
2172 "[NBI set result: %s]\n",
2173 (rpt == PHYDM_SET_SUCCESS) ? "Success" :
2174 ((rpt == PHYDM_SET_NO_NEED) ? "No need" : "Error"));
2175
2176 *_used = used;
2177 *_out_len = out_len;
2178 }
2179
phydm_csi_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2180 void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used, char *output,
2181 u32 *_out_len)
2182 {
2183 struct dm_struct *dm = (struct dm_struct *)dm_void;
2184 u32 used = *_used;
2185 u32 out_len = *_out_len;
2186 u32 val[10] = {0};
2187 char help[] = "-h";
2188 u8 i = 0, input_idx = 0, idx_lmt = 0;
2189 u32 enable = 0; /*@function enable*/
2190 u32 ch = 0;
2191 u32 bw = 0;
2192 u32 f_int = 0; /*@interference frequency*/
2193 u32 sec_ch = 0; /*secondary channel*/
2194 u8 rpt = 0;
2195 u8 wgt = 0;
2196
2197 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2198 idx_lmt = 6;
2199 else
2200 idx_lmt = 5;
2201
2202 for (i = 0; i < idx_lmt; i++) {
2203 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
2204 input_idx++;
2205 }
2206
2207 if (input_idx == 0)
2208 return;
2209
2210 enable = val[0];
2211 ch = val[1];
2212 bw = val[2];
2213 f_int = val[3];
2214 sec_ch = val[4];
2215 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2216 wgt = (u8)val[5];
2217 #endif
2218
2219 if ((strcmp(input[1], help) == 0)) {
2220 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2221 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2222 PDM_SNPF(out_len, used, output + used, out_len - used,
2223 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(KHz)} {Scnd_CH(L=1, H=2)}\n{wgt:(7:3/4),(6~1: 1/2 ~ 1/64),(0:0)}\n");
2224 else
2225 #endif
2226 PDM_SNPF(out_len, used, output + used, out_len - used,
2227 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(Mhz)} {Scnd_CH(L=1, H=2)}\n");
2228
2229 *_used = used;
2230 *_out_len = out_len;
2231 return;
2232
2233 } else if (val[0] == FUNC_ENABLE) {
2234 PDM_SNPF(out_len, used, output + used, out_len - used,
2235 "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
2236 ch, bw, f_int,
2237 (ch > 14) ? "Don't care" :
2238 (((sec_ch == PHYDM_DONT_CARE) ||
2239 (bw == 20) || (ch > 14)) ? "H" : "L"));
2240 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2241 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2242 rpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw,
2243 f_int, sec_ch, wgt);
2244 else
2245 #endif
2246 rpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int,
2247 sec_ch);
2248 } else if (val[0] == FUNC_DISABLE) {
2249 PDM_SNPF(out_len, used, output + used, out_len - used,
2250 "[Disable CSI MASK]\n");
2251 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2252 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2253 rpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw,
2254 f_int, sec_ch, wgt);
2255 else
2256 #endif
2257 rpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int,
2258 sec_ch);
2259 } else {
2260 rpt = PHYDM_SET_FAIL;
2261 }
2262 PDM_SNPF(out_len, used, output + used, out_len - used,
2263 "[CSI MASK set result: %s]\n",
2264 (rpt == PHYDM_SET_SUCCESS) ? "Success" :
2265 ((rpt == PHYDM_SET_NO_NEED) ? "No need" : "Error"));
2266
2267 *_used = used;
2268 *_out_len = out_len;
2269 }
2270
phydm_stop_ck320(void * dm_void,u8 enable)2271 void phydm_stop_ck320(void *dm_void, u8 enable)
2272 {
2273 struct dm_struct *dm = (struct dm_struct *)dm_void;
2274 u32 val = enable ? 1 : 0;
2275
2276 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
2277 odm_set_bb_reg(dm, R_0x8b4, BIT(6), val);
2278 } else {
2279 if (dm->support_ic_type & ODM_IC_N_2SS) /*N-2SS*/
2280 odm_set_bb_reg(dm, R_0x87c, BIT(29), val);
2281 else /*N-1SS*/
2282 odm_set_bb_reg(dm, R_0x87c, BIT(31), val);
2283 }
2284 }
2285
2286 boolean
phydm_bb_ctrl_txagc_ofst(void * dm_void,s8 pw_offset,u8 add_half_db)2287 phydm_bb_ctrl_txagc_ofst(void *dm_void, s8 pw_offset, /*@(unit: dB)*/
2288 u8 add_half_db /*@(+0.5 dB)*/)
2289 {
2290 struct dm_struct *dm = (struct dm_struct *)dm_void;
2291 s8 pw_idx;
2292 u8 offset_bit_num = 0;
2293
2294 if (dm->support_ic_type & N_IC_TX_OFFEST_5_BIT) {
2295 /*@ 5Bit, 0.5dB unit*/
2296 if (pw_offset < -8 || pw_offset > 7) {
2297 pr_debug("[Warning][%s] Ofst=%d", __func__, pw_offset);
2298 return false;
2299 }
2300 offset_bit_num = 5;
2301 } else {
2302 if (pw_offset < -16 || pw_offset > 15) {
2303 pr_debug("[Warning][%s] Ofst=%d", __func__, pw_offset);
2304 return false;
2305 }
2306 if (dm->support_ic_type & N_IC_TX_OFFEST_7_BIT) {
2307 /*@ 7Bit, 0.25dB unit*/
2308 offset_bit_num = 7;
2309 } else {
2310 /*@ 6Bit, 0.5dB unit*/
2311 offset_bit_num = 6;
2312 }
2313 }
2314
2315 pw_idx = (offset_bit_num == 7) ? pw_offset * 4 : pw_offset * 2;
2316
2317 if (add_half_db)
2318 pw_idx = (offset_bit_num == 7) ? pw_idx + 2 : pw_idx + 1;
2319
2320 PHYDM_DBG(dm, ODM_COMP_API, "Pw_ofst=0x%x\n", pw_idx);
2321
2322 switch (dm->ic_ip_series) {
2323 case PHYDM_IC_AC:
2324 odm_set_bb_reg(dm, R_0x8b4, 0x3f, pw_idx); /*6Bit*/
2325 break;
2326 case PHYDM_IC_N:
2327 if (offset_bit_num == 5) {
2328 odm_set_bb_reg(dm, R_0x80c, 0x1f00, pw_idx);
2329 if (dm->num_rf_path >= 2)
2330 odm_set_bb_reg(dm, R_0x80c, 0x3e000, pw_idx);
2331 } else if (offset_bit_num == 6) {
2332 odm_set_bb_reg(dm, R_0x80c, 0x3f00, pw_idx);
2333 if (dm->num_rf_path >= 2)
2334 odm_set_bb_reg(dm, R_0x80c, 0xfc000, pw_idx);
2335 } else { /*7Bit*/
2336 odm_set_bb_reg(dm, R_0x80c, 0x7f00, pw_idx);
2337 if (dm->num_rf_path >= 2)
2338 odm_set_bb_reg(dm, R_0x80c, 0x3f8000, pw_idx);
2339 }
2340 break;
2341 }
2342 return true;
2343 }
2344
2345 boolean
phydm_set_bb_txagc_offset(void * dm_void,s8 pw_offset,u8 add_half_db)2346 phydm_set_bb_txagc_offset(void *dm_void, s8 pw_offset, /*@(unit: dB)*/
2347 u8 add_half_db /*@(+0.5 dB)*/)
2348 {
2349 struct dm_struct *dm = (struct dm_struct *)dm_void;
2350 boolean rpt = false;
2351
2352 PHYDM_DBG(dm, ODM_COMP_API, "power_offset=%d, add_half_db =%d\n",
2353 pw_offset, add_half_db);
2354
2355 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2356 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
2357 rpt = phydm_bb_ctrl_txagc_ofst_jgr3(dm, pw_offset, add_half_db);
2358 } else
2359 #endif
2360 {
2361 rpt = phydm_bb_ctrl_txagc_ofst(dm, pw_offset, add_half_db);
2362 }
2363
2364 PHYDM_DBG(dm, ODM_COMP_API, "TX AGC Offset set_success=%d", rpt);
2365
2366 return rpt;
2367 }
2368
2369 #ifdef PHYDM_COMMON_API_SUPPORT
phydm_reset_txagc(void * dm_void)2370 void phydm_reset_txagc(void *dm_void)
2371 {
2372 struct dm_struct *dm = (struct dm_struct *)dm_void;
2373 u32 r_txagc_cck[4] = {R_0x18a0, R_0x41a0, R_0x52a0, R_0x53a0};
2374 u32 r_txagc_ofdm[4] = {R_0x18e8, R_0x41e8, R_0x52e8, R_0x53e8};
2375 u32 r_txagc_diff = R_0x3a00;
2376 u8 i = 0;
2377
2378 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) {
2379 PHYDM_DBG(dm, ODM_COMP_API, "Only for JGR3 ICs!\n");
2380 return;
2381 }
2382
2383 for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
2384 odm_set_bb_reg(dm, r_txagc_cck[i], 0x7f0000, 0x0);
2385 odm_set_bb_reg(dm, r_txagc_ofdm[i], 0x1fc00, 0x0);
2386 }
2387
2388 for (i = 0; i <= ODM_RATEVHTSS4MCS6; i = i + 4)
2389 odm_set_bb_reg(dm, r_txagc_diff + i, MASKDWORD, 0x0);
2390 }
2391 boolean
phydm_api_shift_txagc(void * dm_void,u32 pwr_offset,enum rf_path path,boolean is_positive)2392 phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,
2393 boolean is_positive) {
2394 struct dm_struct *dm = (struct dm_struct *)dm_void;
2395 boolean ret = false;
2396 u32 txagc_cck = 0;
2397 u32 txagc_ofdm = 0;
2398 u32 r_txagc_ofdm[4] = {R_0x18e8, R_0x41e8, R_0x52e8, R_0x53e8};
2399 u32 r_txagc_cck[4] = {R_0x18a0, R_0x41a0, R_0x52a0, R_0x53a0};
2400 u32 r_new_txagc[1] = {R_0x4308};
2401
2402 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
2403 if (dm->support_ic_type &
2404 (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)) {
2405 if (path > RF_PATH_B) {
2406 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n",
2407 path);
2408 return false;
2409 }
2410 txagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path],
2411 0x7F0000);
2412 txagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path],
2413 0x1FC00);
2414 if (is_positive) {
2415 if (((txagc_cck + pwr_offset) > 127) ||
2416 ((txagc_ofdm + pwr_offset) > 127))
2417 return false;
2418
2419 txagc_cck += pwr_offset;
2420 txagc_ofdm += pwr_offset;
2421 } else {
2422 if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)
2423 return false;
2424
2425 txagc_cck -= pwr_offset;
2426 txagc_ofdm -= pwr_offset;
2427 }
2428 #if (RTL8822C_SUPPORT)
2429 ret = config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_cck,
2430 path, PDM_CCK);
2431 ret &= config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_ofdm,
2432 path, PDM_OFDM);
2433 #endif
2434 #if (RTL8812F_SUPPORT)
2435 ret = config_phydm_write_txagc_ref_8812f(dm, (u8)txagc_cck,
2436 path, PDM_CCK);
2437 ret &= config_phydm_write_txagc_ref_8812f(dm, (u8)txagc_ofdm,
2438 path, PDM_OFDM);
2439 #endif
2440 #if (RTL8197G_SUPPORT)
2441 ret = config_phydm_write_txagc_ref_8197g(dm, (u8)txagc_cck,
2442 path, PDM_CCK);
2443 ret &= config_phydm_write_txagc_ref_8197g(dm, (u8)txagc_ofdm,
2444 path, PDM_OFDM);
2445 #endif
2446 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2447 "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n",
2448 __func__, path, txagc_cck, txagc_ofdm);
2449 }
2450 #endif
2451
2452 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
2453 if (dm->support_ic_type &
2454 (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8814C)) {
2455 if (path > RF_PATH_D) {
2456 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n",
2457 path);
2458 return false;
2459 }
2460 txagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path],
2461 0x7F0000);
2462 txagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path],
2463 0x1FC00);
2464 if (is_positive) {
2465 if (((txagc_cck + pwr_offset) > 127) ||
2466 ((txagc_ofdm + pwr_offset) > 127))
2467 return false;
2468
2469 txagc_cck += pwr_offset;
2470 txagc_ofdm += pwr_offset;
2471 } else {
2472 if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)
2473 return false;
2474
2475 txagc_cck -= pwr_offset;
2476 txagc_ofdm -= pwr_offset;
2477 }
2478 #if (RTL8198F_SUPPORT)
2479 ret = config_phydm_write_txagc_ref_8198f(dm, (u8)txagc_cck,
2480 path, PDM_CCK);
2481 ret &= config_phydm_write_txagc_ref_8198f(dm, (u8)txagc_ofdm,
2482 path, PDM_OFDM);
2483 #endif
2484 #if (RTL8814B_SUPPORT)
2485 ret = config_phydm_write_txagc_ref_8814b(dm, (u8)txagc_cck,
2486 path, PDM_CCK);
2487 ret &= config_phydm_write_txagc_ref_8814b(dm, (u8)txagc_ofdm,
2488 path, PDM_OFDM);
2489 #endif
2490 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2491 "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n",
2492 __func__, path, txagc_cck, txagc_ofdm);
2493 }
2494 #endif
2495
2496 #if (RTL8723F_SUPPORT)
2497 if (dm->support_ic_type & (ODM_RTL8723F)) {
2498 if (path > RF_PATH_A) {
2499 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n",
2500 path);
2501 return false;
2502 }
2503 txagc_cck = (u8)odm_get_bb_reg(dm, r_new_txagc[path],
2504 0x0000007f);
2505 txagc_ofdm = (u8)odm_get_bb_reg(dm, r_new_txagc[path],
2506 0x00007f00);
2507 if (is_positive) {
2508 if (((txagc_cck + pwr_offset) > 127) ||
2509 ((txagc_ofdm + pwr_offset) > 127))
2510 return false;
2511
2512 txagc_cck += pwr_offset;
2513 txagc_ofdm += pwr_offset;
2514 } else {
2515 if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)
2516 return false;
2517
2518 txagc_cck -= pwr_offset;
2519 txagc_ofdm -= pwr_offset;
2520 }
2521 #if (RTL8723F_SUPPORT)
2522 ret = config_phydm_write_txagc_ref_8723f(dm, (u8)txagc_cck,
2523 path, PDM_CCK);
2524 ret &= config_phydm_write_txagc_ref_8723f(dm, (u8)txagc_ofdm,
2525 path, PDM_OFDM);
2526 #endif
2527 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2528 "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n",
2529 __func__, path, txagc_cck, txagc_ofdm);
2530 }
2531 #endif
2532
2533 return ret;
2534 }
2535
2536 boolean
phydm_api_set_txagc(void * dm_void,u32 pwr_idx,enum rf_path path,u8 rate,boolean is_single_rate)2537 phydm_api_set_txagc(void *dm_void, u32 pwr_idx, enum rf_path path,
2538 u8 rate, boolean is_single_rate)
2539 {
2540 struct dm_struct *dm = (struct dm_struct *)dm_void;
2541 boolean ret = false;
2542 #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT ||\
2543 RTL8814B_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
2544 u8 base = 0;
2545 u8 txagc_tmp = 0;
2546 s8 pw_by_rate_tmp = 0;
2547 s8 pw_by_rate_new = 0;
2548 #endif
2549 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2550 u8 i = 0;
2551 #endif
2552
2553 #if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT)
2554 if (dm->support_ic_type &
2555 (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) {
2556 if (is_single_rate) {
2557 #if (RTL8822B_SUPPORT)
2558 if (dm->support_ic_type == ODM_RTL8822B)
2559 ret = phydm_write_txagc_1byte_8822b(dm, pwr_idx,
2560 path, rate);
2561 #endif
2562
2563 #if (RTL8821C_SUPPORT)
2564 if (dm->support_ic_type == ODM_RTL8821C)
2565 ret = phydm_write_txagc_1byte_8821c(dm, pwr_idx,
2566 path, rate);
2567 #endif
2568
2569 #if (RTL8195B_SUPPORT)
2570 if (dm->support_ic_type == ODM_RTL8195B)
2571 ret = phydm_write_txagc_1byte_8195b(dm, pwr_idx,
2572 path, rate);
2573 #endif
2574
2575 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2576 set_current_tx_agc(dm->priv, path, rate, (u8)pwr_idx);
2577 #endif
2578
2579 } else {
2580 #if (RTL8822B_SUPPORT)
2581 if (dm->support_ic_type == ODM_RTL8822B)
2582 ret = config_phydm_write_txagc_8822b(dm,
2583 pwr_idx,
2584 path,
2585 rate);
2586 #endif
2587
2588 #if (RTL8821C_SUPPORT)
2589 if (dm->support_ic_type == ODM_RTL8821C)
2590 ret = config_phydm_write_txagc_8821c(dm,
2591 pwr_idx,
2592 path,
2593 rate);
2594 #endif
2595
2596 #if (RTL8195B_SUPPORT)
2597 if (dm->support_ic_type == ODM_RTL8195B)
2598 ret = config_phydm_write_txagc_8195b(dm,
2599 pwr_idx,
2600 path,
2601 rate);
2602 #endif
2603
2604 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2605 for (i = 0; i < 4; i++)
2606 set_current_tx_agc(dm->priv, path, (rate + i),
2607 (u8)pwr_idx);
2608 #endif
2609 }
2610 }
2611 #endif
2612
2613 #if (RTL8198F_SUPPORT)
2614 if (dm->support_ic_type & ODM_RTL8198F) {
2615 if (rate < 0x4)
2616 txagc_tmp = config_phydm_read_txagc_8198f(dm, path,
2617 rate,
2618 PDM_CCK);
2619 else
2620 txagc_tmp = config_phydm_read_txagc_8198f(dm, path,
2621 rate,
2622 PDM_OFDM);
2623
2624 pw_by_rate_tmp = config_phydm_read_txagc_diff_8198f(dm, rate);
2625 base = txagc_tmp - pw_by_rate_tmp;
2626 base = base & 0x7f;
2627 if (DIFF_2((pwr_idx & 0x7f), base) > 64 || pwr_idx > 127)
2628 return false;
2629
2630 pw_by_rate_new = (s8)(pwr_idx - base);
2631 ret = phydm_write_txagc_1byte_8198f(dm, pw_by_rate_new, rate);
2632 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2633 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2634 __func__, path, rate, base, pw_by_rate_new);
2635 }
2636 #endif
2637
2638 #if (RTL8822C_SUPPORT)
2639 if (dm->support_ic_type & ODM_RTL8822C) {
2640 if (rate < 0x4)
2641 txagc_tmp = config_phydm_read_txagc_8822c(dm, path,
2642 rate,
2643 PDM_CCK);
2644 else
2645 txagc_tmp = config_phydm_read_txagc_8822c(dm, path,
2646 rate,
2647 PDM_OFDM);
2648
2649 pw_by_rate_tmp = config_phydm_read_txagc_diff_8822c(dm, rate);
2650 base = txagc_tmp - pw_by_rate_tmp;
2651 base = base & 0x7f;
2652 if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
2653 return false;
2654
2655 pw_by_rate_new = (s8)(pwr_idx - base);
2656 ret = phydm_write_txagc_1byte_8822c(dm, pw_by_rate_new, rate);
2657 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2658 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2659 __func__, path, rate, base, pw_by_rate_new);
2660 }
2661 #endif
2662
2663 #if (RTL8814B_SUPPORT)
2664 if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) {
2665 if (rate < 0x4)
2666 txagc_tmp = config_phydm_read_txagc_8814b(dm, path,
2667 rate,
2668 PDM_CCK);
2669 else
2670 txagc_tmp = config_phydm_read_txagc_8814b(dm, path,
2671 rate,
2672 PDM_OFDM);
2673
2674 pw_by_rate_tmp = config_phydm_read_txagc_diff_8814b(dm, rate);
2675 base = txagc_tmp - pw_by_rate_tmp;
2676 base = base & 0x7f;
2677 if (DIFF_2((pwr_idx & 0x7f), base) > 64)
2678 return false;
2679
2680 pw_by_rate_new = (s8)(pwr_idx - base);
2681 ret = phydm_write_txagc_1byte_8814b(dm, pw_by_rate_new, rate);
2682 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2683 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2684 __func__, path, rate, base, pw_by_rate_new);
2685 }
2686 #endif
2687
2688 #if (RTL8812F_SUPPORT)
2689 if (dm->support_ic_type & ODM_RTL8812F) {
2690 if (rate < 0x4)
2691 txagc_tmp = config_phydm_read_txagc_8812f(dm, path,
2692 rate,
2693 PDM_CCK);
2694 else
2695 txagc_tmp = config_phydm_read_txagc_8812f(dm, path,
2696 rate,
2697 PDM_OFDM);
2698
2699 pw_by_rate_tmp = config_phydm_read_txagc_diff_8812f(dm, rate);
2700 base = txagc_tmp - pw_by_rate_tmp;
2701 base = base & 0x7f;
2702 if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
2703 return false;
2704
2705 pw_by_rate_new = (s8)(pwr_idx - base);
2706 ret = phydm_write_txagc_1byte_8812f(dm, pw_by_rate_new, rate);
2707 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2708 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2709 __func__, path, rate, base, pw_by_rate_new);
2710 }
2711 #endif
2712
2713 #if (RTL8197G_SUPPORT)
2714 if (dm->support_ic_type & ODM_RTL8197G) {
2715 if (rate < 0x4)
2716 txagc_tmp = config_phydm_read_txagc_8197g(dm, path,
2717 rate,
2718 PDM_CCK);
2719 else
2720 txagc_tmp = config_phydm_read_txagc_8197g(dm, path,
2721 rate,
2722 PDM_OFDM);
2723
2724 pw_by_rate_tmp = config_phydm_read_txagc_diff_8197g(dm, rate);
2725 base = txagc_tmp - pw_by_rate_tmp;
2726 base = base & 0x7f;
2727 if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
2728 return false;
2729
2730 pw_by_rate_new = (s8)(pwr_idx - base);
2731 ret = phydm_write_txagc_1byte_8197g(dm, pw_by_rate_new, rate);
2732 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2733 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2734 __func__, path, rate, base, pw_by_rate_new);
2735 }
2736 #endif
2737 #if (RTL8723F_SUPPORT)
2738 if (dm->support_ic_type & ODM_RTL8723F) {
2739 if (rate < 0x4)
2740 txagc_tmp = config_phydm_read_txagc_8723f(dm, path,
2741 rate,
2742 PDM_CCK);
2743 else
2744 txagc_tmp = config_phydm_read_txagc_8723f(dm, path,
2745 rate,
2746 PDM_OFDM);
2747
2748 pw_by_rate_tmp = config_phydm_read_txagc_diff_8723f(dm, rate);
2749 base = txagc_tmp - pw_by_rate_tmp;
2750 base = base & 0x7f;
2751 if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
2752 return false;
2753
2754 pw_by_rate_new = (s8)(pwr_idx - base);
2755 ret = phydm_write_txagc_1byte_8723f(dm, pw_by_rate_new, rate);
2756 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2757 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2758 __func__, path, rate, base, pw_by_rate_new);
2759 }
2760 #endif
2761
2762 #if (RTL8197F_SUPPORT)
2763 if (dm->support_ic_type & ODM_RTL8197F)
2764 ret = config_phydm_write_txagc_8197f(dm, pwr_idx, path, rate);
2765 #endif
2766
2767 #if (RTL8192F_SUPPORT)
2768 if (dm->support_ic_type & ODM_RTL8192F)
2769 ret = config_phydm_write_txagc_8192f(dm, pwr_idx, path, rate);
2770 #endif
2771
2772 #if (RTL8721D_SUPPORT)
2773 if (dm->support_ic_type & ODM_RTL8721D)
2774 ret = config_phydm_write_txagc_8721d(dm, pwr_idx, path, rate);
2775 #endif
2776 #if (RTL8710C_SUPPORT)
2777 if (dm->support_ic_type & ODM_RTL8710C)
2778 ret = config_phydm_write_txagc_8710c(dm, pwr_idx, path, rate);
2779 #endif
2780 return ret;
2781 }
2782
phydm_api_get_txagc(void * dm_void,enum rf_path path,u8 hw_rate)2783 u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)
2784 {
2785 struct dm_struct *dm = (struct dm_struct *)dm_void;
2786 u8 ret = 0;
2787
2788 #if (RTL8822B_SUPPORT)
2789 if (dm->support_ic_type & ODM_RTL8822B)
2790 ret = config_phydm_read_txagc_8822b(dm, path, hw_rate);
2791 #endif
2792
2793 #if (RTL8197F_SUPPORT)
2794 if (dm->support_ic_type & ODM_RTL8197F)
2795 ret = config_phydm_read_txagc_8197f(dm, path, hw_rate);
2796 #endif
2797
2798 #if (RTL8821C_SUPPORT)
2799 if (dm->support_ic_type & ODM_RTL8821C)
2800 ret = config_phydm_read_txagc_8821c(dm, path, hw_rate);
2801 #endif
2802
2803 #if (RTL8195B_SUPPORT)
2804 if (dm->support_ic_type & ODM_RTL8195B)
2805 ret = config_phydm_read_txagc_8195b(dm, path, hw_rate);
2806 #endif
2807
2808 /*@jj add 20170822*/
2809 #if (RTL8192F_SUPPORT)
2810 if (dm->support_ic_type & ODM_RTL8192F)
2811 ret = config_phydm_read_txagc_8192f(dm, path, hw_rate);
2812 #endif
2813
2814 #if (RTL8198F_SUPPORT)
2815 if (dm->support_ic_type & ODM_RTL8198F) {
2816 if (hw_rate < 0x4) {
2817 ret = config_phydm_read_txagc_8198f(dm, path, hw_rate,
2818 PDM_CCK);
2819 } else {
2820 ret = config_phydm_read_txagc_8198f(dm, path, hw_rate,
2821 PDM_OFDM);
2822 }
2823 }
2824 #endif
2825
2826 #if (RTL8822C_SUPPORT)
2827 if (dm->support_ic_type & ODM_RTL8822C) {
2828 if (hw_rate < 0x4) {
2829 ret = config_phydm_read_txagc_8822c(dm, path, hw_rate,
2830 PDM_CCK);
2831 } else {
2832 ret = config_phydm_read_txagc_8822c(dm, path, hw_rate,
2833 PDM_OFDM);
2834 }
2835 }
2836 #endif
2837
2838 #if (RTL8723F_SUPPORT)
2839 if (dm->support_ic_type & ODM_RTL8723F) {
2840 if (hw_rate < 0x4) {
2841 ret = config_phydm_read_txagc_8723f(dm, path, hw_rate,
2842 PDM_CCK);
2843 } else {
2844 ret = config_phydm_read_txagc_8723f(dm, path, hw_rate,
2845 PDM_OFDM);
2846 }
2847 }
2848 #endif
2849
2850 #if (RTL8814B_SUPPORT)
2851 if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) {
2852 if (hw_rate < 0x4) {
2853 ret = config_phydm_read_txagc_8814b(dm, path, hw_rate,
2854 PDM_CCK);
2855 } else {
2856 ret = config_phydm_read_txagc_8814b(dm, path, hw_rate,
2857 PDM_OFDM);
2858 }
2859 }
2860 #endif
2861
2862 #if (RTL8812F_SUPPORT)
2863 if (dm->support_ic_type & ODM_RTL8812F) {
2864 if (hw_rate < 0x4) {
2865 ret = config_phydm_read_txagc_8812f(dm, path, hw_rate,
2866 PDM_CCK);
2867 } else {
2868 ret = config_phydm_read_txagc_8812f(dm, path, hw_rate,
2869 PDM_OFDM);
2870 }
2871 }
2872 #endif
2873
2874 #if (RTL8197G_SUPPORT)
2875 if (dm->support_ic_type & ODM_RTL8197G) {
2876 if (hw_rate < 0x4) {
2877 ret = config_phydm_read_txagc_8197g(dm, path,
2878 hw_rate,
2879 PDM_CCK);
2880 } else {
2881 ret = config_phydm_read_txagc_8197g(dm, path,
2882 hw_rate,
2883 PDM_OFDM);
2884 }
2885 }
2886 #endif
2887
2888 #if (RTL8721D_SUPPORT)
2889 if (dm->support_ic_type & ODM_RTL8721D)
2890 ret = config_phydm_read_txagc_8721d(dm, path, hw_rate);
2891 #endif
2892 #if (RTL8710C_SUPPORT)
2893 if (dm->support_ic_type & ODM_RTL8710C)
2894 ret = config_phydm_read_txagc_8710c(dm, path, hw_rate);
2895 #endif
2896 return ret;
2897 }
2898
2899 #if (RTL8822C_SUPPORT)
phydm_shift_rxagc_table(void * dm_void,boolean is_pos_shift,u8 sft)2900 void phydm_shift_rxagc_table(void *dm_void, boolean is_pos_shift, u8 sft)
2901 {
2902 struct dm_struct *dm = (struct dm_struct *)dm_void;
2903 u8 i = 0;
2904 u8 j = 0;
2905 u32 reg = 0;
2906 u16 max_rf_gain = 0;
2907 u16 min_rf_gain = 0;
2908
2909 dm->is_agc_tab_pos_shift = is_pos_shift;
2910 dm->agc_table_shift = sft;
2911
2912 for (i = 0; i <= dm->agc_table_cnt; i++) {
2913 max_rf_gain = dm->agc_rf_gain_ori[i][0];
2914 min_rf_gain = dm->agc_rf_gain_ori[i][63];
2915
2916 if (dm->support_ic_type & ODM_RTL8822C)
2917 dm->l_bnd_detect[i] = false;
2918
2919 for (j = 0; j < 64; j++) {
2920 if (is_pos_shift) {
2921 if (j < sft)
2922 reg = (max_rf_gain & 0x3ff);
2923 else
2924 reg = (dm->agc_rf_gain_ori[i][j - sft] &
2925 0x3ff);
2926 } else {
2927 if (j > 63 - sft)
2928 reg = (min_rf_gain & 0x3ff);
2929
2930 else
2931 reg = (dm->agc_rf_gain_ori[i][j + sft] &
2932 0x3ff);
2933 }
2934 dm->agc_rf_gain[i][j] = (u16)(reg & 0x3ff);
2935
2936 reg |= (j & 0x3f) << 16;/*mp_gain_idx*/
2937 reg |= (i & 0xf) << 22;/*table*/
2938 reg |= BIT(29) | BIT(28);/*write en*/
2939 odm_set_bb_reg(dm, R_0x1d90, MASKDWORD, reg);
2940 }
2941 }
2942
2943 if (dm->support_ic_type & ODM_RTL8822C)
2944 odm_set_bb_reg(dm, R_0x828, 0xf8, L_BND_DEFAULT_8822C);
2945 }
2946 #endif
2947
2948 boolean
phydm_api_switch_bw_channel(void * dm_void,u8 ch,u8 pri_ch,enum channel_width bw)2949 phydm_api_switch_bw_channel(void *dm_void, u8 ch, u8 pri_ch,
2950 enum channel_width bw)
2951 {
2952 struct dm_struct *dm = (struct dm_struct *)dm_void;
2953 boolean ret = false;
2954
2955 switch (dm->support_ic_type) {
2956 #if (RTL8822B_SUPPORT)
2957 case ODM_RTL8822B:
2958 ret = config_phydm_switch_channel_bw_8822b(dm, ch, pri_ch, bw);
2959 break;
2960 #endif
2961
2962 #if (RTL8197F_SUPPORT)
2963 case ODM_RTL8197F:
2964 ret = config_phydm_switch_channel_bw_8197f(dm, ch, pri_ch, bw);
2965 break;
2966 #endif
2967
2968 #if (RTL8821C_SUPPORT)
2969 case ODM_RTL8821C:
2970 ret = config_phydm_switch_channel_bw_8821c(dm, ch, pri_ch, bw);
2971 break;
2972 #endif
2973
2974 #if (RTL8195B_SUPPORT)
2975 case ODM_RTL8195B:
2976 ret = config_phydm_switch_channel_bw_8195b(dm, ch, pri_ch, bw);
2977 break;
2978 #endif
2979
2980 #if (RTL8192F_SUPPORT)
2981 case ODM_RTL8192F:
2982 ret = config_phydm_switch_channel_bw_8192f(dm, ch, pri_ch, bw);
2983 break;
2984 #endif
2985
2986 #if (RTL8198F_SUPPORT)
2987 case ODM_RTL8198F:
2988 ret = config_phydm_switch_channel_bw_8198f(dm, ch, pri_ch, bw);
2989 break;
2990 #endif
2991
2992 #if (RTL8822C_SUPPORT)
2993 case ODM_RTL8822C:
2994 ret = config_phydm_switch_channel_bw_8822c(dm, ch, pri_ch, bw);
2995 break;
2996 #endif
2997
2998 #if (RTL8723F_SUPPORT)
2999 case ODM_RTL8723F:
3000 ret = config_phydm_switch_channel_bw_8723f(dm, ch, pri_ch, bw);
3001 break;
3002 #endif
3003
3004 #if (RTL8814B_SUPPORT)
3005 case ODM_RTL8814B:
3006 case ODM_RTL8814C:
3007 ret = config_phydm_switch_channel_bw_8814b(dm, ch, pri_ch, bw);
3008 break;
3009 #endif
3010
3011 #if (RTL8812F_SUPPORT)
3012 case ODM_RTL8812F:
3013 ret = config_phydm_switch_channel_bw_8812f(dm, ch, pri_ch, bw);
3014 break;
3015 #endif
3016
3017 #if (RTL8197G_SUPPORT)
3018 case ODM_RTL8197G:
3019 ret = config_phydm_switch_channel_bw_8197g(dm, ch, pri_ch, bw);
3020 break;
3021 #endif
3022
3023 #if (RTL8721D_SUPPORT)
3024 case ODM_RTL8721D:
3025 ret = config_phydm_switch_channel_bw_8721d(dm, ch, pri_ch, bw);
3026 break;
3027 #endif
3028 #if (RTL8710C_SUPPORT)
3029 case ODM_RTL8710C:
3030 ret = config_phydm_switch_channel_bw_8710c(dm, ch, pri_ch, bw);
3031 break;
3032 #endif
3033
3034 default:
3035 break;
3036 }
3037 return ret;
3038 }
3039
3040 boolean
phydm_api_trx_mode(void * dm_void,enum bb_path tx_path,enum bb_path rx_path,enum bb_path tx_path_ctrl)3041 phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,
3042 enum bb_path tx_path_ctrl)
3043 {
3044 struct dm_struct *dm = (struct dm_struct *)dm_void;
3045 boolean ret = false;
3046 boolean is_2tx = false;
3047
3048 if (tx_path_ctrl == BB_PATH_AB)
3049 is_2tx = true;
3050
3051 switch (dm->support_ic_type) {
3052 #if (RTL8822B_SUPPORT)
3053 case ODM_RTL8822B:
3054 ret = config_phydm_trx_mode_8822b(dm, tx_path, rx_path,
3055 tx_path_ctrl);
3056 break;
3057 #endif
3058
3059 #if (RTL8197F_SUPPORT)
3060 case ODM_RTL8197F:
3061 ret = config_phydm_trx_mode_8197f(dm, tx_path, rx_path, is_2tx);
3062 break;
3063 #endif
3064
3065 #if (RTL8192F_SUPPORT)
3066 case ODM_RTL8192F:
3067 ret = config_phydm_trx_mode_8192f(dm, tx_path, rx_path,
3068 tx_path_ctrl);
3069 break;
3070 #endif
3071
3072 #if (RTL8198F_SUPPORT)
3073 case ODM_RTL8198F:
3074 ret = config_phydm_trx_mode_8198f(dm, tx_path, rx_path, is_2tx);
3075 break;
3076 #endif
3077
3078 #if (RTL8814B_SUPPORT)
3079 case ODM_RTL8814B:
3080 case ODM_RTL8814C:
3081 ret = config_phydm_trx_mode_8814b(dm, tx_path, rx_path);
3082 break;
3083 #endif
3084
3085 #if (RTL8822C_SUPPORT)
3086 case ODM_RTL8822C:
3087 ret = config_phydm_trx_mode_8822c(dm, tx_path, rx_path,
3088 tx_path_ctrl);
3089 break;
3090 #endif
3091
3092 #if (RTL8723F_SUPPORT)
3093 case ODM_RTL8723F:
3094 ret = config_phydm_trx_mode_8723f(dm, tx_path, rx_path,
3095 tx_path_ctrl);
3096 break;
3097 #endif
3098
3099 #if (RTL8812F_SUPPORT)
3100 case ODM_RTL8812F:
3101 ret = config_phydm_trx_mode_8812f(dm, tx_path, rx_path, is_2tx);
3102 break;
3103 #endif
3104
3105 #if (RTL8197G_SUPPORT)
3106 case ODM_RTL8197G:
3107 ret = config_phydm_trx_mode_8197g(dm, tx_path, rx_path, is_2tx);
3108 break;
3109 #endif
3110
3111 #if (RTL8721D_SUPPORT)
3112 case ODM_RTL8721D:
3113 ret = config_phydm_trx_mode_8721d(dm, tx_path, rx_path, is_2tx);
3114 break;
3115 #endif
3116
3117 #if (RTL8710C_SUPPORT)
3118 case ODM_RTL8710C:
3119 ret = config_phydm_trx_mode_8710c(dm, tx_path, rx_path, is_2tx);
3120 break;
3121 #endif
3122 }
3123 return ret;
3124 }
3125 #endif
3126
3127 #ifdef PHYDM_COMMON_API_NOT_SUPPORT
config_phydm_read_txagc_n(void * dm_void,enum rf_path path,u8 hw_rate)3128 u8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate)
3129 {
3130 struct dm_struct *dm = (struct dm_struct *)dm_void;
3131 u8 read_back_data = INVALID_TXAGC_DATA;
3132 u32 reg_txagc;
3133 u32 reg_mask;
3134 /* This function is for 92E/88E etc... */
3135 /* @Input need to be HW rate index, not driver rate index!!!! */
3136
3137 /* @Error handling */
3138 if (path > RF_PATH_B || hw_rate > ODM_RATEMCS15) {
3139 PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: unsupported path (%d)\n",
3140 __func__, path);
3141 return INVALID_TXAGC_DATA;
3142 }
3143
3144 if (path == RF_PATH_A) {
3145 switch (hw_rate) {
3146 case ODM_RATE1M:
3147 reg_txagc = R_0xe08;
3148 reg_mask = 0x00007f00;
3149 break;
3150 case ODM_RATE2M:
3151 reg_txagc = R_0x86c;
3152 reg_mask = 0x00007f00;
3153 break;
3154 case ODM_RATE5_5M:
3155 reg_txagc = R_0x86c;
3156 reg_mask = 0x007f0000;
3157 break;
3158 case ODM_RATE11M:
3159 reg_txagc = R_0x86c;
3160 reg_mask = 0x7f000000;
3161 break;
3162
3163 case ODM_RATE6M:
3164 reg_txagc = R_0xe00;
3165 reg_mask = 0x0000007f;
3166 break;
3167 case ODM_RATE9M:
3168 reg_txagc = R_0xe00;
3169 reg_mask = 0x00007f00;
3170 break;
3171 case ODM_RATE12M:
3172 reg_txagc = R_0xe00;
3173 reg_mask = 0x007f0000;
3174 break;
3175 case ODM_RATE18M:
3176 reg_txagc = R_0xe00;
3177 reg_mask = 0x7f000000;
3178 break;
3179 case ODM_RATE24M:
3180 reg_txagc = R_0xe04;
3181 reg_mask = 0x0000007f;
3182 break;
3183 case ODM_RATE36M:
3184 reg_txagc = R_0xe04;
3185 reg_mask = 0x00007f00;
3186 break;
3187 case ODM_RATE48M:
3188 reg_txagc = R_0xe04;
3189 reg_mask = 0x007f0000;
3190 break;
3191 case ODM_RATE54M:
3192 reg_txagc = R_0xe04;
3193 reg_mask = 0x7f000000;
3194 break;
3195
3196 case ODM_RATEMCS0:
3197 reg_txagc = R_0xe10;
3198 reg_mask = 0x0000007f;
3199 break;
3200 case ODM_RATEMCS1:
3201 reg_txagc = R_0xe10;
3202 reg_mask = 0x00007f00;
3203 break;
3204 case ODM_RATEMCS2:
3205 reg_txagc = R_0xe10;
3206 reg_mask = 0x007f0000;
3207 break;
3208 case ODM_RATEMCS3:
3209 reg_txagc = R_0xe10;
3210 reg_mask = 0x7f000000;
3211 break;
3212 case ODM_RATEMCS4:
3213 reg_txagc = R_0xe14;
3214 reg_mask = 0x0000007f;
3215 break;
3216 case ODM_RATEMCS5:
3217 reg_txagc = R_0xe14;
3218 reg_mask = 0x00007f00;
3219 break;
3220 case ODM_RATEMCS6:
3221 reg_txagc = R_0xe14;
3222 reg_mask = 0x007f0000;
3223 break;
3224 case ODM_RATEMCS7:
3225 reg_txagc = R_0xe14;
3226 reg_mask = 0x7f000000;
3227 break;
3228 case ODM_RATEMCS8:
3229 reg_txagc = R_0xe18;
3230 reg_mask = 0x0000007f;
3231 break;
3232 case ODM_RATEMCS9:
3233 reg_txagc = R_0xe18;
3234 reg_mask = 0x00007f00;
3235 break;
3236 case ODM_RATEMCS10:
3237 reg_txagc = R_0xe18;
3238 reg_mask = 0x007f0000;
3239 break;
3240 case ODM_RATEMCS11:
3241 reg_txagc = R_0xe18;
3242 reg_mask = 0x7f000000;
3243 break;
3244 case ODM_RATEMCS12:
3245 reg_txagc = R_0xe1c;
3246 reg_mask = 0x0000007f;
3247 break;
3248 case ODM_RATEMCS13:
3249 reg_txagc = R_0xe1c;
3250 reg_mask = 0x00007f00;
3251 break;
3252 case ODM_RATEMCS14:
3253 reg_txagc = R_0xe1c;
3254 reg_mask = 0x007f0000;
3255 break;
3256 case ODM_RATEMCS15:
3257 reg_txagc = R_0xe1c;
3258 reg_mask = 0x7f000000;
3259 break;
3260
3261 default:
3262 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid HWrate!\n");
3263 break;
3264 }
3265 } else if (path == RF_PATH_B) {
3266 switch (hw_rate) {
3267 case ODM_RATE1M:
3268 reg_txagc = R_0x838;
3269 reg_mask = 0x00007f00;
3270 break;
3271 case ODM_RATE2M:
3272 reg_txagc = R_0x838;
3273 reg_mask = 0x007f0000;
3274 break;
3275 case ODM_RATE5_5M:
3276 reg_txagc = R_0x838;
3277 reg_mask = 0x7f000000;
3278 break;
3279 case ODM_RATE11M:
3280 reg_txagc = R_0x86c;
3281 reg_mask = 0x0000007f;
3282 break;
3283
3284 case ODM_RATE6M:
3285 reg_txagc = R_0x830;
3286 reg_mask = 0x0000007f;
3287 break;
3288 case ODM_RATE9M:
3289 reg_txagc = R_0x830;
3290 reg_mask = 0x00007f00;
3291 break;
3292 case ODM_RATE12M:
3293 reg_txagc = R_0x830;
3294 reg_mask = 0x007f0000;
3295 break;
3296 case ODM_RATE18M:
3297 reg_txagc = R_0x830;
3298 reg_mask = 0x7f000000;
3299 break;
3300 case ODM_RATE24M:
3301 reg_txagc = R_0x834;
3302 reg_mask = 0x0000007f;
3303 break;
3304 case ODM_RATE36M:
3305 reg_txagc = R_0x834;
3306 reg_mask = 0x00007f00;
3307 break;
3308 case ODM_RATE48M:
3309 reg_txagc = R_0x834;
3310 reg_mask = 0x007f0000;
3311 break;
3312 case ODM_RATE54M:
3313 reg_txagc = R_0x834;
3314 reg_mask = 0x7f000000;
3315 break;
3316
3317 case ODM_RATEMCS0:
3318 reg_txagc = R_0x83c;
3319 reg_mask = 0x0000007f;
3320 break;
3321 case ODM_RATEMCS1:
3322 reg_txagc = R_0x83c;
3323 reg_mask = 0x00007f00;
3324 break;
3325 case ODM_RATEMCS2:
3326 reg_txagc = R_0x83c;
3327 reg_mask = 0x007f0000;
3328 break;
3329 case ODM_RATEMCS3:
3330 reg_txagc = R_0x83c;
3331 reg_mask = 0x7f000000;
3332 break;
3333 case ODM_RATEMCS4:
3334 reg_txagc = R_0x848;
3335 reg_mask = 0x0000007f;
3336 break;
3337 case ODM_RATEMCS5:
3338 reg_txagc = R_0x848;
3339 reg_mask = 0x00007f00;
3340 break;
3341 case ODM_RATEMCS6:
3342 reg_txagc = R_0x848;
3343 reg_mask = 0x007f0000;
3344 break;
3345 case ODM_RATEMCS7:
3346 reg_txagc = R_0x848;
3347 reg_mask = 0x7f000000;
3348 break;
3349
3350 case ODM_RATEMCS8:
3351 reg_txagc = R_0x84c;
3352 reg_mask = 0x0000007f;
3353 break;
3354 case ODM_RATEMCS9:
3355 reg_txagc = R_0x84c;
3356 reg_mask = 0x00007f00;
3357 break;
3358 case ODM_RATEMCS10:
3359 reg_txagc = R_0x84c;
3360 reg_mask = 0x007f0000;
3361 break;
3362 case ODM_RATEMCS11:
3363 reg_txagc = R_0x84c;
3364 reg_mask = 0x7f000000;
3365 break;
3366 case ODM_RATEMCS12:
3367 reg_txagc = R_0x868;
3368 reg_mask = 0x0000007f;
3369 break;
3370 case ODM_RATEMCS13:
3371 reg_txagc = R_0x868;
3372 reg_mask = 0x00007f00;
3373 break;
3374 case ODM_RATEMCS14:
3375 reg_txagc = R_0x868;
3376 reg_mask = 0x007f0000;
3377 break;
3378 case ODM_RATEMCS15:
3379 reg_txagc = R_0x868;
3380 reg_mask = 0x7f000000;
3381 break;
3382
3383 default:
3384 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid HWrate!\n");
3385 break;
3386 }
3387 } else {
3388 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid RF path!!\n");
3389 }
3390 read_back_data = (u8)odm_get_bb_reg(dm, reg_txagc, reg_mask);
3391 PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: path-%d rate index 0x%x = 0x%x\n",
3392 __func__, path, hw_rate, read_back_data);
3393 return read_back_data;
3394 }
3395 #endif
3396
3397 #ifdef CONFIG_MCC_DM
3398 #ifdef DYN_ANT_WEIGHTING_SUPPORT
phydm_set_weighting_cmn(struct dm_struct * dm)3399 void phydm_set_weighting_cmn(struct dm_struct *dm)
3400 {
3401 PHYDM_DBG(dm, DBG_COMP_MCC, "%s\n", __func__);
3402 odm_set_bb_reg(dm, 0xc04, (BIT(18) | BIT(21)), 0x0);
3403 odm_set_bb_reg(dm, 0xe04, (BIT(18) | BIT(21)), 0x0);
3404 }
3405
phydm_set_weighting_mcc(u8 b_equal_weighting,void * dm_void,u8 port)3406 void phydm_set_weighting_mcc(u8 b_equal_weighting, void *dm_void, u8 port)
3407 {
3408 /*u8 reg_8;*/
3409 struct dm_struct *dm = (struct dm_struct *)dm_void;
3410 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3411 u8 val_0x98e, val_0x98f, val_0x81b;
3412 u32 temp_reg;
3413
3414 PHYDM_DBG(dm, DBG_COMP_MCC, "ant_weighting_mcc, port = %d\n", port);
3415 if (b_equal_weighting) {
3416 temp_reg = odm_get_bb_reg(dm, 0x98c, 0x00ff0000);
3417 val_0x98e = (u8)(temp_reg >> 16) & 0xc0;
3418 temp_reg = odm_get_bb_reg(dm, 0x98c, 0xff000000);
3419 val_0x98f = (u8)(temp_reg >> 24) & 0x7f;
3420 temp_reg = odm_get_bb_reg(dm, 0x818, 0xff000000);
3421 val_0x81b = (u8)(temp_reg >> 24) & 0xfd;
3422 PHYDM_DBG(dm, DBG_COMP_MCC, "Equal weighting ,rssi_min = %d\n",
3423 dm->rssi_min);
3424 /*equal weighting*/
3425 } else {
3426 val_0x98e = 0x44;
3427 val_0x98f = 0x43;
3428 temp_reg = odm_get_bb_reg(dm, 0x818, 0xff000000);
3429 val_0x81b = (u8)(temp_reg >> 24) | BIT(2);
3430 PHYDM_DBG(dm, DBG_COMP_MCC, "AGC weighting ,rssi_min = %d\n",
3431 dm->rssi_min);
3432 /*fix sec_min_wgt = 1/2*/
3433 }
3434 mcc_dm->mcc_reg_id[2] = 0x2;
3435 mcc_dm->mcc_dm_reg[2] = 0x98e;
3436 mcc_dm->mcc_dm_val[2][port] = val_0x98e;
3437
3438 mcc_dm->mcc_reg_id[3] = 0x3;
3439 mcc_dm->mcc_dm_reg[3] = 0x98f;
3440 mcc_dm->mcc_dm_val[3][port] = val_0x98f;
3441
3442 mcc_dm->mcc_reg_id[4] = 0x4;
3443 mcc_dm->mcc_dm_reg[4] = 0x81b;
3444 mcc_dm->mcc_dm_val[4][port] = val_0x81b;
3445 }
3446
phydm_dyn_ant_dec_mcc(u8 port,u8 rssi_in,void * dm_void)3447 void phydm_dyn_ant_dec_mcc(u8 port, u8 rssi_in, void *dm_void)
3448 {
3449 struct dm_struct *dm = (struct dm_struct *)dm_void;
3450 u8 rssi_l2h = 43, rssi_h2l = 37;
3451
3452 if (rssi_in == 0xff)
3453 phydm_set_weighting_mcc(FALSE, dm, port);
3454 else if (rssi_in >= rssi_l2h)
3455 phydm_set_weighting_mcc(TRUE, dm, port);
3456 else if (rssi_in <= rssi_h2l)
3457 phydm_set_weighting_mcc(FALSE, dm, port);
3458 }
3459
phydm_dynamic_ant_weighting_mcc_8822b(void * dm_void)3460 void phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void)
3461 {
3462 struct dm_struct *dm = (struct dm_struct *)dm_void;
3463 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3464 u8 i;
3465
3466 phydm_set_weighting_cmn(dm);
3467 for (i = 0; i <= 1; i++)
3468 phydm_dyn_ant_dec_mcc(i, mcc_dm->mcc_rssi[i], dm);
3469 }
3470 #endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/
3471
phydm_mcc_init(void * dm_void)3472 void phydm_mcc_init(void *dm_void)
3473 {
3474 struct dm_struct *dm = (struct dm_struct *)dm_void;
3475 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3476 u8 i;
3477
3478 /*PHYDM_DBG(dm, DBG_COMP_MCC, ("MCC init\n"));*/
3479 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC init\n");
3480 for (i = 0; i < MCC_DM_REG_NUM; i++) {
3481 mcc_dm->mcc_reg_id[i] = 0xff;
3482 mcc_dm->mcc_dm_reg[i] = 0;
3483 mcc_dm->mcc_dm_val[i][0] = 0;
3484 mcc_dm->mcc_dm_val[i][1] = 0;
3485 }
3486 for (i = 0; i < NUM_STA; i++) {
3487 mcc_dm->sta_macid[0][i] = 0xff;
3488 mcc_dm->sta_macid[1][i] = 0xff;
3489 }
3490 /* Function init */
3491 dm->is_stop_dym_ant_weighting = 0;
3492 }
3493
phydm_check(void * dm_void)3494 u8 phydm_check(void *dm_void)
3495 {
3496 struct dm_struct *dm = (struct dm_struct *)dm_void;
3497 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3498 struct cmn_sta_info *p_entry = NULL;
3499 u8 shift = 0;
3500 u8 i = 0;
3501 u8 j = 0;
3502 u8 rssi_min[2] = {0xff, 0xff};
3503 u8 sta_num = 8;
3504 u8 mcc_macid = 0;
3505
3506 for (i = 0; i <= 1; i++) {
3507 for (j = 0; j < sta_num; j++) {
3508 if (mcc_dm->sta_macid[i][j] != 0xff) {
3509 mcc_macid = mcc_dm->sta_macid[i][j];
3510 p_entry = dm->phydm_sta_info[mcc_macid];
3511 if (!p_entry) {
3512 PHYDM_DBG(dm, DBG_COMP_MCC,
3513 "PEntry NULL(mac=%d)\n",
3514 mcc_dm->sta_macid[i][j]);
3515 return _FAIL;
3516 }
3517 PHYDM_DBG(dm, DBG_COMP_MCC,
3518 "undec_smoothed_pwdb=%d\n",
3519 p_entry->rssi_stat.rssi);
3520 if (p_entry->rssi_stat.rssi < rssi_min[i])
3521 rssi_min[i] = p_entry->rssi_stat.rssi;
3522 }
3523 }
3524 }
3525 mcc_dm->mcc_rssi[0] = (u8)rssi_min[0];
3526 mcc_dm->mcc_rssi[1] = (u8)rssi_min[1];
3527 return _SUCCESS;
3528 }
3529
phydm_mcc_h2ccmd_rst(void * dm_void)3530 void phydm_mcc_h2ccmd_rst(void *dm_void)
3531 {
3532 struct dm_struct *dm = (struct dm_struct *)dm_void;
3533 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3534 u8 i;
3535 u8 regid;
3536 u8 h2c_mcc[H2C_MAX_LENGTH];
3537
3538 /* RST MCC */
3539 for (i = 0; i < H2C_MAX_LENGTH; i++)
3540 h2c_mcc[i] = 0xff;
3541 h2c_mcc[0] = 0x00;
3542 odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc);
3543 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC H2C RST\n");
3544 }
3545
phydm_mcc_h2ccmd(void * dm_void)3546 void phydm_mcc_h2ccmd(void *dm_void)
3547 {
3548 struct dm_struct *dm = (struct dm_struct *)dm_void;
3549 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3550 u8 i;
3551 u8 regid;
3552 u8 h2c_mcc[H2C_MAX_LENGTH];
3553
3554 if (mcc_dm->mcc_rf_ch[0] == 0xff && mcc_dm->mcc_rf_ch[1] == 0xff) {
3555 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC channel Error\n");
3556 return;
3557 }
3558 /* Set Channel number */
3559 for (i = 0; i < H2C_MAX_LENGTH; i++)
3560 h2c_mcc[i] = 0xff;
3561 h2c_mcc[0] = 0xe0;
3562 h2c_mcc[1] = (u8)(mcc_dm->mcc_rf_ch[0]);
3563 h2c_mcc[2] = (u8)(mcc_dm->mcc_rf_ch[0] >> 8);
3564 h2c_mcc[3] = (u8)(mcc_dm->mcc_rf_ch[1]);
3565 h2c_mcc[4] = (u8)(mcc_dm->mcc_rf_ch[1] >> 8);
3566 h2c_mcc[5] = 0xff;
3567 h2c_mcc[6] = 0xff;
3568 odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc);
3569 PHYDM_DBG(dm, DBG_COMP_MCC,
3570 "MCC H2C SetCH: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
3571 h2c_mcc[0], h2c_mcc[1], h2c_mcc[2], h2c_mcc[3],
3572 h2c_mcc[4], h2c_mcc[5], h2c_mcc[6]);
3573
3574 /* Set Reg and value*/
3575 for (i = 0; i < H2C_MAX_LENGTH; i++)
3576 h2c_mcc[i] = 0xff;
3577
3578 for (i = 0; i < MCC_DM_REG_NUM; i++) {
3579 regid = mcc_dm->mcc_reg_id[i];
3580 if (regid != 0xff) {
3581 h2c_mcc[0] = 0xa0 | (regid & 0x1f);
3582 h2c_mcc[1] = (u8)(mcc_dm->mcc_dm_reg[i]);
3583 h2c_mcc[2] = (u8)(mcc_dm->mcc_dm_reg[i] >> 8);
3584 h2c_mcc[3] = mcc_dm->mcc_dm_val[i][0];
3585 h2c_mcc[4] = mcc_dm->mcc_dm_val[i][1];
3586 h2c_mcc[5] = 0xff;
3587 h2c_mcc[6] = 0xff;
3588 odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH,
3589 h2c_mcc);
3590 PHYDM_DBG(dm, DBG_COMP_MCC,
3591 "MCC H2C: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
3592 h2c_mcc[0], h2c_mcc[1], h2c_mcc[2],
3593 h2c_mcc[3], h2c_mcc[4],
3594 h2c_mcc[5], h2c_mcc[6]);
3595 }
3596 }
3597 }
3598
phydm_mcc_ctrl(void * dm_void)3599 void phydm_mcc_ctrl(void *dm_void)
3600 {
3601 struct dm_struct *dm = (struct dm_struct *)dm_void;
3602 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3603 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3604
3605 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC status: %x\n", mcc_dm->mcc_status);
3606 /*MCC stage no change*/
3607 if (mcc_dm->mcc_status == mcc_dm->mcc_pre_status)
3608 return;
3609 /*Not in MCC stage*/
3610 if (mcc_dm->mcc_status == 0) {
3611 /* Enable normal Ant-weighting */
3612 dm->is_stop_dym_ant_weighting = 0;
3613 /* Enable normal DIG */
3614 odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, 0x20);
3615 } else {
3616 /* Disable normal Ant-weighting */
3617 dm->is_stop_dym_ant_weighting = 1;
3618 /* Enable normal DIG */
3619 odm_pause_dig(dm, PHYDM_PAUSE_NO_SET, PHYDM_PAUSE_LEVEL_1,
3620 0x20);
3621 }
3622 if (mcc_dm->mcc_status == 0 && mcc_dm->mcc_pre_status != 0)
3623 phydm_mcc_init(dm);
3624 mcc_dm->mcc_pre_status = mcc_dm->mcc_status;
3625 }
3626
phydm_fill_mcccmd(void * dm_void,u8 regid,u16 reg_add,u8 val0,u8 val1)3627 void phydm_fill_mcccmd(void *dm_void, u8 regid, u16 reg_add,
3628 u8 val0, u8 val1)
3629 {
3630 struct dm_struct *dm = (struct dm_struct *)dm_void;
3631 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3632
3633 mcc_dm->mcc_reg_id[regid] = regid;
3634 mcc_dm->mcc_dm_reg[regid] = reg_add;
3635 mcc_dm->mcc_dm_val[regid][0] = val0;
3636 mcc_dm->mcc_dm_val[regid][1] = val1;
3637 }
3638
phydm_mcc_switch(void * dm_void)3639 void phydm_mcc_switch(void *dm_void)
3640 {
3641 struct dm_struct *dm = (struct dm_struct *)dm_void;
3642 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3643 s8 ret;
3644
3645 phydm_mcc_ctrl(dm);
3646 if (mcc_dm->mcc_status == 0) {/*Not in MCC stage*/
3647 phydm_mcc_h2ccmd_rst(dm);
3648 return;
3649 }
3650 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC switch\n");
3651 ret = phydm_check(dm);
3652 if (ret == _FAIL) {
3653 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC check fail\n");
3654 return;
3655 }
3656 /* Set IGI*/
3657 phydm_mcc_igi_cal(dm);
3658
3659 /* Set Antenna Gain*/
3660 #if (RTL8822B_SUPPORT == 1)
3661 phydm_dynamic_ant_weighting_mcc_8822b(dm);
3662 #endif
3663 /* Set H2C Cmd*/
3664 phydm_mcc_h2ccmd(dm);
3665 }
3666 #endif
3667
3668 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
phydm_normal_driver_rx_sniffer(struct dm_struct * dm,u8 * desc,PRT_RFD_STATUS rt_rfd_status,u8 * drv_info,u8 phy_status)3669 void phydm_normal_driver_rx_sniffer(
3670 struct dm_struct *dm,
3671 u8 *desc,
3672 PRT_RFD_STATUS rt_rfd_status,
3673 u8 *drv_info,
3674 u8 phy_status)
3675 {
3676 #if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING))
3677 u32 *msg;
3678 u16 seq_num;
3679
3680 if (rt_rfd_status->packet_report_type != NORMAL_RX)
3681 return;
3682
3683 if (!dm->is_linked) {
3684 if (rt_rfd_status->is_hw_error)
3685 return;
3686 }
3687
3688 if (phy_status == true) {
3689 if (dm->rx_pkt_type == type_block_ack ||
3690 dm->rx_pkt_type == type_rts || dm->rx_pkt_type == type_cts)
3691 seq_num = 0;
3692 else
3693 seq_num = rt_rfd_status->seq_num;
3694
3695 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
3696 "%04d , %01s, rate=0x%02x, L=%04d , %s , %s",
3697 seq_num,
3698 /*rt_rfd_status->mac_id,*/
3699 (rt_rfd_status->is_crc ? "C" :
3700 rt_rfd_status->is_ampdu ? "A" : "_"),
3701 rt_rfd_status->data_rate,
3702 rt_rfd_status->length,
3703 ((rt_rfd_status->band_width == 0) ? "20M" :
3704 ((rt_rfd_status->band_width == 1) ? "40M" : "80M")),
3705 (rt_rfd_status->is_ldpc ? "LDP" : "BCC"));
3706
3707 if (dm->rx_pkt_type == type_asoc_req)
3708 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_REQ");
3709 else if (dm->rx_pkt_type == type_asoc_rsp)
3710 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_RSP");
3711 else if (dm->rx_pkt_type == type_probe_req)
3712 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_REQ");
3713 else if (dm->rx_pkt_type == type_probe_rsp)
3714 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_RSP");
3715 else if (dm->rx_pkt_type == type_deauth)
3716 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "DEAUTH");
3717 else if (dm->rx_pkt_type == type_beacon)
3718 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BEACON");
3719 else if (dm->rx_pkt_type == type_block_ack_req)
3720 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BA_REQ");
3721 else if (dm->rx_pkt_type == type_rts)
3722 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__RTS_");
3723 else if (dm->rx_pkt_type == type_cts)
3724 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__CTS_");
3725 else if (dm->rx_pkt_type == type_ack)
3726 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__ACK_");
3727 else if (dm->rx_pkt_type == type_block_ack)
3728 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__BA__");
3729 else if (dm->rx_pkt_type == type_data)
3730 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "_DATA_");
3731 else if (dm->rx_pkt_type == type_data_ack)
3732 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "Data_Ack");
3733 else if (dm->rx_pkt_type == type_qos_data)
3734 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "QoS_Data");
3735 else
3736 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [0x%x]",
3737 dm->rx_pkt_type);
3738
3739 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [RSSI=%d,%d,%d,%d ]",
3740 dm->rssi_a,
3741 dm->rssi_b,
3742 dm->rssi_c,
3743 dm->rssi_d);
3744
3745 msg = (u32 *)drv_info;
3746
3747 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
3748 " , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n",
3749 msg[6], msg[5], msg[4], msg[3],
3750 msg[2], msg[1], msg[1]);
3751 } else {
3752 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
3753 "%04d , %01s, rate=0x%02x, L=%04d , %s , %s\n",
3754 rt_rfd_status->seq_num,
3755 /*rt_rfd_status->mac_id,*/
3756 (rt_rfd_status->is_crc ? "C" :
3757 (rt_rfd_status->is_ampdu) ? "A" : "_"),
3758 rt_rfd_status->data_rate,
3759 rt_rfd_status->length,
3760 ((rt_rfd_status->band_width == 0) ? "20M" :
3761 ((rt_rfd_status->band_width == 1) ? "40M" : "80M")),
3762 (rt_rfd_status->is_ldpc ? "LDP" : "BCC"));
3763 }
3764
3765 #endif
3766 }
3767
3768 #endif
3769