1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@============================================================*/
27 /*@include files*/
28 /*@============================================================*/
29 #include "mp_precomp.h"
30 #include "phydm_precomp.h"
31
32 /*@<YuChen, 150720> Add for KFree Feature Requested by RF David.*/
33 /*@This is a phydm API*/
34
phydm_set_kfree_to_rf_8814a(void * dm_void,u8 e_rf_path,u8 data)35 void phydm_set_kfree_to_rf_8814a(void *dm_void, u8 e_rf_path, u8 data)
36 {
37 struct dm_struct *dm = (struct dm_struct *)dm_void;
38 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
39 boolean is_odd;
40 u32 tx_gain_bitmask = (BIT(17) | BIT(16) | BIT(15));
41
42 if ((data % 2) != 0) { /*odd->positive*/
43 data = data - 1;
44 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), 1);
45 is_odd = true;
46 } else { /*even->negative*/
47 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), 0);
48 is_odd = false;
49 }
50 RF_DBG(dm, DBG_RF_MP, "phy_ConfigKFree8814A(): RF_0x55[19]= %d\n",
51 is_odd);
52 switch (data) {
53 case 0:
54 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
55 odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 0);
56 cali_info->kfree_offset[e_rf_path] = 0;
57 break;
58 case 2:
59 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
60 odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 0);
61 cali_info->kfree_offset[e_rf_path] = 0;
62 break;
63 case 4:
64 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
65 odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 1);
66 cali_info->kfree_offset[e_rf_path] = 1;
67 break;
68 case 6:
69 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
70 odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 1);
71 cali_info->kfree_offset[e_rf_path] = 1;
72 break;
73 case 8:
74 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
75 odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 2);
76 cali_info->kfree_offset[e_rf_path] = 2;
77 break;
78 case 10:
79 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
80 odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 2);
81 cali_info->kfree_offset[e_rf_path] = 2;
82 break;
83 case 12:
84 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
85 odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 3);
86 cali_info->kfree_offset[e_rf_path] = 3;
87 break;
88 case 14:
89 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
90 odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 3);
91 cali_info->kfree_offset[e_rf_path] = 3;
92 break;
93 case 16:
94 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
95 odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 4);
96 cali_info->kfree_offset[e_rf_path] = 4;
97 break;
98 case 18:
99 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
100 odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 4);
101 cali_info->kfree_offset[e_rf_path] = 4;
102 break;
103 case 20:
104 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
105 odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 5);
106 cali_info->kfree_offset[e_rf_path] = 5;
107 break;
108
109 default:
110 break;
111 }
112
113 if (!is_odd) {
114 /*that means Kfree offset is negative, we need to record it.*/
115 cali_info->kfree_offset[e_rf_path] =
116 (-1) * cali_info->kfree_offset[e_rf_path];
117 RF_DBG(dm, DBG_RF_MP,
118 "phy_ConfigKFree8814A(): kfree_offset = %d\n",
119 cali_info->kfree_offset[e_rf_path]);
120 } else {
121 RF_DBG(dm, DBG_RF_MP,
122 "phy_ConfigKFree8814A(): kfree_offset = %d\n",
123 cali_info->kfree_offset[e_rf_path]);
124 }
125 }
126
phydm_get_thermal_trim_offset_8821c(void * dm_void)127 void phydm_get_thermal_trim_offset_8821c(void *dm_void)
128 {
129 struct dm_struct *dm = (struct dm_struct *)dm_void;
130 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
131
132 u8 pg_therm = 0xff;
133
134 odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_21C, &pg_therm, false);
135
136 if (pg_therm != 0xff) {
137 pg_therm = pg_therm & 0x1f;
138 if ((pg_therm & BIT(0)) == 0)
139 power_trim_info->thermal = (-1 * (pg_therm >> 1));
140 else
141 power_trim_info->thermal = (pg_therm >> 1);
142
143 power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
144 }
145
146 RF_DBG(dm, DBG_RF_MP, "[kfree] 8821c thermal trim flag:0x%02x\n",
147 power_trim_info->flag);
148
149 if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
150 RF_DBG(dm, DBG_RF_MP, "[kfree] 8821c thermal:%d\n",
151 power_trim_info->thermal);
152 }
153
phydm_get_power_trim_offset_8821c(void * dm_void)154 void phydm_get_power_trim_offset_8821c(void *dm_void)
155 {
156 struct dm_struct *dm = (struct dm_struct *)dm_void;
157 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
158
159 u8 pg_power = 0xff, i;
160
161 odm_efuse_one_byte_read(dm, PPG_2G_TXAB_21C, &pg_power, false);
162
163 if (pg_power != 0xff) {
164 power_trim_info->bb_gain[0][0] = pg_power;
165 odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_21C, &pg_power, false);
166 power_trim_info->bb_gain[1][0] = pg_power;
167 odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_21C, &pg_power, false);
168 power_trim_info->bb_gain[2][0] = pg_power;
169 odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_21C, &pg_power, false);
170 power_trim_info->bb_gain[3][0] = pg_power;
171 odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_21C, &pg_power, false);
172 power_trim_info->bb_gain[4][0] = pg_power;
173 odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_21C, &pg_power, false);
174 power_trim_info->bb_gain[5][0] = pg_power;
175 power_trim_info->flag =
176 power_trim_info->flag | KFREE_FLAG_ON |
177 KFREE_FLAG_ON_2G | KFREE_FLAG_ON_5G;
178 }
179
180 RF_DBG(dm, DBG_RF_MP, "[kfree] 8821c power trim flag:0x%02x\n",
181 power_trim_info->flag);
182
183 if (power_trim_info->flag & KFREE_FLAG_ON) {
184 for (i = 0; i < KFREE_BAND_NUM; i++)
185 RF_DBG(dm, DBG_RF_MP,
186 "[kfree] 8821c pwr_trim->bb_gain[%d][0]=0x%X\n",
187 i, power_trim_info->bb_gain[i][0]);
188 }
189 }
190
phydm_set_kfree_to_rf_8821c(void * dm_void,u8 e_rf_path,boolean wlg_btg,u8 data)191 void phydm_set_kfree_to_rf_8821c(void *dm_void, u8 e_rf_path, boolean wlg_btg,
192 u8 data)
193 {
194 struct dm_struct *dm = (struct dm_struct *)dm_void;
195 u8 wlg, btg;
196 u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
197 u32 s_gain_bmask = (BIT(19) | BIT(18) | BIT(17) |
198 BIT(16) | BIT(15) | BIT(14));
199
200 odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);
201 odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 1);
202 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 1);
203 odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 1);
204
205 if (wlg_btg) {
206 wlg = data & 0xf;
207 btg = (data & 0xf0) >> 4;
208
209 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (wlg & BIT(0)));
210 odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, (wlg >> 1));
211
212 odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(19), (btg & BIT(0)));
213 odm_set_rf_reg(dm, e_rf_path, RF_0x65, gain_bmask, (btg >> 1));
214 } else {
215 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), data & BIT(0));
216 odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,
217 ((data & 0x1f) >> 1));
218 }
219
220 RF_DBG(dm, DBG_RF_MP,
221 "[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n",
222 odm_get_rf_reg(dm, e_rf_path, RF_0x55, s_gain_bmask),
223 odm_get_rf_reg(dm, e_rf_path, RF_0x65, s_gain_bmask));
224 }
225
phydm_clear_kfree_to_rf_8821c(void * dm_void,u8 e_rf_path,u8 data)226 void phydm_clear_kfree_to_rf_8821c(void *dm_void, u8 e_rf_path, u8 data)
227 {
228 struct dm_struct *dm = (struct dm_struct *)dm_void;
229 u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
230 u32 s_gain_bmask = (BIT(19) | BIT(18) | BIT(17) |
231 BIT(16) | BIT(15) | BIT(14));
232
233 odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);
234 odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 1);
235 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 1);
236 odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 1);
237
238 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
239 odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, (data >> 1));
240
241 odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(19), (data & BIT(0)));
242 odm_set_rf_reg(dm, e_rf_path, RF_0x65, gain_bmask, (data >> 1));
243
244 odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 0);
245 odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 0);
246 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 0);
247 odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 0);
248
249 RF_DBG(dm, DBG_RF_MP,
250 "[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n",
251 odm_get_rf_reg(dm, e_rf_path, RF_0x55, s_gain_bmask),
252 odm_get_rf_reg(dm, e_rf_path, RF_0x65, s_gain_bmask));
253 }
254
phydm_get_thermal_trim_offset_8822b(void * dm_void)255 void phydm_get_thermal_trim_offset_8822b(void *dm_void)
256 {
257 struct dm_struct *dm = (struct dm_struct *)dm_void;
258 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
259
260 u8 pg_therm = 0xff;
261
262 odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_22B, &pg_therm, false);
263
264 if (pg_therm != 0xff) {
265 pg_therm = pg_therm & 0x1f;
266 if ((pg_therm & BIT(0)) == 0)
267 power_trim_info->thermal = (-1 * (pg_therm >> 1));
268 else
269 power_trim_info->thermal = (pg_therm >> 1);
270
271 power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
272 }
273
274 RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b thermal trim flag:0x%02x\n",
275 power_trim_info->flag);
276
277 if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
278 RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b thermal:%d\n",
279 power_trim_info->thermal);
280 }
281
phydm_get_power_trim_offset_8822b(void * dm_void)282 void phydm_get_power_trim_offset_8822b(void *dm_void)
283 {
284 struct dm_struct *dm = (struct dm_struct *)dm_void;
285 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
286
287 u8 pg_power = 0xff, i, j;
288
289 odm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false);
290
291 if (pg_power != 0xff) {
292 /*Path A*/
293 odm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false);
294 power_trim_info->bb_gain[0][0] = (pg_power & 0xf);
295
296 /*Path B*/
297 odm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false);
298 power_trim_info->bb_gain[0][1] = ((pg_power & 0xf0) >> 4);
299
300 power_trim_info->flag |= KFREE_FLAG_ON_2G;
301 power_trim_info->flag |= KFREE_FLAG_ON;
302 }
303
304 odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22B, &pg_power, false);
305
306 if (pg_power != 0xff) {
307 /*Path A*/
308 odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22B, &pg_power, false);
309 power_trim_info->bb_gain[1][0] = pg_power;
310 odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22B, &pg_power, false);
311 power_trim_info->bb_gain[2][0] = pg_power;
312 odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22B, &pg_power, false);
313 power_trim_info->bb_gain[3][0] = pg_power;
314 odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_22B, &pg_power, false);
315 power_trim_info->bb_gain[4][0] = pg_power;
316 odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_22B, &pg_power, false);
317 power_trim_info->bb_gain[5][0] = pg_power;
318
319 /*Path B*/
320 odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22B, &pg_power, false);
321 power_trim_info->bb_gain[1][1] = pg_power;
322 odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22B, &pg_power, false);
323 power_trim_info->bb_gain[2][1] = pg_power;
324 odm_efuse_one_byte_read(dm, PPG_5GM1_TXB_22B, &pg_power, false);
325 power_trim_info->bb_gain[3][1] = pg_power;
326 odm_efuse_one_byte_read(dm, PPG_5GM2_TXB_22B, &pg_power, false);
327 power_trim_info->bb_gain[4][1] = pg_power;
328 odm_efuse_one_byte_read(dm, PPG_5GH1_TXB_22B, &pg_power, false);
329 power_trim_info->bb_gain[5][1] = pg_power;
330
331 power_trim_info->flag |= KFREE_FLAG_ON_5G;
332 power_trim_info->flag |= KFREE_FLAG_ON;
333 }
334
335 RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b power trim flag:0x%02x\n",
336 power_trim_info->flag);
337
338 if (!(power_trim_info->flag & KFREE_FLAG_ON))
339 return;
340
341 for (i = 0; i < KFREE_BAND_NUM; i++) {
342 for (j = 0; j < 2; j++)
343 RF_DBG(dm, DBG_RF_MP,
344 "[kfree] 8822b PwrTrim->bb_gain[%d][%d]=0x%X\n",
345 i, j, power_trim_info->bb_gain[i][j]);
346 }
347 }
348
phydm_set_pa_bias_to_rf_8822b(void * dm_void,u8 e_rf_path,s8 tx_pa_bias)349 void phydm_set_pa_bias_to_rf_8822b(void *dm_void, u8 e_rf_path, s8 tx_pa_bias)
350 {
351 struct dm_struct *dm = (struct dm_struct *)dm_void;
352 u32 rf_reg_51 = 0, rf_reg_52 = 0, rf_reg_3f = 0;
353 u32 tx_pa_bias_bmask = (BIT(12) | BIT(11) | BIT(10) | BIT(9));
354
355 rf_reg_51 = odm_get_rf_reg(dm, e_rf_path, RF_0x51, RFREGOFFSETMASK);
356 rf_reg_52 = odm_get_rf_reg(dm, e_rf_path, RF_0x52, RFREGOFFSETMASK);
357
358 RF_DBG(dm, DBG_RF_MP,
359 "[kfree] 8822b 2g rf(0x51)=0x%X rf(0x52)=0x%X path=%d\n",
360 rf_reg_51, rf_reg_52, e_rf_path);
361
362 #if 0
363 /*rf3f => rf52[19:17] = rf3f[2:0] rf52[16:15] = rf3f[4:3] rf52[3:0] = rf3f[8:5]*/
364 /*rf3f => rf51[6:3] = rf3f[12:9] rf52[13] = rf3f[13]*/
365 #endif
366 rf_reg_3f = ((rf_reg_52 & 0xe0000) >> 17) |
367 (((rf_reg_52 & 0x18000) >> 15) << 3) |
368 ((rf_reg_52 & 0xf) << 5) |
369 (((rf_reg_51 & 0x78) >> 3) << 9) |
370 (((rf_reg_52 & 0x2000) >> 13) << 13);
371
372 RF_DBG(dm, DBG_RF_MP,
373 "[kfree] 8822b 2g original pa_bias=%d rf_reg_3f=0x%X path=%d\n",
374 tx_pa_bias, rf_reg_3f, e_rf_path);
375
376 tx_pa_bias = (s8)((rf_reg_3f & tx_pa_bias_bmask) >> 9) + tx_pa_bias;
377
378 if (tx_pa_bias < 0)
379 tx_pa_bias = 0;
380 else if (tx_pa_bias > 7)
381 tx_pa_bias = 7;
382
383 rf_reg_3f = ((rf_reg_3f & 0xfe1ff) | (tx_pa_bias << 9));
384
385 RF_DBG(dm, DBG_RF_MP,
386 "[kfree] 8822b 2g 0x%X 0x%X pa_bias=%d rfreg_3f=0x%X path=%d\n",
387 PPG_PABIAS_2GA_22B, PPG_PABIAS_2GB_22B,
388 tx_pa_bias, rf_reg_3f, e_rf_path);
389
390 odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(10), 0x1);
391 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x0);
392 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
393 odm_set_rf_reg(dm, e_rf_path, RF_0x33, BIT(0), 0x1);
394 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
395 odm_set_rf_reg(dm, e_rf_path, RF_0x33, BIT(1), 0x1);
396 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
397 odm_set_rf_reg(dm, e_rf_path, RF_0x33, (BIT(1) | BIT(0)), 0x3);
398 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
399 odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(10), 0x0);
400
401 RF_DBG(dm, DBG_RF_MP,
402 "[kfree] 8822b 2g tx pa bias rf_0x3f(0x%X) path=%d\n",
403 odm_get_rf_reg(dm, e_rf_path, RF_0x3f,
404 (BIT(12) | BIT(11) | BIT(10) | BIT(9))),
405 e_rf_path);
406 }
407
phydm_get_pa_bias_offset_8822b(void * dm_void)408 void phydm_get_pa_bias_offset_8822b(void *dm_void)
409 {
410 struct dm_struct *dm = (struct dm_struct *)dm_void;
411 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
412
413 u8 pg_pa_bias = 0xff, e_rf_path = 0;
414 s8 tx_pa_bias[2] = {0};
415
416 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22B, &pg_pa_bias, false);
417
418 if (pg_pa_bias != 0xff) {
419 /*paht a*/
420 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22B,
421 &pg_pa_bias, false);
422 pg_pa_bias = pg_pa_bias & 0xf;
423
424 if ((pg_pa_bias & BIT(0)) == 0)
425 tx_pa_bias[0] = (-1 * (pg_pa_bias >> 1));
426 else
427 tx_pa_bias[0] = (pg_pa_bias >> 1);
428
429 /*paht b*/
430 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GB_22B,
431 &pg_pa_bias, false);
432 pg_pa_bias = pg_pa_bias & 0xf;
433
434 if ((pg_pa_bias & BIT(0)) == 0)
435 tx_pa_bias[1] = (-1 * (pg_pa_bias >> 1));
436 else
437 tx_pa_bias[1] = (pg_pa_bias >> 1);
438
439 RF_DBG(dm, DBG_RF_MP,
440 "[kfree] 8822b 2g PathA_pa_bias:%d PathB_pa_bias:%d\n",
441 tx_pa_bias[0], tx_pa_bias[1]);
442
443 for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)
444 phydm_set_pa_bias_to_rf_8822b(dm, e_rf_path,
445 tx_pa_bias[e_rf_path]);
446
447 power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
448 } else {
449 RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b 2g tx pa bias no pg\n");
450 }
451 }
452
phydm_set_kfree_to_rf_8822b(void * dm_void,u8 e_rf_path,u8 data)453 void phydm_set_kfree_to_rf_8822b(void *dm_void, u8 e_rf_path, u8 data)
454 {
455 struct dm_struct *dm = (struct dm_struct *)dm_void;
456 u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
457
458 odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);
459 odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1);
460 odm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000);
461 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
462
463 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
464 odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,
465 ((data & 0x1f) >> 1));
466
467 RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b 0x55[19:14]=0x%X path=%d\n",
468 odm_get_rf_reg(dm, e_rf_path, RF_0x55,
469 (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
470 BIT(15) | BIT(14))), e_rf_path);
471 }
472
phydm_clear_kfree_to_rf_8822b(void * dm_void,u8 e_rf_path,u8 data)473 void phydm_clear_kfree_to_rf_8822b(void *dm_void, u8 e_rf_path, u8 data)
474 {
475 struct dm_struct *dm = (struct dm_struct *)dm_void;
476 u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
477
478 odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);
479 odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1);
480 odm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000);
481 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
482
483 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
484 odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,
485 ((data & 0x1f) >> 1));
486
487 odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 0);
488 odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1);
489 odm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000);
490 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 0);
491 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(7), 0);
492
493 RF_DBG(dm, DBG_RF_MP,
494 "[kfree] 8822b clear power trim 0x55[19:14]=0x%X path=%d\n",
495 odm_get_rf_reg(dm, e_rf_path, RF_0x55,
496 (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
497 BIT(15) | BIT(14))), e_rf_path);
498 }
499
phydm_get_thermal_trim_offset_8710b(void * dm_void)500 void phydm_get_thermal_trim_offset_8710b(void *dm_void)
501 {
502 struct dm_struct *dm = (struct dm_struct *)dm_void;
503 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
504
505 u8 pg_therm = 0xff;
506
507 odm_efuse_one_byte_read(dm, 0x0EF, &pg_therm, false);
508
509 if (pg_therm != 0xff) {
510 pg_therm = pg_therm & 0x1f;
511 if ((pg_therm & BIT(0)) == 0)
512 power_trim_info->thermal = (-1 * (pg_therm >> 1));
513 else
514 power_trim_info->thermal = (pg_therm >> 1);
515
516 power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
517 }
518
519 RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b thermal trim flag:0x%02x\n",
520 power_trim_info->flag);
521
522 if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
523 RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b thermal:%d\n",
524 power_trim_info->thermal);
525 }
526
phydm_get_power_trim_offset_8710b(void * dm_void)527 void phydm_get_power_trim_offset_8710b(void *dm_void)
528 {
529 struct dm_struct *dm = (struct dm_struct *)dm_void;
530 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
531
532 u8 pg_power = 0xff;
533
534 odm_efuse_one_byte_read(dm, 0xEE, &pg_power, false);
535
536 if (pg_power != 0xff) {
537 /*Path A*/
538 odm_efuse_one_byte_read(dm, 0xEE, &pg_power, false);
539 power_trim_info->bb_gain[0][0] = (pg_power & 0xf);
540
541 power_trim_info->flag |= KFREE_FLAG_ON_2G;
542 power_trim_info->flag |= KFREE_FLAG_ON;
543 }
544
545 RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b power trim flag:0x%02x\n",
546 power_trim_info->flag);
547
548 if (power_trim_info->flag & KFREE_FLAG_ON)
549 RF_DBG(dm, DBG_RF_MP,
550 "[kfree] 8710b power_trim_data->bb_gain[0][0]=0x%X\n",
551 power_trim_info->bb_gain[0][0]);
552 }
553
phydm_set_kfree_to_rf_8710b(void * dm_void,u8 e_rf_path,u8 data)554 void phydm_set_kfree_to_rf_8710b(void *dm_void, u8 e_rf_path, u8 data)
555 {
556 struct dm_struct *dm = (struct dm_struct *)dm_void;
557 u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15));
558
559 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
560 odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, ((data & 0xf) >> 1));
561
562 RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b 0x55[19:14]=0x%X path=%d\n",
563 odm_get_rf_reg(dm, e_rf_path, RF_0x55,
564 (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
565 BIT(15) | BIT(14))), e_rf_path);
566 }
567
phydm_clear_kfree_to_rf_8710b(void * dm_void,u8 e_rf_path,u8 data)568 void phydm_clear_kfree_to_rf_8710b(void *dm_void, u8 e_rf_path, u8 data)
569 {
570 struct dm_struct *dm = (struct dm_struct *)dm_void;
571 u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
572
573 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
574 odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,
575 ((data & 0x1f) >> 1));
576
577 RF_DBG(dm, DBG_RF_MP,
578 "[kfree] 8710b clear power trim 0x55[19:14]=0x%X path=%d\n",
579 odm_get_rf_reg(dm, e_rf_path, RF_0x55,
580 (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
581 BIT(15) | BIT(14))), e_rf_path);
582 }
583
phydm_get_thermal_trim_offset_8192f(void * dm_void)584 void phydm_get_thermal_trim_offset_8192f(void *dm_void)
585 {
586 struct dm_struct *dm = (struct dm_struct *)dm_void;
587 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
588
589 u8 pg_therm = 0xff;
590
591 odm_efuse_one_byte_read(dm, 0x1EF, &pg_therm, false);
592
593 if (pg_therm != 0xff) {
594 pg_therm = pg_therm & 0x1f;
595 if ((pg_therm & BIT(0)) == 0)
596 power_trim_info->thermal = (-1 * (pg_therm >> 1));
597 else
598 power_trim_info->thermal = (pg_therm >> 1);
599
600 power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
601 }
602
603 RF_DBG(dm, DBG_RF_MP, "[kfree] 8192f thermal trim flag:0x%02x\n",
604 power_trim_info->flag);
605
606 if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
607 RF_DBG(dm, DBG_RF_MP, "[kfree] 8192f thermal:%d\n",
608 power_trim_info->thermal);
609 }
610
phydm_get_power_trim_offset_8192f(void * dm_void)611 void phydm_get_power_trim_offset_8192f(void *dm_void)
612 {
613 struct dm_struct *dm = (struct dm_struct *)dm_void;
614 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
615
616 u8 pg_power1 = 0xff, pg_power2 = 0xff, pg_power3 = 0xff, i, j;
617
618 odm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false); /*CH4-9*/
619
620 if (pg_power1 != 0xff) {
621 /*Path A*/
622 odm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false);
623 power_trim_info->bb_gain[1][0] = (pg_power1 & 0xf);
624 /*Path B*/
625 odm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false);
626 power_trim_info->bb_gain[1][1] = ((pg_power1 & 0xf0) >> 4);
627
628 power_trim_info->flag |= KFREE_FLAG_ON_2G;
629 power_trim_info->flag |= KFREE_FLAG_ON;
630 }
631
632 odm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false); /*CH1-3*/
633
634 if (pg_power2 != 0xff) {
635 /*Path A*/
636 odm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false);
637 power_trim_info->bb_gain[0][0] = (pg_power2 & 0xf);
638 /*Path B*/
639 odm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false);
640 power_trim_info->bb_gain[0][1] = ((pg_power2 & 0xf0) >> 4);
641
642 power_trim_info->flag |= KFREE_FLAG_ON_2G;
643 power_trim_info->flag |= KFREE_FLAG_ON;
644 } else {
645 power_trim_info->bb_gain[0][0] = (pg_power1 & 0xf);
646 power_trim_info->bb_gain[0][1] = ((pg_power1 & 0xf0) >> 4);
647 }
648
649 odm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false); /*CH10-14*/
650
651 if (pg_power3 != 0xff) {
652 /*Path A*/
653 odm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false);
654 power_trim_info->bb_gain[2][0] = (pg_power3 & 0xf);
655 /*Path B*/
656 odm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false);
657 power_trim_info->bb_gain[2][1] = ((pg_power3 & 0xf0) >> 4);
658
659 power_trim_info->flag |= KFREE_FLAG_ON_2G;
660 power_trim_info->flag |= KFREE_FLAG_ON;
661 } else {
662 power_trim_info->bb_gain[2][0] = (pg_power1 & 0xf);
663 power_trim_info->bb_gain[2][1] = ((pg_power1 & 0xf0) >> 4);
664 }
665
666 RF_DBG(dm, DBG_RF_MP, "[kfree] 8192F power trim flag:0x%02x\n",
667 power_trim_info->flag);
668
669 if (!(power_trim_info->flag & KFREE_FLAG_ON))
670 return;
671
672 for (i = 0; i < KFREE_CH_NUM; i++) {
673 for (j = 0; j < 2; j++)
674 RF_DBG(dm, DBG_RF_MP,
675 "[kfree] 8192F PwrTrim->bb_gain[%d][%d]=0x%X\n",
676 i, j, power_trim_info->bb_gain[i][j]);
677 }
678 }
679
phydm_set_kfree_to_rf_8192f(void * dm_void,u8 e_rf_path,u8 channel_idx,u8 data)680 void phydm_set_kfree_to_rf_8192f(void *dm_void, u8 e_rf_path, u8 channel_idx,
681 u8 data)
682 {
683 struct dm_struct *dm = (struct dm_struct *)dm_void;
684
685 /*power_trim based on 55[19:14]*/
686 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
687 /*enable 55[14] for 0.5db step*/
688 odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 1);
689 /*enter power_trim debug mode*/
690 odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 1);
691 /*write enable*/
692 odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1);
693
694 if (e_rf_path == 0) {
695 if (channel_idx == 0) {
696 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);
697 odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
698
699 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);
700 odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
701
702 } else if (channel_idx == 1) {
703 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);
704 odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
705
706 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);
707 odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
708 } else if (channel_idx == 2) {
709 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);
710 odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
711
712 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);
713 odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
714 }
715 } else if (e_rf_path == 1) {
716 if (channel_idx == 0) {
717 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);
718 odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
719
720 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);
721 odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
722 } else if (channel_idx == 1) {
723 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);
724 odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
725
726 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);
727 odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
728 } else if (channel_idx == 2) {
729 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);
730 odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
731
732 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);
733 odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
734 }
735 }
736
737 /*leave power_trim debug mode*/
738 odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);
739 /*write disable*/
740 odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0);
741
742 RF_DBG(dm, DBG_RF_MP,
743 "[kfree] 8192F 0x55[19:14]=0x%X path=%d channel=%d\n",
744 odm_get_rf_reg(dm, e_rf_path, RF_0x55,
745 (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
746 BIT(15) | BIT(14))), e_rf_path, channel_idx);
747 }
748
749 #if 0
750 /*
751 void phydm_clear_kfree_to_rf_8192f(void *dm_void, u8 e_rf_path, u8 data)
752 {
753 struct dm_struct *dm = (struct dm_struct *)dm_void;
754 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
755
756 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
757 odm_set_rf_reg(dm, e_rf_path, RF_0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1));
758
759 RF_DBG(dm, DBG_RF_MP,
760 "[kfree] 8192F clear power trim 0x55[19:14]=0x%X path=%d\n",
761 odm_get_rf_reg(dm, e_rf_path, RF_0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
762 e_rf_path
763 );
764 }
765 */
766 #endif
767
phydm_get_thermal_trim_offset_8198f(void * dm_void)768 void phydm_get_thermal_trim_offset_8198f(void *dm_void)
769 {
770 struct dm_struct *dm = (struct dm_struct *)dm_void;
771 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
772
773 u8 pg_therm = 0;
774
775 odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_98F, &pg_therm, false);
776
777 RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f efuse thermal trim 0x%X=0x%X\n",
778 PPG_THERMAL_OFFSET_98F, pg_therm);
779
780 if (pg_therm != 0) {
781 pg_therm = pg_therm & 0x1f;
782 if ((pg_therm & BIT(0)) == 0)
783 power_trim_info->thermal = (-1 * (pg_therm >> 1));
784 else
785 power_trim_info->thermal = (pg_therm >> 1);
786
787 power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
788 }
789
790 RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f thermal trim flag:0x%02x\n",
791 power_trim_info->flag);
792
793 if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
794 RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f thermal:%d\n",
795 power_trim_info->thermal);
796 }
797
phydm_get_power_trim_offset_8198f(void * dm_void)798 void phydm_get_power_trim_offset_8198f(void *dm_void)
799 {
800 struct dm_struct *dm = (struct dm_struct *)dm_void;
801 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
802
803 u8 i, j;
804 u8 power_trim[6] = {0};
805
806 odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_98F, &power_trim[0], false);
807 odm_efuse_one_byte_read(dm, PPG_2GL_TXCD_98F, &power_trim[1], false);
808 odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_98F, &power_trim[2], false);
809 odm_efuse_one_byte_read(dm, PPG_2GM_TXCD_98F, &power_trim[3], false);
810 odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_98F, &power_trim[4], false);
811 odm_efuse_one_byte_read(dm, PPG_2GH_TXCD_98F, &power_trim[5], false);
812
813 RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f efuse Power Trim 0x%X=0x%X 0x%X=0x%X 0x%X=0x%X 0x%X=0x%X 0x%X=0x%X 0x%X=0x%X\n",
814 PPG_2GL_TXAB_98F, power_trim[0],
815 PPG_2GL_TXCD_98F, power_trim[1],
816 PPG_2GM_TXAB_98F, power_trim[2],
817 PPG_2GM_TXCD_98F, power_trim[3],
818 PPG_2GH_TXAB_98F, power_trim[4],
819 PPG_2GH_TXCD_98F, power_trim[5]
820 );
821
822 j = 0;
823 for (i = 0; i < 6; i++) {
824 if (power_trim[i] == 0x0)
825 j++;
826 }
827
828 if (j == 6) {
829 RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f Power Trim no pg\n");
830 } else {
831 power_trim_info->bb_gain[0][0] = power_trim[0] & 0xf;
832 power_trim_info->bb_gain[0][1] = (power_trim[0] & 0xf0) >> 4;
833
834 power_trim_info->bb_gain[0][2] = power_trim[1] & 0xf;
835 power_trim_info->bb_gain[0][3] = (power_trim[1] & 0xf0) >> 4;
836
837 power_trim_info->bb_gain[1][0] = power_trim[2] & 0xf;
838 power_trim_info->bb_gain[1][1] = (power_trim[2] & 0xf0) >> 4;
839
840 power_trim_info->bb_gain[1][2] = power_trim[3] & 0xf;
841 power_trim_info->bb_gain[1][3] = (power_trim[3] & 0xf0) >> 4;
842
843 power_trim_info->bb_gain[2][0] = power_trim[4] & 0xf;
844 power_trim_info->bb_gain[2][1] = (power_trim[4] & 0xf0) >> 4;
845
846 power_trim_info->bb_gain[2][2] = power_trim[5] & 0xf;
847 power_trim_info->bb_gain[2][3] = (power_trim[5] & 0xf0) >> 4;
848
849 power_trim_info->flag =
850 power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G;
851 }
852
853 RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f power trim flag:0x%02x\n",
854 power_trim_info->flag);
855
856 if (power_trim_info->flag & KFREE_FLAG_ON) {
857 for (i = 0; i < KFREE_BAND_NUM; i++) {
858 for (j = 0; j < MAX_RF_PATH; j++) {
859 RF_DBG(dm, DBG_RF_MP,
860 "[kfree] 8198f pwr_trim->bb_gain[%d][%d]=0x%X\n",
861 i, j, power_trim_info->bb_gain[i][j]);
862 }
863 }
864 }
865 }
866
phydm_get_pa_bias_offset_8198f(void * dm_void)867 void phydm_get_pa_bias_offset_8198f(void *dm_void)
868 {
869 struct dm_struct *dm = (struct dm_struct *)dm_void;
870 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
871
872 u8 i, j;
873 u8 pa_bias[2] = {0};
874 u8 tx_pa_bias[4] = {0};
875
876 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GAB_98F, &pa_bias[0], false);
877 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GCD_98F, &pa_bias[1], false);
878
879 RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f efuse Tx PA Bias 0x%X=0x%X 0x%X=0x%X\n",
880 PPG_PABIAS_2GAB_98F, pa_bias[0], PPG_PABIAS_2GCD_98F, pa_bias[1]);
881
882 j = 0;
883 for (i = 0; i < 2; i++) {
884 if (pa_bias[i] == 0x0)
885 j++;
886 }
887
888 if (j == 2) {
889 RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f Tx PA Bias no pg\n");
890 } else {
891 /*paht ab*/
892 tx_pa_bias[0] = pa_bias[0] & 0xf;
893 tx_pa_bias[1] = ((pa_bias[0] & 0xf0) >> 4);
894
895 /*paht cd*/
896 tx_pa_bias[2] = pa_bias[1] & 0xf;
897 tx_pa_bias[3] = ((pa_bias[1] & 0xf0) >> 4);
898
899 for (i = RF_PATH_A; i < 4; i++) {
900 if ((tx_pa_bias[i] & 0x1) == 1)
901 tx_pa_bias[i] = tx_pa_bias[i] & 0xe;
902 else
903 tx_pa_bias[i] = tx_pa_bias[i] | 0x1;
904 }
905
906 RF_DBG(dm, DBG_RF_MP,
907 "[kfree] 8198f PathA_pa_bias:0x%x PathB_pa_bias:0x%x\n",
908 tx_pa_bias[0], tx_pa_bias[1]);
909
910 RF_DBG(dm, DBG_RF_MP,
911 "[kfree] 8198f PathC_pa_bias:0x%x PathD_pa_bias:0x%x\n",
912 tx_pa_bias[2], tx_pa_bias[3]);
913
914 for (i = RF_PATH_A; i < 4; i++)
915 odm_set_rf_reg(dm, i, 0x60, 0x0000f000, tx_pa_bias[i]);
916
917 power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
918 }
919 }
920
phydm_get_set_lna_offset_8198f(void * dm_void)921 void phydm_get_set_lna_offset_8198f(void *dm_void)
922 {
923 struct dm_struct *dm = (struct dm_struct *)dm_void;
924 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
925
926 u8 i, j;
927 u8 lna_trim[4] = {0};
928 u8 cg[4] = {0}, cs[4] = {0};
929 u32 rf_reg;
930
931 odm_efuse_one_byte_read(dm, PPG_LNA_2GA_98F, &lna_trim[0], false);
932 odm_efuse_one_byte_read(dm, PPG_LNA_2GB_98F, &lna_trim[1], false);
933 odm_efuse_one_byte_read(dm, PPG_LNA_2GC_98F, &lna_trim[2], false);
934 odm_efuse_one_byte_read(dm, PPG_LNA_2GD_98F, &lna_trim[3], false);
935
936 RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f efuse LNA Trim 0x%X=0x%X 0x%X=0x%X 0x%X=0x%X 0x%X=0x%X\n",
937 PPG_LNA_2GA_98F, lna_trim[0],
938 PPG_LNA_2GB_98F, lna_trim[1],
939 PPG_LNA_2GC_98F, lna_trim[2],
940 PPG_LNA_2GD_98F, lna_trim[3]
941 );
942
943 j = 0;
944 for (i = 0; i < 4; i++) {
945 if (lna_trim[i] == 0x0)
946 j++;
947 }
948
949 if (j == 4) {
950 RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f LNA no pg\n");
951 } else {
952
953 for (i = 0; i < 4; i++) {
954 cg[i] = (lna_trim[i] & 0xc) >> 2;
955 cs[i] = lna_trim[i] & 0x3;
956 }
957
958 for (i = RF_PATH_A; i <= RF_PATH_D; i++) {
959 RF_DBG(dm, DBG_RF_MP,
960 "[kfree] 8198f lna cg[%d]=0x%x cs[%d]=0x%x\n",
961 i, cg[i], i, cs[i]);
962 odm_set_rf_reg(dm, i, 0xdf, RFREGOFFSETMASK, 0x2);
963
964 if (cg[i] == 0x3) {
965 rf_reg = odm_get_rf_reg(dm, i, 0x86, (BIT(19) | BIT(18)));
966 rf_reg = rf_reg + 1;
967 if (rf_reg >= 0x3)
968 rf_reg = 0x3;
969 odm_set_rf_reg(dm, i, 0x86, (BIT(19) | BIT(18)), rf_reg);
970 RF_DBG(dm, DBG_RF_MP,
971 "[kfree] 8198f lna CG set rf 0x86 [19:18]=0x%x path=%d\n", rf_reg, i);
972 }
973 if (cs[i] == 0x3) {
974 rf_reg = odm_get_rf_reg(dm, i, 0x86, (BIT(17) | BIT(16)));
975 rf_reg = rf_reg + 1;
976 if (rf_reg >= 0x3)
977 rf_reg = 0x3;
978 odm_set_rf_reg(dm, i, 0x86, (BIT(17) | BIT(16)), rf_reg);
979 RF_DBG(dm, DBG_RF_MP,
980 "[kfree] 8198f lna CS set rf 0x86 [17:16]=0x%x path=%d\n", rf_reg, i);
981 }
982 }
983
984 power_trim_info->lna_flag |= LNA_FLAG_ON;
985 }
986 }
987
988
phydm_set_kfree_to_rf_8198f(void * dm_void,u8 e_rf_path,u8 data)989 void phydm_set_kfree_to_rf_8198f(void *dm_void, u8 e_rf_path, u8 data)
990 {
991 struct dm_struct *dm = (struct dm_struct *)dm_void;
992 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
993 u32 i;
994 s8 pwr_offset[3];
995
996 RF_DBG(dm, DBG_RF_MP,
997 "[kfree] %s:Set kfree to rf 0x33\n", __func__);
998
999 /*power_trim based on 55[19:14]*/
1000 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
1001 /*enable 55[14] for 0.5db step*/
1002 odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 1);
1003 /*enter power_trim debug mode*/
1004 odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);
1005 /*write enable*/
1006 odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1);
1007
1008 for (i =0; i < 3; i++)
1009 pwr_offset[i] = power_trim_info->bb_gain[i][e_rf_path];
1010
1011 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);
1012 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[0]);
1013 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);
1014 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[0]);
1015 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);
1016 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[1]);
1017 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);
1018 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[1]);
1019 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);
1020 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[2]);
1021 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);
1022 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[2]);
1023
1024 /*leave power_trim debug mode*/
1025 /*odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);*/
1026 /*write disable*/
1027 odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0);
1028
1029 }
1030
phydm_clear_kfree_to_rf_8198f(void * dm_void,u8 e_rf_path,u8 data)1031 void phydm_clear_kfree_to_rf_8198f(void *dm_void, u8 e_rf_path, u8 data)
1032 {
1033 struct dm_struct *dm = (struct dm_struct *)dm_void;
1034 #if 0
1035
1036 RF_DBG(dm, DBG_RF_MP,
1037 "[kfree] %s:Clear kfree to rf 0x55\n", __func__);
1038
1039 /*power_trim based on 55[19:14]*/
1040 odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
1041 /*enable 55[14] for 0.5db step*/
1042 odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 1);
1043 /*enter power_trim debug mode*/
1044 odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);
1045 /*write enable*/
1046 odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1);
1047
1048 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);
1049 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
1050 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);
1051 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
1052 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);
1053 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
1054 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);
1055 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
1056 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);
1057 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
1058 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);
1059 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
1060
1061 /*leave power_trim debug mode*/
1062 odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);
1063 /*enable 55[14] for 0.5db step*/
1064 odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 0);
1065 /*write disable*/
1066 odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0);
1067
1068 odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 1);
1069 /*odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 0);*/
1070
1071 #endif
1072
1073 }
1074
phydm_get_set_thermal_trim_offset_8822c(void * dm_void)1075 void phydm_get_set_thermal_trim_offset_8822c(void *dm_void)
1076 {
1077 struct dm_struct *dm = (struct dm_struct *)dm_void;
1078 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1079
1080 u8 pg_therm = 0xff, thermal[2] = {0};
1081
1082 odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_22C, &pg_therm, false);
1083
1084 if (pg_therm != 0xff) {
1085 /*s0*/
1086 pg_therm = pg_therm & 0x1f;
1087
1088 thermal[RF_PATH_A] =
1089 ((pg_therm & 0x1) << 3) | ((pg_therm >> 1) & 0x7);
1090
1091 odm_set_rf_reg(dm, RF_PATH_A, RF_0x43, 0x000f0000, thermal[RF_PATH_A]);
1092
1093 /*s1*/
1094 odm_efuse_one_byte_read(dm, PPG_THERMAL_B_OFFSET_22C, &pg_therm, false);
1095
1096 pg_therm = pg_therm & 0x1f;
1097
1098 thermal[RF_PATH_B] = ((pg_therm & 0x1) << 3) | ((pg_therm >> 1) & 0x7);
1099
1100 odm_set_rf_reg(dm, RF_PATH_B, RF_0x43, 0x000f0000, thermal[RF_PATH_B]);
1101
1102 power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
1103
1104 }
1105
1106 RF_DBG(dm, DBG_RF_MP, "[kfree] 8822c thermal trim flag:0x%02x\n",
1107 power_trim_info->flag);
1108
1109 if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
1110 RF_DBG(dm, DBG_RF_MP, "[kfree] 8822c thermalA:%d thermalB:%d\n",
1111 thermal[RF_PATH_A],
1112 thermal[RF_PATH_B]);
1113 }
1114
phydm_set_power_trim_offset_8822c(void * dm_void)1115 void phydm_set_power_trim_offset_8822c(void *dm_void)
1116 {
1117 struct dm_struct *dm = (struct dm_struct *)dm_void;
1118 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1119 u8 e_rf_path;
1120
1121 for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)
1122 {
1123 odm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 1);
1124
1125 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x0);
1126 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1127 power_trim_info->bb_gain[0][e_rf_path]);
1128 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x1);
1129 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1130 power_trim_info->bb_gain[1][e_rf_path]);
1131 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x2);
1132 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1133 power_trim_info->bb_gain[2][e_rf_path]);
1134 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x3);
1135 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1136 power_trim_info->bb_gain[2][e_rf_path]);
1137 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x4);
1138 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1139 power_trim_info->bb_gain[3][e_rf_path]);
1140 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x5);
1141 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1142 power_trim_info->bb_gain[4][e_rf_path]);
1143 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x6);
1144 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1145 power_trim_info->bb_gain[5][e_rf_path]);
1146 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x7);
1147 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1148 power_trim_info->bb_gain[6][e_rf_path]);
1149 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x8);
1150 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1151 power_trim_info->bb_gain[7][e_rf_path]);
1152 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x9);
1153 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1154 power_trim_info->bb_gain[3][e_rf_path]);
1155 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xa);
1156 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1157 power_trim_info->bb_gain[4][e_rf_path]);
1158 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xb);
1159 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1160 power_trim_info->bb_gain[5][e_rf_path]);
1161 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xc);
1162 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1163 power_trim_info->bb_gain[6][e_rf_path]);
1164 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xd);
1165 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1166 power_trim_info->bb_gain[7][e_rf_path]);
1167 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xe);
1168 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1169 power_trim_info->bb_gain[7][e_rf_path]);
1170
1171 odm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 0);
1172 }
1173 }
1174
phydm_get_set_power_trim_offset_8822c(void * dm_void)1175 void phydm_get_set_power_trim_offset_8822c(void *dm_void)
1176 {
1177 struct dm_struct *dm = (struct dm_struct *)dm_void;
1178 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1179
1180 u8 pg_power = 0xff, i, j;
1181 u8 pg_power1, pg_power2 , pg_power3, pg_power4, pg_power5;
1182
1183 odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_22C, &pg_power1, false);
1184 odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_22C, &pg_power2, false);
1185 odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_22C, &pg_power3, false);
1186 odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22C, &pg_power4, false);
1187 odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22C, &pg_power5, false);
1188
1189 if (pg_power1 != 0xff || pg_power2 != 0xff || pg_power3 != 0xff ||
1190 pg_power4 != 0xff || pg_power5 != 0xff) {
1191 odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_22C, &pg_power, false);
1192 if (pg_power == 0xff)
1193 pg_power = 0;
1194 power_trim_info->bb_gain[0][0] = pg_power & 0xf;
1195 power_trim_info->bb_gain[0][1] = (pg_power & 0xf0) >> 4;
1196
1197 odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_22C, &pg_power, false);
1198 if (pg_power == 0xff)
1199 pg_power = 0;
1200 power_trim_info->bb_gain[1][0] = pg_power & 0xf;
1201 power_trim_info->bb_gain[1][1] = (pg_power & 0xf0) >> 4;
1202
1203 odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_22C, &pg_power, false);
1204 if (pg_power == 0xff)
1205 pg_power = 0;
1206 power_trim_info->bb_gain[2][0] = pg_power & 0xf;
1207 power_trim_info->bb_gain[2][1] = (pg_power & 0xf0) >> 4;
1208
1209 odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22C, &pg_power, false);
1210 if (pg_power == 0xff)
1211 pg_power = 0;
1212 power_trim_info->bb_gain[3][0] = pg_power & 0x1f;
1213 odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22C, &pg_power, false);
1214 if (pg_power == 0xff)
1215 pg_power = 0;
1216 power_trim_info->bb_gain[3][1] = pg_power & 0x1f;
1217
1218 odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22C, &pg_power, false);
1219 if (pg_power == 0xff)
1220 pg_power = 0;
1221 power_trim_info->bb_gain[4][0] = pg_power & 0x1f;
1222 odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22C, &pg_power, false);
1223 if (pg_power == 0xff)
1224 pg_power = 0;
1225 power_trim_info->bb_gain[4][1] = pg_power & 0x1f;
1226
1227 odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22C, &pg_power, false);
1228 if (pg_power == 0xff)
1229 pg_power = 0;
1230 power_trim_info->bb_gain[5][0] = pg_power & 0x1f;
1231 odm_efuse_one_byte_read(dm, PPG_5GM1_TXB_22C, &pg_power, false);
1232 if (pg_power == 0xff)
1233 pg_power = 0;
1234 power_trim_info->bb_gain[5][1] = pg_power & 0x1f;
1235
1236 odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_22C, &pg_power, false);
1237 if (pg_power == 0xff)
1238 pg_power = 0;
1239 power_trim_info->bb_gain[6][0] = pg_power & 0x1f;
1240 odm_efuse_one_byte_read(dm, PPG_5GM2_TXB_22C, &pg_power, false);
1241 if (pg_power == 0xff)
1242 pg_power = 0;
1243 power_trim_info->bb_gain[6][1] = pg_power & 0x1f;
1244
1245 odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_22C, &pg_power, false);
1246 if (pg_power == 0xff)
1247 pg_power = 0;
1248 power_trim_info->bb_gain[7][0] = pg_power & 0x1f;
1249 odm_efuse_one_byte_read(dm, PPG_5GH1_TXB_22C, &pg_power, false);
1250 if (pg_power == 0xff)
1251 pg_power = 0;
1252 power_trim_info->bb_gain[7][1] = pg_power & 0x1f;
1253
1254 power_trim_info->flag =
1255 power_trim_info->flag | KFREE_FLAG_ON |
1256 KFREE_FLAG_ON_2G |
1257 KFREE_FLAG_ON_5G;
1258
1259 phydm_set_power_trim_offset_8822c(dm);
1260 }
1261
1262 RF_DBG(dm, DBG_RF_MP, "[kfree] 8822c power trim flag:0x%02x\n",
1263 power_trim_info->flag);
1264
1265 if (power_trim_info->flag & KFREE_FLAG_ON) {
1266 for (i = 0; i < KFREE_BAND_NUM; i++) {
1267 for (j = 0; j < 2; j++) {
1268 RF_DBG(dm, DBG_RF_MP,
1269 "[kfree] 8822c pwr_trim->bb_gain[%d][%d]=0x%X\n",
1270 i, j, power_trim_info->bb_gain[i][j]);
1271 }
1272 }
1273 }
1274 }
1275
phydm_get_tssi_trim_offset_8822c(void * dm_void)1276 void phydm_get_tssi_trim_offset_8822c(void *dm_void)
1277 {
1278 struct dm_struct *dm = (struct dm_struct *)dm_void;
1279 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1280
1281 u8 i, j;
1282 u8 pg_power[16] = {0};
1283
1284 odm_efuse_one_byte_read(dm, TSSI_2GM_TXA_22C, &pg_power[0], false);
1285 odm_efuse_one_byte_read(dm, TSSI_2GM_TXB_22C, &pg_power[1], false);
1286 odm_efuse_one_byte_read(dm, TSSI_2GH_TXA_22C, &pg_power[2], false);
1287 odm_efuse_one_byte_read(dm, TSSI_2GH_TXB_22C, &pg_power[3], false);
1288 odm_efuse_one_byte_read(dm, TSSI_5GL1_TXA_22C, &pg_power[4], false);
1289 odm_efuse_one_byte_read(dm, TSSI_5GL1_TXB_22C, &pg_power[5], false);
1290 odm_efuse_one_byte_read(dm, TSSI_5GL2_TXA_22C, &pg_power[6], false);
1291 odm_efuse_one_byte_read(dm, TSSI_5GL2_TXB_22C, &pg_power[7], false);
1292 odm_efuse_one_byte_read(dm, TSSI_5GM1_TXA_22C, &pg_power[8], false);
1293 odm_efuse_one_byte_read(dm, TSSI_5GM1_TXB_22C, &pg_power[9], false);
1294 odm_efuse_one_byte_read(dm, TSSI_5GM2_TXA_22C, &pg_power[10], false);
1295 odm_efuse_one_byte_read(dm, TSSI_5GM2_TXB_22C, &pg_power[11], false);
1296 odm_efuse_one_byte_read(dm, TSSI_5GH1_TXA_22C, &pg_power[12], false);
1297 odm_efuse_one_byte_read(dm, TSSI_5GH1_TXB_22C, &pg_power[13], false);
1298 odm_efuse_one_byte_read(dm, TSSI_5GH2_TXA_22C, &pg_power[14], false);
1299 odm_efuse_one_byte_read(dm, TSSI_5GH2_TXB_22C, &pg_power[15], false);
1300
1301 j = 0;
1302 for (i = 0; i < 16; i++) {
1303 if (pg_power[i] == 0xff)
1304 j++;
1305 }
1306
1307 if (j == 16) {
1308 RF_DBG(dm, DBG_RF_MP, "[kfree] 8822c tssi trim no PG\n");
1309 } else {
1310 power_trim_info->tssi_trim[0][0] = (s8)pg_power[0];
1311 power_trim_info->tssi_trim[0][1] = (s8)pg_power[1];
1312 power_trim_info->tssi_trim[1][0] = (s8)pg_power[0];
1313 power_trim_info->tssi_trim[1][1] = (s8)pg_power[1];
1314 power_trim_info->tssi_trim[2][0] = (s8)pg_power[2];
1315 power_trim_info->tssi_trim[2][1] = (s8)pg_power[3];
1316 power_trim_info->tssi_trim[3][0] = (s8)pg_power[4];
1317 power_trim_info->tssi_trim[3][1] = (s8)pg_power[5];
1318 power_trim_info->tssi_trim[4][0] = (s8)pg_power[6];
1319 power_trim_info->tssi_trim[4][1] = (s8)pg_power[7];
1320 power_trim_info->tssi_trim[5][0] = (s8)pg_power[8];
1321 power_trim_info->tssi_trim[5][1] = (s8)pg_power[9];
1322 power_trim_info->tssi_trim[6][0] = (s8)pg_power[10];
1323 power_trim_info->tssi_trim[6][1] = (s8)pg_power[11];
1324 power_trim_info->tssi_trim[7][0] = (s8)pg_power[12];
1325 power_trim_info->tssi_trim[7][1] = (s8)pg_power[13];
1326 power_trim_info->tssi_trim[8][0] = (s8)pg_power[14];
1327 power_trim_info->tssi_trim[8][1] = (s8)pg_power[15];
1328
1329 power_trim_info->flag =
1330 power_trim_info->flag | TSSI_TRIM_FLAG_ON;
1331
1332 if (power_trim_info->flag & TSSI_TRIM_FLAG_ON) {
1333 for (i = 0; i < KFREE_BAND_NUM; i++) {
1334 for (j = 0; j < 2; j++) {
1335 RF_DBG(dm, DBG_RF_MP,
1336 "[kfree] 8822c tssi_trim[%d][%d]=0x%X\n",
1337 i, j, power_trim_info->tssi_trim[i][j]);
1338 }
1339 }
1340 }
1341 }
1342 }
1343
phydm_get_tssi_trim_de_8822c(void * dm_void,u8 path)1344 s8 phydm_get_tssi_trim_de_8822c(void *dm_void, u8 path)
1345 {
1346 struct dm_struct *dm = (struct dm_struct *)dm_void;
1347 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1348
1349 u8 channel = *dm->channel, group = 0;
1350
1351 if (channel >= 1 && channel <= 3)
1352 group = 0;
1353 else if (channel >= 4 && channel <= 9)
1354 group = 1;
1355 else if (channel >= 10 && channel <= 14)
1356 group = 2;
1357 else if (channel >= 36 && channel <= 50)
1358 group = 3;
1359 else if (channel >= 52 && channel <= 64)
1360 group = 4;
1361 else if (channel >= 100 && channel <= 118)
1362 group = 5;
1363 else if (channel >= 120 && channel <= 144)
1364 group = 6;
1365 else if (channel >= 149 && channel <= 165)
1366 group = 7;
1367 else if (channel >= 167 && channel <= 177)
1368 group = 8;
1369 else {
1370 RF_DBG(dm, DBG_RF_MP, "[kfree] Channel(%d) is not exist in Group\n",
1371 channel);
1372 return 0;
1373 }
1374
1375 return power_trim_info->tssi_trim[group][path];
1376 }
1377
1378
1379
phydm_get_set_pa_bias_offset_8822c(void * dm_void)1380 void phydm_get_set_pa_bias_offset_8822c(void *dm_void)
1381 {
1382 struct dm_struct *dm = (struct dm_struct *)dm_void;
1383 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1384
1385 u8 pg_pa_bias = 0xff;
1386
1387 RF_DBG(dm, DBG_RF_MP, "======>%s\n", __func__);
1388
1389 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22C, &pg_pa_bias, false);
1390
1391 if (pg_pa_bias != 0xff) {
1392 /*2G s0*/
1393 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22C,
1394 &pg_pa_bias, false);
1395 pg_pa_bias = pg_pa_bias & 0xf;
1396
1397 RF_DBG(dm, DBG_RF_MP, "[kfree] 2G s0 pa_bias=0x%x\n", pg_pa_bias);
1398
1399 odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x0000f000, pg_pa_bias);
1400
1401 /*2G s1*/
1402 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GB_22C,
1403 &pg_pa_bias, false);
1404 pg_pa_bias = pg_pa_bias & 0xf;
1405
1406 RF_DBG(dm, DBG_RF_MP, "[kfree] 2G s1 pa_bias=0x%x\n", pg_pa_bias);
1407
1408 odm_set_rf_reg(dm, RF_PATH_B, 0x60, 0x0000f000, pg_pa_bias);
1409
1410 /*5G s0*/
1411 odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_22C,
1412 &pg_pa_bias, false);
1413 pg_pa_bias = pg_pa_bias & 0xf;
1414
1415 RF_DBG(dm, DBG_RF_MP, "[kfree] 5G s0 pa_bias=0x%x\n", pg_pa_bias);
1416
1417 odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x000f0000, pg_pa_bias);
1418
1419 /*5G s1*/
1420 odm_efuse_one_byte_read(dm, PPG_PABIAS_5GB_22C,
1421 &pg_pa_bias, false);
1422 pg_pa_bias = pg_pa_bias & 0xf;
1423
1424 RF_DBG(dm, DBG_RF_MP, "[kfree] 5G s1 pa_bias=0x%x\n", pg_pa_bias);
1425
1426 odm_set_rf_reg(dm, RF_PATH_B, 0x60, 0x000f0000, pg_pa_bias);
1427
1428 power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
1429 } else {
1430 RF_DBG(dm, DBG_RF_MP, "[kfree] 8822c tx pa bias no pg\n");
1431 }
1432
1433 }
1434
phydm_get_set_thermal_trim_offset_8812f(void * dm_void)1435 void phydm_get_set_thermal_trim_offset_8812f(void *dm_void)
1436 {
1437 struct dm_struct *dm = (struct dm_struct *)dm_void;
1438 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1439
1440 u8 pg_therm = 0xff, thermal[2] = {0};
1441
1442 odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_22C, &pg_therm, false);
1443
1444 if (pg_therm != 0xff && pg_therm != 0x0) {
1445 /*s0*/
1446 pg_therm = pg_therm & 0x1f;
1447
1448 thermal[RF_PATH_A] =
1449 ((pg_therm & 0x1) << 3) | ((pg_therm >> 1) & 0x7);
1450
1451 odm_set_rf_reg(dm, RF_PATH_A, RF_0x43, 0x000f0000, thermal[RF_PATH_A]);
1452
1453 /*s1*/
1454 odm_efuse_one_byte_read(dm, PPG_THERMAL_B_OFFSET_22C, &pg_therm, false);
1455
1456 pg_therm = pg_therm & 0x1f;
1457
1458 thermal[RF_PATH_B] = ((pg_therm & 0x1) << 3) | ((pg_therm >> 1) & 0x7);
1459
1460 odm_set_rf_reg(dm, RF_PATH_B, RF_0x43, 0x000f0000, thermal[RF_PATH_B]);
1461
1462 power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
1463
1464 }
1465
1466 RF_DBG(dm, DBG_RF_MP, "[kfree] 8812f thermal trim flag:0x%02x\n",
1467 power_trim_info->flag);
1468
1469 if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
1470 RF_DBG(dm, DBG_RF_MP, "[kfree] 8812f thermalA:%d thermalB:%d\n",
1471 thermal[RF_PATH_A],
1472 thermal[RF_PATH_B]);
1473 }
1474
phydm_set_power_trim_offset_8812f(void * dm_void)1475 void phydm_set_power_trim_offset_8812f(void *dm_void)
1476 {
1477 struct dm_struct *dm = (struct dm_struct *)dm_void;
1478 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1479 u8 e_rf_path;
1480
1481 for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)
1482 {
1483 odm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 1);
1484
1485 #if 0
1486 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x0);
1487 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1488 power_trim_info->bb_gain[0][e_rf_path]);
1489 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x1);
1490 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1491 power_trim_info->bb_gain[1][e_rf_path]);
1492 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x2);
1493 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1494 power_trim_info->bb_gain[2][e_rf_path]);
1495 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x3);
1496 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1497 power_trim_info->bb_gain[2][e_rf_path]);
1498 #endif
1499 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x4);
1500 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1501 power_trim_info->bb_gain[3][e_rf_path]);
1502 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x5);
1503 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1504 power_trim_info->bb_gain[4][e_rf_path]);
1505 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x6);
1506 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1507 power_trim_info->bb_gain[5][e_rf_path]);
1508 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x7);
1509 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1510 power_trim_info->bb_gain[6][e_rf_path]);
1511 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x8);
1512 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1513 power_trim_info->bb_gain[7][e_rf_path]);
1514 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x9);
1515 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1516 power_trim_info->bb_gain[3][e_rf_path]);
1517 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xa);
1518 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1519 power_trim_info->bb_gain[4][e_rf_path]);
1520 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xb);
1521 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1522 power_trim_info->bb_gain[5][e_rf_path]);
1523 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xc);
1524 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1525 power_trim_info->bb_gain[6][e_rf_path]);
1526 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xd);
1527 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1528 power_trim_info->bb_gain[7][e_rf_path]);
1529 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xe);
1530 odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
1531 power_trim_info->bb_gain[7][e_rf_path]);
1532
1533 odm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 0);
1534 }
1535 }
1536
phydm_get_set_power_trim_offset_8812f(void * dm_void)1537 void phydm_get_set_power_trim_offset_8812f(void *dm_void)
1538 {
1539 struct dm_struct *dm = (struct dm_struct *)dm_void;
1540 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1541
1542 u8 pg_power = 0xff, i, j;
1543 u8 pg_power1 = 0, pg_power2 = 0, pg_power3 = 0;
1544 u8 pg_power4 = 0, pg_power5 = 0;
1545
1546 odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22C, &pg_power1, false);
1547 odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22C, &pg_power2, false);
1548 odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22C, &pg_power3, false);
1549 odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22C, &pg_power4, false);
1550 odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22C, &pg_power5, false);
1551
1552 if ((pg_power1 != 0xff || pg_power2 != 0xff || pg_power3 != 0xff ||
1553 pg_power4 != 0xff || pg_power5 != 0xff) &&
1554 (pg_power1 != 0x0 || pg_power2 != 0x0 || pg_power3 != 0x0 ||
1555 pg_power4 != 0x0 || pg_power5 != 0x0)) {
1556 #if 0
1557 odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_22C, &pg_power, false);
1558 if (pg_power == 0xff)
1559 pg_power = 0;
1560 power_trim_info->bb_gain[0][0] = pg_power & 0xf;
1561 power_trim_info->bb_gain[0][1] = (pg_power & 0xf0) >> 4;
1562
1563 odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_22C, &pg_power, false);
1564 if (pg_power == 0xff)
1565 pg_power = 0;
1566 power_trim_info->bb_gain[1][0] = pg_power & 0xf;
1567 power_trim_info->bb_gain[1][1] = (pg_power & 0xf0) >> 4;
1568
1569 odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_22C, &pg_power, false);
1570 if (pg_power == 0xff)
1571 pg_power = 0;
1572 power_trim_info->bb_gain[2][0] = pg_power & 0xf;
1573 power_trim_info->bb_gain[2][1] = (pg_power & 0xf0) >> 4;
1574 #endif
1575 odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22C, &pg_power, false);
1576 if (pg_power == 0xff)
1577 pg_power = 0;
1578 power_trim_info->bb_gain[3][0] = pg_power & 0x1f;
1579 odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22C, &pg_power, false);
1580 if (pg_power == 0xff)
1581 pg_power = 0;
1582 power_trim_info->bb_gain[3][1] = pg_power & 0x1f;
1583
1584 odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22C, &pg_power, false);
1585 if (pg_power == 0xff)
1586 pg_power = 0;
1587 power_trim_info->bb_gain[4][0] = pg_power & 0x1f;
1588 odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22C, &pg_power, false);
1589 if (pg_power == 0xff)
1590 pg_power = 0;
1591 power_trim_info->bb_gain[4][1] = pg_power & 0x1f;
1592
1593 odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22C, &pg_power, false);
1594 if (pg_power == 0xff)
1595 pg_power = 0;
1596 power_trim_info->bb_gain[5][0] = pg_power & 0x1f;
1597 odm_efuse_one_byte_read(dm, PPG_5GM1_TXB_22C, &pg_power, false);
1598 if (pg_power == 0xff)
1599 pg_power = 0;
1600 power_trim_info->bb_gain[5][1] = pg_power & 0x1f;
1601
1602 odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_22C, &pg_power, false);
1603 if (pg_power == 0xff)
1604 pg_power = 0;
1605 power_trim_info->bb_gain[6][0] = pg_power & 0x1f;
1606 odm_efuse_one_byte_read(dm, PPG_5GM2_TXB_22C, &pg_power, false);
1607 if (pg_power == 0xff)
1608 pg_power = 0;
1609 power_trim_info->bb_gain[6][1] = pg_power & 0x1f;
1610
1611 odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_22C, &pg_power, false);
1612 if (pg_power == 0xff)
1613 pg_power = 0;
1614 power_trim_info->bb_gain[7][0] = pg_power & 0x1f;
1615 odm_efuse_one_byte_read(dm, PPG_5GH1_TXB_22C, &pg_power, false);
1616 if (pg_power == 0xff)
1617 pg_power = 0;
1618 power_trim_info->bb_gain[7][1] = pg_power & 0x1f;
1619
1620 power_trim_info->flag =
1621 power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_5G;
1622
1623 phydm_set_power_trim_offset_8812f(dm);
1624 }
1625
1626 RF_DBG(dm, DBG_RF_MP, "[kfree] 8812f power trim flag:0x%02x\n",
1627 power_trim_info->flag);
1628
1629 if (power_trim_info->flag & KFREE_FLAG_ON) {
1630 for (i = 0; i < KFREE_BAND_NUM; i++) {
1631 for (j = 0; j < 2; j++) {
1632 RF_DBG(dm, DBG_RF_MP,
1633 "[kfree] 8812f pwr_trim->bb_gain[%d][%d]=0x%X\n",
1634 i, j, power_trim_info->bb_gain[i][j]);
1635 }
1636 }
1637 }
1638 }
1639
phydm_get_tssi_trim_offset_8812f(void * dm_void)1640 void phydm_get_tssi_trim_offset_8812f(void *dm_void)
1641 {
1642 struct dm_struct *dm = (struct dm_struct *)dm_void;
1643 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1644
1645 u8 i, j ;
1646 u8 pg_power[16] = {0};
1647
1648 #if 0
1649 odm_efuse_one_byte_read(dm, TSSI_2GM_TXA_22C, &pg_power[0], false);
1650 odm_efuse_one_byte_read(dm, TSSI_2GM_TXB_22C, &pg_power[1], false);
1651 odm_efuse_one_byte_read(dm, TSSI_2GH_TXA_22C, &pg_power[2], false);
1652 odm_efuse_one_byte_read(dm, TSSI_2GH_TXB_22C, &pg_power[3], false);
1653 #endif
1654 odm_efuse_one_byte_read(dm, TSSI_5GL1_TXA_22C, &pg_power[4], false);
1655 odm_efuse_one_byte_read(dm, TSSI_5GL1_TXB_22C, &pg_power[5], false);
1656 odm_efuse_one_byte_read(dm, TSSI_5GL2_TXA_22C, &pg_power[6], false);
1657 odm_efuse_one_byte_read(dm, TSSI_5GL2_TXB_22C, &pg_power[7], false);
1658 odm_efuse_one_byte_read(dm, TSSI_5GM1_TXA_22C, &pg_power[8], false);
1659 odm_efuse_one_byte_read(dm, TSSI_5GM1_TXB_22C, &pg_power[9], false);
1660 odm_efuse_one_byte_read(dm, TSSI_5GM2_TXA_22C, &pg_power[10], false);
1661 odm_efuse_one_byte_read(dm, TSSI_5GM2_TXB_22C, &pg_power[11], false);
1662 odm_efuse_one_byte_read(dm, TSSI_5GH1_TXA_22C, &pg_power[12], false);
1663 odm_efuse_one_byte_read(dm, TSSI_5GH1_TXB_22C, &pg_power[13], false);
1664 odm_efuse_one_byte_read(dm, TSSI_5GH2_TXA_22C, &pg_power[14], false);
1665 odm_efuse_one_byte_read(dm, TSSI_5GH2_TXB_22C, &pg_power[15], false);
1666
1667 j = 0;
1668 for (i = 4; i < 16; i++) {
1669 if (pg_power[i] == 0xff || pg_power[i] == 0x0)
1670 j++;
1671 }
1672
1673 if (j == 12) {
1674 RF_DBG(dm, DBG_RF_MP, "[kfree] 8812f tssi trim no PG\n");
1675 } else {
1676 #if 0
1677 power_trim_info->tssi_trim[0][0] = (s8)pg_power[0];
1678 power_trim_info->tssi_trim[0][1] = (s8)pg_power[1];
1679 power_trim_info->tssi_trim[1][0] = (s8)pg_power[0];
1680 power_trim_info->tssi_trim[1][1] = (s8)pg_power[1];
1681 power_trim_info->tssi_trim[2][0] = (s8)pg_power[2];
1682 power_trim_info->tssi_trim[2][1] = (s8)pg_power[3];
1683 #endif
1684 power_trim_info->tssi_trim[3][0] = (s8)pg_power[4];
1685 power_trim_info->tssi_trim[3][1] = (s8)pg_power[5];
1686 power_trim_info->tssi_trim[4][0] = (s8)pg_power[6];
1687 power_trim_info->tssi_trim[4][1] = (s8)pg_power[7];
1688 power_trim_info->tssi_trim[5][0] = (s8)pg_power[8];
1689 power_trim_info->tssi_trim[5][1] = (s8)pg_power[9];
1690 power_trim_info->tssi_trim[6][0] = (s8)pg_power[10];
1691 power_trim_info->tssi_trim[6][1] = (s8)pg_power[11];
1692 power_trim_info->tssi_trim[7][0] = (s8)pg_power[12];
1693 power_trim_info->tssi_trim[7][1] = (s8)pg_power[13];
1694 power_trim_info->tssi_trim[8][0] = (s8)pg_power[14];
1695 power_trim_info->tssi_trim[8][1] = (s8)pg_power[15];
1696
1697 power_trim_info->flag =
1698 power_trim_info->flag | TSSI_TRIM_FLAG_ON;
1699
1700 if (power_trim_info->flag & TSSI_TRIM_FLAG_ON) {
1701 for (i = 0; i < KFREE_BAND_NUM; i++) {
1702 for (j = 0; j < 2; j++) {
1703 RF_DBG(dm, DBG_RF_MP,
1704 "[kfree] 8812f tssi_trim[%d][%d]=0x%X\n",
1705 i, j, power_trim_info->tssi_trim[i][j]);
1706 }
1707 }
1708 }
1709 }
1710 }
1711
phydm_get_tssi_trim_de_8812f(void * dm_void,u8 path)1712 s8 phydm_get_tssi_trim_de_8812f(void *dm_void, u8 path)
1713 {
1714 struct dm_struct *dm = (struct dm_struct *)dm_void;
1715 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1716
1717 u8 channel = *dm->channel, group = 0;
1718
1719 if (channel >= 1 && channel <= 3)
1720 group = 0;
1721 else if (channel >= 4 && channel <= 9)
1722 group = 1;
1723 else if (channel >= 10 && channel <= 14)
1724 group = 2;
1725 else if (channel >= 36 && channel <= 50)
1726 group = 3;
1727 else if (channel >= 52 && channel <= 64)
1728 group = 4;
1729 else if (channel >= 100 && channel <= 118)
1730 group = 5;
1731 else if (channel >= 120 && channel <= 144)
1732 group = 6;
1733 else if (channel >= 149 && channel <= 165)
1734 group = 7;
1735 else if (channel >= 167 && channel <= 177)
1736 group = 8;
1737 else {
1738 RF_DBG(dm, DBG_RF_MP, "[kfree] Channel(%d) is not exist in Group\n",
1739 channel);
1740 return 0;
1741 }
1742
1743 return power_trim_info->tssi_trim[group][path];
1744 }
1745
phydm_get_set_pa_bias_offset_8812f(void * dm_void)1746 void phydm_get_set_pa_bias_offset_8812f(void *dm_void)
1747 {
1748 struct dm_struct *dm = (struct dm_struct *)dm_void;
1749 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1750
1751 u8 pg_pa_bias = 0xff;
1752
1753 RF_DBG(dm, DBG_RF_MP, "======>%s\n", __func__);
1754
1755 odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_22C, &pg_pa_bias, false);
1756
1757 if (pg_pa_bias != 0xff && pg_pa_bias != 0x0) {
1758 #if 0
1759 /*2G s0*/
1760 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22C,
1761 &pg_pa_bias, false);
1762 pg_pa_bias = pg_pa_bias & 0xf;
1763
1764 RF_DBG(dm, DBG_RF_MP, "[kfree] 2G s0 pa_bias=0x%x\n", pg_pa_bias);
1765
1766 odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x0000f000, pg_pa_bias);
1767
1768 /*2G s1*/
1769 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GB_22C,
1770 &pg_pa_bias, false);
1771 pg_pa_bias = pg_pa_bias & 0xf;
1772
1773 RF_DBG(dm, DBG_RF_MP, "[kfree] 2G s1 pa_bias=0x%x\n", pg_pa_bias);
1774
1775 odm_set_rf_reg(dm, RF_PATH_B, 0x60, 0x0000f000, pg_pa_bias);
1776 #endif
1777
1778 /*5G s0*/
1779 odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_22C,
1780 &pg_pa_bias, false);
1781 pg_pa_bias = pg_pa_bias & 0xf;
1782
1783 RF_DBG(dm, DBG_RF_MP, "[kfree] 5G s0 pa_bias=0x%x\n", pg_pa_bias);
1784
1785 odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x000f0000, pg_pa_bias);
1786
1787 /*5G s1*/
1788 odm_efuse_one_byte_read(dm, PPG_PABIAS_5GB_22C,
1789 &pg_pa_bias, false);
1790 pg_pa_bias = pg_pa_bias & 0xf;
1791
1792 RF_DBG(dm, DBG_RF_MP, "[kfree] 5G s1 pa_bias=0x%x\n", pg_pa_bias);
1793
1794 odm_set_rf_reg(dm, RF_PATH_B, 0x60, 0x000f0000, pg_pa_bias);
1795
1796 power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
1797 } else {
1798 RF_DBG(dm, DBG_RF_MP, "[kfree] 8812f tx pa bias no pg\n");
1799 }
1800
1801 }
1802
phydm_get_thermal_trim_offset_8195b(void * dm_void)1803 void phydm_get_thermal_trim_offset_8195b(void *dm_void)
1804 {
1805 struct dm_struct *dm = (struct dm_struct *)dm_void;
1806 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1807
1808 u8 pg_therm = 0xff;
1809
1810 odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_95B, &pg_therm, false);
1811
1812 if (pg_therm != 0xff) {
1813 pg_therm = pg_therm & 0x1f;
1814 if ((pg_therm & BIT(0)) == 0)
1815 power_trim_info->thermal = (-1 * (pg_therm >> 1));
1816 else
1817 power_trim_info->thermal = (pg_therm >> 1);
1818
1819 power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
1820 }
1821
1822 RF_DBG(dm, DBG_RF_MP, "[kfree] 8195b thermal trim flag:0x%02x\n",
1823 power_trim_info->flag);
1824
1825 if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
1826 RF_DBG(dm, DBG_RF_MP, "[kfree] 8195b thermal:%d\n",
1827 power_trim_info->thermal);
1828 }
1829
phydm_set_power_trim_rf_8195b(void * dm_void)1830 void phydm_set_power_trim_rf_8195b(void *dm_void)
1831 {
1832 struct dm_struct *dm = (struct dm_struct *)dm_void;
1833 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1834
1835 RF_DBG(dm, DBG_RF_MP,
1836 "[kfree] %s:Set kfree to rf 0x33\n", __func__);
1837
1838 if (power_trim_info->flag & KFREE_FLAG_ON) {
1839 odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, BIT(19), 1);
1840
1841 if (power_trim_info->flag & KFREE_FLAG_ON_2G) {
1842 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x0);
1843 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
1844 power_trim_info->bb_gain[0][RF_PATH_A]);
1845 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x1);
1846 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
1847 power_trim_info->bb_gain[1][RF_PATH_A]);
1848 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x2);
1849 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
1850 power_trim_info->bb_gain[2][RF_PATH_A]);
1851 }
1852
1853 if (power_trim_info->flag & KFREE_FLAG_ON_5G) {
1854 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x4);
1855 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
1856 power_trim_info->bb_gain[3][RF_PATH_A]);
1857 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x5);
1858 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
1859 power_trim_info->bb_gain[4][RF_PATH_A]);
1860 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x6);
1861 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
1862 power_trim_info->bb_gain[5][RF_PATH_A]);
1863 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x7);
1864 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
1865 power_trim_info->bb_gain[6][RF_PATH_A]);
1866 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x8);
1867 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
1868 power_trim_info->bb_gain[7][RF_PATH_A]);
1869 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xe);
1870 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
1871 power_trim_info->bb_gain[7][RF_PATH_A]);
1872 }
1873
1874 odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, BIT(19), 0);
1875 }
1876
1877 }
1878
phydm_get_set_power_trim_offset_8195b(void * dm_void)1879 void phydm_get_set_power_trim_offset_8195b(void *dm_void)
1880 {
1881 struct dm_struct *dm = (struct dm_struct *)dm_void;
1882 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1883
1884 u8 pg_power = 0xff, i, j;
1885
1886 odm_efuse_one_byte_read(dm, PPG_2GL_TXA_95B, &pg_power, false);
1887
1888 if (pg_power != 0xff) {
1889 odm_efuse_one_byte_read(dm, PPG_2GL_TXA_95B, &pg_power, false);
1890 power_trim_info->bb_gain[0][0] = pg_power & 0xf;
1891
1892 odm_efuse_one_byte_read(dm, PPG_2GM_TXA_95B, &pg_power, false);
1893 power_trim_info->bb_gain[1][0] = pg_power & 0xf;
1894
1895 odm_efuse_one_byte_read(dm, PPG_2GH_TXA_95B, &pg_power, false);
1896 power_trim_info->bb_gain[2][0] = pg_power & 0xf;
1897
1898 power_trim_info->flag =
1899 power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G;
1900 }
1901
1902 pg_power = 0xff;
1903
1904 odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_95B, &pg_power, false);
1905
1906 if (pg_power != 0xff) {
1907 odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_95B, &pg_power, false);
1908 power_trim_info->bb_gain[3][0] = pg_power & 0x1f;
1909
1910 odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_95B, &pg_power, false);
1911 power_trim_info->bb_gain[4][0] = pg_power & 0x1f;
1912
1913 odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_95B, &pg_power, false);
1914 power_trim_info->bb_gain[5][0] = pg_power & 0x1f;
1915
1916 odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_95B, &pg_power, false);
1917 power_trim_info->bb_gain[6][0] = pg_power & 0x1f;
1918
1919 odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_95B, &pg_power, false);
1920 power_trim_info->bb_gain[7][0] = pg_power & 0x1f;
1921
1922 power_trim_info->flag =
1923 power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_5G;
1924 }
1925
1926 phydm_set_power_trim_rf_8195b(dm);
1927
1928 RF_DBG(dm, DBG_RF_MP, "[kfree] 8195b power trim flag:0x%02x\n",
1929 power_trim_info->flag);
1930
1931 if (power_trim_info->flag & KFREE_FLAG_ON) {
1932 for (i = 0; i < KFREE_BAND_NUM; i++) {
1933 for (j = 0; j < 1; j++) {
1934 RF_DBG(dm, DBG_RF_MP,
1935 "[kfree] 8195b pwr_trim->bb_gain[%d][%d]=0x%X\n",
1936 i, j, power_trim_info->bb_gain[i][j]);
1937 }
1938 }
1939 }
1940 }
1941
phydm_get_set_pa_bias_offset_8195b(void * dm_void)1942 void phydm_get_set_pa_bias_offset_8195b(void *dm_void)
1943 {
1944 struct dm_struct *dm = (struct dm_struct *)dm_void;
1945 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1946
1947 u8 pg_pa_bias = 0xff;
1948
1949 RF_DBG(dm, DBG_RF_MP, "======>%s\n", __func__);
1950
1951 /*2G*/
1952 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_95B, &pg_pa_bias, false);
1953
1954 if (pg_pa_bias != 0xff) {
1955 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_95B,
1956 &pg_pa_bias, false);
1957 pg_pa_bias = pg_pa_bias & 0xf;
1958
1959 RF_DBG(dm, DBG_RF_MP, "[kfree] 2G pa_bias=0x%x\n", pg_pa_bias);
1960
1961 odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x0000f000, pg_pa_bias);
1962 } else {
1963 RF_DBG(dm, DBG_RF_MP, "[kfree] 8195b 2G tx pa bias no pg\n");
1964 }
1965
1966 /*5G*/
1967 pg_pa_bias = 0xff;
1968
1969 odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_95B, &pg_pa_bias, false);
1970
1971 if (pg_pa_bias != 0xff) {
1972 odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_95B,
1973 &pg_pa_bias, false);
1974 pg_pa_bias = pg_pa_bias & 0xf;
1975
1976 RF_DBG(dm, DBG_RF_MP, "[kfree] 5G pa_bias=0x%x\n", pg_pa_bias);
1977
1978 odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x000f0000, pg_pa_bias);
1979
1980 power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
1981 } else {
1982 RF_DBG(dm, DBG_RF_MP, "[kfree] 8195b 5G tx pa bias no pg\n");
1983 }
1984 }
1985
phydm_get_thermal_trim_offset_8721d(void * dm_void)1986 void phydm_get_thermal_trim_offset_8721d(void *dm_void)
1987 {
1988 struct dm_struct *dm = (struct dm_struct *)dm_void;
1989 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
1990
1991 u8 pg_therm = 0xff;
1992
1993 odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_8721D, &pg_therm, false);
1994
1995 if (pg_therm != 0xff) {
1996 pg_therm = pg_therm & 0x1f;
1997 if ((pg_therm & BIT(0)) == 0)
1998 power_trim_info->thermal = (-1 * (pg_therm >> 1));
1999 else
2000 power_trim_info->thermal = (pg_therm >> 1);
2001
2002 power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
2003 }
2004
2005 RF_DBG(dm, DBG_RF_MP, "[kfree] 8721d thermal trim flag:0x%02x\n",
2006 power_trim_info->flag);
2007
2008 if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
2009 RF_DBG(dm, DBG_RF_MP, "[kfree] 8721d thermal:%d\n",
2010 power_trim_info->thermal);
2011 }
2012
phydm_set_power_trim_rf_8721d(void * dm_void)2013 void phydm_set_power_trim_rf_8721d(void *dm_void)
2014 {
2015 struct dm_struct *dm = (struct dm_struct *)dm_void;
2016 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2017
2018 RF_DBG(dm, DBG_RF_MP, "[kfree] %s:Set kfree to rf 0x33\n", __func__);
2019
2020 odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, BIT(19), 1);
2021
2022 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x0);
2023 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
2024 power_trim_info->bb_gain[0][RF_PATH_A]);
2025 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x1);
2026 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
2027 power_trim_info->bb_gain[1][RF_PATH_A]);
2028 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x2);
2029 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
2030 power_trim_info->bb_gain[2][RF_PATH_A]);
2031 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x3);
2032 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
2033 power_trim_info->bb_gain[2][RF_PATH_A]);
2034 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x4);
2035 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
2036 power_trim_info->bb_gain[3][RF_PATH_A]);
2037 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x5);
2038 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
2039 power_trim_info->bb_gain[4][RF_PATH_A]);
2040 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x6);
2041 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
2042 power_trim_info->bb_gain[5][RF_PATH_A]);
2043 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x7);
2044 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
2045 power_trim_info->bb_gain[6][RF_PATH_A]);
2046 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x8);
2047 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
2048 power_trim_info->bb_gain[7][RF_PATH_A]);
2049 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x9);
2050 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
2051 power_trim_info->bb_gain[3][RF_PATH_A]);
2052 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xa);
2053 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
2054 power_trim_info->bb_gain[4][RF_PATH_A]);
2055 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xb);
2056 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
2057 power_trim_info->bb_gain[5][RF_PATH_A]);
2058 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xc);
2059 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
2060 power_trim_info->bb_gain[6][RF_PATH_A]);
2061 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xd);
2062 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
2063 power_trim_info->bb_gain[7][RF_PATH_A]);
2064 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xe);
2065 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
2066 power_trim_info->bb_gain[7][RF_PATH_A]);
2067
2068 odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, BIT(19), 0);
2069 }
2070
phydm_get_set_power_trim_offset_8721d(void * dm_void)2071 void phydm_get_set_power_trim_offset_8721d(void *dm_void)
2072 {
2073 struct dm_struct *dm = (struct dm_struct *)dm_void;
2074 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2075
2076 u8 pg_power = 0xff, i, j;
2077 u8 pg_power1, pg_power2, pg_power3, pg_power4, pg_power5, pg_power6;
2078
2079 odm_efuse_one_byte_read(dm, PPG_2G_TXA_8721D, &pg_power1, false);
2080 odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_8721D, &pg_power2, false);
2081 odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_8721D, &pg_power3, false);
2082 odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_8721D, &pg_power4, false);
2083 odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_8721D, &pg_power5, false);
2084 odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_8721D, &pg_power6, false);
2085
2086 if (pg_power1 != 0xff || pg_power2 != 0xff || pg_power3 != 0xff ||
2087 pg_power4 != 0xff || pg_power5 != 0xff || pg_power6 != 0xff) {
2088 odm_efuse_one_byte_read(dm, PPG_2G_TXA_8721D, &pg_power, false);
2089 if (pg_power == 0xff)
2090 pg_power = 0;
2091 power_trim_info->bb_gain[0][0] = pg_power & 0xf;
2092 power_trim_info->bb_gain[1][0] = pg_power & 0xf;
2093 power_trim_info->bb_gain[2][0] = pg_power & 0xf;
2094
2095 odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_8721D,
2096 &pg_power, false);
2097 if (pg_power == 0xff)
2098 pg_power = 0;
2099 power_trim_info->bb_gain[3][0] = pg_power & 0x1f;
2100
2101 odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_8721D,
2102 &pg_power, false);
2103 if (pg_power == 0xff)
2104 pg_power = 0;
2105 power_trim_info->bb_gain[4][0] = pg_power & 0x1f;
2106
2107 odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_8721D,
2108 &pg_power, false);
2109 if (pg_power == 0xff)
2110 pg_power = 0;
2111 power_trim_info->bb_gain[5][0] = pg_power & 0x1f;
2112
2113 odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_8721D,
2114 &pg_power, false);
2115 if (pg_power == 0xff)
2116 pg_power = 0;
2117 power_trim_info->bb_gain[6][0] = pg_power & 0x1f;
2118
2119 odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_8721D,
2120 &pg_power, false);
2121 if (pg_power == 0xff)
2122 pg_power = 0;
2123 power_trim_info->bb_gain[7][0] = pg_power & 0x1f;
2124
2125 power_trim_info->flag =
2126 power_trim_info->flag | KFREE_FLAG_ON |
2127 KFREE_FLAG_ON_2G |
2128 KFREE_FLAG_ON_5G;
2129
2130 phydm_set_power_trim_rf_8721d(dm);
2131 }
2132
2133 RF_DBG(dm, DBG_RF_MP, "[kfree] 8721d power trim flag:0x%02x\n",
2134 power_trim_info->flag);
2135
2136 if (power_trim_info->flag & KFREE_FLAG_ON) {
2137 for (i = 0; i < KFREE_BAND_NUM; i++) {
2138 for (j = 0; j < 1; j++) {
2139 RF_DBG(dm, DBG_RF_MP,
2140 "[kfree] 8721d pwr_trim->bb_gain[%d][%d]=0x%X\n",
2141 i, j, power_trim_info->bb_gain[i][j]);
2142 }
2143 }
2144 }
2145 }
2146
phydm_get_set_pa_bias_offset_8721d(void * dm_void)2147 void phydm_get_set_pa_bias_offset_8721d(void *dm_void)
2148 {
2149 #if 0
2150 struct dm_struct *dm = (struct dm_struct *)dm_void;
2151 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2152
2153 u8 pg_pa_bias = 0xff;
2154
2155 RF_DBG(dm, DBG_RF_MP, "======>%s\n", __func__);
2156
2157 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_95B, &pg_pa_bias, false);
2158
2159 if (pg_pa_bias != 0xff) {
2160 /*2G*/
2161 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_95B,
2162 &pg_pa_bias, false);
2163 pg_pa_bias = pg_pa_bias & 0xf;
2164
2165 RF_DBG(dm, DBG_RF_MP, "[kfree] 2G pa_bias=0x%x\n", pg_pa_bias);
2166
2167 odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x0000f000, pg_pa_bias);
2168
2169 /*5G*/
2170 odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_95B,
2171 &pg_pa_bias, false);
2172 pg_pa_bias = pg_pa_bias & 0xf;
2173
2174 RF_DBG(dm, DBG_RF_MP, "[kfree] 5G pa_bias=0x%x\n", pg_pa_bias);
2175
2176 odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x000f0000, pg_pa_bias);
2177
2178 power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
2179 } else {
2180 RF_DBG(dm, DBG_RF_MP, "[kfree] 8721d tx pa bias no pg\n");
2181 }
2182 #endif
2183 }
2184
phydm_get_thermal_trim_offset_8197g(void * dm_void)2185 void phydm_get_thermal_trim_offset_8197g(void *dm_void)
2186 {
2187 struct dm_struct *dm = (struct dm_struct *)dm_void;
2188 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2189
2190 u8 pg_therm = 0xff, i;
2191
2192 odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_97G, &pg_therm, false);
2193
2194 if (pg_therm != 0x0) {
2195 for (i = 0; i < 2; i++) {
2196 if (i == 0)
2197 odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_97G, &pg_therm, false);
2198 else if (i == 1)
2199 odm_efuse_one_byte_read(dm, PPG_THERMAL_B_OFFSET_97G, &pg_therm, false);
2200
2201 RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g Efuse thermal S%d:0x%x\n", i, pg_therm);
2202
2203 pg_therm = pg_therm & 0x1f;
2204 if ((pg_therm & BIT(0)) == 0)
2205 power_trim_info->multi_thermal[i] = (-1 * (pg_therm >> 1));
2206 else
2207 power_trim_info->multi_thermal[i] = (pg_therm >> 1);
2208 }
2209
2210 power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
2211 }
2212
2213 RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g thermal trim flag:0x%02x\n",
2214 power_trim_info->flag);
2215
2216 for (i = 0; i < 2; i++) {
2217 if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
2218 RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g thermal S%d:%d\n",
2219 i ,power_trim_info->multi_thermal[i]);
2220 }
2221 }
2222
phydm_set_power_trim_offset_8197g(void * dm_void)2223 void phydm_set_power_trim_offset_8197g(void *dm_void)
2224 {
2225 struct dm_struct *dm = (struct dm_struct *)dm_void;
2226 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2227 u8 e_rf_path;
2228
2229 for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)
2230 {
2231 odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1);
2232
2233 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 0);
2234 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F,
2235 power_trim_info->bb_gain[0][e_rf_path]);
2236 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 1);
2237 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F,
2238 power_trim_info->bb_gain[0][e_rf_path]);
2239 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 2);
2240 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F,
2241 power_trim_info->bb_gain[1][e_rf_path]);
2242 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 3);
2243 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F,
2244 power_trim_info->bb_gain[1][e_rf_path]);
2245 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 4);
2246 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F,
2247 power_trim_info->bb_gain[2][e_rf_path]);
2248 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 5);
2249 odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F,
2250 power_trim_info->bb_gain[2][e_rf_path]);
2251
2252 odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0);
2253 }
2254
2255 }
2256
phydm_get_set_power_trim_offset_8197g(void * dm_void)2257 void phydm_get_set_power_trim_offset_8197g(void *dm_void)
2258 {
2259 struct dm_struct *dm = (struct dm_struct *)dm_void;
2260 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2261
2262 u8 pg_power = 0, i, j;
2263
2264 odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_97G, &pg_power, false);
2265
2266 if (pg_power != 0) {
2267 power_trim_info->bb_gain[0][0] = pg_power & 0xf;
2268 power_trim_info->bb_gain[0][1] = (pg_power & 0xf0) >> 4;
2269
2270 odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_97G, &pg_power, false);
2271 power_trim_info->bb_gain[1][0] = pg_power & 0xf;
2272 power_trim_info->bb_gain[1][1] = (pg_power & 0xf0) >> 4;
2273
2274 odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_97G, &pg_power, false);
2275 power_trim_info->bb_gain[2][0] = pg_power & 0xf;
2276 power_trim_info->bb_gain[2][1] = (pg_power & 0xf0) >> 4;
2277
2278 phydm_set_power_trim_offset_8197g(dm);
2279
2280 power_trim_info->flag =
2281 power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G;
2282 }
2283
2284 RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g power trim flag:0x%02x\n",
2285 power_trim_info->flag);
2286
2287 if (power_trim_info->flag & KFREE_FLAG_ON) {
2288 for (i = 0; i < KFREE_BAND_NUM; i++) {
2289 for (j = 0; j < MAX_RF_PATH; j++) {
2290 RF_DBG(dm, DBG_RF_MP,
2291 "[kfree] 8197g pwr_trim->bb_gain[%d][%d]=0x%X\n",
2292 i, j, power_trim_info->bb_gain[i][j]);
2293 }
2294 }
2295 }
2296 }
2297
phydm_get_tssi_trim_offset_8197g(void * dm_void)2298 void phydm_get_tssi_trim_offset_8197g(void *dm_void)
2299 {
2300 struct dm_struct *dm = (struct dm_struct *)dm_void;
2301 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2302
2303 u8 i, j;
2304 u8 pg_power[4] = {0};
2305
2306 odm_efuse_one_byte_read(dm, TSSI_2GL_TXA_97G, &pg_power[0], false);
2307 odm_efuse_one_byte_read(dm, TSSI_2GL_TXB_97G, &pg_power[1], false);
2308 odm_efuse_one_byte_read(dm, TSSI_2GH_TXA_97G, &pg_power[2], false);
2309 odm_efuse_one_byte_read(dm, TSSI_2GH_TXB_97G, &pg_power[3], false);
2310
2311 j = 0;
2312 for (i = 0; i < 4; i++) {
2313 if (pg_power[i] == 0x0)
2314 j++;
2315 }
2316
2317 if (j == 4) {
2318 RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g tssi trim no PG\n");
2319 } else {
2320 power_trim_info->tssi_trim[0][0] = (s8)pg_power[0];
2321 power_trim_info->tssi_trim[0][1] = (s8)pg_power[1];
2322 power_trim_info->tssi_trim[1][0] = (s8)pg_power[0];
2323 power_trim_info->tssi_trim[1][1] = (s8)pg_power[1];
2324 power_trim_info->tssi_trim[2][0] = (s8)pg_power[2];
2325 power_trim_info->tssi_trim[2][1] = (s8)pg_power[3];
2326
2327 power_trim_info->flag =
2328 power_trim_info->flag | TSSI_TRIM_FLAG_ON;
2329
2330 for (i = 0; i < KFREE_BAND_NUM; i++) {
2331 for (j = 0; j < MAX_PATH_NUM_8197G; j++) {
2332 RF_DBG(dm, DBG_RF_MP,
2333 "[kfree] 8197g tssi_trim[%d][%d]=0x%X\n",
2334 i, j, power_trim_info->tssi_trim[i][j]);
2335 }
2336 }
2337 }
2338 }
2339
phydm_get_tssi_trim_de_8197g(void * dm_void,u8 path)2340 s8 phydm_get_tssi_trim_de_8197g(void *dm_void, u8 path)
2341 {
2342 struct dm_struct *dm = (struct dm_struct *)dm_void;
2343 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2344
2345 u8 channel = *dm->channel, group = 0;
2346
2347 if (channel >= 1 && channel <= 3)
2348 group = 0;
2349 else if (channel >= 4 && channel <= 9)
2350 group = 1;
2351 else if (channel >= 10 && channel <= 14)
2352 group = 2;
2353 else {
2354 RF_DBG(dm, DBG_RF_MP, "[kfree] Channel(%d) is not exist in Group\n",
2355 channel);
2356 return 0;
2357 }
2358
2359 return power_trim_info->tssi_trim[group][path];
2360 }
2361
phydm_get_set_pa_bias_offset_8197g(void * dm_void)2362 void phydm_get_set_pa_bias_offset_8197g(void *dm_void)
2363 {
2364 struct dm_struct *dm = (struct dm_struct *)dm_void;
2365 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2366
2367 u8 pg_pa_bias = 0xff, i;
2368 u8 tx_pa_bias[4] = {0};
2369
2370 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GAB_97G, &pg_pa_bias, false);
2371
2372 if (pg_pa_bias != 0x0) {
2373 /*paht ab*/
2374 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GAB_97G,
2375 &pg_pa_bias, false);
2376 tx_pa_bias[0] = pg_pa_bias & 0xf;
2377 tx_pa_bias[1] = ((pg_pa_bias & 0xf0) >> 4);
2378
2379 RF_DBG(dm, DBG_RF_MP,
2380 "[kfree] 8197g PathA_pa_bias:0x%x PathB_pa_bias:0x%x\n",
2381 tx_pa_bias[0], tx_pa_bias[1]);
2382
2383 for (i = RF_PATH_A; i < 2; i++)
2384 odm_set_rf_reg(dm, i, 0x60, 0x0000f000, tx_pa_bias[i]);
2385
2386 power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
2387 } else {
2388 RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g tx pa bias no pg\n");
2389 }
2390 }
2391
phydm_get_set_lna_offset_8197g(void * dm_void)2392 void phydm_get_set_lna_offset_8197g(void *dm_void)
2393 {
2394 struct dm_struct *dm = (struct dm_struct *)dm_void;
2395 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2396
2397 u8 pg_lna[2] = {0}, i, pg_lna_tmp = 0;
2398 u32 lna_trim_addr[2] = {0x1884, 0x4184};
2399
2400 odm_efuse_one_byte_read(dm, PPG_LNA_2GA_97G, &pg_lna_tmp, false);
2401
2402 if (pg_lna_tmp != 0) {
2403 odm_efuse_one_byte_read(dm, PPG_LNA_2GA_97G,
2404 &pg_lna[RF_PATH_A], false);
2405 power_trim_info->lna_trim[RF_PATH_A] = (s8)pg_lna[RF_PATH_A];
2406
2407 odm_efuse_one_byte_read(dm, PPG_LNA_2GB_97G,
2408 &pg_lna[RF_PATH_B], false);
2409 power_trim_info->lna_trim[RF_PATH_B] = (s8)pg_lna[RF_PATH_B];
2410
2411 for (i = RF_PATH_A; i < 2; i++) {
2412 if (odm_get_bb_reg(dm, lna_trim_addr[i], 0x00c00000) == 0x2) {
2413 odm_set_rf_reg(dm, i, 0x88, 0x00000f00, (pg_lna[i] & 0xf));
2414 RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g lna trim CG 0x%x path=%d\n", (pg_lna[i] & 0xf), i);
2415 } else if (odm_get_bb_reg(dm, lna_trim_addr[i], 0x00c00000) == 0x3) {
2416 odm_set_rf_reg(dm, i, 0x88, 0x00000f00, ((pg_lna[i] & 0xf0) >> 4));
2417 RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g lna trim CS 0x%x path=%d\n", ((pg_lna[i] & 0xf0) >> 4), i);
2418 }
2419 }
2420
2421 power_trim_info->lna_flag |= LNA_FLAG_ON;
2422 } else {
2423 RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g lna trim no pg\n");
2424 }
2425 }
2426
phydm_set_lna_trim_offset_8197g(void * dm_void,u8 path,u8 cg_cs,u8 enable)2427 void phydm_set_lna_trim_offset_8197g(void *dm_void, u8 path, u8 cg_cs, u8 enable)
2428 {
2429 struct dm_struct *dm = (struct dm_struct *)dm_void;
2430 struct odm_power_trim_data *trim = &dm->power_trim_data;
2431
2432 u8 i;
2433
2434 if (enable == 0) {
2435 for (i = RF_PATH_A; i < 2; i++) {
2436 odm_set_rf_reg(dm, i, 0x88, 0x00000f00, 0x0);
2437 RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g diversity lna trim disable\n");
2438 }
2439 return;
2440 }
2441
2442 /*cg*/
2443 if (cg_cs == 0) {
2444 odm_set_rf_reg(dm, path, 0x88, 0x00000f00, (trim->lna_trim[path] & 0xf));
2445 RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g diversity lna trim CG 0x%x path=%d\n",
2446 (trim->lna_trim[path] & 0xf), path);
2447 } else if (cg_cs == 1) { /*cs*/
2448 odm_set_rf_reg(dm, path, 0x88, 0x00000f00, ((trim->lna_trim[path] & 0xf0) >> 4));
2449 RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g diversity lna trim CS 0x%x path=%d\n",
2450 ((trim->lna_trim[path] & 0xf0) >> 4), path);
2451 }
2452 }
2453
2454
phydm_get_thermal_trim_offset_8710c(void * dm_void)2455 void phydm_get_thermal_trim_offset_8710c(void *dm_void)
2456 {
2457 struct dm_struct *dm = (struct dm_struct *)dm_void;
2458 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2459
2460 u8 pg_therm = 0;
2461
2462 odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_10C, &pg_therm, false);
2463 RF_DBG(dm, DBG_RF_MP, "[kfree] 8710c Efuse thermal:0x%x\n", pg_therm);
2464
2465 if (pg_therm != 0xff) {
2466 pg_therm = pg_therm & 0x1f;
2467 if ((pg_therm & BIT(0)) == 0)
2468 power_trim_info->thermal = (-1 * (pg_therm >> 1));
2469 else
2470 power_trim_info->thermal = (pg_therm >> 1);
2471
2472 power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
2473 }
2474
2475 RF_DBG(dm, DBG_RF_MP, "[kfree] 8710c thermal trim flag:0x%02x\n",
2476 power_trim_info->flag);
2477
2478 if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
2479 RF_DBG(dm, DBG_RF_MP, "[kfree] 8710c thermal:%d\n",
2480 power_trim_info->thermal);
2481 }
2482
phydm_set_power_trim_offset_8710c(void * dm_void)2483 void phydm_set_power_trim_offset_8710c(void *dm_void)
2484 {
2485 struct dm_struct *dm = (struct dm_struct *)dm_void;
2486 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2487
2488 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(18), 1);
2489
2490 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0);
2491 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x3f,
2492 power_trim_info->bb_gain[0][RF_PATH_A]);
2493 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 1);
2494 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x3f,
2495 power_trim_info->bb_gain[1][RF_PATH_A]);
2496 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 2);
2497 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x3f,
2498 power_trim_info->bb_gain[2][RF_PATH_A]);
2499
2500 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(18), 0);
2501 }
2502
phydm_get_set_power_trim_offset_8710c(void * dm_void)2503 void phydm_get_set_power_trim_offset_8710c(void *dm_void)
2504 {
2505 struct dm_struct *dm = (struct dm_struct *)dm_void;
2506 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2507
2508 u8 pg_power = 0, i, j;
2509
2510 odm_efuse_one_byte_read(dm, PPG_2GL_TX_10C, &pg_power, false);
2511
2512 if (pg_power != 0xff) {
2513 power_trim_info->bb_gain[0][RF_PATH_A] = pg_power & 0xf;
2514
2515 odm_efuse_one_byte_read(dm, PPG_2GM_TX_10C, &pg_power, false);
2516 power_trim_info->bb_gain[1][RF_PATH_A] = pg_power & 0xf;
2517
2518 odm_efuse_one_byte_read(dm, PPG_2GH_TX_10C, &pg_power, false);
2519 power_trim_info->bb_gain[2][RF_PATH_A] = pg_power & 0xf;
2520
2521 phydm_set_power_trim_offset_8710c(dm);
2522
2523 power_trim_info->flag =
2524 power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G;
2525 }
2526
2527 RF_DBG(dm, DBG_RF_MP, "[kfree] 8710c power trim flag:0x%02x\n",
2528 power_trim_info->flag);
2529
2530 if (power_trim_info->flag & KFREE_FLAG_ON) {
2531 for (i = 0; i < KFREE_BAND_NUM; i++) {
2532 for (j = 0; j < MAX_RF_PATH; j++) {
2533 RF_DBG(dm, DBG_RF_MP,
2534 "[kfree] 8710c pwr_trim->bb_gain[%d][%d]=0x%X\n",
2535 i, j, power_trim_info->bb_gain[i][j]);
2536 }
2537 }
2538 }
2539 }
2540
phydm_get_set_pa_bias_offset_8710c(void * dm_void)2541 void phydm_get_set_pa_bias_offset_8710c(void *dm_void)
2542 {
2543 struct dm_struct *dm = (struct dm_struct *)dm_void;
2544 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2545
2546 u8 pg_pa_bias = 0xff;
2547 u8 tx_pa_bias = 0;
2548
2549 odm_efuse_one_byte_read(dm, PPG_PABIAS_10C, &pg_pa_bias, false);
2550
2551 if (pg_pa_bias != 0xff) {
2552 tx_pa_bias = pg_pa_bias & 0xf;
2553
2554 RF_DBG(dm, DBG_RF_MP,
2555 "[kfree] 8710c PathA_pa_bias:0x%x\n", tx_pa_bias);
2556
2557 odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x0000f000, tx_pa_bias);
2558
2559 power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
2560 } else {
2561 RF_DBG(dm, DBG_RF_MP, "[kfree] 8710c tx pa bias no pg\n");
2562 }
2563 }
2564
phydm_set_power_trim_offset_8814b(void * dm_void)2565 void phydm_set_power_trim_offset_8814b(void *dm_void)
2566 {
2567 struct dm_struct *dm = (struct dm_struct *)dm_void;
2568 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2569 u8 e_rf_path;
2570
2571 for (e_rf_path = RF_PATH_A; e_rf_path < MAX_PATH_NUM_8814B; e_rf_path++)
2572 {
2573 if (power_trim_info->flag & KFREE_FLAG_ON) {
2574 odm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 1);
2575
2576 if (power_trim_info->flag & KFREE_FLAG_ON_2G) {
2577 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x0);
2578 odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
2579 power_trim_info->bb_gain[0][e_rf_path]);
2580 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x1);
2581 odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
2582 power_trim_info->bb_gain[0][e_rf_path]);
2583 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x2);
2584 odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
2585 power_trim_info->bb_gain[0][e_rf_path]);
2586 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x3);
2587 odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
2588 power_trim_info->bb_gain[0][e_rf_path]);
2589 }
2590
2591 if (power_trim_info->flag & KFREE_FLAG_ON_5G) {
2592 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x4);
2593 odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
2594 power_trim_info->bb_gain[3][e_rf_path]);
2595 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x5);
2596 odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
2597 power_trim_info->bb_gain[4][e_rf_path]);
2598 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x6);
2599 odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
2600 power_trim_info->bb_gain[5][e_rf_path]);
2601 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x7);
2602 odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
2603 power_trim_info->bb_gain[6][e_rf_path]);
2604 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x8);
2605 odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
2606 power_trim_info->bb_gain[7][e_rf_path]);
2607 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x9);
2608 odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
2609 power_trim_info->bb_gain[3][e_rf_path]);
2610 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xa);
2611 odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
2612 power_trim_info->bb_gain[4][e_rf_path]);
2613 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xb);
2614 odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
2615 power_trim_info->bb_gain[5][e_rf_path]);
2616 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xc);
2617 odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
2618 power_trim_info->bb_gain[6][e_rf_path]);
2619 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xd);
2620 odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
2621 power_trim_info->bb_gain[7][e_rf_path]);
2622 odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xe);
2623 odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
2624 power_trim_info->bb_gain[7][e_rf_path]);
2625 }
2626
2627 odm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 0);
2628 }
2629 }
2630 }
2631
phydm_get_set_power_trim_offset_8814b(void * dm_void)2632 void phydm_get_set_power_trim_offset_8814b(void *dm_void)
2633 {
2634 struct dm_struct *dm = (struct dm_struct *)dm_void;
2635 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2636
2637 u8 i, j;
2638 u8 pg_power1, pg_power2;
2639 u8 pg_power_2g[2] = {0}, pg_power_5g[20] = {0};
2640
2641 odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_14B, &pg_power_2g[0], false);
2642 odm_efuse_one_byte_read(dm, PPG_2GL_TXCD_14B, &pg_power_2g[1], false);
2643
2644 j = 0;
2645 for (i = 0; i < 2; i++) {
2646 if (pg_power_2g[i] == 0xff)
2647 j++;
2648 }
2649
2650 if (j == 2) {
2651 RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 2G power trim no PG\n");
2652 } else {
2653 power_trim_info->bb_gain[0][RF_PATH_A] = pg_power_2g[0] & 0xf;
2654 power_trim_info->bb_gain[0][RF_PATH_B] = (pg_power_2g[0] & 0xf0) >> 4;
2655
2656 power_trim_info->bb_gain[0][RF_PATH_C] = pg_power_2g[1] & 0xf;
2657 power_trim_info->bb_gain[0][RF_PATH_D] = (pg_power_2g[1] & 0xf0) >> 4;
2658
2659 power_trim_info->flag =
2660 power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G;
2661 }
2662
2663 odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_14B, &pg_power_5g[0], false);
2664 odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_14B, &pg_power_5g[1], false);
2665 odm_efuse_one_byte_read(dm, PPG_5GL1_TXC_14B, &pg_power_5g[2], false);
2666 odm_efuse_one_byte_read(dm, PPG_5GL1_TXD_14B, &pg_power_5g[3], false);
2667 odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_14B, &pg_power_5g[4], false);
2668 odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_14B, &pg_power_5g[5], false);
2669 odm_efuse_one_byte_read(dm, PPG_5GL2_TXC_14B, &pg_power_5g[6], false);
2670 odm_efuse_one_byte_read(dm, PPG_5GL2_TXD_14B, &pg_power_5g[7], false);
2671 odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_14B, &pg_power_5g[8], false);
2672 odm_efuse_one_byte_read(dm, PPG_5GM1_TXB_14B, &pg_power_5g[9], false);
2673 odm_efuse_one_byte_read(dm, PPG_5GM1_TXC_14B, &pg_power_5g[10], false);
2674 odm_efuse_one_byte_read(dm, PPG_5GM1_TXD_14B, &pg_power_5g[11], false);
2675 odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_14B, &pg_power_5g[12], false);
2676 odm_efuse_one_byte_read(dm, PPG_5GM2_TXB_14B, &pg_power_5g[13], false);
2677 odm_efuse_one_byte_read(dm, PPG_5GM2_TXC_14B, &pg_power_5g[14], false);
2678 odm_efuse_one_byte_read(dm, PPG_5GM2_TXD_14B, &pg_power_5g[15], false);
2679 odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_14B, &pg_power_5g[16], false);
2680 odm_efuse_one_byte_read(dm, PPG_5GH1_TXB_14B, &pg_power_5g[17], false);
2681 odm_efuse_one_byte_read(dm, PPG_5GH1_TXC_14B, &pg_power_5g[18], false);
2682 odm_efuse_one_byte_read(dm, PPG_5GH1_TXD_14B, &pg_power_5g[19], false);
2683
2684 j = 0;
2685 for (i = 0; i < 20; i++) {
2686 if (pg_power_5g[i] == 0xff)
2687 j++;
2688 }
2689
2690 if (j == 20) {
2691 RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 5G power trim no PG\n");
2692 } else {
2693 power_trim_info->bb_gain[3][RF_PATH_A] = pg_power_5g[0] & 0x1f;
2694 power_trim_info->bb_gain[3][RF_PATH_B] = pg_power_5g[1] & 0x1f;
2695 power_trim_info->bb_gain[3][RF_PATH_C] = pg_power_5g[2] & 0x1f;
2696 power_trim_info->bb_gain[3][RF_PATH_D] = pg_power_5g[3] & 0x1f;
2697
2698 power_trim_info->bb_gain[4][RF_PATH_A] = pg_power_5g[4] & 0x1f;
2699 power_trim_info->bb_gain[4][RF_PATH_B] = pg_power_5g[5] & 0x1f;
2700 power_trim_info->bb_gain[4][RF_PATH_C] = pg_power_5g[6] & 0x1f;
2701 power_trim_info->bb_gain[4][RF_PATH_D] = pg_power_5g[7] & 0x1f;
2702
2703 power_trim_info->bb_gain[5][RF_PATH_A] = pg_power_5g[8] & 0x1f;
2704 power_trim_info->bb_gain[5][RF_PATH_B] = pg_power_5g[9] & 0x1f;
2705 power_trim_info->bb_gain[5][RF_PATH_C] = pg_power_5g[10] & 0x1f;
2706 power_trim_info->bb_gain[5][RF_PATH_D] = pg_power_5g[11] & 0x1f;
2707
2708 power_trim_info->bb_gain[6][RF_PATH_A] = pg_power_5g[12] & 0x1f;
2709 power_trim_info->bb_gain[6][RF_PATH_B] = pg_power_5g[13] & 0x1f;
2710 power_trim_info->bb_gain[6][RF_PATH_C] = pg_power_5g[14] & 0x1f;
2711 power_trim_info->bb_gain[6][RF_PATH_D] = pg_power_5g[15] & 0x1f;
2712
2713 power_trim_info->bb_gain[7][RF_PATH_A] = pg_power_5g[16] & 0x1f;
2714 power_trim_info->bb_gain[7][RF_PATH_B] = pg_power_5g[17] & 0x1f;
2715 power_trim_info->bb_gain[7][RF_PATH_C] = pg_power_5g[18] & 0x1f;
2716 power_trim_info->bb_gain[7][RF_PATH_D] = pg_power_5g[19] & 0x1f;
2717
2718 power_trim_info->flag =
2719 power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_5G;
2720
2721 }
2722
2723 phydm_set_power_trim_offset_8814b(dm);
2724
2725 RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b power trim flag:0x%02x\n",
2726 power_trim_info->flag);
2727
2728 if (power_trim_info->flag & KFREE_FLAG_ON) {
2729 for (i = 0; i < KFREE_BAND_NUM; i++) {
2730 for (j = 0; j < MAX_PATH_NUM_8814B; j++) {
2731 RF_DBG(dm, DBG_RF_MP,
2732 "[kfree] 8814b pwr_trim->bb_gain[%d][%d]=0x%X\n",
2733 i, j, power_trim_info->bb_gain[i][j]);
2734 }
2735 }
2736 }
2737 }
2738
phydm_get_tssi_trim_offset_8814b(void * dm_void)2739 void phydm_get_tssi_trim_offset_8814b(void *dm_void)
2740 {
2741 struct dm_struct *dm = (struct dm_struct *)dm_void;
2742 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2743
2744 u8 i, j;
2745 u8 tssi_trim_2g[8] = {0}, tssi_trim_5g[24] = {0};
2746
2747 odm_efuse_one_byte_read(dm, TSSI_2GM_TXA_14B, &tssi_trim_2g[0], false);
2748 odm_efuse_one_byte_read(dm, TSSI_2GM_TXB_14B, &tssi_trim_2g[1], false);
2749 odm_efuse_one_byte_read(dm, TSSI_2GM_TXC_14B, &tssi_trim_2g[2], false);
2750 odm_efuse_one_byte_read(dm, TSSI_2GM_TXD_14B, &tssi_trim_2g[3], false);
2751 odm_efuse_one_byte_read(dm, TSSI_2GH_TXA_14B, &tssi_trim_2g[4], false);
2752 odm_efuse_one_byte_read(dm, TSSI_2GH_TXB_14B, &tssi_trim_2g[5], false);
2753 odm_efuse_one_byte_read(dm, TSSI_2GH_TXC_14B, &tssi_trim_2g[6], false);
2754 odm_efuse_one_byte_read(dm, TSSI_2GH_TXD_14B, &tssi_trim_2g[7], false);
2755
2756 j = 0;
2757 for (i = 0; i < 8; i++) {
2758 if (tssi_trim_2g[i] == 0xff)
2759 j++;
2760 }
2761
2762 if (j == 8) {
2763 RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 2g tssi trim no PG\n");
2764 } else {
2765 power_trim_info->tssi_trim[0][RF_PATH_A] = (s8)tssi_trim_2g[0];
2766 power_trim_info->tssi_trim[0][RF_PATH_B] = (s8)tssi_trim_2g[1];
2767 power_trim_info->tssi_trim[0][RF_PATH_C] = (s8)tssi_trim_2g[2];
2768 power_trim_info->tssi_trim[0][RF_PATH_D] = (s8)tssi_trim_2g[3];
2769 power_trim_info->tssi_trim[1][RF_PATH_A] = (s8)tssi_trim_2g[0];
2770 power_trim_info->tssi_trim[1][RF_PATH_B] = (s8)tssi_trim_2g[1];
2771 power_trim_info->tssi_trim[1][RF_PATH_C] = (s8)tssi_trim_2g[2];
2772 power_trim_info->tssi_trim[1][RF_PATH_D] = (s8)tssi_trim_2g[3];
2773 power_trim_info->tssi_trim[2][RF_PATH_A] = (s8)tssi_trim_2g[4];
2774 power_trim_info->tssi_trim[2][RF_PATH_B] = (s8)tssi_trim_2g[5];
2775 power_trim_info->tssi_trim[2][RF_PATH_C] = (s8)tssi_trim_2g[6];
2776 power_trim_info->tssi_trim[2][RF_PATH_D] = (s8)tssi_trim_2g[7];
2777
2778 power_trim_info->flag =
2779 power_trim_info->flag | TSSI_TRIM_FLAG_ON | KFREE_FLAG_ON_2G;
2780
2781 for (i = 0; i < KFREE_BAND_NUM; i++) {
2782 for (j = 0; j < MAX_PATH_NUM_8814B; j++) {
2783 RF_DBG(dm, DBG_RF_MP,
2784 "[kfree] 8814b 2g tssi_trim[%d][%d]=0x%X\n",
2785 i, j, power_trim_info->tssi_trim[i][j]);
2786 }
2787 }
2788 }
2789
2790 odm_efuse_one_byte_read(dm, TSSI_5GL1_TXA_14B, &tssi_trim_5g[0], false);
2791 odm_efuse_one_byte_read(dm, TSSI_5GL1_TXB_14B, &tssi_trim_5g[1], false);
2792 odm_efuse_one_byte_read(dm, TSSI_5GL1_TXC_14B, &tssi_trim_5g[2], false);
2793 odm_efuse_one_byte_read(dm, TSSI_5GL1_TXD_14B, &tssi_trim_5g[3], false);
2794 odm_efuse_one_byte_read(dm, TSSI_5GL2_TXA_14B, &tssi_trim_5g[4], false);
2795 odm_efuse_one_byte_read(dm, TSSI_5GL2_TXB_14B, &tssi_trim_5g[5], false);
2796 odm_efuse_one_byte_read(dm, TSSI_5GL2_TXC_14B, &tssi_trim_5g[6], false);
2797 odm_efuse_one_byte_read(dm, TSSI_5GL2_TXD_14B, &tssi_trim_5g[7], false);
2798 odm_efuse_one_byte_read(dm, TSSI_5GM1_TXA_14B, &tssi_trim_5g[8], false);
2799 odm_efuse_one_byte_read(dm, TSSI_5GM1_TXB_14B, &tssi_trim_5g[9], false);
2800 odm_efuse_one_byte_read(dm, TSSI_5GM1_TXC_14B, &tssi_trim_5g[10], false);
2801 odm_efuse_one_byte_read(dm, TSSI_5GM1_TXD_14B, &tssi_trim_5g[11], false);
2802 odm_efuse_one_byte_read(dm, TSSI_5GM2_TXA_14B, &tssi_trim_5g[12], false);
2803 odm_efuse_one_byte_read(dm, TSSI_5GM2_TXB_14B, &tssi_trim_5g[13], false);
2804 odm_efuse_one_byte_read(dm, TSSI_5GM2_TXC_14B, &tssi_trim_5g[14], false);
2805 odm_efuse_one_byte_read(dm, TSSI_5GM2_TXD_14B, &tssi_trim_5g[15], false);
2806 odm_efuse_one_byte_read(dm, TSSI_5GH1_TXA_14B, &tssi_trim_5g[16], false);
2807 odm_efuse_one_byte_read(dm, TSSI_5GH1_TXB_14B, &tssi_trim_5g[17], false);
2808 odm_efuse_one_byte_read(dm, TSSI_5GH1_TXC_14B, &tssi_trim_5g[18], false);
2809 odm_efuse_one_byte_read(dm, TSSI_5GH1_TXD_14B, &tssi_trim_5g[19], false);
2810 odm_efuse_one_byte_read(dm, TSSI_5GH2_TXA_14B, &tssi_trim_5g[20], false);
2811 odm_efuse_one_byte_read(dm, TSSI_5GH2_TXB_14B, &tssi_trim_5g[21], false);
2812 odm_efuse_one_byte_read(dm, TSSI_5GH2_TXC_14B, &tssi_trim_5g[22], false);
2813 odm_efuse_one_byte_read(dm, TSSI_5GH2_TXD_14B, &tssi_trim_5g[23], false);
2814
2815 j = 0;
2816 for (i = 0; i < 24; i++) {
2817 if (tssi_trim_5g[i] == 0xff)
2818 j++;
2819 }
2820
2821 if (j == 24) {
2822 RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 5g tssi trim no PG\n");
2823 } else {
2824 power_trim_info->tssi_trim[3][RF_PATH_A] = (s8)tssi_trim_5g[0];
2825 power_trim_info->tssi_trim[3][RF_PATH_B] = (s8)tssi_trim_5g[1];
2826 power_trim_info->tssi_trim[3][RF_PATH_C] = (s8)tssi_trim_5g[2];
2827 power_trim_info->tssi_trim[3][RF_PATH_D] = (s8)tssi_trim_5g[3];
2828 power_trim_info->tssi_trim[4][RF_PATH_A] = (s8)tssi_trim_5g[4];
2829 power_trim_info->tssi_trim[4][RF_PATH_B] = (s8)tssi_trim_5g[5];
2830 power_trim_info->tssi_trim[4][RF_PATH_C] = (s8)tssi_trim_5g[6];
2831 power_trim_info->tssi_trim[4][RF_PATH_D] = (s8)tssi_trim_5g[7];
2832 power_trim_info->tssi_trim[5][RF_PATH_A] = (s8)tssi_trim_5g[8];
2833 power_trim_info->tssi_trim[5][RF_PATH_B] = (s8)tssi_trim_5g[9];
2834 power_trim_info->tssi_trim[5][RF_PATH_C] = (s8)tssi_trim_5g[10];
2835 power_trim_info->tssi_trim[5][RF_PATH_D] = (s8)tssi_trim_5g[11];
2836 power_trim_info->tssi_trim[6][RF_PATH_A] = (s8)tssi_trim_5g[12];
2837 power_trim_info->tssi_trim[6][RF_PATH_B] = (s8)tssi_trim_5g[13];
2838 power_trim_info->tssi_trim[6][RF_PATH_C] = (s8)tssi_trim_5g[14];
2839 power_trim_info->tssi_trim[6][RF_PATH_D] = (s8)tssi_trim_5g[15];
2840 power_trim_info->tssi_trim[7][RF_PATH_A] = (s8)tssi_trim_5g[16];
2841 power_trim_info->tssi_trim[7][RF_PATH_B] = (s8)tssi_trim_5g[17];
2842 power_trim_info->tssi_trim[7][RF_PATH_C] = (s8)tssi_trim_5g[18];
2843 power_trim_info->tssi_trim[7][RF_PATH_D] = (s8)tssi_trim_5g[19];
2844 power_trim_info->tssi_trim[8][RF_PATH_A] = (s8)tssi_trim_5g[20];
2845 power_trim_info->tssi_trim[8][RF_PATH_B] = (s8)tssi_trim_5g[21];
2846 power_trim_info->tssi_trim[8][RF_PATH_C] = (s8)tssi_trim_5g[22];
2847 power_trim_info->tssi_trim[8][RF_PATH_D] = (s8)tssi_trim_5g[23];
2848
2849 power_trim_info->flag =
2850 power_trim_info->flag | TSSI_TRIM_FLAG_ON | KFREE_FLAG_ON_5G;
2851
2852 for (i = 0; i < KFREE_BAND_NUM; i++) {
2853 for (j = 0; j < MAX_PATH_NUM_8814B; j++) {
2854 RF_DBG(dm, DBG_RF_MP,
2855 "[kfree] 8814b 5g tssi_trim[%d][%d]=0x%X\n",
2856 i, j, power_trim_info->tssi_trim[i][j]);
2857 }
2858 }
2859 }
2860 }
2861
phydm_get_tssi_trim_de_8814b(void * dm_void,u8 path)2862 s8 phydm_get_tssi_trim_de_8814b(void *dm_void, u8 path)
2863 {
2864 struct dm_struct *dm = (struct dm_struct *)dm_void;
2865 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2866
2867 u8 channel = *dm->channel, group = 0;
2868
2869 if (channel >= 1 && channel <= 3)
2870 group = 0;
2871 else if (channel >= 4 && channel <= 9)
2872 group = 1;
2873 else if (channel >= 10 && channel <= 14)
2874 group = 2;
2875 else if (channel >= 36 && channel <= 50)
2876 group = 3;
2877 else if (channel >= 52 && channel <= 64)
2878 group = 4;
2879 else if (channel >= 100 && channel <= 118)
2880 group = 5;
2881 else if (channel >= 120 && channel <= 144)
2882 group = 6;
2883 else if (channel >= 149 && channel <= 165)
2884 group = 7;
2885 else if (channel >= 167 && channel <= 177)
2886 group = 8;
2887 else {
2888 RF_DBG(dm, DBG_RF_MP, "[kfree] Channel(%d) is not exist in Group\n",
2889 channel);
2890 return 0;
2891 }
2892
2893 return power_trim_info->tssi_trim[group][path];
2894 }
2895
phydm_set_pabias_bandedge_2g_rf_8814b(void * dm_void)2896 void phydm_set_pabias_bandedge_2g_rf_8814b(void *dm_void)
2897 {
2898 #if 0
2899 struct dm_struct *dm = (struct dm_struct *)dm_void;
2900 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
2901
2902 u32 rf_reg_51 = 0, rf_reg_52 = 0, rf_reg_53 = 0, rf_reg_3f = 0;
2903 u8 i, j;
2904 s32 pa_bias_tmp, bandedge_tmp, reg_tmp;
2905
2906 #if 0
2907 /*2.4G bias*/
2908 /*rf3f == rf53*/
2909 #endif
2910 for (i = 0; i < MAX_PATH_NUM_8814B; i++) {
2911 rf_reg_51 = odm_get_rf_reg(dm, i, RF_0x51, RFREGOFFSETMASK);
2912 rf_reg_52 = odm_get_rf_reg(dm, i, RF_0x52, RFREGOFFSETMASK);
2913 rf_reg_53 = odm_get_rf_reg(dm, i, RF_0x53, RFREGOFFSETMASK);
2914
2915 RF_DBG(dm, DBG_RF_MP,
2916 "[kfree] 8814b 2g rf(0x51)=0x%X rf(0x52)=0x%X rf(0x53)=0x%X path=%d\n",
2917 rf_reg_51, rf_reg_52, rf_reg_53, i);
2918
2919 /*2.4G bias*/
2920 rf_reg_3f = rf_reg_53;
2921 pa_bias_tmp = rf_reg_3f & 0xf;
2922
2923 reg_tmp = pa_bias_tmp + power_trim_info->pa_bias_trim[0][i];
2924
2925 RF_DBG(dm, DBG_RF_MP,
2926 "[kfree] 8814b 2g pa bias reg_tmp(%d) = pa_bias_tmp(%d) + power_trim_info->pa_bias_trim[0][%d](%d)\n",
2927 reg_tmp, pa_bias_tmp, i, power_trim_info->pa_bias_trim[0][i]);
2928
2929 #if 0
2930 if (reg_tmp < 0) {
2931 reg_tmp = 0;
2932 RF_DBG(dm, DBG_RF_MP,
2933 "[kfree] 2g pa bias reg_tmp < 0. Set 0 path=%d\n", i);
2934 } else if (reg_tmp > 7) {
2935 reg_tmp = 7;
2936 RF_DBG(dm, DBG_RF_MP,
2937 "[kfree] 2g pa bias reg_tmp > 7. Set 7 path=%d\n", i);
2938 }
2939 #endif
2940
2941 rf_reg_3f = ((rf_reg_3f & 0xffff0) | reg_tmp);
2942 rf_reg_3f = ((rf_reg_3f & 0x0ffff) | 0x10000);
2943
2944 odm_set_rf_reg(dm, i, RF_0xef, BIT(10), 0x1);
2945 for (j = 0; j <= 0xf; j++) {
2946 odm_set_rf_reg(dm, i, RF_0x30, RFREGOFFSETMASK, (j << 16));
2947 odm_set_rf_reg(dm, i, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
2948 RF_DBG(dm, DBG_RF_MP,
2949 "[kfree] 8814b 2G pa bias write RF_0x30=0x%05x RF_0x3f=0x%x path=%d\n",
2950 (j << 16), rf_reg_3f, i);
2951 }
2952 odm_set_rf_reg(dm, i, RF_0xef, BIT(10), 0x0);
2953
2954 #if 0
2955 /*2.4G bandedge*/
2956 /*rf3f =>*/
2957 /*rf51[3:1] = rf3f[17:15]*/
2958 /*rf52[2:0] = rf3f[14:12]*/
2959 /*rf52[18] = rf3f[11]*/
2960 /*rf51[6:4] = rf3f[10:8]*/
2961 /*rf51[11:8] = rf3f[7:4]*/
2962 /*rf51[16:13] = rf3f[3:0]*/
2963 #endif
2964 /*2.4G bandedge*/
2965 rf_reg_3f = (((rf_reg_51 & 0xe) >> 1) << 15) |
2966 ((rf_reg_52 & 0x7) << 12) |
2967 (((rf_reg_52 & 0x40000) >> 18) << 11) |
2968 (((rf_reg_51 & 0x70) >> 4) << 8) |
2969 (((rf_reg_51 & 0xf00) >> 8) << 4) |
2970 ((rf_reg_51 & 0x1e000) >> 13);
2971
2972 bandedge_tmp = rf_reg_3f & 0xf;
2973
2974 reg_tmp = bandedge_tmp + power_trim_info->pa_bias_trim[0][i];
2975
2976 RF_DBG(dm, DBG_RF_MP,
2977 "[kfree] 8814b 2g bandedge reg_tmp(%d) = bandedge_tmp(%d) + power_trim_info->pa_bias_trim[0][%d](%d)\n",
2978 reg_tmp, bandedge_tmp, i, power_trim_info->pa_bias_trim[0][i]);
2979
2980 #if 0
2981 if (reg_tmp < 0) {
2982 reg_tmp = 0;
2983 RF_DBG(dm, DBG_RF_MP,
2984 "[kfree] 2g bandedge reg_tmp < 0. Set 0 path=%d\n", i);
2985 } else if (reg_tmp > 7) {
2986 reg_tmp = 7;
2987 RF_DBG(dm, DBG_RF_MP,
2988 "[kfree] 2g bandedge reg_tmp > 7. Set 7 path=%d\n", i);
2989 }
2990 #endif
2991
2992 rf_reg_3f = ((rf_reg_3f & 0xffff0) | reg_tmp);
2993
2994 RF_DBG(dm, DBG_RF_MP,
2995 "[kfree] 8814b 2G bandedge RF_0x30=0x%05X RF_0x3f=0x%x path=%d\n",
2996 0x00001, rf_reg_3f, i);
2997 RF_DBG(dm, DBG_RF_MP,
2998 "[kfree] 8814b 2G bandedge RF_0x30=0x%05X RF_0x3f=0x%x path=%d\n",
2999 0x0000b, rf_reg_3f, i);
3000 RF_DBG(dm, DBG_RF_MP,
3001 "[kfree] 8814b 2G bandedge RF_0x30=0x%05X RF_0x3f=0x%x path=%d\n",
3002 0x00023, rf_reg_3f, i);
3003 RF_DBG(dm, DBG_RF_MP,
3004 "[kfree] 8814b 2G bandedge RF_0x30=0x%05X RF_0x3f=0x%x path=%d\n",
3005 0x00029, rf_reg_3f, i);
3006 RF_DBG(dm, DBG_RF_MP,
3007 "[kfree] 8814b 2G bandedge RF_0x30=0x%05X RF_0x3f=0x%x path=%d\n",
3008 0x0002a, rf_reg_3f, i);
3009
3010 odm_set_rf_reg(dm, i, RF_0xef, BIT(8), 0x1);
3011 odm_set_rf_reg(dm, i, RF_0x33, RFREGOFFSETMASK, 0x00001);
3012 odm_set_rf_reg(dm, i, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
3013 odm_set_rf_reg(dm, i, RF_0x33, RFREGOFFSETMASK, 0x0000b);
3014 odm_set_rf_reg(dm, i, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
3015 odm_set_rf_reg(dm, i, RF_0x33, RFREGOFFSETMASK, 0x00023);
3016 odm_set_rf_reg(dm, i, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
3017 odm_set_rf_reg(dm, i, RF_0x33, RFREGOFFSETMASK, 0x00029);
3018 odm_set_rf_reg(dm, i, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
3019 odm_set_rf_reg(dm, i, RF_0x33, RFREGOFFSETMASK, 0x0002a);
3020 odm_set_rf_reg(dm, i, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
3021 odm_set_rf_reg(dm, i, RF_0xef, BIT(8), 0x0);
3022
3023 }
3024 #endif
3025 }
3026
phydm_set_pabias_bandedge_5g_rf_8814b(void * dm_void)3027 void phydm_set_pabias_bandedge_5g_rf_8814b(void *dm_void)
3028 {
3029 #if 0
3030 struct dm_struct *dm = (struct dm_struct *)dm_void;
3031 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
3032
3033 u32 rf_reg_18[MAX_PATH_NUM_8814B] = {0},
3034 rf_reg_61[15][MAX_PATH_NUM_8814B] = {0},
3035 rf_reg_62[3][MAX_PATH_NUM_8814B] = {0};
3036 u8 i, j;
3037 u32 bandedge[15][MAX_PATH_NUM_8814B] = {0},
3038 pa_bias[3][MAX_PATH_NUM_8814B] = {0};
3039
3040 s32 pa_bias_tmp, reg_tmp;
3041
3042
3043 for (i = 0; i < MAX_PATH_NUM_8814B; i++) {
3044 rf_reg_18[i] = odm_get_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK);
3045
3046 for (j = 0; j < 3; j++) {
3047 if (j == 0)
3048 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x10d24);
3049 else if (j == 1)
3050 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x30d64);
3051 else if (j == 2)
3052 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x50da9);
3053
3054 rf_reg_62[j][i] = odm_get_rf_reg(dm, i, 0x62, RFREGOFFSETMASK);
3055
3056 #if 0
3057 /*5G bias*/
3058 /*rf62[19:16] == rf30[11:8]*/
3059 /*rf62[15:12] == rf30[7:4]*/
3060 /*rf62[11:8] == rf3030[3:0]*/
3061 #endif
3062 pa_bias[j][i] = (((rf_reg_62[j][i] & 0xf0000) >> 16) << 8) |
3063 (((rf_reg_62[j][i] & 0xf000) >> 12) << 4) |
3064 ((rf_reg_62[j][i] & 0xf00) >> 8);
3065 }
3066
3067 for (j = 0; j < 15; j++) {
3068 if (j == 0)
3069 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x10d24);/*ch36*/
3070 else if (j == 1)
3071 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x11926);/*ch38*/
3072 else if (j == 2)
3073 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x1252a);/*ch42*/
3074 else if (j == 3)
3075 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x1253a);/*ch58*/
3076 else if (j == 4)
3077 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x1193e);/*ch62*/
3078 else if (j == 5)
3079 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x10d40);/*ch64*/
3080 else if (j == 6)
3081 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x30d64);/*ch100*/
3082 else if (j == 7)
3083 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x31966);/*ch102*/
3084 else if (j == 8)
3085 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x3256a);/*ch106*/
3086 else if (j == 9)
3087 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x3257a);/*ch122*/
3088 else if (j == 10)
3089 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x31986);/*ch134*/
3090 else if (j == 11)
3091 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x30d8c);/*ch140*/
3092 else if (j == 12)
3093 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x50d95);/*ch149*/
3094 else if (j == 13)
3095 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x51997);/*ch151*/
3096 else if (j == 14)
3097 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x5259b);/*ch155*/
3098
3099
3100 rf_reg_61[j][i] = odm_get_rf_reg(dm, i, RF_0x61, RFREGOFFSETMASK);
3101 #if 0
3102 /*5G bandedge*/
3103 /*rf61[11:8] == rf30[11:8]*/
3104 /*rf61[7:4] == rf30[7:4]*/
3105 /*rf61[3:0] == rf3030[3:0]*/
3106 #endif
3107 bandedge[j][i] = rf_reg_61[j][i] & 0xfff;
3108 }
3109
3110 odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, rf_reg_18[i]);
3111 }
3112
3113 for (i = 0; i < MAX_PATH_NUM_8814B; i++) {
3114 for (j = 0; j < 3; j++) {
3115 RF_DBG(dm, DBG_RF_MP,
3116 "[kfree] pa_bias[%d][%d]=0x%x\n", j, i, pa_bias[j][i]);
3117 }
3118 }
3119
3120 for (i = 0; i < MAX_PATH_NUM_8814B; i++) {
3121 for (j = 0; j < 15; j++) {
3122 RF_DBG(dm, DBG_RF_MP,
3123 "[kfree] bandedge[%d][%d]=0x%x\n", j, i, bandedge[j][i]);
3124 }
3125 }
3126
3127 /*5G bias*/
3128 for (i = 0; i < MAX_PATH_NUM_8814B; i++) {
3129 odm_set_rf_reg(dm, i, RF_0xee, BIT(8), 0x1);
3130 for (j = 0; j <= 0xb; j++) {
3131
3132 if (j >= 0 && j <= 3)
3133 pa_bias_tmp = pa_bias[0][i] & 0xf;
3134 else if (j >= 4 && j <= 0x7)
3135 pa_bias_tmp = pa_bias[1][i] & 0xf;
3136 else if (j >= 0x8 && j <= 0xb)
3137 pa_bias_tmp = pa_bias[2][i] & 0xf;
3138
3139 reg_tmp = pa_bias_tmp + power_trim_info->pa_bias_trim[1][i];
3140
3141 RF_DBG(dm, DBG_RF_MP,
3142 "[kfree] 8814b 5g pa bias reg_tmp(%d) = pa_bias_tmp(%d) + power_trim_info->pa_bias_trim[1][%d](%d)\n",
3143 reg_tmp, pa_bias_tmp, i, power_trim_info->pa_bias_trim[1][i]);
3144 #if 0
3145 if (reg_tmp < 0) {
3146 reg_tmp = 0;
3147 RF_DBG(dm, DBG_RF_MP,
3148 "[kfree] 5g pa bias reg_tmp < 0. Set 0 path=%d\n", i);
3149 } else if (reg_tmp > 7) {
3150 reg_tmp = 7;
3151 RF_DBG(dm, DBG_RF_MP,
3152 "[kfree] 5g pa bias reg_tmp > 7. Set 7 path=%d\n", i);
3153 }
3154 #endif
3155 if (j >= 0 && j <= 3)
3156 reg_tmp = ((pa_bias[0][i] & 0xffff0) | reg_tmp | (j << 12));
3157 else if (j >= 4 && j <= 0x7)
3158 reg_tmp = ((pa_bias[1][i] & 0xffff0) | reg_tmp | (j << 12));
3159 else if (j >= 0x8 && j <= 0xb)
3160 reg_tmp = ((pa_bias[2][i] & 0xffff0) | reg_tmp | (j << 12));
3161
3162 RF_DBG(dm, DBG_RF_MP,
3163 "[kfree] 8814b write RF_0x30=0x%05x path=%d\n",
3164 reg_tmp, i);
3165
3166 odm_set_rf_reg(dm, i, RF_0x30, RFREGOFFSETMASK, reg_tmp);
3167 }
3168 odm_set_rf_reg(dm, i, RF_0xee, BIT(8), 0x0);
3169 }
3170
3171 /*5G bandedge*/
3172 for (i = 0; i < MAX_PATH_NUM_8814B; i++) {
3173 odm_set_rf_reg(dm, i, RF_0xee, BIT(9), 0x1);
3174 for (j = 0; j <= 0xe; j++) {
3175 reg_tmp = bandedge[j][i] + power_trim_info->pa_bias_trim[1][i];
3176
3177 RF_DBG(dm, DBG_RF_MP,
3178 "[kfree] 8814b 5g bandedge reg_tmp(%d)(0x%X) = bandedge_org(%d) + power_trim_info->pa_bias_trim[1][%d](%d)\n",
3179 reg_tmp, reg_tmp, bandedge[j][i], i, power_trim_info->pa_bias_trim[1][i]);
3180 #if 0
3181 if (reg_tmp < 0) {
3182 reg_tmp = 0;
3183 RF_DBG(dm, DBG_RF_MP,
3184 "[kfree] 5g bandedge reg_tmp < 0. Set 0 path=%d\n", i);
3185 } else if (reg_tmp > 7) {
3186 reg_tmp = 7;
3187 RF_DBG(dm, DBG_RF_MP,
3188 "[kfree] 5g bandedge reg_tmp > 7. Set 7 path=%d\n", i);
3189 }
3190 #endif
3191
3192 reg_tmp = ((bandedge[j][i] & 0xffff0) | reg_tmp | (j << 12));
3193
3194 RF_DBG(dm, DBG_RF_MP,
3195 "[kfree] 8814b write RF_0x30=0x%05x path=%d\n",
3196 reg_tmp, i);
3197
3198 odm_set_rf_reg(dm, i, RF_0x30, RFREGOFFSETMASK, reg_tmp);
3199 }
3200 odm_set_rf_reg(dm, i, RF_0xee, BIT(9), 0x0);
3201 }
3202
3203 #endif
3204 }
3205
3206
phydm_get_pa_bias_offset_8814b(void * dm_void)3207 void phydm_get_pa_bias_offset_8814b(void *dm_void)
3208 {
3209 struct dm_struct *dm = (struct dm_struct *)dm_void;
3210 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
3211
3212 u8 i, j, k;
3213 u8 tssi_pa_bias_2g[2] = {0}, tssi_pa_bias_5g[2] = {0};
3214
3215 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GAC_14B, &tssi_pa_bias_2g[0], false);
3216 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GBD_14B, &tssi_pa_bias_2g[1], false);
3217
3218 j = 0;
3219 for (i = 0; i < 2; i++) {
3220 if (tssi_pa_bias_2g[i] == 0xff)
3221 j++;
3222 }
3223
3224 if (j == 2) {
3225 RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 2g PA Bias K no PG\n");
3226 } else {
3227 power_trim_info->pa_bias_trim[0][RF_PATH_A] = tssi_pa_bias_2g[0] & 0xf;
3228 power_trim_info->pa_bias_trim[0][RF_PATH_C] = (tssi_pa_bias_2g[0] & 0xf0) >> 4;
3229 power_trim_info->pa_bias_trim[0][RF_PATH_B] = tssi_pa_bias_2g[1] & 0xf;
3230 power_trim_info->pa_bias_trim[0][RF_PATH_D] = (tssi_pa_bias_2g[1] & 0xf0) >> 4;
3231
3232 for (k = 0; k < MAX_PATH_NUM_8814B; k++) {
3233 RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 2g PA Bias K efuse:0x%x path=%d\n",
3234 power_trim_info->pa_bias_trim[0][k], k);
3235 odm_set_rf_reg(dm, k, 0x60, 0x0000f000, power_trim_info->pa_bias_trim[0][k]);
3236 }
3237
3238 #if 0
3239 for (k = 0; k < MAX_PATH_NUM_8814B; k++) {
3240 if ((power_trim_info->pa_bias_trim[0][k] & BIT(0)) == 0)
3241 power_trim_info->pa_bias_trim[0][k] = (-1 * (power_trim_info->pa_bias_trim[0][k] >> 1));
3242 else
3243 power_trim_info->pa_bias_trim[0][k] = (power_trim_info->pa_bias_trim[0][k] >> 1);
3244
3245 RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 2g PA Bias K power_trim_info->pa_bias_trim[0][%d]=0x%x\n",
3246 k, power_trim_info->pa_bias_trim[0][k]);
3247 }
3248
3249 phydm_set_pabias_bandedge_2g_rf_8814b(dm);
3250 #endif
3251 }
3252
3253 odm_efuse_one_byte_read(dm, PPG_PABIAS_5GAC_14B, &tssi_pa_bias_5g[0], false);
3254 odm_efuse_one_byte_read(dm, PPG_PABIAS_5GBD_14B, &tssi_pa_bias_5g[1], false);
3255
3256 j = 0;
3257 for (i = 0; i < 2; i++) {
3258 if (tssi_pa_bias_5g[i] == 0xff)
3259 j++;
3260 }
3261
3262 if (j == 2) {
3263 RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 5g PA Bias K no PG\n");
3264 } else {
3265 power_trim_info->pa_bias_trim[1][RF_PATH_A] = tssi_pa_bias_5g[0] & 0xf;
3266 power_trim_info->pa_bias_trim[1][RF_PATH_C] = (tssi_pa_bias_5g[0] & 0xf0) >> 4;
3267 power_trim_info->pa_bias_trim[1][RF_PATH_B] = tssi_pa_bias_5g[1] & 0xf;
3268 power_trim_info->pa_bias_trim[1][RF_PATH_D] = (tssi_pa_bias_5g[1] & 0xf0) >> 4;
3269
3270 for (k = 0; k < MAX_PATH_NUM_8814B; k++) {
3271 RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 5g PA Bias K efuse:0x%x path=%d\n",
3272 power_trim_info->pa_bias_trim[1][k], k);
3273
3274 odm_set_rf_reg(dm, k, 0x60, 0x000f0000, power_trim_info->pa_bias_trim[1][k]);
3275 }
3276 #if 0
3277 for (k = 0; k < MAX_PATH_NUM_8814B; k++) {
3278 if ((power_trim_info->pa_bias_trim[1][k] & BIT(0)) == 0)
3279 power_trim_info->pa_bias_trim[1][k] = (-1 * (power_trim_info->pa_bias_trim[1][k] >> 1));
3280 else
3281 power_trim_info->pa_bias_trim[1][k] = (power_trim_info->pa_bias_trim[1][k] >> 1);
3282
3283 RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 5g PA Bias K power_trim_info->pa_bias_trim[1][%d]=0x%x\n",
3284 k, power_trim_info->pa_bias_trim[1][k]);
3285 }
3286
3287 phydm_set_pabias_bandedge_5g_rf_8814b(dm);
3288 #endif
3289 }
3290
3291
3292 }
3293
phydm_get_thermal_trim_offset_8814b(void * dm_void)3294 void phydm_get_thermal_trim_offset_8814b(void *dm_void)
3295 {
3296 struct dm_struct *dm = (struct dm_struct *)dm_void;
3297 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
3298
3299 u8 pg_therm = 0xff, i;
3300
3301 odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_14B, &pg_therm, false);
3302
3303 if (pg_therm != 0xff) {
3304 for (i = 0; i < MAX_PATH_NUM_8814B; i++) {
3305 if (i == 0)
3306 odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_14B, &pg_therm, false);
3307 else if (i == 1)
3308 odm_efuse_one_byte_read(dm, PPG_THERMAL_B_OFFSET_14B, &pg_therm, false);
3309 else if (i == 2)
3310 odm_efuse_one_byte_read(dm, PPG_THERMAL_C_OFFSET_14B, &pg_therm, false);
3311 else if (i == 3)
3312 odm_efuse_one_byte_read(dm, PPG_THERMAL_D_OFFSET_14B, &pg_therm, false);
3313
3314 RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b Efuse thermal S%d:0x%x\n", i, pg_therm);
3315 pg_therm = pg_therm & 0x1f;
3316 if ((pg_therm & BIT(0)) == 0)
3317 power_trim_info->multi_thermal[i] = (-1 * (pg_therm >> 1));
3318 else
3319 power_trim_info->multi_thermal[i] = (pg_therm >> 1);
3320 }
3321
3322 power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
3323 }
3324
3325 RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b thermal trim flag:0x%02x\n",
3326 power_trim_info->flag);
3327
3328 for (i = 0; i < MAX_RF_PATH; i++) {
3329 if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
3330 RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b thermal S%d:%d\n",
3331 i ,power_trim_info->multi_thermal[i]);
3332 }
3333 }
3334
phydm_get_thermal_trim_offset_8723f(void * dm_void)3335 void phydm_get_thermal_trim_offset_8723f(void *dm_void)
3336 {
3337 struct dm_struct *dm = (struct dm_struct *)dm_void;
3338 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
3339 u8 pg_therm = 0xff;
3340
3341 #if 1
3342 odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_8723F, &pg_therm, false);
3343
3344 if (pg_therm != 0xff) {
3345 pg_therm = pg_therm & 0x1f;
3346 if ((pg_therm & BIT(0)) == 0)
3347 power_trim_info->thermal = (-1 * (pg_therm >> 1));
3348 else
3349 power_trim_info->thermal = (pg_therm >> 1);
3350
3351 power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
3352 }
3353 /*if (pg_therm != 0xff) {
3354 pg_therm = pg_therm & 0x1f;
3355 thermal[RF_PATH_A] =((pg_therm & 0x1) << 3) | ((pg_therm >> 1) & 0x7);
3356 odm_set_rf_reg(dm, RF_PATH_A, RF_0x43, 0x000f0000, thermal[RF_PATH_A]);
3357 }*/
3358
3359 RF_DBG(dm, DBG_RF_MP, "[kfree] 8723F thermal trim flag:0x%02x\n",
3360 power_trim_info->flag);
3361
3362 if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
3363 RF_DBG(dm, DBG_RF_MP, "[kfree] 8723F thermal:%d\n",
3364 power_trim_info->thermal);
3365 #endif
3366 }
3367
phydm_get_set_power_trim_offset_8723f(void * dm_void)3368 void phydm_get_set_power_trim_offset_8723f(void *dm_void)
3369 {
3370 struct dm_struct *dm = (struct dm_struct *)dm_void;
3371 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
3372 u8 pg_power = 0xff, i, j;
3373 u8 pg_power1, pg_power2 , pg_power3, pg_power4, pg_power5;
3374 #if 0
3375 odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_22C, &pg_power1, false);
3376 odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_22C, &pg_power2, false);
3377 odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_22C, &pg_power3, false);
3378 odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22C, &pg_power4, false);
3379 odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22C, &pg_power5, false);
3380
3381 if (pg_power1 != 0xff || pg_power2 != 0xff || pg_power3 != 0xff ||
3382 pg_power4 != 0xff || pg_power5 != 0xff) {
3383 odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_22C, &pg_power, false);
3384 if (pg_power == 0xff)
3385 pg_power = 0;
3386 power_trim_info->bb_gain[0][0] = pg_power & 0xf;
3387 power_trim_info->bb_gain[0][1] = (pg_power & 0xf0) >> 4;
3388
3389 odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_22C, &pg_power, false);
3390 if (pg_power == 0xff)
3391 pg_power = 0;
3392 power_trim_info->bb_gain[1][0] = pg_power & 0xf;
3393 power_trim_info->bb_gain[1][1] = (pg_power & 0xf0) >> 4;
3394
3395 odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_22C, &pg_power, false);
3396 if (pg_power == 0xff)
3397 pg_power = 0;
3398 power_trim_info->bb_gain[2][0] = pg_power & 0xf;
3399 power_trim_info->bb_gain[2][1] = (pg_power & 0xf0) >> 4;
3400
3401 odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22C, &pg_power, false);
3402 if (pg_power == 0xff)
3403 pg_power = 0;
3404 power_trim_info->bb_gain[3][0] = pg_power & 0x1f;
3405 odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22C, &pg_power, false);
3406 if (pg_power == 0xff)
3407 pg_power = 0;
3408 power_trim_info->bb_gain[3][1] = pg_power & 0x1f;
3409
3410 odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22C, &pg_power, false);
3411 if (pg_power == 0xff)
3412 pg_power = 0;
3413 power_trim_info->bb_gain[4][0] = pg_power & 0x1f;
3414 odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22C, &pg_power, false);
3415 if (pg_power == 0xff)
3416 pg_power = 0;
3417 power_trim_info->bb_gain[4][1] = pg_power & 0x1f;
3418
3419 odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22C, &pg_power, false);
3420 if (pg_power == 0xff)
3421 pg_power = 0;
3422 power_trim_info->bb_gain[5][0] = pg_power & 0x1f;
3423 odm_efuse_one_byte_read(dm, PPG_5GM1_TXB_22C, &pg_power, false);
3424 if (pg_power == 0xff)
3425 pg_power = 0;
3426 power_trim_info->bb_gain[5][1] = pg_power & 0x1f;
3427
3428 odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_22C, &pg_power, false);
3429 if (pg_power == 0xff)
3430 pg_power = 0;
3431 power_trim_info->bb_gain[6][0] = pg_power & 0x1f;
3432 odm_efuse_one_byte_read(dm, PPG_5GM2_TXB_22C, &pg_power, false);
3433 if (pg_power == 0xff)
3434 pg_power = 0;
3435 power_trim_info->bb_gain[6][1] = pg_power & 0x1f;
3436
3437 odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_22C, &pg_power, false);
3438 if (pg_power == 0xff)
3439 pg_power = 0;
3440 power_trim_info->bb_gain[7][0] = pg_power & 0x1f;
3441 odm_efuse_one_byte_read(dm, PPG_5GH1_TXB_22C, &pg_power, false);
3442 if (pg_power == 0xff)
3443 pg_power = 0;
3444 power_trim_info->bb_gain[7][1] = pg_power & 0x1f;
3445
3446 power_trim_info->flag =
3447 power_trim_info->flag | KFREE_FLAG_ON |
3448 KFREE_FLAG_ON_2G |
3449 KFREE_FLAG_ON_5G;
3450
3451 phydm_set_power_trim_offset_8822c(dm);
3452 }
3453
3454 RF_DBG(dm, DBG_RF_MP, "[kfree] 8822c power trim flag:0x%02x\n",
3455 power_trim_info->flag);
3456
3457 if (power_trim_info->flag & KFREE_FLAG_ON) {
3458 for (i = 0; i < KFREE_BAND_NUM; i++) {
3459 for (j = 0; j < 2; j++) {
3460 RF_DBG(dm, DBG_RF_MP,
3461 "[kfree] 8822c pwr_trim->bb_gain[%d][%d]=0x%X\n",
3462 i, j, power_trim_info->bb_gain[i][j]);
3463 }
3464 }
3465 }
3466 #endif
3467 }
3468
phydm_get_tssi_trim_offset_8723f(void * dm_void)3469 void phydm_get_tssi_trim_offset_8723f(void *dm_void)
3470 {
3471 struct dm_struct *dm = (struct dm_struct *)dm_void;
3472 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
3473 u8 i, j, k;
3474 u8 pg_power[16] = {0xff, 0xff, 0xff, 0xff,
3475 0xff, 0xff, 0xff, 0xff,
3476 0xff, 0xff, 0xff, 0xff,
3477 0xff, 0xff, 0xff, 0xff};
3478 #if 1
3479 odm_efuse_one_byte_read(dm, PPG_S0_CH3_TSSIDE_8723F, &pg_power[0], false);
3480 odm_efuse_one_byte_read(dm, PPG_S1_CH3_TSSIDE_8723F, &pg_power[1], false);
3481 odm_efuse_one_byte_read(dm, PPG_S0_CH11_TSSIDE_8723F, &pg_power[2], false);
3482 odm_efuse_one_byte_read(dm, PPG_S1_CH11_TSSIDE_8723F, &pg_power[3], false);
3483 odm_efuse_one_byte_read(dm, PPG_S0_CH42_TSSIDE_8723F, &pg_power[4], false);
3484 odm_efuse_one_byte_read(dm, PPG_S0_CH58_TSSIDE_8723F, &pg_power[6], false);
3485 odm_efuse_one_byte_read(dm, PPG_S0_CH110_TSSIDE_8723F, &pg_power[8], false);
3486 odm_efuse_one_byte_read(dm, PPG_S0_CH134_TSSIDE_8723F, &pg_power[10], false);
3487 odm_efuse_one_byte_read(dm, PPG_S0_CH159_TSSIDE_8723F, &pg_power[12], false);
3488 odm_efuse_one_byte_read(dm, PPG_S0_CH171_TSSIDE_8723F, &pg_power[14], false);
3489
3490 j = 0;
3491 for (i = 0; i < 16; i++) {
3492 if ((pg_power[i] & 0xff) == 0xff)
3493 j++;
3494 }
3495
3496 if (j == 16) {
3497 for (i = 0; i < 9; i++)
3498 for(k = 0; i < 2; i++)
3499 power_trim_info->tssi_trim[i][k] = 0;
3500 RF_DBG(dm, DBG_RF_MP, "[kfree] 8723F tssi trim no PG\n");
3501 } else {
3502 power_trim_info->tssi_trim[0][0] = (s8)pg_power[0];
3503 power_trim_info->tssi_trim[0][1] = (s8)pg_power[1];
3504 power_trim_info->tssi_trim[1][0] = (s8)pg_power[2];
3505 power_trim_info->tssi_trim[1][1] = (s8)pg_power[3];
3506 power_trim_info->tssi_trim[2][0] = (s8)pg_power[4];
3507 power_trim_info->tssi_trim[2][1] = 0;
3508 power_trim_info->tssi_trim[3][0] = (s8)pg_power[6];
3509 power_trim_info->tssi_trim[3][1] = 0;
3510 power_trim_info->tssi_trim[4][0] = (s8)pg_power[8];
3511 power_trim_info->tssi_trim[4][1] = 0;
3512 power_trim_info->tssi_trim[5][0] = (s8)pg_power[10];
3513 power_trim_info->tssi_trim[5][1] = 0;
3514 power_trim_info->tssi_trim[6][0] = (s8)pg_power[12];
3515 power_trim_info->tssi_trim[6][1] = 0;
3516 power_trim_info->tssi_trim[7][0] = (s8)pg_power[14];
3517 power_trim_info->tssi_trim[7][1] = 0;
3518
3519 power_trim_info->flag =
3520 power_trim_info->flag | TSSI_TRIM_FLAG_ON;
3521
3522 if (power_trim_info->flag & TSSI_TRIM_FLAG_ON) {
3523 for (i = 0; i < 8; i++) { //KFREE_BAND_NUM
3524 for (j = 0; j < 2; j++) {
3525 RF_DBG(dm, DBG_RF_MP,
3526 "[kfree] 8723F tssi_trim[%d][%d]=0x%X\n",
3527 i, j, power_trim_info->tssi_trim[i][j]);
3528 }
3529 }
3530 }
3531 }
3532 #endif
3533 }
3534
phydm_get_tssi_trim_de_8723f(void * dm_void,u8 path)3535 s8 phydm_get_tssi_trim_de_8723f(void *dm_void, u8 path)
3536 {
3537 struct dm_struct *dm = (struct dm_struct *)dm_void;
3538 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
3539 u8 channel = *dm->channel, group = 0;
3540
3541 if (channel >= 1 && channel <= 7) {
3542 group = 0;
3543 } else if (channel >= 8 && channel <= 14) {
3544 group = 1;
3545 } else if (channel >= 36 && channel <= 50) {
3546 group = 2;
3547 } else if (channel >= 52 && channel <= 64) {
3548 group = 3;
3549 } else if (channel >= 100 && channel <= 128) {
3550 group = 4;
3551 } else if (channel >= 129 && channel <= 144) {
3552 group = 5;
3553 } else if (channel >= 149 && channel <= 163) {
3554 group = 6;
3555 } else if (channel >= 164 && channel <= 177) {
3556 group = 7;
3557 } else {
3558 RF_DBG(dm, DBG_RF_MP, "[kfree] Channel(%d) is not exist in Group\n", channel);
3559 return 0;
3560 }
3561
3562 return power_trim_info->tssi_trim[group][path];
3563 }
3564
phydm_get_set_pa_bias_offset_8723f(void * dm_void)3565 void phydm_get_set_pa_bias_offset_8723f(void *dm_void)
3566 {
3567 struct dm_struct *dm = (struct dm_struct *)dm_void;
3568 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
3569
3570 u8 i;
3571 u8 ppa_bias_2g[2] = {0}, ppa_bias_5g = 0;
3572
3573 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_8723F, &ppa_bias_2g[0], false);
3574 odm_efuse_one_byte_read(dm, PPG_PABIAS_2GB_8723F, &ppa_bias_2g[1], false);
3575 odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_8723F, &ppa_bias_5g, false);
3576
3577 if (ppa_bias_2g[0] == 0xff && ppa_bias_2g[1] == 0xff) {
3578 RF_DBG(dm, DBG_RF_MP, "[kfree] 8723f 2g PA Bias K no PG\n");
3579 } else {
3580 for (i = 0; i < MAX_PATH_NUM_8723F; i++) {
3581 power_trim_info->pa_bias_trim[0][i] = ppa_bias_2g[i] & 0xf;
3582 RF_DBG(dm, DBG_RF_MP,
3583 "[kfree] 8723f S%d 2g PA Bias K efuse:0x%x\n",
3584 i, power_trim_info->pa_bias_trim[0][i]);
3585 odm_set_rf_reg(dm, i, RF_0x60, 0x0f000, power_trim_info->pa_bias_trim[0][i]);
3586 }
3587 power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
3588 }
3589
3590 if (ppa_bias_5g == 0xff) {
3591 RF_DBG(dm, DBG_RF_MP, "[kfree] 8723f 5g PA Bias K no PG\n");
3592 } else {
3593 power_trim_info->pa_bias_trim[1][RF_PATH_A] = ppa_bias_5g & 0xf;
3594 RF_DBG(dm, DBG_RF_MP, "[kfree] 8723f 5g PA Bias K efuse:0x%x\n",
3595 power_trim_info->pa_bias_trim[1][RF_PATH_A]);
3596
3597 odm_set_rf_reg(dm, RF_PATH_A, RF_0x60, 0xf0000, power_trim_info->pa_bias_trim[1][0]);
3598 power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
3599 }
3600 }
3601
phydm_get_set_lna_offset_8723f(void * dm_void)3602 void phydm_get_set_lna_offset_8723f(void *dm_void)
3603 {
3604 struct dm_struct *dm = (struct dm_struct *)dm_void;
3605 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
3606
3607 u8 i;
3608 u8 pg_lna_2g[2] = {0}, pg_lna_5g = 0;
3609
3610 odm_efuse_one_byte_read(dm, PPG_LNA_2GA_8723F, &pg_lna_2g[0], false);
3611 odm_efuse_one_byte_read(dm, PPG_LNA_2GB_8723F, &pg_lna_2g[1], false);
3612 odm_efuse_one_byte_read(dm, PPG_LNA_5GA_8723F, &pg_lna_5g, false);
3613
3614 if (pg_lna_2g[0] == 0xff && pg_lna_2g[1] == 0xff) {
3615 RF_DBG(dm, DBG_RF_MP, "[kfree] 8723f 2g LNA Bias K no PG\n");
3616 } else {
3617 for (i = 0; i < MAX_PATH_NUM_8723F; i++) {
3618 power_trim_info->lna_trim[i] = pg_lna_2g[i] & 0x3f;
3619 RF_DBG(dm, DBG_RF_MP,
3620 "[kfree] 8723f S%d 2g LNA Bias K efuse:0x%x\n",
3621 i, power_trim_info->lna_trim[i]);
3622 odm_set_rf_reg(dm, i, RF_0x88, 0x003f0, power_trim_info->lna_trim[i]);
3623 }
3624 power_trim_info->lna_flag |= LNA_FLAG_ON;
3625 }
3626
3627 if (pg_lna_5g == 0xff) {
3628 RF_DBG(dm, DBG_RF_MP, "[kfree] 8723f 5g LNA Bias K no PG\n");
3629 } else {
3630 power_trim_info->lna_trim[2] = pg_lna_5g & 0x3f;
3631 RF_DBG(dm, DBG_RF_MP, "[kfree] 8723f 5g LNA Bias K efuse:0x%x\n",
3632 power_trim_info->lna_trim[2]);
3633
3634 odm_set_rf_reg(dm, RF_PATH_A, RF_0x8b, 0x03f00, power_trim_info->lna_trim[2]);
3635 power_trim_info->lna_flag |= LNA_FLAG_ON;
3636 }
3637 }
3638
phydm_get_tssi_trim_de(void * dm_void,u8 path)3639 s8 phydm_get_tssi_trim_de(void *dm_void, u8 path)
3640 {
3641 struct dm_struct *dm = (struct dm_struct *)dm_void;
3642
3643 if (dm->support_ic_type & ODM_RTL8822C)
3644 return phydm_get_tssi_trim_de_8822c(dm, path);
3645 else if (dm->support_ic_type & ODM_RTL8812F)
3646 return phydm_get_tssi_trim_de_8812f(dm, path);
3647 else if (dm->support_ic_type & ODM_RTL8197G)
3648 return phydm_get_tssi_trim_de_8197g(dm, path);
3649 else if (dm->support_ic_type & ODM_RTL8814B)
3650 return phydm_get_tssi_trim_de_8814b(dm, path);
3651 else if (dm->support_ic_type & ODM_RTL8723F)
3652 return phydm_get_tssi_trim_de_8723f(dm, path);
3653 else
3654 return 0;
3655 }
3656
phydm_do_new_kfree(void * dm_void)3657 void phydm_do_new_kfree(void *dm_void)
3658 {
3659 struct dm_struct *dm = (struct dm_struct *)dm_void;
3660
3661 if (dm->support_ic_type & ODM_RTL8822C) {
3662 phydm_get_set_thermal_trim_offset_8822c(dm);
3663 phydm_get_set_power_trim_offset_8822c(dm);
3664 phydm_get_set_pa_bias_offset_8822c(dm);
3665 phydm_get_tssi_trim_offset_8822c(dm);
3666 }
3667
3668 if (dm->support_ic_type & ODM_RTL8812F) {
3669 phydm_get_set_thermal_trim_offset_8812f(dm);
3670 phydm_get_set_power_trim_offset_8812f(dm);
3671 phydm_get_set_pa_bias_offset_8812f(dm);
3672 phydm_get_tssi_trim_offset_8812f(dm);
3673 }
3674
3675 if (dm->support_ic_type & ODM_RTL8195B) {
3676 phydm_get_thermal_trim_offset_8195b(dm);
3677 phydm_get_set_power_trim_offset_8195b(dm);
3678 phydm_get_set_pa_bias_offset_8195b(dm);
3679 }
3680
3681 if (dm->support_ic_type & ODM_RTL8721D) {
3682 phydm_get_thermal_trim_offset_8721d(dm);
3683 phydm_get_set_power_trim_offset_8721d(dm);
3684 /*phydm_get_set_pa_bias_offset_8721d(dm);*/
3685 }
3686
3687 if (dm->support_ic_type & ODM_RTL8198F) {
3688 phydm_get_pa_bias_offset_8198f(dm);
3689 phydm_get_set_lna_offset_8198f(dm);
3690 }
3691
3692 if (dm->support_ic_type & ODM_RTL8197G) {
3693 phydm_get_thermal_trim_offset_8197g(dm);
3694 phydm_get_set_power_trim_offset_8197g(dm);
3695 phydm_get_set_pa_bias_offset_8197g(dm);
3696 phydm_get_tssi_trim_offset_8197g(dm);
3697 phydm_get_set_lna_offset_8197g(dm);
3698 }
3699
3700 if (dm->support_ic_type & ODM_RTL8710C) {
3701 phydm_get_thermal_trim_offset_8710c(dm);
3702 phydm_get_set_power_trim_offset_8710c(dm);
3703 phydm_get_set_pa_bias_offset_8710c(dm);
3704 }
3705
3706 if (dm->support_ic_type & ODM_RTL8814B) {
3707 phydm_get_thermal_trim_offset_8814b(dm);
3708 phydm_get_set_power_trim_offset_8814b(dm);
3709 phydm_get_pa_bias_offset_8814b(dm);
3710 phydm_get_tssi_trim_offset_8814b(dm);
3711 }
3712 if (dm->support_ic_type & ODM_RTL8723F) {
3713 phydm_get_thermal_trim_offset_8723f(dm);
3714 phydm_get_set_power_trim_offset_8723f(dm);
3715 phydm_get_set_pa_bias_offset_8723f(dm);
3716 phydm_get_set_lna_offset_8723f(dm);
3717 phydm_get_tssi_trim_offset_8723f(dm);
3718 }
3719 }
3720
phydm_set_kfree_to_rf(void * dm_void,u8 e_rf_path,u8 data)3721 void phydm_set_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data)
3722 {
3723 struct dm_struct *dm = (struct dm_struct *)dm_void;
3724
3725 if (dm->support_ic_type & ODM_RTL8814A)
3726 phydm_set_kfree_to_rf_8814a(dm, e_rf_path, data);
3727
3728 if ((dm->support_ic_type & ODM_RTL8821C) &&
3729 (*dm->band_type == ODM_BAND_2_4G))
3730 phydm_set_kfree_to_rf_8821c(dm, e_rf_path, true, data);
3731 else if (dm->support_ic_type & ODM_RTL8821C)
3732 phydm_set_kfree_to_rf_8821c(dm, e_rf_path, false, data);
3733
3734 if (dm->support_ic_type & ODM_RTL8822B)
3735 phydm_set_kfree_to_rf_8822b(dm, e_rf_path, data);
3736
3737 if (dm->support_ic_type & ODM_RTL8710B)
3738 phydm_set_kfree_to_rf_8710b(dm, e_rf_path, data);
3739
3740 if (dm->support_ic_type & ODM_RTL8198F)
3741 phydm_set_kfree_to_rf_8198f(dm, e_rf_path, data);
3742 }
3743
phydm_clear_kfree_to_rf(void * dm_void,u8 e_rf_path,u8 data)3744 void phydm_clear_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data)
3745 {
3746 struct dm_struct *dm = (struct dm_struct *)dm_void;
3747
3748 if (dm->support_ic_type & ODM_RTL8822B)
3749 phydm_clear_kfree_to_rf_8822b(dm, e_rf_path, 1);
3750
3751 if (dm->support_ic_type & ODM_RTL8821C)
3752 phydm_clear_kfree_to_rf_8821c(dm, e_rf_path, 1);
3753
3754 if (dm->support_ic_type & ODM_RTL8198F)
3755 phydm_clear_kfree_to_rf_8198f(dm, e_rf_path, 0);
3756 }
3757
phydm_get_thermal_trim_offset(void * dm_void)3758 void phydm_get_thermal_trim_offset(void *dm_void)
3759 {
3760 struct dm_struct *dm = (struct dm_struct *)dm_void;
3761
3762 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
3763 void *adapter = dm->adapter;
3764 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
3765 PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;
3766 u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
3767
3768 if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
3769 RF_DBG(dm, DBG_RF_MP, "[kfree] dump efuse fail !!!\n");
3770 #endif
3771
3772 if (dm->support_ic_type & ODM_RTL8821C)
3773 phydm_get_thermal_trim_offset_8821c(dm_void);
3774 else if (dm->support_ic_type & ODM_RTL8822B)
3775 phydm_get_thermal_trim_offset_8822b(dm_void);
3776 else if (dm->support_ic_type & ODM_RTL8710B)
3777 phydm_get_thermal_trim_offset_8710b(dm_void);
3778 else if (dm->support_ic_type & ODM_RTL8192F)
3779 phydm_get_thermal_trim_offset_8192f(dm_void);
3780 else if (dm->support_ic_type & ODM_RTL8198F)
3781 phydm_get_thermal_trim_offset_8198f(dm_void);
3782 }
3783
phydm_get_power_trim_offset(void * dm_void)3784 void phydm_get_power_trim_offset(void *dm_void)
3785 {
3786 struct dm_struct *dm = (struct dm_struct *)dm_void;
3787
3788 #if 0 //(DM_ODM_SUPPORT_TYPE & ODM_WIN) // 2017 MH DM Should use the same code.s
3789 void *adapter = dm->adapter;
3790 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
3791 PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;
3792 u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
3793
3794 if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO(adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
3795 RF_DBG(dm, DBG_RF_MP, "[kfree] dump efuse fail !!!\n");
3796 #endif
3797
3798 if (dm->support_ic_type & ODM_RTL8821C)
3799 phydm_get_power_trim_offset_8821c(dm_void);
3800 else if (dm->support_ic_type & ODM_RTL8822B)
3801 phydm_get_power_trim_offset_8822b(dm_void);
3802 else if (dm->support_ic_type & ODM_RTL8710B)
3803 phydm_get_power_trim_offset_8710b(dm_void);
3804 else if (dm->support_ic_type & ODM_RTL8192F)
3805 phydm_get_power_trim_offset_8192f(dm_void);
3806 else if (dm->support_ic_type & ODM_RTL8198F)
3807 phydm_get_power_trim_offset_8198f(dm_void);
3808 }
3809
phydm_get_pa_bias_offset(void * dm_void)3810 void phydm_get_pa_bias_offset(void *dm_void)
3811 {
3812 struct dm_struct *dm = (struct dm_struct *)dm_void;
3813
3814 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
3815 void *adapter = dm->adapter;
3816 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
3817 PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;
3818 u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
3819
3820 if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
3821 RF_DBG(dm, DBG_RF_MP, "[kfree] dump efuse fail !!!\n");
3822 #endif
3823
3824 if (dm->support_ic_type & ODM_RTL8822B)
3825 phydm_get_pa_bias_offset_8822b(dm_void);
3826 }
3827
phydm_get_thermal_offset(void * dm_void)3828 s8 phydm_get_thermal_offset(void *dm_void)
3829 {
3830 struct dm_struct *dm = (struct dm_struct *)dm_void;
3831 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
3832
3833 if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
3834 return power_trim_info->thermal;
3835 else
3836 return 0;
3837 }
3838
phydm_get_multi_thermal_offset(void * dm_void,u8 path)3839 s8 phydm_get_multi_thermal_offset(void *dm_void, u8 path)
3840 {
3841 struct dm_struct *dm = (struct dm_struct *)dm_void;
3842 struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
3843
3844 if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
3845 return power_trim_info->multi_thermal[path];
3846 else
3847 return 0;
3848 }
3849
phydm_do_kfree(void * dm_void,u8 channel_to_sw)3850 void phydm_do_kfree(void *dm_void, u8 channel_to_sw)
3851 {
3852 struct dm_struct *dm = (struct dm_struct *)dm_void;
3853 struct odm_power_trim_data *pwrtrim = &dm->power_trim_data;
3854 u8 channel_idx = 0, rfpath = 0, max_path = 0, kfree_band_num = 0;
3855 u8 i, j;
3856 s8 bb_gain;
3857
3858 if (dm->support_ic_type & ODM_RTL8814A)
3859 max_path = 4; /*0~3*/
3860 else if (dm->support_ic_type &
3861 (ODM_RTL8812 | ODM_RTL8822B | ODM_RTL8192F)) {
3862 max_path = 2; /*0~1*/
3863 kfree_band_num = KFREE_BAND_NUM;
3864 } else if (dm->support_ic_type & ODM_RTL8821C) {
3865 max_path = 1;
3866 kfree_band_num = KFREE_BAND_NUM;
3867 } else if (dm->support_ic_type & ODM_RTL8710B) {
3868 max_path = 1;
3869 kfree_band_num = 1;
3870 } else if (dm->support_ic_type & ODM_RTL8198F) {
3871 max_path = 4;
3872 kfree_band_num = 3;
3873 }
3874
3875 if (dm->support_ic_type &
3876 (ODM_RTL8192F | ODM_RTL8822B | ODM_RTL8821C |
3877 ODM_RTL8814A | ODM_RTL8710B)) {
3878 for (i = 0; i < kfree_band_num; i++) {
3879 for (j = 0; j < max_path; j++)
3880 RF_DBG(dm, DBG_RF_MP,
3881 "[kfree] PwrTrim->gain[%d][%d]=0x%X\n",
3882 i, j, pwrtrim->bb_gain[i][j]);
3883 }
3884 }
3885 if (*dm->band_type == ODM_BAND_2_4G &&
3886 pwrtrim->flag & KFREE_FLAG_ON_2G) {
3887 if (!(dm->support_ic_type & ODM_RTL8192F)) {
3888 if (channel_to_sw >= 1 && channel_to_sw <= 14)
3889 channel_idx = PHYDM_2G;
3890 for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {
3891 RF_DBG(dm, DBG_RF_MP,
3892 "[kfree] %s:chnl=%d PATH=%d gain:0x%X\n",
3893 __func__, channel_to_sw, rfpath,
3894 pwrtrim->bb_gain[channel_idx][rfpath]);
3895 bb_gain = pwrtrim->bb_gain[channel_idx][rfpath];
3896 phydm_set_kfree_to_rf(dm, rfpath, bb_gain);
3897 }
3898 } else if (dm->support_ic_type & ODM_RTL8192F) {
3899 if (channel_to_sw >= 1 && channel_to_sw <= 3)
3900 channel_idx = 0;
3901 if (channel_to_sw >= 4 && channel_to_sw <= 9)
3902 channel_idx = 1;
3903 if (channel_to_sw >= 10 && channel_to_sw <= 14)
3904 channel_idx = 2;
3905 for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {
3906 RF_DBG(dm, DBG_RF_MP,
3907 "[kfree] %s:chnl=%d PATH=%d gain:0x%X\n",
3908 __func__, channel_to_sw, rfpath,
3909 pwrtrim->bb_gain[channel_idx][rfpath]);
3910 bb_gain = pwrtrim->bb_gain[channel_idx][rfpath];
3911 phydm_set_kfree_to_rf_8192f(dm, rfpath,
3912 channel_idx,
3913 bb_gain);
3914 }
3915 }
3916 } else if (*dm->band_type == ODM_BAND_5G &&
3917 pwrtrim->flag & KFREE_FLAG_ON_5G) {
3918 if (channel_to_sw >= 36 && channel_to_sw <= 48)
3919 channel_idx = PHYDM_5GLB1;
3920 if (channel_to_sw >= 52 && channel_to_sw <= 64)
3921 channel_idx = PHYDM_5GLB2;
3922 if (channel_to_sw >= 100 && channel_to_sw <= 120)
3923 channel_idx = PHYDM_5GMB1;
3924 if (channel_to_sw >= 122 && channel_to_sw <= 144)
3925 channel_idx = PHYDM_5GMB2;
3926 if (channel_to_sw >= 149 && channel_to_sw <= 177)
3927 channel_idx = PHYDM_5GHB;
3928
3929 for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {
3930 RF_DBG(dm, DBG_RF_MP,
3931 "[kfree] %s: channel=%d PATH=%d bb_gain:0x%X\n",
3932 __func__, channel_to_sw, rfpath,
3933 pwrtrim->bb_gain[channel_idx][rfpath]);
3934 bb_gain = pwrtrim->bb_gain[channel_idx][rfpath];
3935 phydm_set_kfree_to_rf(dm, rfpath, bb_gain);
3936 }
3937 } else {
3938 RF_DBG(dm, DBG_RF_MP, "[kfree] Set default Register\n");
3939 if (!(dm->support_ic_type & ODM_RTL8192F)) {
3940 for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {
3941 bb_gain = pwrtrim->bb_gain[channel_idx][rfpath];
3942 phydm_clear_kfree_to_rf(dm, rfpath, bb_gain);
3943 }
3944 }
3945 #if 0
3946 /*else if(dm->support_ic_type & ODM_RTL8192F){
3947 if (channel_to_sw >= 1 && channel_to_sw <= 3)
3948 channel_idx = 0;
3949 if (channel_to_sw >= 4 && channel_to_sw <= 9)
3950 channel_idx = 1;
3951 if (channel_to_sw >= 9 && channel_to_sw <= 14)
3952 channel_idx = 2;
3953 for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++)
3954 phydm_clear_kfree_to_rf_8192f(dm, rfpath, pwrtrim->bb_gain[channel_idx][rfpath]);
3955 }*/
3956 #endif
3957 }
3958 }
3959
phydm_config_new_kfree(void * dm_void)3960 void phydm_config_new_kfree(void *dm_void)
3961 {
3962 struct dm_struct *dm = (struct dm_struct *)dm_void;
3963 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
3964
3965 if (cali_info->reg_rf_kfree_enable == 2) {
3966 RF_DBG(dm, DBG_RF_MP,
3967 "[kfree] %s: reg_rf_kfree_enable == 2, Disable\n",
3968 __func__);
3969 return;
3970 } else if (cali_info->reg_rf_kfree_enable == 1 ||
3971 cali_info->reg_rf_kfree_enable == 0) {
3972 RF_DBG(dm, DBG_RF_MP,
3973 "[kfree] %s: reg_rf_kfree_enable == true\n", __func__);
3974
3975 phydm_do_new_kfree(dm);
3976 }
3977 }
3978
phydm_config_kfree(void * dm_void,u8 channel_to_sw)3979 void phydm_config_kfree(void *dm_void, u8 channel_to_sw)
3980 {
3981 struct dm_struct *dm = (struct dm_struct *)dm_void;
3982 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
3983 struct odm_power_trim_data *pwrtrim = &dm->power_trim_data;
3984
3985 RF_DBG(dm, DBG_RF_MP, "===>[kfree] phy_ConfigKFree()\n");
3986
3987 if (cali_info->reg_rf_kfree_enable == 2) {
3988 RF_DBG(dm, DBG_RF_MP,
3989 "[kfree] %s: reg_rf_kfree_enable == 2, Disable\n",
3990 __func__);
3991 return;
3992 } else if (cali_info->reg_rf_kfree_enable == 1 ||
3993 cali_info->reg_rf_kfree_enable == 0) {
3994 RF_DBG(dm, DBG_RF_MP,
3995 "[kfree] %s: reg_rf_kfree_enable == true\n", __func__);
3996 /*Make sure the targetval is defined*/
3997 if (!(pwrtrim->flag & KFREE_FLAG_ON)) {
3998 RF_DBG(dm, DBG_RF_MP,
3999 "[kfree] %s: efuse is 0xff, KFree not work\n",
4000 __func__);
4001 return;
4002 }
4003 #if 0
4004 /*if kfree_table[0] == 0xff, means no Kfree*/
4005 #endif
4006 phydm_do_kfree(dm, channel_to_sw);
4007 }
4008 RF_DBG(dm, DBG_RF_MP, "<===[kfree] phy_ConfigKFree()\n");
4009 }
4010
phydm_set_lna_trim_offset(void * dm_void,u8 path,u8 cg_cs,u8 enable)4011 void phydm_set_lna_trim_offset (void *dm_void, u8 path, u8 cg_cs, u8 enable)
4012 {
4013 struct dm_struct *dm = (struct dm_struct *)dm_void;
4014
4015 if (dm->support_ic_type & ODM_RTL8197G)
4016 phydm_set_lna_trim_offset_8197g(dm, path, cg_cs, enable);
4017 }
4018
4019