1 /* 2 * linux-5.4/drivers/media/platform/sunxi-vin/vin-csi/parser_reg.h 3 * 4 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd. 5 * 6 * Authors: Zhao Wei <zhaowei@allwinnertech.com> 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef __CSIC__PARSER__REG__H__ 20 #define __CSIC__PARSER__REG__H__ 21 22 #include <media/sunxi_camera_v2.h> 23 #include <linux/types.h> 24 #include <media/v4l2-mediabus.h> 25 26 #define MAX_CH_NUM 4 27 28 29 /*register value*/ 30 31 enum prs_mode { 32 PRS_NCSI = 0, 33 PRS_MCSI, 34 }; 35 36 enum ref_pol { 37 ACTIVE_LOW, /* active low */ 38 ACTIVE_HIGH, /* active high */ 39 }; 40 41 enum edge_pol { 42 FALLING, /* active falling */ 43 RISING, /* active rising */ 44 }; 45 46 enum prs_if { 47 /* YUV(separate syncs) */ 48 /* YUYV422 Interleaved or RAW * (All data in one data bus) */ 49 PRS_IF_INTLV = 0x00, 50 PRS_IF_INTLV_16BIT = 0x01, /* 16 bit YUYV422 Interleaved */ 51 52 /* CCIR656(embedded syncs) */ 53 PRS_IF_BT656_1CH = 0x04, /* BT656 1 channel */ 54 PRS_IF_BT1120_1CH = 0x05, /* 16bit BT656(BT1120 like) 1 channel */ 55 /* BT656 2 channels (All data * interleaved in one data bus) */ 56 PRS_IF_BT656_2CH = 0x0c, 57 /* 16bit BT656(BT1120 like) 2 channels * (All data interleaved in one data bus) */ 58 PRS_IF_BT1120_2CH = 0x0d, 59 /* BT656 4 channels (All data * interleaved in one data bus) */ 60 PRS_IF_BT656_4CH = 0x0e, 61 /* 16bit BT656(BT1120 like) 4 channels * (All data interleaved in one data bus) */ 62 PRS_IF_BT1120_4CH = 0x0f, 63 }; 64 65 enum output_mode { 66 FIELD_MODE = 0, 67 FRAME_MODE = 1, 68 }; 69 70 enum input_seq { 71 /* valid input is yuv422 or yuv420*/ 72 SEQ_YUYV = 0, 73 SEQ_YVYU, 74 SEQ_UYVY, 75 SEQ_VYUY, 76 }; 77 78 enum if_data_width { 79 DW_8BIT = 0, 80 DW_10BIT = 1, 81 DW_12BIT = 2, 82 DW_8PLUS2 = 3, 83 DW_2MULTI8 = 4, 84 }; 85 86 enum seq_8plus2 { 87 B6_D98_D70 = 0, 88 D92_B6_D10 = 1, 89 D70_D98_B6 = 2, 90 D70_B6_D98 = 3, 91 }; 92 93 /* 94 * field dt mode 95 */ 96 enum field_dt_mode { 97 FIELD_VSYNC = 0, 98 FIELD_ONLY = 1, 99 VSYNC_ONLY = 2, 100 }; 101 102 /* 103 * data clock edge 104 */ 105 enum clk_pol { 106 CLK_RISING, /* active rising */ 107 CLK_FALLING, /* active falling */ 108 }; 109 110 /* 111 * input reference polarity 112 */ 113 enum refer_pol { 114 REF_NEGATIVE, /* active low */ 115 REF_POSITIVE, /* active high */ 116 }; 117 118 enum field_pol { 119 /* For YUV HV timing, Field polarity */ 120 FIELD_NEG = 0, /* field=0 indicate odd, field=1 indicate even */ 121 FIELD_POS = 1, /* field=1 indicate odd, field=0 indicate even */ 122 /* For BT656 timing, Field sequence */ 123 FIELD_TF = 0, /* top filed first */ 124 FIELD_BF = 1, /* bottom field first */ 125 }; 126 127 enum src_type { 128 PROGRESSED = 0, /* progressed */ 129 INTERLACE = 1, /* interlace */ 130 }; 131 132 enum cap_mode { 133 SCAP = 1, 134 VCAP, 135 }; 136 137 enum prs_input_fmt { 138 FMT_RAW = 0, /* raw stream */ 139 FMT_YUV422 = 3, /* yuv422 */ 140 FMT_YUV420 = 4, /* yuv420 */ 141 }; 142 143 144 /* 145 * parser interrupt select 146 */ 147 enum prs_int_sel { 148 PRS_INT_PARA0 = 0X1, 149 PRS_INT_PARA1 = 0X2, 150 PRS_INT_MUL_ERR = 0X4, 151 }; 152 153 /* 154 * csi buffer 155 */ 156 157 enum csi_buf_sel { 158 CSI_BUF_0_A = 0, /* FIFO for Y address A */ 159 CSI_BUF_0_B, /* FIFO for Y address B */ 160 CSI_BUF_1_A, /* FIFO for Cb address A */ 161 CSI_BUF_1_B, /* FIFO for Cb address B */ 162 CSI_BUF_2_A, /* FIFO for Cr address A */ 163 CSI_BUF_2_B, /* FIFO for Cr address B */ 164 }; 165 166 struct bus_timing { 167 enum ref_pol href_pol; 168 enum ref_pol vref_pol; 169 enum edge_pol pclk_sample; 170 enum ref_pol field_even_pol; /*field 0/1 0:odd 1:even*/ 171 }; 172 173 struct frame_size { 174 unsigned int width; /* in pixel unit */ 175 unsigned int height; /* in pixel unit */ 176 }; 177 178 struct frame_offset { 179 unsigned int hoff; /* in pixel unit */ 180 unsigned int voff; /* in pixel unit */ 181 }; 182 183 struct bus_info { 184 enum v4l2_mbus_type bus_if; 185 struct bus_timing bus_tmg; 186 u32 bus_ch_fmt[MAX_CH_NUM]; /* define the same as V4L2 */ 187 unsigned int ch_total_num; 188 }; 189 190 /* 191 * frame arrangement 192 * Indicate that how the channel images are put together into one buffer 193 */ 194 struct frame_arrange { 195 unsigned char column; 196 unsigned char row; 197 }; 198 199 struct frame_info { 200 struct frame_arrange arrange; 201 struct frame_size ch_size[MAX_CH_NUM]; 202 struct frame_offset ch_offset[MAX_CH_NUM]; 203 unsigned int pix_ch_fmt[MAX_CH_NUM]; 204 enum v4l2_field ch_field[MAX_CH_NUM]; /* define the same as V4L2 */ 205 unsigned int frm_byte_size; 206 }; 207 208 /*register data struct*/ 209 210 struct prs_ncsi_if_cfg { 211 unsigned int pclk_shift; 212 enum src_type type; 213 enum field_pol field; 214 enum refer_pol vref; 215 enum refer_pol href; 216 enum clk_pol clk; 217 enum field_dt_mode field_dt; 218 bool ddr_sample; 219 enum seq_8plus2 seq_8_2; 220 enum if_data_width dw; 221 enum input_seq seq; 222 enum output_mode mode; 223 enum prs_if intf; 224 }; 225 226 struct prs_mcsi_if_cfg { 227 enum input_seq seq; 228 enum output_mode mode; 229 }; 230 231 struct prs_cap_mode { 232 unsigned int cap_mask; 233 enum cap_mode mode; 234 }; 235 236 struct prs_signal_status { 237 unsigned int pclk_sta; 238 unsigned int data_sta; 239 }; 240 241 struct prs_ncsi_bt656_header { 242 unsigned int ch0_id; 243 unsigned int ch1_id; 244 unsigned int ch2_id; 245 unsigned int ch3_id; 246 }; 247 248 struct prs_output_size { 249 unsigned int hor_len; 250 unsigned int hor_start; 251 unsigned int ver_len; 252 unsigned int ver_start; 253 }; 254 255 struct prs_input_para { 256 unsigned int src_type; 257 unsigned int input_vt; 258 unsigned int input_ht; 259 unsigned int input_hb; 260 unsigned int input_hs; 261 }; 262 263 struct prs_int_status { 264 bool input_src_pd0; 265 bool input_src_pd1; 266 bool mul_err_pd; 267 }; 268 269 struct prs_fps_ds { 270 unsigned int ch0_fps_ds; 271 unsigned int ch1_fps_ds; 272 unsigned int ch2_fps_ds; 273 unsigned int ch3_fps_ds; 274 }; 275 276 int csic_prs_set_base_addr(unsigned int sel, unsigned long addr); 277 void csic_prs_enable(unsigned int sel); 278 void csic_prs_disable(unsigned int sel); 279 void csic_prs_mode(unsigned int sel, enum prs_mode mode); 280 void csic_prs_pclk_en(unsigned int sel, unsigned int en); 281 void csic_prs_ncsi_en(unsigned int sel, unsigned int en); 282 void csic_prs_mcsi_en(unsigned int sel, unsigned int en); 283 void csic_prs_ch_en(unsigned int sel, unsigned int en); 284 void csic_prs_ncsi_if_cfg(unsigned int sel, struct prs_ncsi_if_cfg *if_cfg); 285 void csic_prs_mcsi_if_cfg(unsigned int sel, struct prs_mcsi_if_cfg *if_cfg); 286 void csic_prs_capture_start(unsigned int sel, unsigned int ch_total_num, 287 struct prs_cap_mode *mode); 288 void csic_prs_capture_stop(unsigned int sel); 289 void csic_prs_fps_ds(unsigned int sel, struct prs_fps_ds *prs_fps_ds); 290 void csic_prs_signal_status(unsigned int sel, 291 struct prs_signal_status *status); 292 void csic_prs_ncsi_bt656_header_cfg(unsigned int sel, 293 struct prs_ncsi_bt656_header *header); 294 void csic_prs_input_fmt_cfg(unsigned int sel, unsigned int ch, 295 enum prs_input_fmt fmt); 296 void csic_prs_output_size_cfg(unsigned int sel, unsigned int ch, 297 struct prs_output_size *size); 298 void csic_prs_set_pclk_dly(unsigned int sel, unsigned int pclk_dly); 299 /*for csic sync*/ 300 void csic_prs_sync_en_cfg(unsigned int sel, struct csi_sync_ctrl *sync); 301 void csic_prs_sync_en(unsigned int sel, struct csi_sync_ctrl *sync); 302 void csic_prs_sync_cfg(unsigned int sel, struct csi_sync_ctrl *sync); 303 void csic_prs_sync_wait_N(unsigned int sel, struct csi_sync_ctrl *sync); 304 void csic_prs_sync_wait_M(unsigned int sel, struct csi_sync_ctrl *sync); 305 306 void csic_prs_xs_en(unsigned int sel, struct csi_sync_ctrl *sync); 307 void csic_prs_xs_period_len_register(unsigned int sel, struct csi_sync_ctrl *sync); 308 /* for debug */ 309 void csic_prs_input_para_get(unsigned int sel, unsigned int ch, 310 struct prs_input_para *para); 311 void csic_prs_int_enable(unsigned int sel, unsigned int ch, 312 enum prs_int_sel interrupt); 313 void csic_prs_int_disable(unsigned int sel, unsigned int ch, 314 enum prs_int_sel interrupt); 315 void csic_prs_int_get_status(unsigned int sel, unsigned int ch, 316 struct prs_int_status *status); 317 void csic_prs_int_clear_status(unsigned int sel, unsigned int ch, 318 enum prs_int_sel interrupt); 319 320 #endif /* __CSIC__PARSER__REG__H__ */ 321