1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6 #include "qla_def.h"
7
8 #include <linux/moduleparam.h>
9 #include <linux/vmalloc.h>
10 #include <linux/delay.h>
11 #include <linux/kthread.h>
12 #include <linux/mutex.h>
13 #include <linux/kobject.h>
14 #include <linux/slab.h>
15 #include <linux/blk-mq-pci.h>
16 #include <linux/refcount.h>
17 #include <linux/crash_dump.h>
18
19 #include <scsi/scsi_tcq.h>
20 #include <scsi/scsicam.h>
21 #include <scsi/scsi_transport.h>
22 #include <scsi/scsi_transport_fc.h>
23
24 #include "qla_target.h"
25
26 /*
27 * Driver version
28 */
29 char qla2x00_version_str[40];
30
31 static int apidev_major;
32
33 /*
34 * SRB allocation cache
35 */
36 struct kmem_cache *srb_cachep;
37
38 int ql2xfulldump_on_mpifail;
39 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR);
40 MODULE_PARM_DESC(ql2xfulldump_on_mpifail,
41 "Set this to take full dump on MPI hang.");
42
43 int ql2xenforce_iocb_limit = 1;
44 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR);
45 MODULE_PARM_DESC(ql2xenforce_iocb_limit,
46 "Enforce IOCB throttling, to avoid FW congestion. (default: 1)");
47
48 /*
49 * CT6 CTX allocation cache
50 */
51 static struct kmem_cache *ctx_cachep;
52 /*
53 * error level for logging
54 */
55 uint ql_errlev = 0x8001;
56
57 static int ql2xenableclass2;
58 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
59 MODULE_PARM_DESC(ql2xenableclass2,
60 "Specify if Class 2 operations are supported from the very "
61 "beginning. Default is 0 - class 2 not supported.");
62
63
64 int ql2xlogintimeout = 20;
65 module_param(ql2xlogintimeout, int, S_IRUGO);
66 MODULE_PARM_DESC(ql2xlogintimeout,
67 "Login timeout value in seconds.");
68
69 int qlport_down_retry;
70 module_param(qlport_down_retry, int, S_IRUGO);
71 MODULE_PARM_DESC(qlport_down_retry,
72 "Maximum number of command retries to a port that returns "
73 "a PORT-DOWN status.");
74
75 int ql2xplogiabsentdevice;
76 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
77 MODULE_PARM_DESC(ql2xplogiabsentdevice,
78 "Option to enable PLOGI to devices that are not present after "
79 "a Fabric scan. This is needed for several broken switches. "
80 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
81
82 int ql2xloginretrycount;
83 module_param(ql2xloginretrycount, int, S_IRUGO);
84 MODULE_PARM_DESC(ql2xloginretrycount,
85 "Specify an alternate value for the NVRAM login retry count.");
86
87 int ql2xallocfwdump = 1;
88 module_param(ql2xallocfwdump, int, S_IRUGO);
89 MODULE_PARM_DESC(ql2xallocfwdump,
90 "Option to enable allocation of memory for a firmware dump "
91 "during HBA initialization. Memory allocation requirements "
92 "vary by ISP type. Default is 1 - allocate memory.");
93
94 int ql2xextended_error_logging;
95 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
96 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
97 MODULE_PARM_DESC(ql2xextended_error_logging,
98 "Option to enable extended error logging,\n"
99 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
100 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
101 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
102 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
103 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
104 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
105 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
106 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
107 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
108 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
109 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
110 "\t\t0x1e400000 - Preferred value for capturing essential "
111 "debug information (equivalent to old "
112 "ql2xextended_error_logging=1).\n"
113 "\t\tDo LOGICAL OR of the value to enable more than one level");
114
115 int ql2xshiftctondsd = 6;
116 module_param(ql2xshiftctondsd, int, S_IRUGO);
117 MODULE_PARM_DESC(ql2xshiftctondsd,
118 "Set to control shifting of command type processing "
119 "based on total number of SG elements.");
120
121 int ql2xfdmienable = 1;
122 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
123 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
124 MODULE_PARM_DESC(ql2xfdmienable,
125 "Enables FDMI registrations. "
126 "0 - no FDMI registrations. "
127 "1 - provide FDMI registrations (default).");
128
129 #define MAX_Q_DEPTH 64
130 static int ql2xmaxqdepth = MAX_Q_DEPTH;
131 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
132 MODULE_PARM_DESC(ql2xmaxqdepth,
133 "Maximum queue depth to set for each LUN. "
134 "Default is 64.");
135
136 int ql2xenabledif = 2;
137 module_param(ql2xenabledif, int, S_IRUGO);
138 MODULE_PARM_DESC(ql2xenabledif,
139 " Enable T10-CRC-DIF:\n"
140 " Default is 2.\n"
141 " 0 -- No DIF Support\n"
142 " 1 -- Enable DIF for all types\n"
143 " 2 -- Enable DIF for all types, except Type 0.\n");
144
145 #if (IS_ENABLED(CONFIG_NVME_FC))
146 int ql2xnvmeenable = 1;
147 #else
148 int ql2xnvmeenable;
149 #endif
150 module_param(ql2xnvmeenable, int, 0644);
151 MODULE_PARM_DESC(ql2xnvmeenable,
152 "Enables NVME support. "
153 "0 - no NVMe. Default is Y");
154
155 int ql2xenablehba_err_chk = 2;
156 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
157 MODULE_PARM_DESC(ql2xenablehba_err_chk,
158 " Enable T10-CRC-DIF Error isolation by HBA:\n"
159 " Default is 2.\n"
160 " 0 -- Error isolation disabled\n"
161 " 1 -- Error isolation enabled only for DIX Type 0\n"
162 " 2 -- Error isolation enabled for all Types\n");
163
164 int ql2xiidmaenable = 1;
165 module_param(ql2xiidmaenable, int, S_IRUGO);
166 MODULE_PARM_DESC(ql2xiidmaenable,
167 "Enables iIDMA settings "
168 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
169
170 int ql2xmqsupport = 1;
171 module_param(ql2xmqsupport, int, S_IRUGO);
172 MODULE_PARM_DESC(ql2xmqsupport,
173 "Enable on demand multiple queue pairs support "
174 "Default is 1 for supported. "
175 "Set it to 0 to turn off mq qpair support.");
176
177 int ql2xfwloadbin;
178 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
179 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
180 MODULE_PARM_DESC(ql2xfwloadbin,
181 "Option to specify location from which to load ISP firmware:.\n"
182 " 2 -- load firmware via the request_firmware() (hotplug).\n"
183 " interface.\n"
184 " 1 -- load firmware from flash.\n"
185 " 0 -- use default semantics.\n");
186
187 int ql2xetsenable;
188 module_param(ql2xetsenable, int, S_IRUGO);
189 MODULE_PARM_DESC(ql2xetsenable,
190 "Enables firmware ETS burst."
191 "Default is 0 - skip ETS enablement.");
192
193 int ql2xdbwr = 1;
194 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
195 MODULE_PARM_DESC(ql2xdbwr,
196 "Option to specify scheme for request queue posting.\n"
197 " 0 -- Regular doorbell.\n"
198 " 1 -- CAMRAM doorbell (faster).\n");
199
200 int ql2xgffidenable;
201 module_param(ql2xgffidenable, int, S_IRUGO);
202 MODULE_PARM_DESC(ql2xgffidenable,
203 "Enables GFF_ID checks of port type. "
204 "Default is 0 - Do not use GFF_ID information.");
205
206 int ql2xasynctmfenable = 1;
207 module_param(ql2xasynctmfenable, int, S_IRUGO);
208 MODULE_PARM_DESC(ql2xasynctmfenable,
209 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
210 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
211
212 int ql2xdontresethba;
213 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
214 MODULE_PARM_DESC(ql2xdontresethba,
215 "Option to specify reset behaviour.\n"
216 " 0 (Default) -- Reset on failure.\n"
217 " 1 -- Do not reset on failure.\n");
218
219 uint64_t ql2xmaxlun = MAX_LUNS;
220 module_param(ql2xmaxlun, ullong, S_IRUGO);
221 MODULE_PARM_DESC(ql2xmaxlun,
222 "Defines the maximum LU number to register with the SCSI "
223 "midlayer. Default is 65535.");
224
225 int ql2xmdcapmask = 0x1F;
226 module_param(ql2xmdcapmask, int, S_IRUGO);
227 MODULE_PARM_DESC(ql2xmdcapmask,
228 "Set the Minidump driver capture mask level. "
229 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
230
231 int ql2xmdenable = 1;
232 module_param(ql2xmdenable, int, S_IRUGO);
233 MODULE_PARM_DESC(ql2xmdenable,
234 "Enable/disable MiniDump. "
235 "0 - MiniDump disabled. "
236 "1 (Default) - MiniDump enabled.");
237
238 int ql2xexlogins;
239 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
240 MODULE_PARM_DESC(ql2xexlogins,
241 "Number of extended Logins. "
242 "0 (Default)- Disabled.");
243
244 int ql2xexchoffld = 1024;
245 module_param(ql2xexchoffld, uint, 0644);
246 MODULE_PARM_DESC(ql2xexchoffld,
247 "Number of target exchanges.");
248
249 int ql2xiniexchg = 1024;
250 module_param(ql2xiniexchg, uint, 0644);
251 MODULE_PARM_DESC(ql2xiniexchg,
252 "Number of initiator exchanges.");
253
254 int ql2xfwholdabts;
255 module_param(ql2xfwholdabts, int, S_IRUGO);
256 MODULE_PARM_DESC(ql2xfwholdabts,
257 "Allow FW to hold status IOCB until ABTS rsp received. "
258 "0 (Default) Do not set fw option. "
259 "1 - Set fw option to hold ABTS.");
260
261 int ql2xmvasynctoatio = 1;
262 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
263 MODULE_PARM_DESC(ql2xmvasynctoatio,
264 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
265 "0 (Default). Do not move IOCBs"
266 "1 - Move IOCBs.");
267
268 int ql2xautodetectsfp = 1;
269 module_param(ql2xautodetectsfp, int, 0444);
270 MODULE_PARM_DESC(ql2xautodetectsfp,
271 "Detect SFP range and set appropriate distance.\n"
272 "1 (Default): Enable\n");
273
274 int ql2xenablemsix = 1;
275 module_param(ql2xenablemsix, int, 0444);
276 MODULE_PARM_DESC(ql2xenablemsix,
277 "Set to enable MSI or MSI-X interrupt mechanism.\n"
278 " Default is 1, enable MSI-X interrupt mechanism.\n"
279 " 0 -- enable traditional pin-based mechanism.\n"
280 " 1 -- enable MSI-X interrupt mechanism.\n"
281 " 2 -- enable MSI interrupt mechanism.\n");
282
283 int qla2xuseresexchforels;
284 module_param(qla2xuseresexchforels, int, 0444);
285 MODULE_PARM_DESC(qla2xuseresexchforels,
286 "Reserve 1/2 of emergency exchanges for ELS.\n"
287 " 0 (default): disabled");
288
289 static int ql2xprotmask;
290 module_param(ql2xprotmask, int, 0644);
291 MODULE_PARM_DESC(ql2xprotmask,
292 "Override DIF/DIX protection capabilities mask\n"
293 "Default is 0 which sets protection mask based on "
294 "capabilities reported by HBA firmware.\n");
295
296 static int ql2xprotguard;
297 module_param(ql2xprotguard, int, 0644);
298 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
299 " 0 -- Let HBA firmware decide\n"
300 " 1 -- Force T10 CRC\n"
301 " 2 -- Force IP checksum\n");
302
303 int ql2xdifbundlinginternalbuffers;
304 module_param(ql2xdifbundlinginternalbuffers, int, 0644);
305 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
306 "Force using internal buffers for DIF information\n"
307 "0 (Default). Based on check.\n"
308 "1 Force using internal buffers\n");
309
310 int ql2xsmartsan;
311 module_param(ql2xsmartsan, int, 0444);
312 module_param_named(smartsan, ql2xsmartsan, int, 0444);
313 MODULE_PARM_DESC(ql2xsmartsan,
314 "Send SmartSAN Management Attributes for FDMI Registration."
315 " Default is 0 - No SmartSAN registration,"
316 " 1 - Register SmartSAN Management Attributes.");
317
318 int ql2xrdpenable;
319 module_param(ql2xrdpenable, int, 0444);
320 module_param_named(rdpenable, ql2xrdpenable, int, 0444);
321 MODULE_PARM_DESC(ql2xrdpenable,
322 "Enables RDP responses. "
323 "0 - no RDP responses (default). "
324 "1 - provide RDP responses.");
325
326 static void qla2x00_clear_drv_active(struct qla_hw_data *);
327 static void qla2x00_free_device(scsi_qla_host_t *);
328 static int qla2xxx_map_queues(struct Scsi_Host *shost);
329 static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
330
331
332 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
333 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
334
335 /* TODO Convert to inlines
336 *
337 * Timer routines
338 */
339
340 __inline__ void
qla2x00_start_timer(scsi_qla_host_t * vha,unsigned long interval)341 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
342 {
343 timer_setup(&vha->timer, qla2x00_timer, 0);
344 vha->timer.expires = jiffies + interval * HZ;
345 add_timer(&vha->timer);
346 vha->timer_active = 1;
347 }
348
349 static inline void
qla2x00_restart_timer(scsi_qla_host_t * vha,unsigned long interval)350 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
351 {
352 /* Currently used for 82XX only. */
353 if (vha->device_flags & DFLG_DEV_FAILED) {
354 ql_dbg(ql_dbg_timer, vha, 0x600d,
355 "Device in a failed state, returning.\n");
356 return;
357 }
358
359 mod_timer(&vha->timer, jiffies + interval * HZ);
360 }
361
362 static __inline__ void
qla2x00_stop_timer(scsi_qla_host_t * vha)363 qla2x00_stop_timer(scsi_qla_host_t *vha)
364 {
365 del_timer_sync(&vha->timer);
366 vha->timer_active = 0;
367 }
368
369 static int qla2x00_do_dpc(void *data);
370
371 static void qla2x00_rst_aen(scsi_qla_host_t *);
372
373 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
374 struct req_que **, struct rsp_que **);
375 static void qla2x00_free_fw_dump(struct qla_hw_data *);
376 static void qla2x00_mem_free(struct qla_hw_data *);
377 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
378 struct qla_qpair *qpair);
379
380 /* -------------------------------------------------------------------------- */
qla_init_base_qpair(struct scsi_qla_host * vha,struct req_que * req,struct rsp_que * rsp)381 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
382 struct rsp_que *rsp)
383 {
384 struct qla_hw_data *ha = vha->hw;
385
386 rsp->qpair = ha->base_qpair;
387 rsp->req = req;
388 ha->base_qpair->hw = ha;
389 ha->base_qpair->req = req;
390 ha->base_qpair->rsp = rsp;
391 ha->base_qpair->vha = vha;
392 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
393 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
394 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
395 ha->base_qpair->srb_mempool = ha->srb_mempool;
396 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
397 ha->base_qpair->enable_class_2 = ql2xenableclass2;
398 /* init qpair to this cpu. Will adjust at run time. */
399 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
400 ha->base_qpair->pdev = ha->pdev;
401
402 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
403 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
404 }
405
qla2x00_alloc_queues(struct qla_hw_data * ha,struct req_que * req,struct rsp_que * rsp)406 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
407 struct rsp_que *rsp)
408 {
409 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
410
411 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
412 GFP_KERNEL);
413 if (!ha->req_q_map) {
414 ql_log(ql_log_fatal, vha, 0x003b,
415 "Unable to allocate memory for request queue ptrs.\n");
416 goto fail_req_map;
417 }
418
419 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
420 GFP_KERNEL);
421 if (!ha->rsp_q_map) {
422 ql_log(ql_log_fatal, vha, 0x003c,
423 "Unable to allocate memory for response queue ptrs.\n");
424 goto fail_rsp_map;
425 }
426
427 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
428 if (ha->base_qpair == NULL) {
429 ql_log(ql_log_warn, vha, 0x00e0,
430 "Failed to allocate base queue pair memory.\n");
431 goto fail_base_qpair;
432 }
433
434 qla_init_base_qpair(vha, req, rsp);
435
436 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
437 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
438 GFP_KERNEL);
439 if (!ha->queue_pair_map) {
440 ql_log(ql_log_fatal, vha, 0x0180,
441 "Unable to allocate memory for queue pair ptrs.\n");
442 goto fail_qpair_map;
443 }
444 }
445
446 /*
447 * Make sure we record at least the request and response queue zero in
448 * case we need to free them if part of the probe fails.
449 */
450 ha->rsp_q_map[0] = rsp;
451 ha->req_q_map[0] = req;
452 set_bit(0, ha->rsp_qid_map);
453 set_bit(0, ha->req_qid_map);
454 return 0;
455
456 fail_qpair_map:
457 kfree(ha->base_qpair);
458 ha->base_qpair = NULL;
459 fail_base_qpair:
460 kfree(ha->rsp_q_map);
461 ha->rsp_q_map = NULL;
462 fail_rsp_map:
463 kfree(ha->req_q_map);
464 ha->req_q_map = NULL;
465 fail_req_map:
466 return -ENOMEM;
467 }
468
qla2x00_free_req_que(struct qla_hw_data * ha,struct req_que * req)469 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
470 {
471 if (IS_QLAFX00(ha)) {
472 if (req && req->ring_fx00)
473 dma_free_coherent(&ha->pdev->dev,
474 (req->length_fx00 + 1) * sizeof(request_t),
475 req->ring_fx00, req->dma_fx00);
476 } else if (req && req->ring)
477 dma_free_coherent(&ha->pdev->dev,
478 (req->length + 1) * sizeof(request_t),
479 req->ring, req->dma);
480
481 if (req)
482 kfree(req->outstanding_cmds);
483
484 kfree(req);
485 }
486
qla2x00_free_rsp_que(struct qla_hw_data * ha,struct rsp_que * rsp)487 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
488 {
489 if (IS_QLAFX00(ha)) {
490 if (rsp && rsp->ring_fx00)
491 dma_free_coherent(&ha->pdev->dev,
492 (rsp->length_fx00 + 1) * sizeof(request_t),
493 rsp->ring_fx00, rsp->dma_fx00);
494 } else if (rsp && rsp->ring) {
495 dma_free_coherent(&ha->pdev->dev,
496 (rsp->length + 1) * sizeof(response_t),
497 rsp->ring, rsp->dma);
498 }
499 kfree(rsp);
500 }
501
qla2x00_free_queues(struct qla_hw_data * ha)502 static void qla2x00_free_queues(struct qla_hw_data *ha)
503 {
504 struct req_que *req;
505 struct rsp_que *rsp;
506 int cnt;
507 unsigned long flags;
508
509 if (ha->queue_pair_map) {
510 kfree(ha->queue_pair_map);
511 ha->queue_pair_map = NULL;
512 }
513 if (ha->base_qpair) {
514 kfree(ha->base_qpair);
515 ha->base_qpair = NULL;
516 }
517
518 spin_lock_irqsave(&ha->hardware_lock, flags);
519 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
520 if (!test_bit(cnt, ha->req_qid_map))
521 continue;
522
523 req = ha->req_q_map[cnt];
524 clear_bit(cnt, ha->req_qid_map);
525 ha->req_q_map[cnt] = NULL;
526
527 spin_unlock_irqrestore(&ha->hardware_lock, flags);
528 qla2x00_free_req_que(ha, req);
529 spin_lock_irqsave(&ha->hardware_lock, flags);
530 }
531 spin_unlock_irqrestore(&ha->hardware_lock, flags);
532
533 kfree(ha->req_q_map);
534 ha->req_q_map = NULL;
535
536
537 spin_lock_irqsave(&ha->hardware_lock, flags);
538 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
539 if (!test_bit(cnt, ha->rsp_qid_map))
540 continue;
541
542 rsp = ha->rsp_q_map[cnt];
543 clear_bit(cnt, ha->rsp_qid_map);
544 ha->rsp_q_map[cnt] = NULL;
545 spin_unlock_irqrestore(&ha->hardware_lock, flags);
546 qla2x00_free_rsp_que(ha, rsp);
547 spin_lock_irqsave(&ha->hardware_lock, flags);
548 }
549 spin_unlock_irqrestore(&ha->hardware_lock, flags);
550
551 kfree(ha->rsp_q_map);
552 ha->rsp_q_map = NULL;
553 }
554
555 static char *
qla2x00_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)556 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
557 {
558 struct qla_hw_data *ha = vha->hw;
559 static const char *const pci_bus_modes[] = {
560 "33", "66", "100", "133",
561 };
562 uint16_t pci_bus;
563
564 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
565 if (pci_bus) {
566 snprintf(str, str_len, "PCI-X (%s MHz)",
567 pci_bus_modes[pci_bus]);
568 } else {
569 pci_bus = (ha->pci_attr & BIT_8) >> 8;
570 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
571 }
572
573 return str;
574 }
575
576 static char *
qla24xx_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)577 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
578 {
579 static const char *const pci_bus_modes[] = {
580 "33", "66", "100", "133",
581 };
582 struct qla_hw_data *ha = vha->hw;
583 uint32_t pci_bus;
584
585 if (pci_is_pcie(ha->pdev)) {
586 uint32_t lstat, lspeed, lwidth;
587 const char *speed_str;
588
589 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
590 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
591 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
592
593 switch (lspeed) {
594 case 1:
595 speed_str = "2.5GT/s";
596 break;
597 case 2:
598 speed_str = "5.0GT/s";
599 break;
600 case 3:
601 speed_str = "8.0GT/s";
602 break;
603 case 4:
604 speed_str = "16.0GT/s";
605 break;
606 default:
607 speed_str = "<unknown>";
608 break;
609 }
610 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
611
612 return str;
613 }
614
615 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
616 if (pci_bus == 0 || pci_bus == 8)
617 snprintf(str, str_len, "PCI (%s MHz)",
618 pci_bus_modes[pci_bus >> 3]);
619 else
620 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
621 pci_bus & 4 ? 2 : 1,
622 pci_bus_modes[pci_bus & 3]);
623
624 return str;
625 }
626
627 static char *
qla2x00_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)628 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
629 {
630 char un_str[10];
631 struct qla_hw_data *ha = vha->hw;
632
633 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
634 ha->fw_minor_version, ha->fw_subminor_version);
635
636 if (ha->fw_attributes & BIT_9) {
637 strcat(str, "FLX");
638 return (str);
639 }
640
641 switch (ha->fw_attributes & 0xFF) {
642 case 0x7:
643 strcat(str, "EF");
644 break;
645 case 0x17:
646 strcat(str, "TP");
647 break;
648 case 0x37:
649 strcat(str, "IP");
650 break;
651 case 0x77:
652 strcat(str, "VI");
653 break;
654 default:
655 sprintf(un_str, "(%x)", ha->fw_attributes);
656 strcat(str, un_str);
657 break;
658 }
659 if (ha->fw_attributes & 0x100)
660 strcat(str, "X");
661
662 return (str);
663 }
664
665 static char *
qla24xx_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)666 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
667 {
668 struct qla_hw_data *ha = vha->hw;
669
670 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
671 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
672 return str;
673 }
674
qla2x00_sp_free_dma(srb_t * sp)675 void qla2x00_sp_free_dma(srb_t *sp)
676 {
677 struct qla_hw_data *ha = sp->vha->hw;
678 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
679
680 if (sp->flags & SRB_DMA_VALID) {
681 scsi_dma_unmap(cmd);
682 sp->flags &= ~SRB_DMA_VALID;
683 }
684
685 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
686 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
687 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
688 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
689 }
690
691 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
692 /* List assured to be having elements */
693 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
694 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
695 }
696
697 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
698 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
699
700 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
701 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
702 }
703
704 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
705 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx;
706
707 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
708 ctx1->fcp_cmnd_dma);
709 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
710 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
711 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
712 mempool_free(ctx1, ha->ctx_mempool);
713 }
714 }
715
qla2x00_sp_compl(srb_t * sp,int res)716 void qla2x00_sp_compl(srb_t *sp, int res)
717 {
718 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
719 struct completion *comp = sp->comp;
720
721 sp->free(sp);
722 cmd->result = res;
723 CMD_SP(cmd) = NULL;
724 cmd->scsi_done(cmd);
725 if (comp)
726 complete(comp);
727 }
728
qla2xxx_qpair_sp_free_dma(srb_t * sp)729 void qla2xxx_qpair_sp_free_dma(srb_t *sp)
730 {
731 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
732 struct qla_hw_data *ha = sp->fcport->vha->hw;
733
734 if (sp->flags & SRB_DMA_VALID) {
735 scsi_dma_unmap(cmd);
736 sp->flags &= ~SRB_DMA_VALID;
737 }
738
739 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
740 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
741 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
742 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
743 }
744
745 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
746 /* List assured to be having elements */
747 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
748 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
749 }
750
751 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
752 struct crc_context *difctx = sp->u.scmd.crc_ctx;
753 struct dsd_dma *dif_dsd, *nxt_dsd;
754
755 list_for_each_entry_safe(dif_dsd, nxt_dsd,
756 &difctx->ldif_dma_hndl_list, list) {
757 list_del(&dif_dsd->list);
758 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
759 dif_dsd->dsd_list_dma);
760 kfree(dif_dsd);
761 difctx->no_dif_bundl--;
762 }
763
764 list_for_each_entry_safe(dif_dsd, nxt_dsd,
765 &difctx->ldif_dsd_list, list) {
766 list_del(&dif_dsd->list);
767 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
768 dif_dsd->dsd_list_dma);
769 kfree(dif_dsd);
770 difctx->no_ldif_dsd--;
771 }
772
773 if (difctx->no_ldif_dsd) {
774 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
775 "%s: difctx->no_ldif_dsd=%x\n",
776 __func__, difctx->no_ldif_dsd);
777 }
778
779 if (difctx->no_dif_bundl) {
780 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
781 "%s: difctx->no_dif_bundl=%x\n",
782 __func__, difctx->no_dif_bundl);
783 }
784 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
785 }
786
787 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
788 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx;
789
790 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
791 ctx1->fcp_cmnd_dma);
792 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
793 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
794 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
795 mempool_free(ctx1, ha->ctx_mempool);
796 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
797 }
798
799 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
800 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
801
802 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
803 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
804 }
805 }
806
qla2xxx_qpair_sp_compl(srb_t * sp,int res)807 void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
808 {
809 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
810 struct completion *comp = sp->comp;
811
812 sp->free(sp);
813 cmd->result = res;
814 CMD_SP(cmd) = NULL;
815 cmd->scsi_done(cmd);
816 if (comp)
817 complete(comp);
818 }
819
820 static int
qla2xxx_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)821 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
822 {
823 scsi_qla_host_t *vha = shost_priv(host);
824 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
825 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
826 struct qla_hw_data *ha = vha->hw;
827 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
828 srb_t *sp;
829 int rval;
830
831 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
832 WARN_ON_ONCE(!rport)) {
833 cmd->result = DID_NO_CONNECT << 16;
834 goto qc24_fail_command;
835 }
836
837 if (ha->mqenable) {
838 uint32_t tag;
839 uint16_t hwq;
840 struct qla_qpair *qpair = NULL;
841
842 tag = blk_mq_unique_tag(cmd->request);
843 hwq = blk_mq_unique_tag_to_hwq(tag);
844 qpair = ha->queue_pair_map[hwq];
845
846 if (qpair)
847 return qla2xxx_mqueuecommand(host, cmd, qpair);
848 }
849
850 if (ha->flags.eeh_busy) {
851 if (ha->flags.pci_channel_io_perm_failure) {
852 ql_dbg(ql_dbg_aer, vha, 0x9010,
853 "PCI Channel IO permanent failure, exiting "
854 "cmd=%p.\n", cmd);
855 cmd->result = DID_NO_CONNECT << 16;
856 } else {
857 ql_dbg(ql_dbg_aer, vha, 0x9011,
858 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
859 cmd->result = DID_REQUEUE << 16;
860 }
861 goto qc24_fail_command;
862 }
863
864 rval = fc_remote_port_chkready(rport);
865 if (rval) {
866 cmd->result = rval;
867 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
868 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
869 cmd, rval);
870 goto qc24_fail_command;
871 }
872
873 if (!vha->flags.difdix_supported &&
874 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
875 ql_dbg(ql_dbg_io, vha, 0x3004,
876 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
877 cmd);
878 cmd->result = DID_NO_CONNECT << 16;
879 goto qc24_fail_command;
880 }
881
882 if (!fcport) {
883 cmd->result = DID_NO_CONNECT << 16;
884 goto qc24_fail_command;
885 }
886
887 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
888 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
889 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
890 ql_dbg(ql_dbg_io, vha, 0x3005,
891 "Returning DNC, fcport_state=%d loop_state=%d.\n",
892 atomic_read(&fcport->state),
893 atomic_read(&base_vha->loop_state));
894 cmd->result = DID_NO_CONNECT << 16;
895 goto qc24_fail_command;
896 }
897 goto qc24_target_busy;
898 }
899
900 /*
901 * Return target busy if we've received a non-zero retry_delay_timer
902 * in a FCP_RSP.
903 */
904 if (fcport->retry_delay_timestamp == 0) {
905 /* retry delay not set */
906 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
907 fcport->retry_delay_timestamp = 0;
908 else
909 goto qc24_target_busy;
910
911 sp = scsi_cmd_priv(cmd);
912 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
913
914 sp->u.scmd.cmd = cmd;
915 sp->type = SRB_SCSI_CMD;
916
917 CMD_SP(cmd) = (void *)sp;
918 sp->free = qla2x00_sp_free_dma;
919 sp->done = qla2x00_sp_compl;
920
921 rval = ha->isp_ops->start_scsi(sp);
922 if (rval != QLA_SUCCESS) {
923 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
924 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
925 goto qc24_host_busy_free_sp;
926 }
927
928 return 0;
929
930 qc24_host_busy_free_sp:
931 sp->free(sp);
932
933 qc24_target_busy:
934 return SCSI_MLQUEUE_TARGET_BUSY;
935
936 qc24_fail_command:
937 cmd->scsi_done(cmd);
938
939 return 0;
940 }
941
942 /* For MQ supported I/O */
943 int
qla2xxx_mqueuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd,struct qla_qpair * qpair)944 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
945 struct qla_qpair *qpair)
946 {
947 scsi_qla_host_t *vha = shost_priv(host);
948 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
949 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
950 struct qla_hw_data *ha = vha->hw;
951 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
952 srb_t *sp;
953 int rval;
954
955 rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE;
956 if (rval) {
957 cmd->result = rval;
958 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
959 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
960 cmd, rval);
961 goto qc24_fail_command;
962 }
963
964 if (!fcport) {
965 cmd->result = DID_NO_CONNECT << 16;
966 goto qc24_fail_command;
967 }
968
969 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
970 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
971 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
972 ql_dbg(ql_dbg_io, vha, 0x3077,
973 "Returning DNC, fcport_state=%d loop_state=%d.\n",
974 atomic_read(&fcport->state),
975 atomic_read(&base_vha->loop_state));
976 cmd->result = DID_NO_CONNECT << 16;
977 goto qc24_fail_command;
978 }
979 goto qc24_target_busy;
980 }
981
982 /*
983 * Return target busy if we've received a non-zero retry_delay_timer
984 * in a FCP_RSP.
985 */
986 if (fcport->retry_delay_timestamp == 0) {
987 /* retry delay not set */
988 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
989 fcport->retry_delay_timestamp = 0;
990 else
991 goto qc24_target_busy;
992
993 sp = scsi_cmd_priv(cmd);
994 qla2xxx_init_sp(sp, vha, qpair, fcport);
995
996 sp->u.scmd.cmd = cmd;
997 sp->type = SRB_SCSI_CMD;
998 CMD_SP(cmd) = (void *)sp;
999 sp->free = qla2xxx_qpair_sp_free_dma;
1000 sp->done = qla2xxx_qpair_sp_compl;
1001
1002 rval = ha->isp_ops->start_scsi_mq(sp);
1003 if (rval != QLA_SUCCESS) {
1004 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1005 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1006 goto qc24_host_busy_free_sp;
1007 }
1008
1009 return 0;
1010
1011 qc24_host_busy_free_sp:
1012 sp->free(sp);
1013
1014 qc24_target_busy:
1015 return SCSI_MLQUEUE_TARGET_BUSY;
1016
1017 qc24_fail_command:
1018 cmd->scsi_done(cmd);
1019
1020 return 0;
1021 }
1022
1023 /*
1024 * qla2x00_eh_wait_on_command
1025 * Waits for the command to be returned by the Firmware for some
1026 * max time.
1027 *
1028 * Input:
1029 * cmd = Scsi Command to wait on.
1030 *
1031 * Return:
1032 * Completed in time : QLA_SUCCESS
1033 * Did not complete in time : QLA_FUNCTION_FAILED
1034 */
1035 static int
qla2x00_eh_wait_on_command(struct scsi_cmnd * cmd)1036 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1037 {
1038 #define ABORT_POLLING_PERIOD 1000
1039 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
1040 unsigned long wait_iter = ABORT_WAIT_ITER;
1041 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1042 struct qla_hw_data *ha = vha->hw;
1043 int ret = QLA_SUCCESS;
1044
1045 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
1046 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1047 "Return:eh_wait.\n");
1048 return ret;
1049 }
1050
1051 while (CMD_SP(cmd) && wait_iter--) {
1052 msleep(ABORT_POLLING_PERIOD);
1053 }
1054 if (CMD_SP(cmd))
1055 ret = QLA_FUNCTION_FAILED;
1056
1057 return ret;
1058 }
1059
1060 /*
1061 * qla2x00_wait_for_hba_online
1062 * Wait till the HBA is online after going through
1063 * <= MAX_RETRIES_OF_ISP_ABORT or
1064 * finally HBA is disabled ie marked offline
1065 *
1066 * Input:
1067 * ha - pointer to host adapter structure
1068 *
1069 * Note:
1070 * Does context switching-Release SPIN_LOCK
1071 * (if any) before calling this routine.
1072 *
1073 * Return:
1074 * Success (Adapter is online) : 0
1075 * Failed (Adapter is offline/disabled) : 1
1076 */
1077 int
qla2x00_wait_for_hba_online(scsi_qla_host_t * vha)1078 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1079 {
1080 int return_status;
1081 unsigned long wait_online;
1082 struct qla_hw_data *ha = vha->hw;
1083 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1084
1085 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1086 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1087 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1088 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1089 ha->dpc_active) && time_before(jiffies, wait_online)) {
1090
1091 msleep(1000);
1092 }
1093 if (base_vha->flags.online)
1094 return_status = QLA_SUCCESS;
1095 else
1096 return_status = QLA_FUNCTION_FAILED;
1097
1098 return (return_status);
1099 }
1100
test_fcport_count(scsi_qla_host_t * vha)1101 static inline int test_fcport_count(scsi_qla_host_t *vha)
1102 {
1103 struct qla_hw_data *ha = vha->hw;
1104 unsigned long flags;
1105 int res;
1106
1107 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1108 ql_dbg(ql_dbg_init, vha, 0x00ec,
1109 "tgt %p, fcport_count=%d\n",
1110 vha, vha->fcport_count);
1111 res = (vha->fcport_count == 0);
1112 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1113
1114 return res;
1115 }
1116
1117 /*
1118 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1119 * it has dependency on UNLOADING flag to stop device discovery
1120 */
1121 void
qla2x00_wait_for_sess_deletion(scsi_qla_host_t * vha)1122 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1123 {
1124 u8 i;
1125
1126 qla2x00_mark_all_devices_lost(vha);
1127
1128 for (i = 0; i < 10; i++) {
1129 if (wait_event_timeout(vha->fcport_waitQ,
1130 test_fcport_count(vha), HZ) > 0)
1131 break;
1132 }
1133
1134 flush_workqueue(vha->hw->wq);
1135 }
1136
1137 /*
1138 * qla2x00_wait_for_hba_ready
1139 * Wait till the HBA is ready before doing driver unload
1140 *
1141 * Input:
1142 * ha - pointer to host adapter structure
1143 *
1144 * Note:
1145 * Does context switching-Release SPIN_LOCK
1146 * (if any) before calling this routine.
1147 *
1148 */
1149 static void
qla2x00_wait_for_hba_ready(scsi_qla_host_t * vha)1150 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1151 {
1152 struct qla_hw_data *ha = vha->hw;
1153 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1154
1155 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1156 ha->flags.mbox_busy) ||
1157 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1158 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1159 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1160 break;
1161 msleep(1000);
1162 }
1163 }
1164
1165 int
qla2x00_wait_for_chip_reset(scsi_qla_host_t * vha)1166 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1167 {
1168 int return_status;
1169 unsigned long wait_reset;
1170 struct qla_hw_data *ha = vha->hw;
1171 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1172
1173 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1174 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1175 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1176 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1177 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1178
1179 msleep(1000);
1180
1181 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1182 ha->flags.chip_reset_done)
1183 break;
1184 }
1185 if (ha->flags.chip_reset_done)
1186 return_status = QLA_SUCCESS;
1187 else
1188 return_status = QLA_FUNCTION_FAILED;
1189
1190 return return_status;
1191 }
1192
1193 #define ISP_REG_DISCONNECT 0xffffffffU
1194 /**************************************************************************
1195 * qla2x00_isp_reg_stat
1196 *
1197 * Description:
1198 * Read the host status register of ISP before aborting the command.
1199 *
1200 * Input:
1201 * ha = pointer to host adapter structure.
1202 *
1203 *
1204 * Returns:
1205 * Either true or false.
1206 *
1207 * Note: Return true if there is register disconnect.
1208 **************************************************************************/
1209 static inline
qla2x00_isp_reg_stat(struct qla_hw_data * ha)1210 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1211 {
1212 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1213 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
1214
1215 if (IS_P3P_TYPE(ha))
1216 return ((rd_reg_dword(®82->host_int)) == ISP_REG_DISCONNECT);
1217 else
1218 return ((rd_reg_dword(®->host_status)) ==
1219 ISP_REG_DISCONNECT);
1220 }
1221
1222 /**************************************************************************
1223 * qla2xxx_eh_abort
1224 *
1225 * Description:
1226 * The abort function will abort the specified command.
1227 *
1228 * Input:
1229 * cmd = Linux SCSI command packet to be aborted.
1230 *
1231 * Returns:
1232 * Either SUCCESS or FAILED.
1233 *
1234 * Note:
1235 * Only return FAILED if command not returned by firmware.
1236 **************************************************************************/
1237 static int
qla2xxx_eh_abort(struct scsi_cmnd * cmd)1238 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1239 {
1240 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1241 DECLARE_COMPLETION_ONSTACK(comp);
1242 srb_t *sp;
1243 int ret;
1244 unsigned int id;
1245 uint64_t lun;
1246 int rval;
1247 struct qla_hw_data *ha = vha->hw;
1248 uint32_t ratov_j;
1249 struct qla_qpair *qpair;
1250 unsigned long flags;
1251 int fast_fail_status = SUCCESS;
1252
1253 if (qla2x00_isp_reg_stat(ha)) {
1254 ql_log(ql_log_info, vha, 0x8042,
1255 "PCI/Register disconnect, exiting.\n");
1256 return FAILED;
1257 }
1258
1259 /* Save any FAST_IO_FAIL value to return later if abort succeeds */
1260 ret = fc_block_scsi_eh(cmd);
1261 if (ret != 0)
1262 fast_fail_status = ret;
1263
1264 sp = scsi_cmd_priv(cmd);
1265 qpair = sp->qpair;
1266
1267 if ((sp->fcport && sp->fcport->deleted) || !qpair)
1268 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED;
1269
1270 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1271 sp->comp = ∁
1272 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1273
1274
1275 id = cmd->device->id;
1276 lun = cmd->device->lun;
1277
1278 ql_dbg(ql_dbg_taskm, vha, 0x8002,
1279 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1280 vha->host_no, id, lun, sp, cmd, sp->handle);
1281
1282 /*
1283 * Abort will release the original Command/sp from FW. Let the
1284 * original command call scsi_done. In return, he will wakeup
1285 * this sleeping thread.
1286 */
1287 rval = ha->isp_ops->abort_command(sp);
1288
1289 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1290 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
1291
1292 /* Wait for the command completion. */
1293 ratov_j = ha->r_a_tov/10 * 4 * 1000;
1294 ratov_j = msecs_to_jiffies(ratov_j);
1295 switch (rval) {
1296 case QLA_SUCCESS:
1297 if (!wait_for_completion_timeout(&comp, ratov_j)) {
1298 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1299 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1300 __func__, ha->r_a_tov/10);
1301 ret = FAILED;
1302 } else {
1303 ret = fast_fail_status;
1304 }
1305 break;
1306 default:
1307 ret = FAILED;
1308 break;
1309 }
1310
1311 sp->comp = NULL;
1312
1313 ql_log(ql_log_info, vha, 0x801c,
1314 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1315 vha->host_no, id, lun, ret);
1316
1317 return ret;
1318 }
1319
1320 /*
1321 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1322 */
1323 int
qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t * vha,unsigned int t,uint64_t l,enum nexus_wait_type type)1324 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1325 uint64_t l, enum nexus_wait_type type)
1326 {
1327 int cnt, match, status;
1328 unsigned long flags;
1329 struct qla_hw_data *ha = vha->hw;
1330 struct req_que *req;
1331 srb_t *sp;
1332 struct scsi_cmnd *cmd;
1333
1334 status = QLA_SUCCESS;
1335
1336 spin_lock_irqsave(&ha->hardware_lock, flags);
1337 req = vha->req;
1338 for (cnt = 1; status == QLA_SUCCESS &&
1339 cnt < req->num_outstanding_cmds; cnt++) {
1340 sp = req->outstanding_cmds[cnt];
1341 if (!sp)
1342 continue;
1343 if (sp->type != SRB_SCSI_CMD)
1344 continue;
1345 if (vha->vp_idx != sp->vha->vp_idx)
1346 continue;
1347 match = 0;
1348 cmd = GET_CMD_SP(sp);
1349 switch (type) {
1350 case WAIT_HOST:
1351 match = 1;
1352 break;
1353 case WAIT_TARGET:
1354 match = cmd->device->id == t;
1355 break;
1356 case WAIT_LUN:
1357 match = (cmd->device->id == t &&
1358 cmd->device->lun == l);
1359 break;
1360 }
1361 if (!match)
1362 continue;
1363
1364 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1365 status = qla2x00_eh_wait_on_command(cmd);
1366 spin_lock_irqsave(&ha->hardware_lock, flags);
1367 }
1368 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1369
1370 return status;
1371 }
1372
1373 static char *reset_errors[] = {
1374 "HBA not online",
1375 "HBA not ready",
1376 "Task management failed",
1377 "Waiting for command completions",
1378 };
1379
1380 static int
__qla2xxx_eh_generic_reset(char * name,enum nexus_wait_type type,struct scsi_cmnd * cmd,int (* do_reset)(struct fc_port *,uint64_t,int))1381 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1382 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1383 {
1384 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1385 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1386 int err;
1387
1388 if (!fcport) {
1389 return FAILED;
1390 }
1391
1392 err = fc_block_scsi_eh(cmd);
1393 if (err != 0)
1394 return err;
1395
1396 if (fcport->deleted)
1397 return SUCCESS;
1398
1399 ql_log(ql_log_info, vha, 0x8009,
1400 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
1401 cmd->device->id, cmd->device->lun, cmd);
1402
1403 err = 0;
1404 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1405 ql_log(ql_log_warn, vha, 0x800a,
1406 "Wait for hba online failed for cmd=%p.\n", cmd);
1407 goto eh_reset_failed;
1408 }
1409 err = 2;
1410 if (do_reset(fcport, cmd->device->lun, 1)
1411 != QLA_SUCCESS) {
1412 ql_log(ql_log_warn, vha, 0x800c,
1413 "do_reset failed for cmd=%p.\n", cmd);
1414 goto eh_reset_failed;
1415 }
1416 err = 3;
1417 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1418 cmd->device->lun, type) != QLA_SUCCESS) {
1419 ql_log(ql_log_warn, vha, 0x800d,
1420 "wait for pending cmds failed for cmd=%p.\n", cmd);
1421 goto eh_reset_failed;
1422 }
1423
1424 ql_log(ql_log_info, vha, 0x800e,
1425 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
1426 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1427
1428 return SUCCESS;
1429
1430 eh_reset_failed:
1431 ql_log(ql_log_info, vha, 0x800f,
1432 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
1433 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1434 cmd);
1435 return FAILED;
1436 }
1437
1438 static int
qla2xxx_eh_device_reset(struct scsi_cmnd * cmd)1439 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1440 {
1441 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1442 struct qla_hw_data *ha = vha->hw;
1443
1444 if (qla2x00_isp_reg_stat(ha)) {
1445 ql_log(ql_log_info, vha, 0x803e,
1446 "PCI/Register disconnect, exiting.\n");
1447 return FAILED;
1448 }
1449
1450 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1451 ha->isp_ops->lun_reset);
1452 }
1453
1454 static int
qla2xxx_eh_target_reset(struct scsi_cmnd * cmd)1455 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1456 {
1457 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1458 struct qla_hw_data *ha = vha->hw;
1459
1460 if (qla2x00_isp_reg_stat(ha)) {
1461 ql_log(ql_log_info, vha, 0x803f,
1462 "PCI/Register disconnect, exiting.\n");
1463 return FAILED;
1464 }
1465
1466 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1467 ha->isp_ops->target_reset);
1468 }
1469
1470 /**************************************************************************
1471 * qla2xxx_eh_bus_reset
1472 *
1473 * Description:
1474 * The bus reset function will reset the bus and abort any executing
1475 * commands.
1476 *
1477 * Input:
1478 * cmd = Linux SCSI command packet of the command that cause the
1479 * bus reset.
1480 *
1481 * Returns:
1482 * SUCCESS/FAILURE (defined as macro in scsi.h).
1483 *
1484 **************************************************************************/
1485 static int
qla2xxx_eh_bus_reset(struct scsi_cmnd * cmd)1486 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1487 {
1488 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1489 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1490 int ret = FAILED;
1491 unsigned int id;
1492 uint64_t lun;
1493 struct qla_hw_data *ha = vha->hw;
1494
1495 if (qla2x00_isp_reg_stat(ha)) {
1496 ql_log(ql_log_info, vha, 0x8040,
1497 "PCI/Register disconnect, exiting.\n");
1498 return FAILED;
1499 }
1500
1501 id = cmd->device->id;
1502 lun = cmd->device->lun;
1503
1504 if (!fcport) {
1505 return ret;
1506 }
1507
1508 ret = fc_block_scsi_eh(cmd);
1509 if (ret != 0)
1510 return ret;
1511 ret = FAILED;
1512
1513 if (qla2x00_chip_is_down(vha))
1514 return ret;
1515
1516 ql_log(ql_log_info, vha, 0x8012,
1517 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1518
1519 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1520 ql_log(ql_log_fatal, vha, 0x8013,
1521 "Wait for hba online failed board disabled.\n");
1522 goto eh_bus_reset_done;
1523 }
1524
1525 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1526 ret = SUCCESS;
1527
1528 if (ret == FAILED)
1529 goto eh_bus_reset_done;
1530
1531 /* Flush outstanding commands. */
1532 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1533 QLA_SUCCESS) {
1534 ql_log(ql_log_warn, vha, 0x8014,
1535 "Wait for pending commands failed.\n");
1536 ret = FAILED;
1537 }
1538
1539 eh_bus_reset_done:
1540 ql_log(ql_log_warn, vha, 0x802b,
1541 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1542 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1543
1544 return ret;
1545 }
1546
1547 /**************************************************************************
1548 * qla2xxx_eh_host_reset
1549 *
1550 * Description:
1551 * The reset function will reset the Adapter.
1552 *
1553 * Input:
1554 * cmd = Linux SCSI command packet of the command that cause the
1555 * adapter reset.
1556 *
1557 * Returns:
1558 * Either SUCCESS or FAILED.
1559 *
1560 * Note:
1561 **************************************************************************/
1562 static int
qla2xxx_eh_host_reset(struct scsi_cmnd * cmd)1563 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1564 {
1565 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1566 struct qla_hw_data *ha = vha->hw;
1567 int ret = FAILED;
1568 unsigned int id;
1569 uint64_t lun;
1570 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1571
1572 if (qla2x00_isp_reg_stat(ha)) {
1573 ql_log(ql_log_info, vha, 0x8041,
1574 "PCI/Register disconnect, exiting.\n");
1575 schedule_work(&ha->board_disable);
1576 return SUCCESS;
1577 }
1578
1579 id = cmd->device->id;
1580 lun = cmd->device->lun;
1581
1582 ql_log(ql_log_info, vha, 0x8018,
1583 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1584
1585 /*
1586 * No point in issuing another reset if one is active. Also do not
1587 * attempt a reset if we are updating flash.
1588 */
1589 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1590 goto eh_host_reset_lock;
1591
1592 if (vha != base_vha) {
1593 if (qla2x00_vp_abort_isp(vha))
1594 goto eh_host_reset_lock;
1595 } else {
1596 if (IS_P3P_TYPE(vha->hw)) {
1597 if (!qla82xx_fcoe_ctx_reset(vha)) {
1598 /* Ctx reset success */
1599 ret = SUCCESS;
1600 goto eh_host_reset_lock;
1601 }
1602 /* fall thru if ctx reset failed */
1603 }
1604 if (ha->wq)
1605 flush_workqueue(ha->wq);
1606
1607 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1608 if (ha->isp_ops->abort_isp(base_vha)) {
1609 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1610 /* failed. schedule dpc to try */
1611 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1612
1613 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1614 ql_log(ql_log_warn, vha, 0x802a,
1615 "wait for hba online failed.\n");
1616 goto eh_host_reset_lock;
1617 }
1618 }
1619 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1620 }
1621
1622 /* Waiting for command to be returned to OS.*/
1623 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1624 QLA_SUCCESS)
1625 ret = SUCCESS;
1626
1627 eh_host_reset_lock:
1628 ql_log(ql_log_info, vha, 0x8017,
1629 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1630 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1631
1632 return ret;
1633 }
1634
1635 /*
1636 * qla2x00_loop_reset
1637 * Issue loop reset.
1638 *
1639 * Input:
1640 * ha = adapter block pointer.
1641 *
1642 * Returns:
1643 * 0 = success
1644 */
1645 int
qla2x00_loop_reset(scsi_qla_host_t * vha)1646 qla2x00_loop_reset(scsi_qla_host_t *vha)
1647 {
1648 int ret;
1649 struct qla_hw_data *ha = vha->hw;
1650
1651 if (IS_QLAFX00(ha))
1652 return QLA_SUCCESS;
1653
1654 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1655 atomic_set(&vha->loop_state, LOOP_DOWN);
1656 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1657 qla2x00_mark_all_devices_lost(vha);
1658 ret = qla2x00_full_login_lip(vha);
1659 if (ret != QLA_SUCCESS) {
1660 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1661 "full_login_lip=%d.\n", ret);
1662 }
1663 }
1664
1665 if (ha->flags.enable_lip_reset) {
1666 ret = qla2x00_lip_reset(vha);
1667 if (ret != QLA_SUCCESS)
1668 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1669 "lip_reset failed (%d).\n", ret);
1670 }
1671
1672 /* Issue marker command only when we are going to start the I/O */
1673 vha->marker_needed = 1;
1674
1675 return QLA_SUCCESS;
1676 }
1677
1678 /*
1679 * The caller must ensure that no completion interrupts will happen
1680 * while this function is in progress.
1681 */
qla2x00_abort_srb(struct qla_qpair * qp,srb_t * sp,const int res,unsigned long * flags)1682 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1683 unsigned long *flags)
1684 __releases(qp->qp_lock_ptr)
1685 __acquires(qp->qp_lock_ptr)
1686 {
1687 DECLARE_COMPLETION_ONSTACK(comp);
1688 scsi_qla_host_t *vha = qp->vha;
1689 struct qla_hw_data *ha = vha->hw;
1690 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1691 int rval;
1692 bool ret_cmd;
1693 uint32_t ratov_j;
1694
1695 lockdep_assert_held(qp->qp_lock_ptr);
1696
1697 if (qla2x00_chip_is_down(vha)) {
1698 sp->done(sp, res);
1699 return;
1700 }
1701
1702 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1703 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1704 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1705 !qla2x00_isp_reg_stat(ha))) {
1706 if (sp->comp) {
1707 sp->done(sp, res);
1708 return;
1709 }
1710
1711 sp->comp = ∁
1712 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1713
1714 rval = ha->isp_ops->abort_command(sp);
1715 /* Wait for command completion. */
1716 ret_cmd = false;
1717 ratov_j = ha->r_a_tov/10 * 4 * 1000;
1718 ratov_j = msecs_to_jiffies(ratov_j);
1719 switch (rval) {
1720 case QLA_SUCCESS:
1721 if (wait_for_completion_timeout(&comp, ratov_j)) {
1722 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1723 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1724 __func__, ha->r_a_tov/10);
1725 ret_cmd = true;
1726 }
1727 /* else FW return SP to driver */
1728 break;
1729 default:
1730 ret_cmd = true;
1731 break;
1732 }
1733
1734 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1735 if (ret_cmd && blk_mq_request_started(cmd->request))
1736 sp->done(sp, res);
1737 } else {
1738 sp->done(sp, res);
1739 }
1740 }
1741
1742 /*
1743 * The caller must ensure that no completion interrupts will happen
1744 * while this function is in progress.
1745 */
1746 static void
__qla2x00_abort_all_cmds(struct qla_qpair * qp,int res)1747 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
1748 {
1749 int cnt;
1750 unsigned long flags;
1751 srb_t *sp;
1752 scsi_qla_host_t *vha = qp->vha;
1753 struct qla_hw_data *ha = vha->hw;
1754 struct req_que *req;
1755 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1756 struct qla_tgt_cmd *cmd;
1757
1758 if (!ha->req_q_map)
1759 return;
1760 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1761 req = qp->req;
1762 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1763 sp = req->outstanding_cmds[cnt];
1764 if (sp) {
1765 switch (sp->cmd_type) {
1766 case TYPE_SRB:
1767 qla2x00_abort_srb(qp, sp, res, &flags);
1768 break;
1769 case TYPE_TGT_CMD:
1770 if (!vha->hw->tgt.tgt_ops || !tgt ||
1771 qla_ini_mode_enabled(vha)) {
1772 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1773 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1774 vha->dpc_flags);
1775 continue;
1776 }
1777 cmd = (struct qla_tgt_cmd *)sp;
1778 cmd->aborted = 1;
1779 break;
1780 case TYPE_TGT_TMCMD:
1781 /* Skip task management functions. */
1782 break;
1783 default:
1784 break;
1785 }
1786 req->outstanding_cmds[cnt] = NULL;
1787 }
1788 }
1789 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1790 }
1791
1792 /*
1793 * The caller must ensure that no completion interrupts will happen
1794 * while this function is in progress.
1795 */
1796 void
qla2x00_abort_all_cmds(scsi_qla_host_t * vha,int res)1797 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1798 {
1799 int que;
1800 struct qla_hw_data *ha = vha->hw;
1801
1802 /* Continue only if initialization complete. */
1803 if (!ha->base_qpair)
1804 return;
1805 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1806
1807 if (!ha->queue_pair_map)
1808 return;
1809 for (que = 0; que < ha->max_qpairs; que++) {
1810 if (!ha->queue_pair_map[que])
1811 continue;
1812
1813 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1814 }
1815 }
1816
1817 static int
qla2xxx_slave_alloc(struct scsi_device * sdev)1818 qla2xxx_slave_alloc(struct scsi_device *sdev)
1819 {
1820 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1821
1822 if (!rport || fc_remote_port_chkready(rport))
1823 return -ENXIO;
1824
1825 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1826
1827 return 0;
1828 }
1829
1830 static int
qla2xxx_slave_configure(struct scsi_device * sdev)1831 qla2xxx_slave_configure(struct scsi_device *sdev)
1832 {
1833 scsi_qla_host_t *vha = shost_priv(sdev->host);
1834 struct req_que *req = vha->req;
1835
1836 if (IS_T10_PI_CAPABLE(vha->hw))
1837 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1838
1839 scsi_change_queue_depth(sdev, req->max_q_depth);
1840 return 0;
1841 }
1842
1843 static void
qla2xxx_slave_destroy(struct scsi_device * sdev)1844 qla2xxx_slave_destroy(struct scsi_device *sdev)
1845 {
1846 sdev->hostdata = NULL;
1847 }
1848
1849 /**
1850 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1851 * @ha: HA context
1852 *
1853 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1854 * supported addressing method.
1855 */
1856 static void
qla2x00_config_dma_addressing(struct qla_hw_data * ha)1857 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1858 {
1859 /* Assume a 32bit DMA mask. */
1860 ha->flags.enable_64bit_addressing = 0;
1861
1862 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1863 /* Any upper-dword bits set? */
1864 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1865 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1866 /* Ok, a 64bit DMA mask is applicable. */
1867 ha->flags.enable_64bit_addressing = 1;
1868 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1869 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1870 return;
1871 }
1872 }
1873
1874 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1875 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1876 }
1877
1878 static void
qla2x00_enable_intrs(struct qla_hw_data * ha)1879 qla2x00_enable_intrs(struct qla_hw_data *ha)
1880 {
1881 unsigned long flags = 0;
1882 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1883
1884 spin_lock_irqsave(&ha->hardware_lock, flags);
1885 ha->interrupts_on = 1;
1886 /* enable risc and host interrupts */
1887 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC);
1888 rd_reg_word(®->ictrl);
1889 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1890
1891 }
1892
1893 static void
qla2x00_disable_intrs(struct qla_hw_data * ha)1894 qla2x00_disable_intrs(struct qla_hw_data *ha)
1895 {
1896 unsigned long flags = 0;
1897 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1898
1899 spin_lock_irqsave(&ha->hardware_lock, flags);
1900 ha->interrupts_on = 0;
1901 /* disable risc and host interrupts */
1902 wrt_reg_word(®->ictrl, 0);
1903 rd_reg_word(®->ictrl);
1904 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1905 }
1906
1907 static void
qla24xx_enable_intrs(struct qla_hw_data * ha)1908 qla24xx_enable_intrs(struct qla_hw_data *ha)
1909 {
1910 unsigned long flags = 0;
1911 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1912
1913 spin_lock_irqsave(&ha->hardware_lock, flags);
1914 ha->interrupts_on = 1;
1915 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT);
1916 rd_reg_dword(®->ictrl);
1917 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1918 }
1919
1920 static void
qla24xx_disable_intrs(struct qla_hw_data * ha)1921 qla24xx_disable_intrs(struct qla_hw_data *ha)
1922 {
1923 unsigned long flags = 0;
1924 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1925
1926 if (IS_NOPOLLING_TYPE(ha))
1927 return;
1928 spin_lock_irqsave(&ha->hardware_lock, flags);
1929 ha->interrupts_on = 0;
1930 wrt_reg_dword(®->ictrl, 0);
1931 rd_reg_dword(®->ictrl);
1932 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1933 }
1934
1935 static int
qla2x00_iospace_config(struct qla_hw_data * ha)1936 qla2x00_iospace_config(struct qla_hw_data *ha)
1937 {
1938 resource_size_t pio;
1939 uint16_t msix;
1940
1941 if (pci_request_selected_regions(ha->pdev, ha->bars,
1942 QLA2XXX_DRIVER_NAME)) {
1943 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1944 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1945 pci_name(ha->pdev));
1946 goto iospace_error_exit;
1947 }
1948 if (!(ha->bars & 1))
1949 goto skip_pio;
1950
1951 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1952 pio = pci_resource_start(ha->pdev, 0);
1953 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1954 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1955 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1956 "Invalid pci I/O region size (%s).\n",
1957 pci_name(ha->pdev));
1958 pio = 0;
1959 }
1960 } else {
1961 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1962 "Region #0 no a PIO resource (%s).\n",
1963 pci_name(ha->pdev));
1964 pio = 0;
1965 }
1966 ha->pio_address = pio;
1967 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1968 "PIO address=%llu.\n",
1969 (unsigned long long)ha->pio_address);
1970
1971 skip_pio:
1972 /* Use MMIO operations for all accesses. */
1973 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1974 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1975 "Region #1 not an MMIO resource (%s), aborting.\n",
1976 pci_name(ha->pdev));
1977 goto iospace_error_exit;
1978 }
1979 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1980 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1981 "Invalid PCI mem region size (%s), aborting.\n",
1982 pci_name(ha->pdev));
1983 goto iospace_error_exit;
1984 }
1985
1986 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1987 if (!ha->iobase) {
1988 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1989 "Cannot remap MMIO (%s), aborting.\n",
1990 pci_name(ha->pdev));
1991 goto iospace_error_exit;
1992 }
1993
1994 /* Determine queue resources */
1995 ha->max_req_queues = ha->max_rsp_queues = 1;
1996 ha->msix_count = QLA_BASE_VECTORS;
1997
1998 /* Check if FW supports MQ or not */
1999 if (!(ha->fw_attributes & BIT_6))
2000 goto mqiobase_exit;
2001
2002 if (!ql2xmqsupport || !ql2xnvmeenable ||
2003 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
2004 goto mqiobase_exit;
2005
2006 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2007 pci_resource_len(ha->pdev, 3));
2008 if (ha->mqiobase) {
2009 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2010 "MQIO Base=%p.\n", ha->mqiobase);
2011 /* Read MSIX vector size of the board */
2012 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
2013 ha->msix_count = msix + 1;
2014 /* Max queues are bounded by available msix vectors */
2015 /* MB interrupt uses 1 vector */
2016 ha->max_req_queues = ha->msix_count - 1;
2017 ha->max_rsp_queues = ha->max_req_queues;
2018 /* Queue pairs is the max value minus the base queue pair */
2019 ha->max_qpairs = ha->max_rsp_queues - 1;
2020 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2021 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2022
2023 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2024 "MSI-X vector count: %d.\n", ha->msix_count);
2025 } else
2026 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2027 "BAR 3 not enabled.\n");
2028
2029 mqiobase_exit:
2030 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2031 "MSIX Count: %d.\n", ha->msix_count);
2032 return (0);
2033
2034 iospace_error_exit:
2035 return (-ENOMEM);
2036 }
2037
2038
2039 static int
qla83xx_iospace_config(struct qla_hw_data * ha)2040 qla83xx_iospace_config(struct qla_hw_data *ha)
2041 {
2042 uint16_t msix;
2043
2044 if (pci_request_selected_regions(ha->pdev, ha->bars,
2045 QLA2XXX_DRIVER_NAME)) {
2046 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2047 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2048 pci_name(ha->pdev));
2049
2050 goto iospace_error_exit;
2051 }
2052
2053 /* Use MMIO operations for all accesses. */
2054 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2055 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2056 "Invalid pci I/O region size (%s).\n",
2057 pci_name(ha->pdev));
2058 goto iospace_error_exit;
2059 }
2060 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2061 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2062 "Invalid PCI mem region size (%s), aborting\n",
2063 pci_name(ha->pdev));
2064 goto iospace_error_exit;
2065 }
2066
2067 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2068 if (!ha->iobase) {
2069 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2070 "Cannot remap MMIO (%s), aborting.\n",
2071 pci_name(ha->pdev));
2072 goto iospace_error_exit;
2073 }
2074
2075 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2076 /* 83XX 26XX always use MQ type access for queues
2077 * - mbar 2, a.k.a region 4 */
2078 ha->max_req_queues = ha->max_rsp_queues = 1;
2079 ha->msix_count = QLA_BASE_VECTORS;
2080 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2081 pci_resource_len(ha->pdev, 4));
2082
2083 if (!ha->mqiobase) {
2084 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2085 "BAR2/region4 not enabled\n");
2086 goto mqiobase_exit;
2087 }
2088
2089 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2090 pci_resource_len(ha->pdev, 2));
2091 if (ha->msixbase) {
2092 /* Read MSIX vector size of the board */
2093 pci_read_config_word(ha->pdev,
2094 QLA_83XX_PCI_MSIX_CONTROL, &msix);
2095 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
2096 /*
2097 * By default, driver uses at least two msix vectors
2098 * (default & rspq)
2099 */
2100 if (ql2xmqsupport || ql2xnvmeenable) {
2101 /* MB interrupt uses 1 vector */
2102 ha->max_req_queues = ha->msix_count - 1;
2103
2104 /* ATIOQ needs 1 vector. That's 1 less QPair */
2105 if (QLA_TGT_MODE_ENABLED())
2106 ha->max_req_queues--;
2107
2108 ha->max_rsp_queues = ha->max_req_queues;
2109
2110 /* Queue pairs is the max value minus
2111 * the base queue pair */
2112 ha->max_qpairs = ha->max_req_queues - 1;
2113 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2114 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2115 }
2116 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2117 "MSI-X vector count: %d.\n", ha->msix_count);
2118 } else
2119 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2120 "BAR 1 not enabled.\n");
2121
2122 mqiobase_exit:
2123 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2124 "MSIX Count: %d.\n", ha->msix_count);
2125 return 0;
2126
2127 iospace_error_exit:
2128 return -ENOMEM;
2129 }
2130
2131 static struct isp_operations qla2100_isp_ops = {
2132 .pci_config = qla2100_pci_config,
2133 .reset_chip = qla2x00_reset_chip,
2134 .chip_diag = qla2x00_chip_diag,
2135 .config_rings = qla2x00_config_rings,
2136 .reset_adapter = qla2x00_reset_adapter,
2137 .nvram_config = qla2x00_nvram_config,
2138 .update_fw_options = qla2x00_update_fw_options,
2139 .load_risc = qla2x00_load_risc,
2140 .pci_info_str = qla2x00_pci_info_str,
2141 .fw_version_str = qla2x00_fw_version_str,
2142 .intr_handler = qla2100_intr_handler,
2143 .enable_intrs = qla2x00_enable_intrs,
2144 .disable_intrs = qla2x00_disable_intrs,
2145 .abort_command = qla2x00_abort_command,
2146 .target_reset = qla2x00_abort_target,
2147 .lun_reset = qla2x00_lun_reset,
2148 .fabric_login = qla2x00_login_fabric,
2149 .fabric_logout = qla2x00_fabric_logout,
2150 .calc_req_entries = qla2x00_calc_iocbs_32,
2151 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2152 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2153 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2154 .read_nvram = qla2x00_read_nvram_data,
2155 .write_nvram = qla2x00_write_nvram_data,
2156 .fw_dump = qla2100_fw_dump,
2157 .beacon_on = NULL,
2158 .beacon_off = NULL,
2159 .beacon_blink = NULL,
2160 .read_optrom = qla2x00_read_optrom_data,
2161 .write_optrom = qla2x00_write_optrom_data,
2162 .get_flash_version = qla2x00_get_flash_version,
2163 .start_scsi = qla2x00_start_scsi,
2164 .start_scsi_mq = NULL,
2165 .abort_isp = qla2x00_abort_isp,
2166 .iospace_config = qla2x00_iospace_config,
2167 .initialize_adapter = qla2x00_initialize_adapter,
2168 };
2169
2170 static struct isp_operations qla2300_isp_ops = {
2171 .pci_config = qla2300_pci_config,
2172 .reset_chip = qla2x00_reset_chip,
2173 .chip_diag = qla2x00_chip_diag,
2174 .config_rings = qla2x00_config_rings,
2175 .reset_adapter = qla2x00_reset_adapter,
2176 .nvram_config = qla2x00_nvram_config,
2177 .update_fw_options = qla2x00_update_fw_options,
2178 .load_risc = qla2x00_load_risc,
2179 .pci_info_str = qla2x00_pci_info_str,
2180 .fw_version_str = qla2x00_fw_version_str,
2181 .intr_handler = qla2300_intr_handler,
2182 .enable_intrs = qla2x00_enable_intrs,
2183 .disable_intrs = qla2x00_disable_intrs,
2184 .abort_command = qla2x00_abort_command,
2185 .target_reset = qla2x00_abort_target,
2186 .lun_reset = qla2x00_lun_reset,
2187 .fabric_login = qla2x00_login_fabric,
2188 .fabric_logout = qla2x00_fabric_logout,
2189 .calc_req_entries = qla2x00_calc_iocbs_32,
2190 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2191 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2192 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2193 .read_nvram = qla2x00_read_nvram_data,
2194 .write_nvram = qla2x00_write_nvram_data,
2195 .fw_dump = qla2300_fw_dump,
2196 .beacon_on = qla2x00_beacon_on,
2197 .beacon_off = qla2x00_beacon_off,
2198 .beacon_blink = qla2x00_beacon_blink,
2199 .read_optrom = qla2x00_read_optrom_data,
2200 .write_optrom = qla2x00_write_optrom_data,
2201 .get_flash_version = qla2x00_get_flash_version,
2202 .start_scsi = qla2x00_start_scsi,
2203 .start_scsi_mq = NULL,
2204 .abort_isp = qla2x00_abort_isp,
2205 .iospace_config = qla2x00_iospace_config,
2206 .initialize_adapter = qla2x00_initialize_adapter,
2207 };
2208
2209 static struct isp_operations qla24xx_isp_ops = {
2210 .pci_config = qla24xx_pci_config,
2211 .reset_chip = qla24xx_reset_chip,
2212 .chip_diag = qla24xx_chip_diag,
2213 .config_rings = qla24xx_config_rings,
2214 .reset_adapter = qla24xx_reset_adapter,
2215 .nvram_config = qla24xx_nvram_config,
2216 .update_fw_options = qla24xx_update_fw_options,
2217 .load_risc = qla24xx_load_risc,
2218 .pci_info_str = qla24xx_pci_info_str,
2219 .fw_version_str = qla24xx_fw_version_str,
2220 .intr_handler = qla24xx_intr_handler,
2221 .enable_intrs = qla24xx_enable_intrs,
2222 .disable_intrs = qla24xx_disable_intrs,
2223 .abort_command = qla24xx_abort_command,
2224 .target_reset = qla24xx_abort_target,
2225 .lun_reset = qla24xx_lun_reset,
2226 .fabric_login = qla24xx_login_fabric,
2227 .fabric_logout = qla24xx_fabric_logout,
2228 .calc_req_entries = NULL,
2229 .build_iocbs = NULL,
2230 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2231 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2232 .read_nvram = qla24xx_read_nvram_data,
2233 .write_nvram = qla24xx_write_nvram_data,
2234 .fw_dump = qla24xx_fw_dump,
2235 .beacon_on = qla24xx_beacon_on,
2236 .beacon_off = qla24xx_beacon_off,
2237 .beacon_blink = qla24xx_beacon_blink,
2238 .read_optrom = qla24xx_read_optrom_data,
2239 .write_optrom = qla24xx_write_optrom_data,
2240 .get_flash_version = qla24xx_get_flash_version,
2241 .start_scsi = qla24xx_start_scsi,
2242 .start_scsi_mq = NULL,
2243 .abort_isp = qla2x00_abort_isp,
2244 .iospace_config = qla2x00_iospace_config,
2245 .initialize_adapter = qla2x00_initialize_adapter,
2246 };
2247
2248 static struct isp_operations qla25xx_isp_ops = {
2249 .pci_config = qla25xx_pci_config,
2250 .reset_chip = qla24xx_reset_chip,
2251 .chip_diag = qla24xx_chip_diag,
2252 .config_rings = qla24xx_config_rings,
2253 .reset_adapter = qla24xx_reset_adapter,
2254 .nvram_config = qla24xx_nvram_config,
2255 .update_fw_options = qla24xx_update_fw_options,
2256 .load_risc = qla24xx_load_risc,
2257 .pci_info_str = qla24xx_pci_info_str,
2258 .fw_version_str = qla24xx_fw_version_str,
2259 .intr_handler = qla24xx_intr_handler,
2260 .enable_intrs = qla24xx_enable_intrs,
2261 .disable_intrs = qla24xx_disable_intrs,
2262 .abort_command = qla24xx_abort_command,
2263 .target_reset = qla24xx_abort_target,
2264 .lun_reset = qla24xx_lun_reset,
2265 .fabric_login = qla24xx_login_fabric,
2266 .fabric_logout = qla24xx_fabric_logout,
2267 .calc_req_entries = NULL,
2268 .build_iocbs = NULL,
2269 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2270 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2271 .read_nvram = qla25xx_read_nvram_data,
2272 .write_nvram = qla25xx_write_nvram_data,
2273 .fw_dump = qla25xx_fw_dump,
2274 .beacon_on = qla24xx_beacon_on,
2275 .beacon_off = qla24xx_beacon_off,
2276 .beacon_blink = qla24xx_beacon_blink,
2277 .read_optrom = qla25xx_read_optrom_data,
2278 .write_optrom = qla24xx_write_optrom_data,
2279 .get_flash_version = qla24xx_get_flash_version,
2280 .start_scsi = qla24xx_dif_start_scsi,
2281 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2282 .abort_isp = qla2x00_abort_isp,
2283 .iospace_config = qla2x00_iospace_config,
2284 .initialize_adapter = qla2x00_initialize_adapter,
2285 };
2286
2287 static struct isp_operations qla81xx_isp_ops = {
2288 .pci_config = qla25xx_pci_config,
2289 .reset_chip = qla24xx_reset_chip,
2290 .chip_diag = qla24xx_chip_diag,
2291 .config_rings = qla24xx_config_rings,
2292 .reset_adapter = qla24xx_reset_adapter,
2293 .nvram_config = qla81xx_nvram_config,
2294 .update_fw_options = qla24xx_update_fw_options,
2295 .load_risc = qla81xx_load_risc,
2296 .pci_info_str = qla24xx_pci_info_str,
2297 .fw_version_str = qla24xx_fw_version_str,
2298 .intr_handler = qla24xx_intr_handler,
2299 .enable_intrs = qla24xx_enable_intrs,
2300 .disable_intrs = qla24xx_disable_intrs,
2301 .abort_command = qla24xx_abort_command,
2302 .target_reset = qla24xx_abort_target,
2303 .lun_reset = qla24xx_lun_reset,
2304 .fabric_login = qla24xx_login_fabric,
2305 .fabric_logout = qla24xx_fabric_logout,
2306 .calc_req_entries = NULL,
2307 .build_iocbs = NULL,
2308 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2309 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2310 .read_nvram = NULL,
2311 .write_nvram = NULL,
2312 .fw_dump = qla81xx_fw_dump,
2313 .beacon_on = qla24xx_beacon_on,
2314 .beacon_off = qla24xx_beacon_off,
2315 .beacon_blink = qla83xx_beacon_blink,
2316 .read_optrom = qla25xx_read_optrom_data,
2317 .write_optrom = qla24xx_write_optrom_data,
2318 .get_flash_version = qla24xx_get_flash_version,
2319 .start_scsi = qla24xx_dif_start_scsi,
2320 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2321 .abort_isp = qla2x00_abort_isp,
2322 .iospace_config = qla2x00_iospace_config,
2323 .initialize_adapter = qla2x00_initialize_adapter,
2324 };
2325
2326 static struct isp_operations qla82xx_isp_ops = {
2327 .pci_config = qla82xx_pci_config,
2328 .reset_chip = qla82xx_reset_chip,
2329 .chip_diag = qla24xx_chip_diag,
2330 .config_rings = qla82xx_config_rings,
2331 .reset_adapter = qla24xx_reset_adapter,
2332 .nvram_config = qla81xx_nvram_config,
2333 .update_fw_options = qla24xx_update_fw_options,
2334 .load_risc = qla82xx_load_risc,
2335 .pci_info_str = qla24xx_pci_info_str,
2336 .fw_version_str = qla24xx_fw_version_str,
2337 .intr_handler = qla82xx_intr_handler,
2338 .enable_intrs = qla82xx_enable_intrs,
2339 .disable_intrs = qla82xx_disable_intrs,
2340 .abort_command = qla24xx_abort_command,
2341 .target_reset = qla24xx_abort_target,
2342 .lun_reset = qla24xx_lun_reset,
2343 .fabric_login = qla24xx_login_fabric,
2344 .fabric_logout = qla24xx_fabric_logout,
2345 .calc_req_entries = NULL,
2346 .build_iocbs = NULL,
2347 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2348 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2349 .read_nvram = qla24xx_read_nvram_data,
2350 .write_nvram = qla24xx_write_nvram_data,
2351 .fw_dump = qla82xx_fw_dump,
2352 .beacon_on = qla82xx_beacon_on,
2353 .beacon_off = qla82xx_beacon_off,
2354 .beacon_blink = NULL,
2355 .read_optrom = qla82xx_read_optrom_data,
2356 .write_optrom = qla82xx_write_optrom_data,
2357 .get_flash_version = qla82xx_get_flash_version,
2358 .start_scsi = qla82xx_start_scsi,
2359 .start_scsi_mq = NULL,
2360 .abort_isp = qla82xx_abort_isp,
2361 .iospace_config = qla82xx_iospace_config,
2362 .initialize_adapter = qla2x00_initialize_adapter,
2363 };
2364
2365 static struct isp_operations qla8044_isp_ops = {
2366 .pci_config = qla82xx_pci_config,
2367 .reset_chip = qla82xx_reset_chip,
2368 .chip_diag = qla24xx_chip_diag,
2369 .config_rings = qla82xx_config_rings,
2370 .reset_adapter = qla24xx_reset_adapter,
2371 .nvram_config = qla81xx_nvram_config,
2372 .update_fw_options = qla24xx_update_fw_options,
2373 .load_risc = qla82xx_load_risc,
2374 .pci_info_str = qla24xx_pci_info_str,
2375 .fw_version_str = qla24xx_fw_version_str,
2376 .intr_handler = qla8044_intr_handler,
2377 .enable_intrs = qla82xx_enable_intrs,
2378 .disable_intrs = qla82xx_disable_intrs,
2379 .abort_command = qla24xx_abort_command,
2380 .target_reset = qla24xx_abort_target,
2381 .lun_reset = qla24xx_lun_reset,
2382 .fabric_login = qla24xx_login_fabric,
2383 .fabric_logout = qla24xx_fabric_logout,
2384 .calc_req_entries = NULL,
2385 .build_iocbs = NULL,
2386 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2387 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2388 .read_nvram = NULL,
2389 .write_nvram = NULL,
2390 .fw_dump = qla8044_fw_dump,
2391 .beacon_on = qla82xx_beacon_on,
2392 .beacon_off = qla82xx_beacon_off,
2393 .beacon_blink = NULL,
2394 .read_optrom = qla8044_read_optrom_data,
2395 .write_optrom = qla8044_write_optrom_data,
2396 .get_flash_version = qla82xx_get_flash_version,
2397 .start_scsi = qla82xx_start_scsi,
2398 .start_scsi_mq = NULL,
2399 .abort_isp = qla8044_abort_isp,
2400 .iospace_config = qla82xx_iospace_config,
2401 .initialize_adapter = qla2x00_initialize_adapter,
2402 };
2403
2404 static struct isp_operations qla83xx_isp_ops = {
2405 .pci_config = qla25xx_pci_config,
2406 .reset_chip = qla24xx_reset_chip,
2407 .chip_diag = qla24xx_chip_diag,
2408 .config_rings = qla24xx_config_rings,
2409 .reset_adapter = qla24xx_reset_adapter,
2410 .nvram_config = qla81xx_nvram_config,
2411 .update_fw_options = qla24xx_update_fw_options,
2412 .load_risc = qla81xx_load_risc,
2413 .pci_info_str = qla24xx_pci_info_str,
2414 .fw_version_str = qla24xx_fw_version_str,
2415 .intr_handler = qla24xx_intr_handler,
2416 .enable_intrs = qla24xx_enable_intrs,
2417 .disable_intrs = qla24xx_disable_intrs,
2418 .abort_command = qla24xx_abort_command,
2419 .target_reset = qla24xx_abort_target,
2420 .lun_reset = qla24xx_lun_reset,
2421 .fabric_login = qla24xx_login_fabric,
2422 .fabric_logout = qla24xx_fabric_logout,
2423 .calc_req_entries = NULL,
2424 .build_iocbs = NULL,
2425 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2426 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2427 .read_nvram = NULL,
2428 .write_nvram = NULL,
2429 .fw_dump = qla83xx_fw_dump,
2430 .beacon_on = qla24xx_beacon_on,
2431 .beacon_off = qla24xx_beacon_off,
2432 .beacon_blink = qla83xx_beacon_blink,
2433 .read_optrom = qla25xx_read_optrom_data,
2434 .write_optrom = qla24xx_write_optrom_data,
2435 .get_flash_version = qla24xx_get_flash_version,
2436 .start_scsi = qla24xx_dif_start_scsi,
2437 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2438 .abort_isp = qla2x00_abort_isp,
2439 .iospace_config = qla83xx_iospace_config,
2440 .initialize_adapter = qla2x00_initialize_adapter,
2441 };
2442
2443 static struct isp_operations qlafx00_isp_ops = {
2444 .pci_config = qlafx00_pci_config,
2445 .reset_chip = qlafx00_soft_reset,
2446 .chip_diag = qlafx00_chip_diag,
2447 .config_rings = qlafx00_config_rings,
2448 .reset_adapter = qlafx00_soft_reset,
2449 .nvram_config = NULL,
2450 .update_fw_options = NULL,
2451 .load_risc = NULL,
2452 .pci_info_str = qlafx00_pci_info_str,
2453 .fw_version_str = qlafx00_fw_version_str,
2454 .intr_handler = qlafx00_intr_handler,
2455 .enable_intrs = qlafx00_enable_intrs,
2456 .disable_intrs = qlafx00_disable_intrs,
2457 .abort_command = qla24xx_async_abort_command,
2458 .target_reset = qlafx00_abort_target,
2459 .lun_reset = qlafx00_lun_reset,
2460 .fabric_login = NULL,
2461 .fabric_logout = NULL,
2462 .calc_req_entries = NULL,
2463 .build_iocbs = NULL,
2464 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2465 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2466 .read_nvram = qla24xx_read_nvram_data,
2467 .write_nvram = qla24xx_write_nvram_data,
2468 .fw_dump = NULL,
2469 .beacon_on = qla24xx_beacon_on,
2470 .beacon_off = qla24xx_beacon_off,
2471 .beacon_blink = NULL,
2472 .read_optrom = qla24xx_read_optrom_data,
2473 .write_optrom = qla24xx_write_optrom_data,
2474 .get_flash_version = qla24xx_get_flash_version,
2475 .start_scsi = qlafx00_start_scsi,
2476 .start_scsi_mq = NULL,
2477 .abort_isp = qlafx00_abort_isp,
2478 .iospace_config = qlafx00_iospace_config,
2479 .initialize_adapter = qlafx00_initialize_adapter,
2480 };
2481
2482 static struct isp_operations qla27xx_isp_ops = {
2483 .pci_config = qla25xx_pci_config,
2484 .reset_chip = qla24xx_reset_chip,
2485 .chip_diag = qla24xx_chip_diag,
2486 .config_rings = qla24xx_config_rings,
2487 .reset_adapter = qla24xx_reset_adapter,
2488 .nvram_config = qla81xx_nvram_config,
2489 .update_fw_options = qla24xx_update_fw_options,
2490 .load_risc = qla81xx_load_risc,
2491 .pci_info_str = qla24xx_pci_info_str,
2492 .fw_version_str = qla24xx_fw_version_str,
2493 .intr_handler = qla24xx_intr_handler,
2494 .enable_intrs = qla24xx_enable_intrs,
2495 .disable_intrs = qla24xx_disable_intrs,
2496 .abort_command = qla24xx_abort_command,
2497 .target_reset = qla24xx_abort_target,
2498 .lun_reset = qla24xx_lun_reset,
2499 .fabric_login = qla24xx_login_fabric,
2500 .fabric_logout = qla24xx_fabric_logout,
2501 .calc_req_entries = NULL,
2502 .build_iocbs = NULL,
2503 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2504 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2505 .read_nvram = NULL,
2506 .write_nvram = NULL,
2507 .fw_dump = qla27xx_fwdump,
2508 .mpi_fw_dump = qla27xx_mpi_fwdump,
2509 .beacon_on = qla24xx_beacon_on,
2510 .beacon_off = qla24xx_beacon_off,
2511 .beacon_blink = qla83xx_beacon_blink,
2512 .read_optrom = qla25xx_read_optrom_data,
2513 .write_optrom = qla24xx_write_optrom_data,
2514 .get_flash_version = qla24xx_get_flash_version,
2515 .start_scsi = qla24xx_dif_start_scsi,
2516 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2517 .abort_isp = qla2x00_abort_isp,
2518 .iospace_config = qla83xx_iospace_config,
2519 .initialize_adapter = qla2x00_initialize_adapter,
2520 };
2521
2522 static inline void
qla2x00_set_isp_flags(struct qla_hw_data * ha)2523 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2524 {
2525 ha->device_type = DT_EXTENDED_IDS;
2526 switch (ha->pdev->device) {
2527 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2528 ha->isp_type |= DT_ISP2100;
2529 ha->device_type &= ~DT_EXTENDED_IDS;
2530 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2531 break;
2532 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2533 ha->isp_type |= DT_ISP2200;
2534 ha->device_type &= ~DT_EXTENDED_IDS;
2535 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2536 break;
2537 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2538 ha->isp_type |= DT_ISP2300;
2539 ha->device_type |= DT_ZIO_SUPPORTED;
2540 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2541 break;
2542 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2543 ha->isp_type |= DT_ISP2312;
2544 ha->device_type |= DT_ZIO_SUPPORTED;
2545 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2546 break;
2547 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2548 ha->isp_type |= DT_ISP2322;
2549 ha->device_type |= DT_ZIO_SUPPORTED;
2550 if (ha->pdev->subsystem_vendor == 0x1028 &&
2551 ha->pdev->subsystem_device == 0x0170)
2552 ha->device_type |= DT_OEM_001;
2553 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2554 break;
2555 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2556 ha->isp_type |= DT_ISP6312;
2557 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2558 break;
2559 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2560 ha->isp_type |= DT_ISP6322;
2561 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2562 break;
2563 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2564 ha->isp_type |= DT_ISP2422;
2565 ha->device_type |= DT_ZIO_SUPPORTED;
2566 ha->device_type |= DT_FWI2;
2567 ha->device_type |= DT_IIDMA;
2568 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2569 break;
2570 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2571 ha->isp_type |= DT_ISP2432;
2572 ha->device_type |= DT_ZIO_SUPPORTED;
2573 ha->device_type |= DT_FWI2;
2574 ha->device_type |= DT_IIDMA;
2575 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2576 break;
2577 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2578 ha->isp_type |= DT_ISP8432;
2579 ha->device_type |= DT_ZIO_SUPPORTED;
2580 ha->device_type |= DT_FWI2;
2581 ha->device_type |= DT_IIDMA;
2582 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2583 break;
2584 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2585 ha->isp_type |= DT_ISP5422;
2586 ha->device_type |= DT_FWI2;
2587 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2588 break;
2589 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2590 ha->isp_type |= DT_ISP5432;
2591 ha->device_type |= DT_FWI2;
2592 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2593 break;
2594 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2595 ha->isp_type |= DT_ISP2532;
2596 ha->device_type |= DT_ZIO_SUPPORTED;
2597 ha->device_type |= DT_FWI2;
2598 ha->device_type |= DT_IIDMA;
2599 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2600 break;
2601 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2602 ha->isp_type |= DT_ISP8001;
2603 ha->device_type |= DT_ZIO_SUPPORTED;
2604 ha->device_type |= DT_FWI2;
2605 ha->device_type |= DT_IIDMA;
2606 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2607 break;
2608 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2609 ha->isp_type |= DT_ISP8021;
2610 ha->device_type |= DT_ZIO_SUPPORTED;
2611 ha->device_type |= DT_FWI2;
2612 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2613 /* Initialize 82XX ISP flags */
2614 qla82xx_init_flags(ha);
2615 break;
2616 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2617 ha->isp_type |= DT_ISP8044;
2618 ha->device_type |= DT_ZIO_SUPPORTED;
2619 ha->device_type |= DT_FWI2;
2620 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2621 /* Initialize 82XX ISP flags */
2622 qla82xx_init_flags(ha);
2623 break;
2624 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2625 ha->isp_type |= DT_ISP2031;
2626 ha->device_type |= DT_ZIO_SUPPORTED;
2627 ha->device_type |= DT_FWI2;
2628 ha->device_type |= DT_IIDMA;
2629 ha->device_type |= DT_T10_PI;
2630 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2631 break;
2632 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2633 ha->isp_type |= DT_ISP8031;
2634 ha->device_type |= DT_ZIO_SUPPORTED;
2635 ha->device_type |= DT_FWI2;
2636 ha->device_type |= DT_IIDMA;
2637 ha->device_type |= DT_T10_PI;
2638 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2639 break;
2640 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2641 ha->isp_type |= DT_ISPFX00;
2642 break;
2643 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2644 ha->isp_type |= DT_ISP2071;
2645 ha->device_type |= DT_ZIO_SUPPORTED;
2646 ha->device_type |= DT_FWI2;
2647 ha->device_type |= DT_IIDMA;
2648 ha->device_type |= DT_T10_PI;
2649 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2650 break;
2651 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2652 ha->isp_type |= DT_ISP2271;
2653 ha->device_type |= DT_ZIO_SUPPORTED;
2654 ha->device_type |= DT_FWI2;
2655 ha->device_type |= DT_IIDMA;
2656 ha->device_type |= DT_T10_PI;
2657 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2658 break;
2659 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2660 ha->isp_type |= DT_ISP2261;
2661 ha->device_type |= DT_ZIO_SUPPORTED;
2662 ha->device_type |= DT_FWI2;
2663 ha->device_type |= DT_IIDMA;
2664 ha->device_type |= DT_T10_PI;
2665 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2666 break;
2667 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2668 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2669 ha->isp_type |= DT_ISP2081;
2670 ha->device_type |= DT_ZIO_SUPPORTED;
2671 ha->device_type |= DT_FWI2;
2672 ha->device_type |= DT_IIDMA;
2673 ha->device_type |= DT_T10_PI;
2674 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2675 break;
2676 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2677 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2678 ha->isp_type |= DT_ISP2281;
2679 ha->device_type |= DT_ZIO_SUPPORTED;
2680 ha->device_type |= DT_FWI2;
2681 ha->device_type |= DT_IIDMA;
2682 ha->device_type |= DT_T10_PI;
2683 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2684 break;
2685 }
2686
2687 if (IS_QLA82XX(ha))
2688 ha->port_no = ha->portnum & 1;
2689 else {
2690 /* Get adapter physical port no from interrupt pin register. */
2691 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2692 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2693 IS_QLA27XX(ha) || IS_QLA28XX(ha))
2694 ha->port_no--;
2695 else
2696 ha->port_no = !(ha->port_no & 1);
2697 }
2698
2699 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2700 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2701 ha->device_type, ha->port_no, ha->fw_srisc_address);
2702 }
2703
2704 static void
qla2xxx_scan_start(struct Scsi_Host * shost)2705 qla2xxx_scan_start(struct Scsi_Host *shost)
2706 {
2707 scsi_qla_host_t *vha = shost_priv(shost);
2708
2709 if (vha->hw->flags.running_gold_fw)
2710 return;
2711
2712 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2713 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2714 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2715 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2716 }
2717
2718 static int
qla2xxx_scan_finished(struct Scsi_Host * shost,unsigned long time)2719 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2720 {
2721 scsi_qla_host_t *vha = shost_priv(shost);
2722
2723 if (test_bit(UNLOADING, &vha->dpc_flags))
2724 return 1;
2725 if (!vha->host)
2726 return 1;
2727 if (time > vha->hw->loop_reset_delay * HZ)
2728 return 1;
2729
2730 return atomic_read(&vha->loop_state) == LOOP_READY;
2731 }
2732
qla2x00_iocb_work_fn(struct work_struct * work)2733 static void qla2x00_iocb_work_fn(struct work_struct *work)
2734 {
2735 struct scsi_qla_host *vha = container_of(work,
2736 struct scsi_qla_host, iocb_work);
2737 struct qla_hw_data *ha = vha->hw;
2738 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2739 int i = 2;
2740 unsigned long flags;
2741
2742 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2743 return;
2744
2745 while (!list_empty(&vha->work_list) && i > 0) {
2746 qla2x00_do_work(vha);
2747 i--;
2748 }
2749
2750 spin_lock_irqsave(&vha->work_lock, flags);
2751 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2752 spin_unlock_irqrestore(&vha->work_lock, flags);
2753 }
2754
2755 /*
2756 * PCI driver interface
2757 */
2758 static int
qla2x00_probe_one(struct pci_dev * pdev,const struct pci_device_id * id)2759 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2760 {
2761 int ret = -ENODEV;
2762 struct Scsi_Host *host;
2763 scsi_qla_host_t *base_vha = NULL;
2764 struct qla_hw_data *ha;
2765 char pci_info[30];
2766 char fw_str[30], wq_name[30];
2767 struct scsi_host_template *sht;
2768 int bars, mem_only = 0;
2769 uint16_t req_length = 0, rsp_length = 0;
2770 struct req_que *req = NULL;
2771 struct rsp_que *rsp = NULL;
2772 int i;
2773
2774 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2775 sht = &qla2xxx_driver_template;
2776 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2777 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2778 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2779 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2780 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2781 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2782 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2783 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2784 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2785 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2786 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2787 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2788 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2789 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2790 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2791 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2792 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2793 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2794 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
2795 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2796 mem_only = 1;
2797 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2798 "Mem only adapter.\n");
2799 }
2800 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2801 "Bars=%d.\n", bars);
2802
2803 if (mem_only) {
2804 if (pci_enable_device_mem(pdev))
2805 return ret;
2806 } else {
2807 if (pci_enable_device(pdev))
2808 return ret;
2809 }
2810
2811 if (is_kdump_kernel()) {
2812 ql2xmqsupport = 0;
2813 ql2xallocfwdump = 0;
2814 }
2815
2816 /* This may fail but that's ok */
2817 pci_enable_pcie_error_reporting(pdev);
2818
2819 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2820 if (!ha) {
2821 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2822 "Unable to allocate memory for ha.\n");
2823 goto disable_device;
2824 }
2825 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2826 "Memory allocated for ha=%p.\n", ha);
2827 ha->pdev = pdev;
2828 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2829 spin_lock_init(&ha->tgt.q_full_lock);
2830 spin_lock_init(&ha->tgt.sess_lock);
2831 spin_lock_init(&ha->tgt.atio_lock);
2832
2833 atomic_set(&ha->nvme_active_aen_cnt, 0);
2834
2835 /* Clear our data area */
2836 ha->bars = bars;
2837 ha->mem_only = mem_only;
2838 spin_lock_init(&ha->hardware_lock);
2839 spin_lock_init(&ha->vport_slock);
2840 mutex_init(&ha->selflogin_lock);
2841 mutex_init(&ha->optrom_mutex);
2842
2843 /* Set ISP-type information. */
2844 qla2x00_set_isp_flags(ha);
2845
2846 /* Set EEH reset type to fundamental if required by hba */
2847 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2848 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
2849 pdev->needs_freset = 1;
2850
2851 ha->prev_topology = 0;
2852 ha->init_cb_size = sizeof(init_cb_t);
2853 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2854 ha->optrom_size = OPTROM_SIZE_2300;
2855 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
2856 atomic_set(&ha->num_pend_mbx_stage1, 0);
2857 atomic_set(&ha->num_pend_mbx_stage2, 0);
2858 atomic_set(&ha->num_pend_mbx_stage3, 0);
2859 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2860 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
2861
2862 /* Assign ISP specific operations. */
2863 if (IS_QLA2100(ha)) {
2864 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2865 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2866 req_length = REQUEST_ENTRY_CNT_2100;
2867 rsp_length = RESPONSE_ENTRY_CNT_2100;
2868 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2869 ha->gid_list_info_size = 4;
2870 ha->flash_conf_off = ~0;
2871 ha->flash_data_off = ~0;
2872 ha->nvram_conf_off = ~0;
2873 ha->nvram_data_off = ~0;
2874 ha->isp_ops = &qla2100_isp_ops;
2875 } else if (IS_QLA2200(ha)) {
2876 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2877 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2878 req_length = REQUEST_ENTRY_CNT_2200;
2879 rsp_length = RESPONSE_ENTRY_CNT_2100;
2880 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2881 ha->gid_list_info_size = 4;
2882 ha->flash_conf_off = ~0;
2883 ha->flash_data_off = ~0;
2884 ha->nvram_conf_off = ~0;
2885 ha->nvram_data_off = ~0;
2886 ha->isp_ops = &qla2100_isp_ops;
2887 } else if (IS_QLA23XX(ha)) {
2888 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2889 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2890 req_length = REQUEST_ENTRY_CNT_2200;
2891 rsp_length = RESPONSE_ENTRY_CNT_2300;
2892 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2893 ha->gid_list_info_size = 6;
2894 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2895 ha->optrom_size = OPTROM_SIZE_2322;
2896 ha->flash_conf_off = ~0;
2897 ha->flash_data_off = ~0;
2898 ha->nvram_conf_off = ~0;
2899 ha->nvram_data_off = ~0;
2900 ha->isp_ops = &qla2300_isp_ops;
2901 } else if (IS_QLA24XX_TYPE(ha)) {
2902 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2903 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2904 req_length = REQUEST_ENTRY_CNT_24XX;
2905 rsp_length = RESPONSE_ENTRY_CNT_2300;
2906 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2907 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2908 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2909 ha->gid_list_info_size = 8;
2910 ha->optrom_size = OPTROM_SIZE_24XX;
2911 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2912 ha->isp_ops = &qla24xx_isp_ops;
2913 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2914 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2915 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2916 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2917 } else if (IS_QLA25XX(ha)) {
2918 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2919 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2920 req_length = REQUEST_ENTRY_CNT_24XX;
2921 rsp_length = RESPONSE_ENTRY_CNT_2300;
2922 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2923 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2924 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2925 ha->gid_list_info_size = 8;
2926 ha->optrom_size = OPTROM_SIZE_25XX;
2927 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2928 ha->isp_ops = &qla25xx_isp_ops;
2929 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2930 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2931 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2932 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2933 } else if (IS_QLA81XX(ha)) {
2934 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2935 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2936 req_length = REQUEST_ENTRY_CNT_24XX;
2937 rsp_length = RESPONSE_ENTRY_CNT_2300;
2938 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2939 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2940 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2941 ha->gid_list_info_size = 8;
2942 ha->optrom_size = OPTROM_SIZE_81XX;
2943 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2944 ha->isp_ops = &qla81xx_isp_ops;
2945 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2946 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2947 ha->nvram_conf_off = ~0;
2948 ha->nvram_data_off = ~0;
2949 } else if (IS_QLA82XX(ha)) {
2950 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2951 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2952 req_length = REQUEST_ENTRY_CNT_82XX;
2953 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2954 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2955 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2956 ha->gid_list_info_size = 8;
2957 ha->optrom_size = OPTROM_SIZE_82XX;
2958 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2959 ha->isp_ops = &qla82xx_isp_ops;
2960 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2961 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2962 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2963 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2964 } else if (IS_QLA8044(ha)) {
2965 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2966 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2967 req_length = REQUEST_ENTRY_CNT_82XX;
2968 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2969 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2970 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2971 ha->gid_list_info_size = 8;
2972 ha->optrom_size = OPTROM_SIZE_83XX;
2973 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2974 ha->isp_ops = &qla8044_isp_ops;
2975 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2976 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2977 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2978 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2979 } else if (IS_QLA83XX(ha)) {
2980 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2981 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2982 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2983 req_length = REQUEST_ENTRY_CNT_83XX;
2984 rsp_length = RESPONSE_ENTRY_CNT_83XX;
2985 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2986 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2987 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2988 ha->gid_list_info_size = 8;
2989 ha->optrom_size = OPTROM_SIZE_83XX;
2990 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2991 ha->isp_ops = &qla83xx_isp_ops;
2992 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2993 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2994 ha->nvram_conf_off = ~0;
2995 ha->nvram_data_off = ~0;
2996 } else if (IS_QLAFX00(ha)) {
2997 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2998 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2999 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3000 req_length = REQUEST_ENTRY_CNT_FX00;
3001 rsp_length = RESPONSE_ENTRY_CNT_FX00;
3002 ha->isp_ops = &qlafx00_isp_ops;
3003 ha->port_down_retry_count = 30; /* default value */
3004 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3005 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
3006 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
3007 ha->mr.fw_hbt_en = 1;
3008 ha->mr.host_info_resend = false;
3009 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
3010 } else if (IS_QLA27XX(ha)) {
3011 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3012 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3013 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3014 req_length = REQUEST_ENTRY_CNT_83XX;
3015 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3016 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3017 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3018 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3019 ha->gid_list_info_size = 8;
3020 ha->optrom_size = OPTROM_SIZE_83XX;
3021 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3022 ha->isp_ops = &qla27xx_isp_ops;
3023 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3024 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3025 ha->nvram_conf_off = ~0;
3026 ha->nvram_data_off = ~0;
3027 } else if (IS_QLA28XX(ha)) {
3028 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3029 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3030 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3031 req_length = REQUEST_ENTRY_CNT_24XX;
3032 rsp_length = RESPONSE_ENTRY_CNT_2300;
3033 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3034 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3035 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3036 ha->gid_list_info_size = 8;
3037 ha->optrom_size = OPTROM_SIZE_28XX;
3038 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3039 ha->isp_ops = &qla27xx_isp_ops;
3040 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3041 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3042 ha->nvram_conf_off = ~0;
3043 ha->nvram_data_off = ~0;
3044 }
3045
3046 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3047 "mbx_count=%d, req_length=%d, "
3048 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
3049 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3050 "max_fibre_devices=%d.\n",
3051 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3052 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3053 ha->nvram_npiv_size, ha->max_fibre_devices);
3054 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3055 "isp_ops=%p, flash_conf_off=%d, "
3056 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3057 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3058 ha->nvram_conf_off, ha->nvram_data_off);
3059
3060 /* Configure PCI I/O space */
3061 ret = ha->isp_ops->iospace_config(ha);
3062 if (ret)
3063 goto iospace_config_failed;
3064
3065 ql_log_pci(ql_log_info, pdev, 0x001d,
3066 "Found an ISP%04X irq %d iobase 0x%p.\n",
3067 pdev->device, pdev->irq, ha->iobase);
3068 mutex_init(&ha->vport_lock);
3069 mutex_init(&ha->mq_lock);
3070 init_completion(&ha->mbx_cmd_comp);
3071 complete(&ha->mbx_cmd_comp);
3072 init_completion(&ha->mbx_intr_comp);
3073 init_completion(&ha->dcbx_comp);
3074 init_completion(&ha->lb_portup_comp);
3075
3076 set_bit(0, (unsigned long *) ha->vp_idx_map);
3077
3078 qla2x00_config_dma_addressing(ha);
3079 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3080 "64 Bit addressing is %s.\n",
3081 ha->flags.enable_64bit_addressing ? "enable" :
3082 "disable");
3083 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3084 if (ret) {
3085 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3086 "Failed to allocate memory for adapter, aborting.\n");
3087
3088 goto probe_hw_failed;
3089 }
3090
3091 req->max_q_depth = MAX_Q_DEPTH;
3092 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3093 req->max_q_depth = ql2xmaxqdepth;
3094
3095
3096 base_vha = qla2x00_create_host(sht, ha);
3097 if (!base_vha) {
3098 ret = -ENOMEM;
3099 goto probe_hw_failed;
3100 }
3101
3102 pci_set_drvdata(pdev, base_vha);
3103 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3104
3105 host = base_vha->host;
3106 base_vha->req = req;
3107 if (IS_QLA2XXX_MIDTYPE(ha))
3108 base_vha->mgmt_svr_loop_id =
3109 qla2x00_reserve_mgmt_server_loop_id(base_vha);
3110 else
3111 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3112 base_vha->vp_idx;
3113
3114 /* Setup fcport template structure. */
3115 ha->mr.fcport.vha = base_vha;
3116 ha->mr.fcport.port_type = FCT_UNKNOWN;
3117 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3118 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3119 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3120 ha->mr.fcport.scan_state = 1;
3121
3122 /* Set the SG table size based on ISP type */
3123 if (!IS_FWI2_CAPABLE(ha)) {
3124 if (IS_QLA2100(ha))
3125 host->sg_tablesize = 32;
3126 } else {
3127 if (!IS_QLA82XX(ha))
3128 host->sg_tablesize = QLA_SG_ALL;
3129 }
3130 host->max_id = ha->max_fibre_devices;
3131 host->cmd_per_lun = 3;
3132 host->unique_id = host->host_no;
3133 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3134 host->max_cmd_len = 32;
3135 else
3136 host->max_cmd_len = MAX_CMDSZ;
3137 host->max_channel = MAX_BUSES - 1;
3138 /* Older HBAs support only 16-bit LUNs */
3139 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3140 ql2xmaxlun > 0xffff)
3141 host->max_lun = 0xffff;
3142 else
3143 host->max_lun = ql2xmaxlun;
3144 host->transportt = qla2xxx_transport_template;
3145 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3146
3147 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3148 "max_id=%d this_id=%d "
3149 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3150 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3151 host->this_id, host->cmd_per_lun, host->unique_id,
3152 host->max_cmd_len, host->max_channel, host->max_lun,
3153 host->transportt, sht->vendor_id);
3154
3155 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3156
3157 /* Set up the irqs */
3158 ret = qla2x00_request_irqs(ha, rsp);
3159 if (ret)
3160 goto probe_failed;
3161
3162 /* Alloc arrays of request and response ring ptrs */
3163 ret = qla2x00_alloc_queues(ha, req, rsp);
3164 if (ret) {
3165 ql_log(ql_log_fatal, base_vha, 0x003d,
3166 "Failed to allocate memory for queue pointers..."
3167 "aborting.\n");
3168 ret = -ENODEV;
3169 goto probe_failed;
3170 }
3171
3172 if (ha->mqenable) {
3173 /* number of hardware queues supported by blk/scsi-mq*/
3174 host->nr_hw_queues = ha->max_qpairs;
3175
3176 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3177 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3178 } else {
3179 if (ql2xnvmeenable) {
3180 host->nr_hw_queues = ha->max_qpairs;
3181 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3182 "FC-NVMe support is enabled, HW queues=%d\n",
3183 host->nr_hw_queues);
3184 } else {
3185 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3186 "blk/scsi-mq disabled.\n");
3187 }
3188 }
3189
3190 qlt_probe_one_stage1(base_vha, ha);
3191
3192 pci_save_state(pdev);
3193
3194 /* Assign back pointers */
3195 rsp->req = req;
3196 req->rsp = rsp;
3197
3198 if (IS_QLAFX00(ha)) {
3199 ha->rsp_q_map[0] = rsp;
3200 ha->req_q_map[0] = req;
3201 set_bit(0, ha->req_qid_map);
3202 set_bit(0, ha->rsp_qid_map);
3203 }
3204
3205 /* FWI2-capable only. */
3206 req->req_q_in = &ha->iobase->isp24.req_q_in;
3207 req->req_q_out = &ha->iobase->isp24.req_q_out;
3208 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3209 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3210 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3211 IS_QLA28XX(ha)) {
3212 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3213 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3214 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3215 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
3216 }
3217
3218 if (IS_QLAFX00(ha)) {
3219 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3220 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3221 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3222 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3223 }
3224
3225 if (IS_P3P_TYPE(ha)) {
3226 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3227 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3228 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3229 }
3230
3231 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3232 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3233 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3234 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3235 "req->req_q_in=%p req->req_q_out=%p "
3236 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3237 req->req_q_in, req->req_q_out,
3238 rsp->rsp_q_in, rsp->rsp_q_out);
3239 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3240 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3241 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3242 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3243 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3244 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3245
3246 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
3247 if (unlikely(!ha->wq)) {
3248 ret = -ENOMEM;
3249 goto probe_failed;
3250 }
3251
3252 if (ha->isp_ops->initialize_adapter(base_vha)) {
3253 ql_log(ql_log_fatal, base_vha, 0x00d6,
3254 "Failed to initialize adapter - Adapter flags %x.\n",
3255 base_vha->device_flags);
3256
3257 if (IS_QLA82XX(ha)) {
3258 qla82xx_idc_lock(ha);
3259 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3260 QLA8XXX_DEV_FAILED);
3261 qla82xx_idc_unlock(ha);
3262 ql_log(ql_log_fatal, base_vha, 0x00d7,
3263 "HW State: FAILED.\n");
3264 } else if (IS_QLA8044(ha)) {
3265 qla8044_idc_lock(ha);
3266 qla8044_wr_direct(base_vha,
3267 QLA8044_CRB_DEV_STATE_INDEX,
3268 QLA8XXX_DEV_FAILED);
3269 qla8044_idc_unlock(ha);
3270 ql_log(ql_log_fatal, base_vha, 0x0150,
3271 "HW State: FAILED.\n");
3272 }
3273
3274 ret = -ENODEV;
3275 goto probe_failed;
3276 }
3277
3278 if (IS_QLAFX00(ha))
3279 host->can_queue = QLAFX00_MAX_CANQUEUE;
3280 else
3281 host->can_queue = req->num_outstanding_cmds - 10;
3282
3283 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3284 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3285 host->can_queue, base_vha->req,
3286 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3287
3288 if (ha->mqenable) {
3289 bool startit = false;
3290
3291 if (QLA_TGT_MODE_ENABLED())
3292 startit = false;
3293
3294 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
3295 startit = true;
3296
3297 /* Create start of day qpairs for Block MQ */
3298 for (i = 0; i < ha->max_qpairs; i++)
3299 qla2xxx_create_qpair(base_vha, 5, 0, startit);
3300 }
3301 qla_init_iocb_limit(base_vha);
3302
3303 if (ha->flags.running_gold_fw)
3304 goto skip_dpc;
3305
3306 /*
3307 * Startup the kernel thread for this host adapter
3308 */
3309 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3310 "%s_dpc", base_vha->host_str);
3311 if (IS_ERR(ha->dpc_thread)) {
3312 ql_log(ql_log_fatal, base_vha, 0x00ed,
3313 "Failed to start DPC thread.\n");
3314 ret = PTR_ERR(ha->dpc_thread);
3315 ha->dpc_thread = NULL;
3316 goto probe_failed;
3317 }
3318 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3319 "DPC thread started successfully.\n");
3320
3321 /*
3322 * If we're not coming up in initiator mode, we might sit for
3323 * a while without waking up the dpc thread, which leads to a
3324 * stuck process warning. So just kick the dpc once here and
3325 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3326 */
3327 qla2xxx_wake_dpc(base_vha);
3328
3329 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3330
3331 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3332 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3333 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3334 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3335
3336 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3337 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3338 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3339 INIT_WORK(&ha->idc_state_handler,
3340 qla83xx_idc_state_handler_work);
3341 INIT_WORK(&ha->nic_core_unrecoverable,
3342 qla83xx_nic_core_unrecoverable_work);
3343 }
3344
3345 skip_dpc:
3346 list_add_tail(&base_vha->list, &ha->vp_list);
3347 base_vha->host->irq = ha->pdev->irq;
3348
3349 /* Initialized the timer */
3350 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3351 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3352 "Started qla2x00_timer with "
3353 "interval=%d.\n", WATCH_INTERVAL);
3354 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3355 "Detected hba at address=%p.\n",
3356 ha);
3357
3358 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3359 if (ha->fw_attributes & BIT_4) {
3360 int prot = 0, guard;
3361
3362 base_vha->flags.difdix_supported = 1;
3363 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3364 "Registering for DIF/DIX type 1 and 3 protection.\n");
3365 if (ql2xenabledif == 1)
3366 prot = SHOST_DIX_TYPE0_PROTECTION;
3367 if (ql2xprotmask)
3368 scsi_host_set_prot(host, ql2xprotmask);
3369 else
3370 scsi_host_set_prot(host,
3371 prot | SHOST_DIF_TYPE1_PROTECTION
3372 | SHOST_DIF_TYPE2_PROTECTION
3373 | SHOST_DIF_TYPE3_PROTECTION
3374 | SHOST_DIX_TYPE1_PROTECTION
3375 | SHOST_DIX_TYPE2_PROTECTION
3376 | SHOST_DIX_TYPE3_PROTECTION);
3377
3378 guard = SHOST_DIX_GUARD_CRC;
3379
3380 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3381 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3382 guard |= SHOST_DIX_GUARD_IP;
3383
3384 if (ql2xprotguard)
3385 scsi_host_set_guard(host, ql2xprotguard);
3386 else
3387 scsi_host_set_guard(host, guard);
3388 } else
3389 base_vha->flags.difdix_supported = 0;
3390 }
3391
3392 ha->isp_ops->enable_intrs(ha);
3393
3394 if (IS_QLAFX00(ha)) {
3395 ret = qlafx00_fx_disc(base_vha,
3396 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3397 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3398 QLA_SG_ALL : 128;
3399 }
3400
3401 ret = scsi_add_host(host, &pdev->dev);
3402 if (ret)
3403 goto probe_failed;
3404
3405 base_vha->flags.init_done = 1;
3406 base_vha->flags.online = 1;
3407 ha->prev_minidump_failed = 0;
3408
3409 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3410 "Init done and hba is online.\n");
3411
3412 if (qla_ini_mode_enabled(base_vha) ||
3413 qla_dual_mode_enabled(base_vha))
3414 scsi_scan_host(host);
3415 else
3416 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3417 "skipping scsi_scan_host() for non-initiator port\n");
3418
3419 qla2x00_alloc_sysfs_attr(base_vha);
3420
3421 if (IS_QLAFX00(ha)) {
3422 ret = qlafx00_fx_disc(base_vha,
3423 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3424
3425 /* Register system information */
3426 ret = qlafx00_fx_disc(base_vha,
3427 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3428 }
3429
3430 qla2x00_init_host_attr(base_vha);
3431
3432 qla2x00_dfs_setup(base_vha);
3433
3434 ql_log(ql_log_info, base_vha, 0x00fb,
3435 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3436 ql_log(ql_log_info, base_vha, 0x00fc,
3437 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3438 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3439 sizeof(pci_info)),
3440 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3441 base_vha->host_no,
3442 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3443
3444 qlt_add_target(ha, base_vha);
3445
3446 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3447
3448 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3449 return -ENODEV;
3450
3451 return 0;
3452
3453 probe_failed:
3454 if (base_vha->gnl.l) {
3455 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3456 base_vha->gnl.l, base_vha->gnl.ldma);
3457 base_vha->gnl.l = NULL;
3458 }
3459
3460 if (base_vha->timer_active)
3461 qla2x00_stop_timer(base_vha);
3462 base_vha->flags.online = 0;
3463 if (ha->dpc_thread) {
3464 struct task_struct *t = ha->dpc_thread;
3465
3466 ha->dpc_thread = NULL;
3467 kthread_stop(t);
3468 }
3469
3470 qla2x00_free_device(base_vha);
3471 scsi_host_put(base_vha->host);
3472 /*
3473 * Need to NULL out local req/rsp after
3474 * qla2x00_free_device => qla2x00_free_queues frees
3475 * what these are pointing to. Or else we'll
3476 * fall over below in qla2x00_free_req/rsp_que.
3477 */
3478 req = NULL;
3479 rsp = NULL;
3480
3481 probe_hw_failed:
3482 qla2x00_mem_free(ha);
3483 qla2x00_free_req_que(ha, req);
3484 qla2x00_free_rsp_que(ha, rsp);
3485 qla2x00_clear_drv_active(ha);
3486
3487 iospace_config_failed:
3488 if (IS_P3P_TYPE(ha)) {
3489 if (!ha->nx_pcibase)
3490 iounmap((device_reg_t *)ha->nx_pcibase);
3491 if (!ql2xdbwr)
3492 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3493 } else {
3494 if (ha->iobase)
3495 iounmap(ha->iobase);
3496 if (ha->cregbase)
3497 iounmap(ha->cregbase);
3498 }
3499 pci_release_selected_regions(ha->pdev, ha->bars);
3500 kfree(ha);
3501
3502 disable_device:
3503 pci_disable_device(pdev);
3504 return ret;
3505 }
3506
__qla_set_remove_flag(scsi_qla_host_t * base_vha)3507 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha)
3508 {
3509 scsi_qla_host_t *vp;
3510 unsigned long flags;
3511 struct qla_hw_data *ha;
3512
3513 if (!base_vha)
3514 return;
3515
3516 ha = base_vha->hw;
3517
3518 spin_lock_irqsave(&ha->vport_slock, flags);
3519 list_for_each_entry(vp, &ha->vp_list, list)
3520 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);
3521
3522 /*
3523 * Indicate device removal to prevent future board_disable
3524 * and wait until any pending board_disable has completed.
3525 */
3526 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3527 spin_unlock_irqrestore(&ha->vport_slock, flags);
3528 }
3529
3530 static void
qla2x00_shutdown(struct pci_dev * pdev)3531 qla2x00_shutdown(struct pci_dev *pdev)
3532 {
3533 scsi_qla_host_t *vha;
3534 struct qla_hw_data *ha;
3535
3536 vha = pci_get_drvdata(pdev);
3537 ha = vha->hw;
3538
3539 ql_log(ql_log_info, vha, 0xfffa,
3540 "Adapter shutdown\n");
3541
3542 /*
3543 * Prevent future board_disable and wait
3544 * until any pending board_disable has completed.
3545 */
3546 __qla_set_remove_flag(vha);
3547 cancel_work_sync(&ha->board_disable);
3548
3549 if (!atomic_read(&pdev->enable_cnt))
3550 return;
3551
3552 /* Notify ISPFX00 firmware */
3553 if (IS_QLAFX00(ha))
3554 qlafx00_driver_shutdown(vha, 20);
3555
3556 /* Turn-off FCE trace */
3557 if (ha->flags.fce_enabled) {
3558 qla2x00_disable_fce_trace(vha, NULL, NULL);
3559 ha->flags.fce_enabled = 0;
3560 }
3561
3562 /* Turn-off EFT trace */
3563 if (ha->eft)
3564 qla2x00_disable_eft_trace(vha);
3565
3566 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3567 IS_QLA28XX(ha)) {
3568 if (ha->flags.fw_started)
3569 qla2x00_abort_isp_cleanup(vha);
3570 } else {
3571 /* Stop currently executing firmware. */
3572 qla2x00_try_to_stop_firmware(vha);
3573 }
3574
3575 /* Disable timer */
3576 if (vha->timer_active)
3577 qla2x00_stop_timer(vha);
3578
3579 /* Turn adapter off line */
3580 vha->flags.online = 0;
3581
3582 /* turn-off interrupts on the card */
3583 if (ha->interrupts_on) {
3584 vha->flags.init_done = 0;
3585 ha->isp_ops->disable_intrs(ha);
3586 }
3587
3588 qla2x00_free_irqs(vha);
3589
3590 qla2x00_free_fw_dump(ha);
3591
3592 pci_disable_device(pdev);
3593 ql_log(ql_log_info, vha, 0xfffe,
3594 "Adapter shutdown successfully.\n");
3595 }
3596
3597 /* Deletes all the virtual ports for a given ha */
3598 static void
qla2x00_delete_all_vps(struct qla_hw_data * ha,scsi_qla_host_t * base_vha)3599 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3600 {
3601 scsi_qla_host_t *vha;
3602 unsigned long flags;
3603
3604 mutex_lock(&ha->vport_lock);
3605 while (ha->cur_vport_count) {
3606 spin_lock_irqsave(&ha->vport_slock, flags);
3607
3608 BUG_ON(base_vha->list.next == &ha->vp_list);
3609 /* This assumes first entry in ha->vp_list is always base vha */
3610 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3611 scsi_host_get(vha->host);
3612
3613 spin_unlock_irqrestore(&ha->vport_slock, flags);
3614 mutex_unlock(&ha->vport_lock);
3615
3616 qla_nvme_delete(vha);
3617
3618 fc_vport_terminate(vha->fc_vport);
3619 scsi_host_put(vha->host);
3620
3621 mutex_lock(&ha->vport_lock);
3622 }
3623 mutex_unlock(&ha->vport_lock);
3624 }
3625
3626 /* Stops all deferred work threads */
3627 static void
qla2x00_destroy_deferred_work(struct qla_hw_data * ha)3628 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3629 {
3630 /* Cancel all work and destroy DPC workqueues */
3631 if (ha->dpc_lp_wq) {
3632 cancel_work_sync(&ha->idc_aen);
3633 destroy_workqueue(ha->dpc_lp_wq);
3634 ha->dpc_lp_wq = NULL;
3635 }
3636
3637 if (ha->dpc_hp_wq) {
3638 cancel_work_sync(&ha->nic_core_reset);
3639 cancel_work_sync(&ha->idc_state_handler);
3640 cancel_work_sync(&ha->nic_core_unrecoverable);
3641 destroy_workqueue(ha->dpc_hp_wq);
3642 ha->dpc_hp_wq = NULL;
3643 }
3644
3645 /* Kill the kernel thread for this host */
3646 if (ha->dpc_thread) {
3647 struct task_struct *t = ha->dpc_thread;
3648
3649 /*
3650 * qla2xxx_wake_dpc checks for ->dpc_thread
3651 * so we need to zero it out.
3652 */
3653 ha->dpc_thread = NULL;
3654 kthread_stop(t);
3655 }
3656 }
3657
3658 static void
qla2x00_unmap_iobases(struct qla_hw_data * ha)3659 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3660 {
3661 if (IS_QLA82XX(ha)) {
3662
3663 iounmap((device_reg_t *)ha->nx_pcibase);
3664 if (!ql2xdbwr)
3665 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3666 } else {
3667 if (ha->iobase)
3668 iounmap(ha->iobase);
3669
3670 if (ha->cregbase)
3671 iounmap(ha->cregbase);
3672
3673 if (ha->mqiobase)
3674 iounmap(ha->mqiobase);
3675
3676 if (ha->msixbase)
3677 iounmap(ha->msixbase);
3678 }
3679 }
3680
3681 static void
qla2x00_clear_drv_active(struct qla_hw_data * ha)3682 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3683 {
3684 if (IS_QLA8044(ha)) {
3685 qla8044_idc_lock(ha);
3686 qla8044_clear_drv_active(ha);
3687 qla8044_idc_unlock(ha);
3688 } else if (IS_QLA82XX(ha)) {
3689 qla82xx_idc_lock(ha);
3690 qla82xx_clear_drv_active(ha);
3691 qla82xx_idc_unlock(ha);
3692 }
3693 }
3694
3695 static void
qla2x00_remove_one(struct pci_dev * pdev)3696 qla2x00_remove_one(struct pci_dev *pdev)
3697 {
3698 scsi_qla_host_t *base_vha;
3699 struct qla_hw_data *ha;
3700
3701 base_vha = pci_get_drvdata(pdev);
3702 ha = base_vha->hw;
3703 ql_log(ql_log_info, base_vha, 0xb079,
3704 "Removing driver\n");
3705 __qla_set_remove_flag(base_vha);
3706 cancel_work_sync(&ha->board_disable);
3707
3708 /*
3709 * If the PCI device is disabled then there was a PCI-disconnect and
3710 * qla2x00_disable_board_on_pci_error has taken care of most of the
3711 * resources.
3712 */
3713 if (!atomic_read(&pdev->enable_cnt)) {
3714 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3715 base_vha->gnl.l, base_vha->gnl.ldma);
3716 base_vha->gnl.l = NULL;
3717 scsi_host_put(base_vha->host);
3718 kfree(ha);
3719 pci_set_drvdata(pdev, NULL);
3720 return;
3721 }
3722 qla2x00_wait_for_hba_ready(base_vha);
3723
3724 /*
3725 * if UNLOADING flag is already set, then continue unload,
3726 * where it was set first.
3727 */
3728 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
3729 return;
3730
3731 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3732 IS_QLA28XX(ha)) {
3733 if (ha->flags.fw_started)
3734 qla2x00_abort_isp_cleanup(base_vha);
3735 } else if (!IS_QLAFX00(ha)) {
3736 if (IS_QLA8031(ha)) {
3737 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3738 "Clearing fcoe driver presence.\n");
3739 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3740 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3741 "Error while clearing DRV-Presence.\n");
3742 }
3743
3744 qla2x00_try_to_stop_firmware(base_vha);
3745 }
3746
3747 qla2x00_wait_for_sess_deletion(base_vha);
3748
3749 qla_nvme_delete(base_vha);
3750
3751 dma_free_coherent(&ha->pdev->dev,
3752 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3753
3754 base_vha->gnl.l = NULL;
3755
3756 vfree(base_vha->scan.l);
3757
3758 if (IS_QLAFX00(ha))
3759 qlafx00_driver_shutdown(base_vha, 20);
3760
3761 qla2x00_delete_all_vps(ha, base_vha);
3762
3763 qla2x00_dfs_remove(base_vha);
3764
3765 qla84xx_put_chip(base_vha);
3766
3767 /* Disable timer */
3768 if (base_vha->timer_active)
3769 qla2x00_stop_timer(base_vha);
3770
3771 base_vha->flags.online = 0;
3772
3773 /* free DMA memory */
3774 if (ha->exlogin_buf)
3775 qla2x00_free_exlogin_buffer(ha);
3776
3777 /* free DMA memory */
3778 if (ha->exchoffld_buf)
3779 qla2x00_free_exchoffld_buffer(ha);
3780
3781 qla2x00_destroy_deferred_work(ha);
3782
3783 qlt_remove_target(ha, base_vha);
3784
3785 qla2x00_free_sysfs_attr(base_vha, true);
3786
3787 fc_remove_host(base_vha->host);
3788 qlt_remove_target_resources(ha);
3789
3790 scsi_remove_host(base_vha->host);
3791
3792 qla2x00_free_device(base_vha);
3793
3794 qla2x00_clear_drv_active(ha);
3795
3796 scsi_host_put(base_vha->host);
3797
3798 qla2x00_unmap_iobases(ha);
3799
3800 pci_release_selected_regions(ha->pdev, ha->bars);
3801 kfree(ha);
3802
3803 pci_disable_pcie_error_reporting(pdev);
3804
3805 pci_disable_device(pdev);
3806 }
3807
3808 static inline void
qla24xx_free_purex_list(struct purex_list * list)3809 qla24xx_free_purex_list(struct purex_list *list)
3810 {
3811 struct list_head *item, *next;
3812 ulong flags;
3813
3814 spin_lock_irqsave(&list->lock, flags);
3815 list_for_each_safe(item, next, &list->head) {
3816 list_del(item);
3817 kfree(list_entry(item, struct purex_item, list));
3818 }
3819 spin_unlock_irqrestore(&list->lock, flags);
3820 }
3821
3822 static void
qla2x00_free_device(scsi_qla_host_t * vha)3823 qla2x00_free_device(scsi_qla_host_t *vha)
3824 {
3825 struct qla_hw_data *ha = vha->hw;
3826
3827 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3828
3829 /* Disable timer */
3830 if (vha->timer_active)
3831 qla2x00_stop_timer(vha);
3832
3833 qla25xx_delete_queues(vha);
3834 vha->flags.online = 0;
3835
3836 /* turn-off interrupts on the card */
3837 if (ha->interrupts_on) {
3838 vha->flags.init_done = 0;
3839 ha->isp_ops->disable_intrs(ha);
3840 }
3841
3842 qla2x00_free_fcports(vha);
3843
3844 qla2x00_free_irqs(vha);
3845
3846 /* Flush the work queue and remove it */
3847 if (ha->wq) {
3848 flush_workqueue(ha->wq);
3849 destroy_workqueue(ha->wq);
3850 ha->wq = NULL;
3851 }
3852
3853
3854 qla24xx_free_purex_list(&vha->purex_list);
3855
3856 qla2x00_mem_free(ha);
3857
3858 qla82xx_md_free(vha);
3859
3860 qla2x00_free_queues(ha);
3861 }
3862
qla2x00_free_fcports(struct scsi_qla_host * vha)3863 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3864 {
3865 fc_port_t *fcport, *tfcport;
3866
3867 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
3868 qla2x00_free_fcport(fcport);
3869 }
3870
3871 static inline void
qla2x00_schedule_rport_del(struct scsi_qla_host * vha,fc_port_t * fcport)3872 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport)
3873 {
3874 int now;
3875
3876 if (!fcport->rport)
3877 return;
3878
3879 if (fcport->rport) {
3880 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3881 "%s %8phN. rport %p roles %x\n",
3882 __func__, fcport->port_name, fcport->rport,
3883 fcport->rport->roles);
3884 fc_remote_port_delete(fcport->rport);
3885 }
3886 qlt_do_generation_tick(vha, &now);
3887 }
3888
3889 /*
3890 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3891 *
3892 * Input: ha = adapter block pointer. fcport = port structure pointer.
3893 *
3894 * Return: None.
3895 *
3896 * Context:
3897 */
qla2x00_mark_device_lost(scsi_qla_host_t * vha,fc_port_t * fcport,int do_login)3898 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3899 int do_login)
3900 {
3901 if (IS_QLAFX00(vha->hw)) {
3902 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3903 qla2x00_schedule_rport_del(vha, fcport);
3904 return;
3905 }
3906
3907 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3908 vha->vp_idx == fcport->vha->vp_idx) {
3909 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3910 qla2x00_schedule_rport_del(vha, fcport);
3911 }
3912 /*
3913 * We may need to retry the login, so don't change the state of the
3914 * port but do the retries.
3915 */
3916 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3917 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3918
3919 if (!do_login)
3920 return;
3921
3922 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3923 }
3924
3925 void
qla2x00_mark_all_devices_lost(scsi_qla_host_t * vha)3926 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha)
3927 {
3928 fc_port_t *fcport;
3929
3930 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3931 "Mark all dev lost\n");
3932
3933 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3934 if (fcport->loop_id != FC_NO_LOOP_ID &&
3935 (fcport->flags & FCF_FCP2_DEVICE) &&
3936 fcport->port_type == FCT_TARGET &&
3937 !qla2x00_reset_active(vha)) {
3938 ql_dbg(ql_dbg_disc, vha, 0x211a,
3939 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC",
3940 fcport->flags, fcport->port_type,
3941 fcport->d_id.b24, fcport->port_name);
3942 continue;
3943 }
3944 fcport->scan_state = 0;
3945 qlt_schedule_sess_for_deletion(fcport);
3946 }
3947 }
3948
qla2x00_set_reserved_loop_ids(struct qla_hw_data * ha)3949 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
3950 {
3951 int i;
3952
3953 if (IS_FWI2_CAPABLE(ha))
3954 return;
3955
3956 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
3957 set_bit(i, ha->loop_id_map);
3958 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
3959 set_bit(BROADCAST, ha->loop_id_map);
3960 }
3961
3962 /*
3963 * qla2x00_mem_alloc
3964 * Allocates adapter memory.
3965 *
3966 * Returns:
3967 * 0 = success.
3968 * !0 = failure.
3969 */
3970 static int
qla2x00_mem_alloc(struct qla_hw_data * ha,uint16_t req_len,uint16_t rsp_len,struct req_que ** req,struct rsp_que ** rsp)3971 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3972 struct req_que **req, struct rsp_que **rsp)
3973 {
3974 char name[16];
3975
3976 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3977 &ha->init_cb_dma, GFP_KERNEL);
3978 if (!ha->init_cb)
3979 goto fail;
3980
3981 if (qlt_mem_alloc(ha) < 0)
3982 goto fail_free_init_cb;
3983
3984 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3985 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3986 if (!ha->gid_list)
3987 goto fail_free_tgt_mem;
3988
3989 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3990 if (!ha->srb_mempool)
3991 goto fail_free_gid_list;
3992
3993 if (IS_P3P_TYPE(ha)) {
3994 /* Allocate cache for CT6 Ctx. */
3995 if (!ctx_cachep) {
3996 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3997 sizeof(struct ct6_dsd), 0,
3998 SLAB_HWCACHE_ALIGN, NULL);
3999 if (!ctx_cachep)
4000 goto fail_free_srb_mempool;
4001 }
4002 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4003 ctx_cachep);
4004 if (!ha->ctx_mempool)
4005 goto fail_free_srb_mempool;
4006 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4007 "ctx_cachep=%p ctx_mempool=%p.\n",
4008 ctx_cachep, ha->ctx_mempool);
4009 }
4010
4011 /* Get memory for cached NVRAM */
4012 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4013 if (!ha->nvram)
4014 goto fail_free_ctx_mempool;
4015
4016 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4017 ha->pdev->device);
4018 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4019 DMA_POOL_SIZE, 8, 0);
4020 if (!ha->s_dma_pool)
4021 goto fail_free_nvram;
4022
4023 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4024 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4025 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4026
4027 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
4028 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4029 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4030 if (!ha->dl_dma_pool) {
4031 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4032 "Failed to allocate memory for dl_dma_pool.\n");
4033 goto fail_s_dma_pool;
4034 }
4035
4036 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4037 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4038 if (!ha->fcp_cmnd_dma_pool) {
4039 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4040 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
4041 goto fail_dl_dma_pool;
4042 }
4043
4044 if (ql2xenabledif) {
4045 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4046 struct dsd_dma *dsd, *nxt;
4047 uint i;
4048 /* Creata a DMA pool of buffers for DIF bundling */
4049 ha->dif_bundl_pool = dma_pool_create(name,
4050 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4051 if (!ha->dif_bundl_pool) {
4052 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4053 "%s: failed create dif_bundl_pool\n",
4054 __func__);
4055 goto fail_dif_bundl_dma_pool;
4056 }
4057
4058 INIT_LIST_HEAD(&ha->pool.good.head);
4059 INIT_LIST_HEAD(&ha->pool.unusable.head);
4060 ha->pool.good.count = 0;
4061 ha->pool.unusable.count = 0;
4062 for (i = 0; i < 128; i++) {
4063 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4064 if (!dsd) {
4065 ql_dbg_pci(ql_dbg_init, ha->pdev,
4066 0xe0ee, "%s: failed alloc dsd\n",
4067 __func__);
4068 return -ENOMEM;
4069 }
4070 ha->dif_bundle_kallocs++;
4071
4072 dsd->dsd_addr = dma_pool_alloc(
4073 ha->dif_bundl_pool, GFP_ATOMIC,
4074 &dsd->dsd_list_dma);
4075 if (!dsd->dsd_addr) {
4076 ql_dbg_pci(ql_dbg_init, ha->pdev,
4077 0xe0ee,
4078 "%s: failed alloc ->dsd_addr\n",
4079 __func__);
4080 kfree(dsd);
4081 ha->dif_bundle_kallocs--;
4082 continue;
4083 }
4084 ha->dif_bundle_dma_allocs++;
4085
4086 /*
4087 * if DMA buffer crosses 4G boundary,
4088 * put it on bad list
4089 */
4090 if (MSD(dsd->dsd_list_dma) ^
4091 MSD(dsd->dsd_list_dma + bufsize)) {
4092 list_add_tail(&dsd->list,
4093 &ha->pool.unusable.head);
4094 ha->pool.unusable.count++;
4095 } else {
4096 list_add_tail(&dsd->list,
4097 &ha->pool.good.head);
4098 ha->pool.good.count++;
4099 }
4100 }
4101
4102 /* return the good ones back to the pool */
4103 list_for_each_entry_safe(dsd, nxt,
4104 &ha->pool.good.head, list) {
4105 list_del(&dsd->list);
4106 dma_pool_free(ha->dif_bundl_pool,
4107 dsd->dsd_addr, dsd->dsd_list_dma);
4108 ha->dif_bundle_dma_allocs--;
4109 kfree(dsd);
4110 ha->dif_bundle_kallocs--;
4111 }
4112
4113 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4114 "%s: dif dma pool (good=%u unusable=%u)\n",
4115 __func__, ha->pool.good.count,
4116 ha->pool.unusable.count);
4117 }
4118
4119 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4120 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4121 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4122 ha->dif_bundl_pool);
4123 }
4124
4125 /* Allocate memory for SNS commands */
4126 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4127 /* Get consistent memory allocated for SNS commands */
4128 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4129 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4130 if (!ha->sns_cmd)
4131 goto fail_dma_pool;
4132 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4133 "sns_cmd: %p.\n", ha->sns_cmd);
4134 } else {
4135 /* Get consistent memory allocated for MS IOCB */
4136 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4137 &ha->ms_iocb_dma);
4138 if (!ha->ms_iocb)
4139 goto fail_dma_pool;
4140 /* Get consistent memory allocated for CT SNS commands */
4141 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4142 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4143 if (!ha->ct_sns)
4144 goto fail_free_ms_iocb;
4145 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4146 "ms_iocb=%p ct_sns=%p.\n",
4147 ha->ms_iocb, ha->ct_sns);
4148 }
4149
4150 /* Allocate memory for request ring */
4151 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4152 if (!*req) {
4153 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4154 "Failed to allocate memory for req.\n");
4155 goto fail_req;
4156 }
4157 (*req)->length = req_len;
4158 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4159 ((*req)->length + 1) * sizeof(request_t),
4160 &(*req)->dma, GFP_KERNEL);
4161 if (!(*req)->ring) {
4162 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4163 "Failed to allocate memory for req_ring.\n");
4164 goto fail_req_ring;
4165 }
4166 /* Allocate memory for response ring */
4167 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4168 if (!*rsp) {
4169 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4170 "Failed to allocate memory for rsp.\n");
4171 goto fail_rsp;
4172 }
4173 (*rsp)->hw = ha;
4174 (*rsp)->length = rsp_len;
4175 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4176 ((*rsp)->length + 1) * sizeof(response_t),
4177 &(*rsp)->dma, GFP_KERNEL);
4178 if (!(*rsp)->ring) {
4179 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4180 "Failed to allocate memory for rsp_ring.\n");
4181 goto fail_rsp_ring;
4182 }
4183 (*req)->rsp = *rsp;
4184 (*rsp)->req = *req;
4185 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4186 "req=%p req->length=%d req->ring=%p rsp=%p "
4187 "rsp->length=%d rsp->ring=%p.\n",
4188 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4189 (*rsp)->ring);
4190 /* Allocate memory for NVRAM data for vports */
4191 if (ha->nvram_npiv_size) {
4192 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4193 sizeof(struct qla_npiv_entry),
4194 GFP_KERNEL);
4195 if (!ha->npiv_info) {
4196 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4197 "Failed to allocate memory for npiv_info.\n");
4198 goto fail_npiv_info;
4199 }
4200 } else
4201 ha->npiv_info = NULL;
4202
4203 /* Get consistent memory allocated for EX-INIT-CB. */
4204 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4205 IS_QLA28XX(ha)) {
4206 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4207 &ha->ex_init_cb_dma);
4208 if (!ha->ex_init_cb)
4209 goto fail_ex_init_cb;
4210 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4211 "ex_init_cb=%p.\n", ha->ex_init_cb);
4212 }
4213
4214 /* Get consistent memory allocated for Special Features-CB. */
4215 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4216 ha->sf_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4217 &ha->sf_init_cb_dma);
4218 if (!ha->sf_init_cb)
4219 goto fail_sf_init_cb;
4220 memset(ha->sf_init_cb, 0, sizeof(struct init_sf_cb));
4221 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
4222 "sf_init_cb=%p.\n", ha->sf_init_cb);
4223 }
4224
4225 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4226
4227 /* Get consistent memory allocated for Async Port-Database. */
4228 if (!IS_FWI2_CAPABLE(ha)) {
4229 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4230 &ha->async_pd_dma);
4231 if (!ha->async_pd)
4232 goto fail_async_pd;
4233 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4234 "async_pd=%p.\n", ha->async_pd);
4235 }
4236
4237 INIT_LIST_HEAD(&ha->vp_list);
4238
4239 /* Allocate memory for our loop_id bitmap */
4240 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4241 sizeof(long),
4242 GFP_KERNEL);
4243 if (!ha->loop_id_map)
4244 goto fail_loop_id_map;
4245 else {
4246 qla2x00_set_reserved_loop_ids(ha);
4247 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4248 "loop_id_map=%p.\n", ha->loop_id_map);
4249 }
4250
4251 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4252 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4253 if (!ha->sfp_data) {
4254 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4255 "Unable to allocate memory for SFP read-data.\n");
4256 goto fail_sfp_data;
4257 }
4258
4259 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4260 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4261 GFP_KERNEL);
4262 if (!ha->flt) {
4263 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4264 "Unable to allocate memory for FLT.\n");
4265 goto fail_flt_buffer;
4266 }
4267
4268 return 0;
4269
4270 fail_flt_buffer:
4271 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4272 ha->sfp_data, ha->sfp_data_dma);
4273 fail_sfp_data:
4274 kfree(ha->loop_id_map);
4275 fail_loop_id_map:
4276 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4277 fail_async_pd:
4278 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma);
4279 fail_sf_init_cb:
4280 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4281 fail_ex_init_cb:
4282 kfree(ha->npiv_info);
4283 fail_npiv_info:
4284 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4285 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4286 (*rsp)->ring = NULL;
4287 (*rsp)->dma = 0;
4288 fail_rsp_ring:
4289 kfree(*rsp);
4290 *rsp = NULL;
4291 fail_rsp:
4292 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4293 sizeof(request_t), (*req)->ring, (*req)->dma);
4294 (*req)->ring = NULL;
4295 (*req)->dma = 0;
4296 fail_req_ring:
4297 kfree(*req);
4298 *req = NULL;
4299 fail_req:
4300 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4301 ha->ct_sns, ha->ct_sns_dma);
4302 ha->ct_sns = NULL;
4303 ha->ct_sns_dma = 0;
4304 fail_free_ms_iocb:
4305 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4306 ha->ms_iocb = NULL;
4307 ha->ms_iocb_dma = 0;
4308
4309 if (ha->sns_cmd)
4310 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4311 ha->sns_cmd, ha->sns_cmd_dma);
4312 fail_dma_pool:
4313 if (ql2xenabledif) {
4314 struct dsd_dma *dsd, *nxt;
4315
4316 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4317 list) {
4318 list_del(&dsd->list);
4319 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4320 dsd->dsd_list_dma);
4321 ha->dif_bundle_dma_allocs--;
4322 kfree(dsd);
4323 ha->dif_bundle_kallocs--;
4324 ha->pool.unusable.count--;
4325 }
4326 dma_pool_destroy(ha->dif_bundl_pool);
4327 ha->dif_bundl_pool = NULL;
4328 }
4329
4330 fail_dif_bundl_dma_pool:
4331 if (IS_QLA82XX(ha) || ql2xenabledif) {
4332 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4333 ha->fcp_cmnd_dma_pool = NULL;
4334 }
4335 fail_dl_dma_pool:
4336 if (IS_QLA82XX(ha) || ql2xenabledif) {
4337 dma_pool_destroy(ha->dl_dma_pool);
4338 ha->dl_dma_pool = NULL;
4339 }
4340 fail_s_dma_pool:
4341 dma_pool_destroy(ha->s_dma_pool);
4342 ha->s_dma_pool = NULL;
4343 fail_free_nvram:
4344 kfree(ha->nvram);
4345 ha->nvram = NULL;
4346 fail_free_ctx_mempool:
4347 mempool_destroy(ha->ctx_mempool);
4348 ha->ctx_mempool = NULL;
4349 fail_free_srb_mempool:
4350 mempool_destroy(ha->srb_mempool);
4351 ha->srb_mempool = NULL;
4352 fail_free_gid_list:
4353 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4354 ha->gid_list,
4355 ha->gid_list_dma);
4356 ha->gid_list = NULL;
4357 ha->gid_list_dma = 0;
4358 fail_free_tgt_mem:
4359 qlt_mem_free(ha);
4360 fail_free_init_cb:
4361 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4362 ha->init_cb_dma);
4363 ha->init_cb = NULL;
4364 ha->init_cb_dma = 0;
4365 fail:
4366 ql_log(ql_log_fatal, NULL, 0x0030,
4367 "Memory allocation failure.\n");
4368 return -ENOMEM;
4369 }
4370
4371 int
qla2x00_set_exlogins_buffer(scsi_qla_host_t * vha)4372 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4373 {
4374 int rval;
4375 uint16_t size, max_cnt;
4376 uint32_t temp;
4377 struct qla_hw_data *ha = vha->hw;
4378
4379 /* Return if we don't need to alloacate any extended logins */
4380 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400)
4381 return QLA_SUCCESS;
4382
4383 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4384 return QLA_SUCCESS;
4385
4386 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4387 max_cnt = 0;
4388 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4389 if (rval != QLA_SUCCESS) {
4390 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4391 "Failed to get exlogin status.\n");
4392 return rval;
4393 }
4394
4395 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4396 temp *= size;
4397
4398 if (temp != ha->exlogin_size) {
4399 qla2x00_free_exlogin_buffer(ha);
4400 ha->exlogin_size = temp;
4401
4402 ql_log(ql_log_info, vha, 0xd024,
4403 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4404 max_cnt, size, temp);
4405
4406 ql_log(ql_log_info, vha, 0xd025,
4407 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4408
4409 /* Get consistent memory for extended logins */
4410 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4411 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4412 if (!ha->exlogin_buf) {
4413 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4414 "Failed to allocate memory for exlogin_buf_dma.\n");
4415 return -ENOMEM;
4416 }
4417 }
4418
4419 /* Now configure the dma buffer */
4420 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4421 if (rval) {
4422 ql_log(ql_log_fatal, vha, 0xd033,
4423 "Setup extended login buffer ****FAILED****.\n");
4424 qla2x00_free_exlogin_buffer(ha);
4425 }
4426
4427 return rval;
4428 }
4429
4430 /*
4431 * qla2x00_free_exlogin_buffer
4432 *
4433 * Input:
4434 * ha = adapter block pointer
4435 */
4436 void
qla2x00_free_exlogin_buffer(struct qla_hw_data * ha)4437 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4438 {
4439 if (ha->exlogin_buf) {
4440 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4441 ha->exlogin_buf, ha->exlogin_buf_dma);
4442 ha->exlogin_buf = NULL;
4443 ha->exlogin_size = 0;
4444 }
4445 }
4446
4447 static void
qla2x00_number_of_exch(scsi_qla_host_t * vha,u32 * ret_cnt,u16 max_cnt)4448 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4449 {
4450 u32 temp;
4451 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
4452 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4453
4454 if (max_cnt > vha->hw->max_exchg)
4455 max_cnt = vha->hw->max_exchg;
4456
4457 if (qla_ini_mode_enabled(vha)) {
4458 if (vha->ql2xiniexchg > max_cnt)
4459 vha->ql2xiniexchg = max_cnt;
4460
4461 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4462 *ret_cnt = vha->ql2xiniexchg;
4463
4464 } else if (qla_tgt_mode_enabled(vha)) {
4465 if (vha->ql2xexchoffld > max_cnt) {
4466 vha->ql2xexchoffld = max_cnt;
4467 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4468 }
4469
4470 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4471 *ret_cnt = vha->ql2xexchoffld;
4472 } else if (qla_dual_mode_enabled(vha)) {
4473 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4474 if (temp > max_cnt) {
4475 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4476 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4477 temp = max_cnt;
4478 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4479 }
4480
4481 if (temp > FW_DEF_EXCHANGES_CNT)
4482 *ret_cnt = temp;
4483 }
4484 }
4485
4486 int
qla2x00_set_exchoffld_buffer(scsi_qla_host_t * vha)4487 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4488 {
4489 int rval;
4490 u16 size, max_cnt;
4491 u32 actual_cnt, totsz;
4492 struct qla_hw_data *ha = vha->hw;
4493
4494 if (!ha->flags.exchoffld_enabled)
4495 return QLA_SUCCESS;
4496
4497 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4498 return QLA_SUCCESS;
4499
4500 max_cnt = 0;
4501 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4502 if (rval != QLA_SUCCESS) {
4503 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4504 "Failed to get exlogin status.\n");
4505 return rval;
4506 }
4507
4508 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4509 ql_log(ql_log_info, vha, 0xd014,
4510 "Actual exchange offload count: %d.\n", actual_cnt);
4511
4512 totsz = actual_cnt * size;
4513
4514 if (totsz != ha->exchoffld_size) {
4515 qla2x00_free_exchoffld_buffer(ha);
4516 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4517 ha->exchoffld_size = 0;
4518 ha->flags.exchoffld_enabled = 0;
4519 return QLA_SUCCESS;
4520 }
4521
4522 ha->exchoffld_size = totsz;
4523
4524 ql_log(ql_log_info, vha, 0xd016,
4525 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4526 max_cnt, actual_cnt, size, totsz);
4527
4528 ql_log(ql_log_info, vha, 0xd017,
4529 "Exchange Buffers requested size = 0x%x\n",
4530 ha->exchoffld_size);
4531
4532 /* Get consistent memory for extended logins */
4533 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4534 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4535 if (!ha->exchoffld_buf) {
4536 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4537 "Failed to allocate memory for Exchange Offload.\n");
4538
4539 if (ha->max_exchg >
4540 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4541 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4542 } else if (ha->max_exchg >
4543 (FW_DEF_EXCHANGES_CNT + 512)) {
4544 ha->max_exchg -= 512;
4545 } else {
4546 ha->flags.exchoffld_enabled = 0;
4547 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4548 "Disabling Exchange offload due to lack of memory\n");
4549 }
4550 ha->exchoffld_size = 0;
4551
4552 return -ENOMEM;
4553 }
4554 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4555 /* pathological case */
4556 qla2x00_free_exchoffld_buffer(ha);
4557 ha->exchoffld_size = 0;
4558 ha->flags.exchoffld_enabled = 0;
4559 ql_log(ql_log_info, vha, 0xd016,
4560 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4561 ha->exchoffld_size, actual_cnt, size, totsz);
4562 return 0;
4563 }
4564
4565 /* Now configure the dma buffer */
4566 rval = qla_set_exchoffld_mem_cfg(vha);
4567 if (rval) {
4568 ql_log(ql_log_fatal, vha, 0xd02e,
4569 "Setup exchange offload buffer ****FAILED****.\n");
4570 qla2x00_free_exchoffld_buffer(ha);
4571 } else {
4572 /* re-adjust number of target exchange */
4573 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4574
4575 if (qla_ini_mode_enabled(vha))
4576 icb->exchange_count = 0;
4577 else
4578 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4579 }
4580
4581 return rval;
4582 }
4583
4584 /*
4585 * qla2x00_free_exchoffld_buffer
4586 *
4587 * Input:
4588 * ha = adapter block pointer
4589 */
4590 void
qla2x00_free_exchoffld_buffer(struct qla_hw_data * ha)4591 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4592 {
4593 if (ha->exchoffld_buf) {
4594 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4595 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4596 ha->exchoffld_buf = NULL;
4597 ha->exchoffld_size = 0;
4598 }
4599 }
4600
4601 /*
4602 * qla2x00_free_fw_dump
4603 * Frees fw dump stuff.
4604 *
4605 * Input:
4606 * ha = adapter block pointer
4607 */
4608 static void
qla2x00_free_fw_dump(struct qla_hw_data * ha)4609 qla2x00_free_fw_dump(struct qla_hw_data *ha)
4610 {
4611 struct fwdt *fwdt = ha->fwdt;
4612 uint j;
4613
4614 if (ha->fce)
4615 dma_free_coherent(&ha->pdev->dev,
4616 FCE_SIZE, ha->fce, ha->fce_dma);
4617
4618 if (ha->eft)
4619 dma_free_coherent(&ha->pdev->dev,
4620 EFT_SIZE, ha->eft, ha->eft_dma);
4621
4622 if (ha->fw_dump)
4623 vfree(ha->fw_dump);
4624
4625 ha->fce = NULL;
4626 ha->fce_dma = 0;
4627 ha->flags.fce_enabled = 0;
4628 ha->eft = NULL;
4629 ha->eft_dma = 0;
4630 ha->fw_dumped = false;
4631 ha->fw_dump_cap_flags = 0;
4632 ha->fw_dump_reading = 0;
4633 ha->fw_dump = NULL;
4634 ha->fw_dump_len = 0;
4635
4636 for (j = 0; j < 2; j++, fwdt++) {
4637 if (fwdt->template)
4638 vfree(fwdt->template);
4639 fwdt->template = NULL;
4640 fwdt->length = 0;
4641 }
4642 }
4643
4644 /*
4645 * qla2x00_mem_free
4646 * Frees all adapter allocated memory.
4647 *
4648 * Input:
4649 * ha = adapter block pointer.
4650 */
4651 static void
qla2x00_mem_free(struct qla_hw_data * ha)4652 qla2x00_mem_free(struct qla_hw_data *ha)
4653 {
4654 qla2x00_free_fw_dump(ha);
4655
4656 if (ha->mctp_dump)
4657 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4658 ha->mctp_dump_dma);
4659 ha->mctp_dump = NULL;
4660
4661 mempool_destroy(ha->srb_mempool);
4662 ha->srb_mempool = NULL;
4663
4664 if (ha->dcbx_tlv)
4665 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4666 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4667 ha->dcbx_tlv = NULL;
4668
4669 if (ha->xgmac_data)
4670 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4671 ha->xgmac_data, ha->xgmac_data_dma);
4672 ha->xgmac_data = NULL;
4673
4674 if (ha->sns_cmd)
4675 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4676 ha->sns_cmd, ha->sns_cmd_dma);
4677 ha->sns_cmd = NULL;
4678 ha->sns_cmd_dma = 0;
4679
4680 if (ha->ct_sns)
4681 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4682 ha->ct_sns, ha->ct_sns_dma);
4683 ha->ct_sns = NULL;
4684 ha->ct_sns_dma = 0;
4685
4686 if (ha->sfp_data)
4687 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4688 ha->sfp_data_dma);
4689 ha->sfp_data = NULL;
4690
4691 if (ha->flt)
4692 dma_free_coherent(&ha->pdev->dev,
4693 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4694 ha->flt, ha->flt_dma);
4695 ha->flt = NULL;
4696 ha->flt_dma = 0;
4697
4698 if (ha->ms_iocb)
4699 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4700 ha->ms_iocb = NULL;
4701 ha->ms_iocb_dma = 0;
4702
4703 if (ha->sf_init_cb)
4704 dma_pool_free(ha->s_dma_pool,
4705 ha->sf_init_cb, ha->sf_init_cb_dma);
4706
4707 if (ha->ex_init_cb)
4708 dma_pool_free(ha->s_dma_pool,
4709 ha->ex_init_cb, ha->ex_init_cb_dma);
4710 ha->ex_init_cb = NULL;
4711 ha->ex_init_cb_dma = 0;
4712
4713 if (ha->async_pd)
4714 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4715 ha->async_pd = NULL;
4716 ha->async_pd_dma = 0;
4717
4718 dma_pool_destroy(ha->s_dma_pool);
4719 ha->s_dma_pool = NULL;
4720
4721 if (ha->gid_list)
4722 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4723 ha->gid_list, ha->gid_list_dma);
4724 ha->gid_list = NULL;
4725 ha->gid_list_dma = 0;
4726
4727 if (IS_QLA82XX(ha)) {
4728 if (!list_empty(&ha->gbl_dsd_list)) {
4729 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4730
4731 /* clean up allocated prev pool */
4732 list_for_each_entry_safe(dsd_ptr,
4733 tdsd_ptr, &ha->gbl_dsd_list, list) {
4734 dma_pool_free(ha->dl_dma_pool,
4735 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4736 list_del(&dsd_ptr->list);
4737 kfree(dsd_ptr);
4738 }
4739 }
4740 }
4741
4742 dma_pool_destroy(ha->dl_dma_pool);
4743 ha->dl_dma_pool = NULL;
4744
4745 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4746 ha->fcp_cmnd_dma_pool = NULL;
4747
4748 mempool_destroy(ha->ctx_mempool);
4749 ha->ctx_mempool = NULL;
4750
4751 if (ql2xenabledif && ha->dif_bundl_pool) {
4752 struct dsd_dma *dsd, *nxt;
4753
4754 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4755 list) {
4756 list_del(&dsd->list);
4757 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4758 dsd->dsd_list_dma);
4759 ha->dif_bundle_dma_allocs--;
4760 kfree(dsd);
4761 ha->dif_bundle_kallocs--;
4762 ha->pool.unusable.count--;
4763 }
4764 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4765 list_del(&dsd->list);
4766 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4767 dsd->dsd_list_dma);
4768 ha->dif_bundle_dma_allocs--;
4769 kfree(dsd);
4770 ha->dif_bundle_kallocs--;
4771 }
4772 }
4773
4774 dma_pool_destroy(ha->dif_bundl_pool);
4775 ha->dif_bundl_pool = NULL;
4776
4777 qlt_mem_free(ha);
4778
4779 if (ha->init_cb)
4780 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
4781 ha->init_cb, ha->init_cb_dma);
4782 ha->init_cb = NULL;
4783 ha->init_cb_dma = 0;
4784
4785 vfree(ha->optrom_buffer);
4786 ha->optrom_buffer = NULL;
4787 kfree(ha->nvram);
4788 ha->nvram = NULL;
4789 kfree(ha->npiv_info);
4790 ha->npiv_info = NULL;
4791 kfree(ha->swl);
4792 ha->swl = NULL;
4793 kfree(ha->loop_id_map);
4794 ha->sf_init_cb = NULL;
4795 ha->sf_init_cb_dma = 0;
4796 ha->loop_id_map = NULL;
4797 }
4798
qla2x00_create_host(struct scsi_host_template * sht,struct qla_hw_data * ha)4799 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4800 struct qla_hw_data *ha)
4801 {
4802 struct Scsi_Host *host;
4803 struct scsi_qla_host *vha = NULL;
4804
4805 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
4806 if (!host) {
4807 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4808 "Failed to allocate host from the scsi layer, aborting.\n");
4809 return NULL;
4810 }
4811
4812 /* Clear our data area */
4813 vha = shost_priv(host);
4814 memset(vha, 0, sizeof(scsi_qla_host_t));
4815
4816 vha->host = host;
4817 vha->host_no = host->host_no;
4818 vha->hw = ha;
4819
4820 vha->qlini_mode = ql2x_ini_mode;
4821 vha->ql2xexchoffld = ql2xexchoffld;
4822 vha->ql2xiniexchg = ql2xiniexchg;
4823
4824 INIT_LIST_HEAD(&vha->vp_fcports);
4825 INIT_LIST_HEAD(&vha->work_list);
4826 INIT_LIST_HEAD(&vha->list);
4827 INIT_LIST_HEAD(&vha->qla_cmd_list);
4828 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
4829 INIT_LIST_HEAD(&vha->logo_list);
4830 INIT_LIST_HEAD(&vha->plogi_ack_list);
4831 INIT_LIST_HEAD(&vha->qp_list);
4832 INIT_LIST_HEAD(&vha->gnl.fcports);
4833 INIT_LIST_HEAD(&vha->gpnid_list);
4834 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
4835
4836 INIT_LIST_HEAD(&vha->purex_list.head);
4837 spin_lock_init(&vha->purex_list.lock);
4838
4839 spin_lock_init(&vha->work_lock);
4840 spin_lock_init(&vha->cmd_list_lock);
4841 init_waitqueue_head(&vha->fcport_waitQ);
4842 init_waitqueue_head(&vha->vref_waitq);
4843
4844 vha->gnl.size = sizeof(struct get_name_list_extended) *
4845 (ha->max_loop_id + 1);
4846 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4847 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4848 if (!vha->gnl.l) {
4849 ql_log(ql_log_fatal, vha, 0xd04a,
4850 "Alloc failed for name list.\n");
4851 scsi_host_put(vha->host);
4852 return NULL;
4853 }
4854
4855 /* todo: what about ext login? */
4856 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4857 vha->scan.l = vmalloc(vha->scan.size);
4858 if (!vha->scan.l) {
4859 ql_log(ql_log_fatal, vha, 0xd04a,
4860 "Alloc failed for scan database.\n");
4861 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4862 vha->gnl.l, vha->gnl.ldma);
4863 vha->gnl.l = NULL;
4864 scsi_host_put(vha->host);
4865 return NULL;
4866 }
4867 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
4868
4869 sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no);
4870 ql_dbg(ql_dbg_init, vha, 0x0041,
4871 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4872 vha->host, vha->hw, vha,
4873 dev_name(&(ha->pdev->dev)));
4874
4875 return vha;
4876 }
4877
4878 struct qla_work_evt *
qla2x00_alloc_work(struct scsi_qla_host * vha,enum qla_work_type type)4879 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
4880 {
4881 struct qla_work_evt *e;
4882 uint8_t bail;
4883
4884 if (test_bit(UNLOADING, &vha->dpc_flags))
4885 return NULL;
4886
4887 QLA_VHA_MARK_BUSY(vha, bail);
4888 if (bail)
4889 return NULL;
4890
4891 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
4892 if (!e) {
4893 QLA_VHA_MARK_NOT_BUSY(vha);
4894 return NULL;
4895 }
4896
4897 INIT_LIST_HEAD(&e->list);
4898 e->type = type;
4899 e->flags = QLA_EVT_FLAG_FREE;
4900 return e;
4901 }
4902
4903 int
qla2x00_post_work(struct scsi_qla_host * vha,struct qla_work_evt * e)4904 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
4905 {
4906 unsigned long flags;
4907 bool q = false;
4908
4909 spin_lock_irqsave(&vha->work_lock, flags);
4910 list_add_tail(&e->list, &vha->work_list);
4911
4912 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4913 q = true;
4914
4915 spin_unlock_irqrestore(&vha->work_lock, flags);
4916
4917 if (q)
4918 queue_work(vha->hw->wq, &vha->iocb_work);
4919
4920 return QLA_SUCCESS;
4921 }
4922
4923 int
qla2x00_post_aen_work(struct scsi_qla_host * vha,enum fc_host_event_code code,u32 data)4924 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
4925 u32 data)
4926 {
4927 struct qla_work_evt *e;
4928
4929 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
4930 if (!e)
4931 return QLA_FUNCTION_FAILED;
4932
4933 e->u.aen.code = code;
4934 e->u.aen.data = data;
4935 return qla2x00_post_work(vha, e);
4936 }
4937
4938 int
qla2x00_post_idc_ack_work(struct scsi_qla_host * vha,uint16_t * mb)4939 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4940 {
4941 struct qla_work_evt *e;
4942
4943 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
4944 if (!e)
4945 return QLA_FUNCTION_FAILED;
4946
4947 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4948 return qla2x00_post_work(vha, e);
4949 }
4950
4951 #define qla2x00_post_async_work(name, type) \
4952 int qla2x00_post_async_##name##_work( \
4953 struct scsi_qla_host *vha, \
4954 fc_port_t *fcport, uint16_t *data) \
4955 { \
4956 struct qla_work_evt *e; \
4957 \
4958 e = qla2x00_alloc_work(vha, type); \
4959 if (!e) \
4960 return QLA_FUNCTION_FAILED; \
4961 \
4962 e->u.logio.fcport = fcport; \
4963 if (data) { \
4964 e->u.logio.data[0] = data[0]; \
4965 e->u.logio.data[1] = data[1]; \
4966 } \
4967 fcport->flags |= FCF_ASYNC_ACTIVE; \
4968 return qla2x00_post_work(vha, e); \
4969 }
4970
4971 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4972 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4973 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4974 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4975 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
4976
4977 int
qla2x00_post_uevent_work(struct scsi_qla_host * vha,u32 code)4978 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4979 {
4980 struct qla_work_evt *e;
4981
4982 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4983 if (!e)
4984 return QLA_FUNCTION_FAILED;
4985
4986 e->u.uevent.code = code;
4987 return qla2x00_post_work(vha, e);
4988 }
4989
4990 static void
qla2x00_uevent_emit(struct scsi_qla_host * vha,u32 code)4991 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4992 {
4993 char event_string[40];
4994 char *envp[] = { event_string, NULL };
4995
4996 switch (code) {
4997 case QLA_UEVENT_CODE_FW_DUMP:
4998 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
4999 vha->host_no);
5000 break;
5001 default:
5002 /* do nothing */
5003 break;
5004 }
5005 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5006 }
5007
5008 int
qlafx00_post_aenfx_work(struct scsi_qla_host * vha,uint32_t evtcode,uint32_t * data,int cnt)5009 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5010 uint32_t *data, int cnt)
5011 {
5012 struct qla_work_evt *e;
5013
5014 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5015 if (!e)
5016 return QLA_FUNCTION_FAILED;
5017
5018 e->u.aenfx.evtcode = evtcode;
5019 e->u.aenfx.count = cnt;
5020 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5021 return qla2x00_post_work(vha, e);
5022 }
5023
qla24xx_sched_upd_fcport(fc_port_t * fcport)5024 void qla24xx_sched_upd_fcport(fc_port_t *fcport)
5025 {
5026 unsigned long flags;
5027
5028 if (IS_SW_RESV_ADDR(fcport->d_id))
5029 return;
5030
5031 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5032 if (fcport->disc_state == DSC_UPD_FCPORT) {
5033 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5034 return;
5035 }
5036 fcport->jiffies_at_registration = jiffies;
5037 fcport->sec_since_registration = 0;
5038 fcport->next_disc_state = DSC_DELETED;
5039 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
5040 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5041
5042 queue_work(system_unbound_wq, &fcport->reg_work);
5043 }
5044
5045 static
qla24xx_create_new_sess(struct scsi_qla_host * vha,struct qla_work_evt * e)5046 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5047 {
5048 unsigned long flags;
5049 fc_port_t *fcport = NULL, *tfcp;
5050 struct qlt_plogi_ack_t *pla =
5051 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
5052 uint8_t free_fcport = 0;
5053
5054 ql_dbg(ql_dbg_disc, vha, 0xffff,
5055 "%s %d %8phC enter\n",
5056 __func__, __LINE__, e->u.new_sess.port_name);
5057
5058 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5059 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5060 if (fcport) {
5061 fcport->d_id = e->u.new_sess.id;
5062 if (pla) {
5063 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5064 memcpy(fcport->node_name,
5065 pla->iocb.u.isp24.u.plogi.node_name,
5066 WWN_SIZE);
5067 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5068 /* we took an extra ref_count to prevent PLOGI ACK when
5069 * fcport/sess has not been created.
5070 */
5071 pla->ref_count--;
5072 }
5073 } else {
5074 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5075 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5076 if (fcport) {
5077 fcport->d_id = e->u.new_sess.id;
5078 fcport->flags |= FCF_FABRIC_DEVICE;
5079 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5080
5081 memcpy(fcport->port_name, e->u.new_sess.port_name,
5082 WWN_SIZE);
5083
5084 fcport->fc4_type = e->u.new_sess.fc4_type;
5085 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
5086 fcport->dm_login_expire = jiffies +
5087 QLA_N2N_WAIT_TIME * HZ;
5088 fcport->fc4_type = FS_FC4TYPE_FCP;
5089 fcport->n2n_flag = 1;
5090 if (vha->flags.nvme_enabled)
5091 fcport->fc4_type |= FS_FC4TYPE_NVME;
5092 }
5093
5094 } else {
5095 ql_dbg(ql_dbg_disc, vha, 0xffff,
5096 "%s %8phC mem alloc fail.\n",
5097 __func__, e->u.new_sess.port_name);
5098
5099 if (pla) {
5100 list_del(&pla->list);
5101 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5102 }
5103 return;
5104 }
5105
5106 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5107 /* search again to make sure no one else got ahead */
5108 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5109 e->u.new_sess.port_name, 1);
5110 if (tfcp) {
5111 /* should rarily happen */
5112 ql_dbg(ql_dbg_disc, vha, 0xffff,
5113 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5114 __func__, tfcp->port_name, tfcp->disc_state,
5115 tfcp->fw_login_state);
5116
5117 free_fcport = 1;
5118 } else {
5119 list_add_tail(&fcport->list, &vha->vp_fcports);
5120
5121 }
5122 if (pla) {
5123 qlt_plogi_ack_link(vha, pla, fcport,
5124 QLT_PLOGI_LINK_SAME_WWN);
5125 pla->ref_count--;
5126 }
5127 }
5128 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5129
5130 if (fcport) {
5131 fcport->id_changed = 1;
5132 fcport->scan_state = QLA_FCPORT_FOUND;
5133 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5134 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5135
5136 if (pla) {
5137 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5138 u16 wd3_lo;
5139
5140 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5141 fcport->local = 0;
5142 fcport->loop_id =
5143 le16_to_cpu(
5144 pla->iocb.u.isp24.nport_handle);
5145 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5146 wd3_lo =
5147 le16_to_cpu(
5148 pla->iocb.u.isp24.u.prli.wd3_lo);
5149
5150 if (wd3_lo & BIT_7)
5151 fcport->conf_compl_supported = 1;
5152
5153 if ((wd3_lo & BIT_4) == 0)
5154 fcport->port_type = FCT_INITIATOR;
5155 else
5156 fcport->port_type = FCT_TARGET;
5157 }
5158 qlt_plogi_ack_unref(vha, pla);
5159 } else {
5160 fc_port_t *dfcp = NULL;
5161
5162 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5163 tfcp = qla2x00_find_fcport_by_nportid(vha,
5164 &e->u.new_sess.id, 1);
5165 if (tfcp && (tfcp != fcport)) {
5166 /*
5167 * We have a conflict fcport with same NportID.
5168 */
5169 ql_dbg(ql_dbg_disc, vha, 0xffff,
5170 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5171 __func__, tfcp->port_name, tfcp->disc_state,
5172 tfcp->fw_login_state);
5173
5174 switch (tfcp->disc_state) {
5175 case DSC_DELETED:
5176 break;
5177 case DSC_DELETE_PEND:
5178 fcport->login_pause = 1;
5179 tfcp->conflict = fcport;
5180 break;
5181 default:
5182 fcport->login_pause = 1;
5183 tfcp->conflict = fcport;
5184 dfcp = tfcp;
5185 break;
5186 }
5187 }
5188 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5189 if (dfcp)
5190 qlt_schedule_sess_for_deletion(tfcp);
5191
5192 if (N2N_TOPO(vha->hw)) {
5193 fcport->flags &= ~FCF_FABRIC_DEVICE;
5194 fcport->keep_nport_handle = 1;
5195 if (vha->flags.nvme_enabled) {
5196 fcport->fc4_type =
5197 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP);
5198 fcport->n2n_flag = 1;
5199 }
5200 fcport->fw_login_state = 0;
5201
5202 schedule_delayed_work(&vha->scan.scan_work, 5);
5203 } else {
5204 qla24xx_fcport_handle_login(vha, fcport);
5205 }
5206 }
5207 }
5208
5209 if (free_fcport) {
5210 qla2x00_free_fcport(fcport);
5211 if (pla) {
5212 list_del(&pla->list);
5213 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5214 }
5215 }
5216 }
5217
qla_sp_retry(struct scsi_qla_host * vha,struct qla_work_evt * e)5218 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5219 {
5220 struct srb *sp = e->u.iosb.sp;
5221 int rval;
5222
5223 rval = qla2x00_start_sp(sp);
5224 if (rval != QLA_SUCCESS) {
5225 ql_dbg(ql_dbg_disc, vha, 0x2043,
5226 "%s: %s: Re-issue IOCB failed (%d).\n",
5227 __func__, sp->name, rval);
5228 qla24xx_sp_unmap(vha, sp);
5229 }
5230 }
5231
5232 void
qla2x00_do_work(struct scsi_qla_host * vha)5233 qla2x00_do_work(struct scsi_qla_host *vha)
5234 {
5235 struct qla_work_evt *e, *tmp;
5236 unsigned long flags;
5237 LIST_HEAD(work);
5238 int rc;
5239
5240 spin_lock_irqsave(&vha->work_lock, flags);
5241 list_splice_init(&vha->work_list, &work);
5242 spin_unlock_irqrestore(&vha->work_lock, flags);
5243
5244 list_for_each_entry_safe(e, tmp, &work, list) {
5245 rc = QLA_SUCCESS;
5246 switch (e->type) {
5247 case QLA_EVT_AEN:
5248 fc_host_post_event(vha->host, fc_get_event_number(),
5249 e->u.aen.code, e->u.aen.data);
5250 break;
5251 case QLA_EVT_IDC_ACK:
5252 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5253 break;
5254 case QLA_EVT_ASYNC_LOGIN:
5255 qla2x00_async_login(vha, e->u.logio.fcport,
5256 e->u.logio.data);
5257 break;
5258 case QLA_EVT_ASYNC_LOGOUT:
5259 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
5260 break;
5261 case QLA_EVT_ASYNC_ADISC:
5262 qla2x00_async_adisc(vha, e->u.logio.fcport,
5263 e->u.logio.data);
5264 break;
5265 case QLA_EVT_UEVENT:
5266 qla2x00_uevent_emit(vha, e->u.uevent.code);
5267 break;
5268 case QLA_EVT_AENFX:
5269 qlafx00_process_aen(vha, e);
5270 break;
5271 case QLA_EVT_GPNID:
5272 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5273 break;
5274 case QLA_EVT_UNMAP:
5275 qla24xx_sp_unmap(vha, e->u.iosb.sp);
5276 break;
5277 case QLA_EVT_RELOGIN:
5278 qla2x00_relogin(vha);
5279 break;
5280 case QLA_EVT_NEW_SESS:
5281 qla24xx_create_new_sess(vha, e);
5282 break;
5283 case QLA_EVT_GPDB:
5284 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5285 e->u.fcport.opt);
5286 break;
5287 case QLA_EVT_PRLI:
5288 qla24xx_async_prli(vha, e->u.fcport.fcport);
5289 break;
5290 case QLA_EVT_GPSC:
5291 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5292 break;
5293 case QLA_EVT_GNL:
5294 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5295 break;
5296 case QLA_EVT_NACK:
5297 qla24xx_do_nack_work(vha, e);
5298 break;
5299 case QLA_EVT_ASYNC_PRLO:
5300 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
5301 break;
5302 case QLA_EVT_ASYNC_PRLO_DONE:
5303 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5304 e->u.logio.data);
5305 break;
5306 case QLA_EVT_GPNFT:
5307 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5308 e->u.gpnft.sp);
5309 break;
5310 case QLA_EVT_GPNFT_DONE:
5311 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5312 break;
5313 case QLA_EVT_GNNFT_DONE:
5314 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5315 break;
5316 case QLA_EVT_GNNID:
5317 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5318 break;
5319 case QLA_EVT_GFPNID:
5320 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5321 break;
5322 case QLA_EVT_SP_RETRY:
5323 qla_sp_retry(vha, e);
5324 break;
5325 case QLA_EVT_IIDMA:
5326 qla_do_iidma_work(vha, e->u.fcport.fcport);
5327 break;
5328 case QLA_EVT_ELS_PLOGI:
5329 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5330 e->u.fcport.fcport, false);
5331 break;
5332 }
5333
5334 if (rc == EAGAIN) {
5335 /* put 'work' at head of 'vha->work_list' */
5336 spin_lock_irqsave(&vha->work_lock, flags);
5337 list_splice(&work, &vha->work_list);
5338 spin_unlock_irqrestore(&vha->work_lock, flags);
5339 break;
5340 }
5341 list_del_init(&e->list);
5342 if (e->flags & QLA_EVT_FLAG_FREE)
5343 kfree(e);
5344
5345 /* For each work completed decrement vha ref count */
5346 QLA_VHA_MARK_NOT_BUSY(vha);
5347 }
5348 }
5349
qla24xx_post_relogin_work(struct scsi_qla_host * vha)5350 int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5351 {
5352 struct qla_work_evt *e;
5353
5354 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5355
5356 if (!e) {
5357 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5358 return QLA_FUNCTION_FAILED;
5359 }
5360
5361 return qla2x00_post_work(vha, e);
5362 }
5363
5364 /* Relogins all the fcports of a vport
5365 * Context: dpc thread
5366 */
qla2x00_relogin(struct scsi_qla_host * vha)5367 void qla2x00_relogin(struct scsi_qla_host *vha)
5368 {
5369 fc_port_t *fcport;
5370 int status, relogin_needed = 0;
5371 struct event_arg ea;
5372
5373 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5374 /*
5375 * If the port is not ONLINE then try to login
5376 * to it if we haven't run out of retries.
5377 */
5378 if (atomic_read(&fcport->state) != FCS_ONLINE &&
5379 fcport->login_retry) {
5380 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5381 fcport->disc_state == DSC_LOGIN_COMPLETE)
5382 continue;
5383
5384 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5385 fcport->disc_state == DSC_DELETE_PEND) {
5386 relogin_needed = 1;
5387 } else {
5388 if (vha->hw->current_topology != ISP_CFG_NL) {
5389 memset(&ea, 0, sizeof(ea));
5390 ea.fcport = fcport;
5391 qla24xx_handle_relogin_event(vha, &ea);
5392 } else if (vha->hw->current_topology ==
5393 ISP_CFG_NL &&
5394 IS_QLA2XXX_MIDTYPE(vha->hw)) {
5395 (void)qla24xx_fcport_handle_login(vha,
5396 fcport);
5397 } else if (vha->hw->current_topology ==
5398 ISP_CFG_NL) {
5399 fcport->login_retry--;
5400 status =
5401 qla2x00_local_device_login(vha,
5402 fcport);
5403 if (status == QLA_SUCCESS) {
5404 fcport->old_loop_id =
5405 fcport->loop_id;
5406 ql_dbg(ql_dbg_disc, vha, 0x2003,
5407 "Port login OK: logged in ID 0x%x.\n",
5408 fcport->loop_id);
5409 qla2x00_update_fcport
5410 (vha, fcport);
5411 } else if (status == 1) {
5412 set_bit(RELOGIN_NEEDED,
5413 &vha->dpc_flags);
5414 /* retry the login again */
5415 ql_dbg(ql_dbg_disc, vha, 0x2007,
5416 "Retrying %d login again loop_id 0x%x.\n",
5417 fcport->login_retry,
5418 fcport->loop_id);
5419 } else {
5420 fcport->login_retry = 0;
5421 }
5422
5423 if (fcport->login_retry == 0 &&
5424 status != QLA_SUCCESS)
5425 qla2x00_clear_loop_id(fcport);
5426 }
5427 }
5428 }
5429 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5430 break;
5431 }
5432
5433 if (relogin_needed)
5434 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5435
5436 ql_dbg(ql_dbg_disc, vha, 0x400e,
5437 "Relogin end.\n");
5438 }
5439
5440 /* Schedule work on any of the dpc-workqueues */
5441 void
qla83xx_schedule_work(scsi_qla_host_t * base_vha,int work_code)5442 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5443 {
5444 struct qla_hw_data *ha = base_vha->hw;
5445
5446 switch (work_code) {
5447 case MBA_IDC_AEN: /* 0x8200 */
5448 if (ha->dpc_lp_wq)
5449 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5450 break;
5451
5452 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5453 if (!ha->flags.nic_core_reset_hdlr_active) {
5454 if (ha->dpc_hp_wq)
5455 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5456 } else
5457 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5458 "NIC Core reset is already active. Skip "
5459 "scheduling it again.\n");
5460 break;
5461 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5462 if (ha->dpc_hp_wq)
5463 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5464 break;
5465 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5466 if (ha->dpc_hp_wq)
5467 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5468 break;
5469 default:
5470 ql_log(ql_log_warn, base_vha, 0xb05f,
5471 "Unknown work-code=0x%x.\n", work_code);
5472 }
5473
5474 return;
5475 }
5476
5477 /* Work: Perform NIC Core Unrecoverable state handling */
5478 void
qla83xx_nic_core_unrecoverable_work(struct work_struct * work)5479 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5480 {
5481 struct qla_hw_data *ha =
5482 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
5483 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5484 uint32_t dev_state = 0;
5485
5486 qla83xx_idc_lock(base_vha, 0);
5487 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5488 qla83xx_reset_ownership(base_vha);
5489 if (ha->flags.nic_core_reset_owner) {
5490 ha->flags.nic_core_reset_owner = 0;
5491 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5492 QLA8XXX_DEV_FAILED);
5493 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5494 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5495 }
5496 qla83xx_idc_unlock(base_vha, 0);
5497 }
5498
5499 /* Work: Execute IDC state handler */
5500 void
qla83xx_idc_state_handler_work(struct work_struct * work)5501 qla83xx_idc_state_handler_work(struct work_struct *work)
5502 {
5503 struct qla_hw_data *ha =
5504 container_of(work, struct qla_hw_data, idc_state_handler);
5505 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5506 uint32_t dev_state = 0;
5507
5508 qla83xx_idc_lock(base_vha, 0);
5509 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5510 if (dev_state == QLA8XXX_DEV_FAILED ||
5511 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5512 qla83xx_idc_state_handler(base_vha);
5513 qla83xx_idc_unlock(base_vha, 0);
5514 }
5515
5516 static int
qla83xx_check_nic_core_fw_alive(scsi_qla_host_t * base_vha)5517 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5518 {
5519 int rval = QLA_SUCCESS;
5520 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5521 uint32_t heart_beat_counter1, heart_beat_counter2;
5522
5523 do {
5524 if (time_after(jiffies, heart_beat_wait)) {
5525 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5526 "Nic Core f/w is not alive.\n");
5527 rval = QLA_FUNCTION_FAILED;
5528 break;
5529 }
5530
5531 qla83xx_idc_lock(base_vha, 0);
5532 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5533 &heart_beat_counter1);
5534 qla83xx_idc_unlock(base_vha, 0);
5535 msleep(100);
5536 qla83xx_idc_lock(base_vha, 0);
5537 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5538 &heart_beat_counter2);
5539 qla83xx_idc_unlock(base_vha, 0);
5540 } while (heart_beat_counter1 == heart_beat_counter2);
5541
5542 return rval;
5543 }
5544
5545 /* Work: Perform NIC Core Reset handling */
5546 void
qla83xx_nic_core_reset_work(struct work_struct * work)5547 qla83xx_nic_core_reset_work(struct work_struct *work)
5548 {
5549 struct qla_hw_data *ha =
5550 container_of(work, struct qla_hw_data, nic_core_reset);
5551 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5552 uint32_t dev_state = 0;
5553
5554 if (IS_QLA2031(ha)) {
5555 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5556 ql_log(ql_log_warn, base_vha, 0xb081,
5557 "Failed to dump mctp\n");
5558 return;
5559 }
5560
5561 if (!ha->flags.nic_core_reset_hdlr_active) {
5562 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5563 qla83xx_idc_lock(base_vha, 0);
5564 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5565 &dev_state);
5566 qla83xx_idc_unlock(base_vha, 0);
5567 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5568 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5569 "Nic Core f/w is alive.\n");
5570 return;
5571 }
5572 }
5573
5574 ha->flags.nic_core_reset_hdlr_active = 1;
5575 if (qla83xx_nic_core_reset(base_vha)) {
5576 /* NIC Core reset failed. */
5577 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5578 "NIC Core reset failed.\n");
5579 }
5580 ha->flags.nic_core_reset_hdlr_active = 0;
5581 }
5582 }
5583
5584 /* Work: Handle 8200 IDC aens */
5585 void
qla83xx_service_idc_aen(struct work_struct * work)5586 qla83xx_service_idc_aen(struct work_struct *work)
5587 {
5588 struct qla_hw_data *ha =
5589 container_of(work, struct qla_hw_data, idc_aen);
5590 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5591 uint32_t dev_state, idc_control;
5592
5593 qla83xx_idc_lock(base_vha, 0);
5594 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5595 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5596 qla83xx_idc_unlock(base_vha, 0);
5597 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5598 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5599 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5600 "Application requested NIC Core Reset.\n");
5601 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5602 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5603 QLA_SUCCESS) {
5604 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5605 "Other protocol driver requested NIC Core Reset.\n");
5606 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5607 }
5608 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5609 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5610 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5611 }
5612 }
5613
5614 static void
qla83xx_wait_logic(void)5615 qla83xx_wait_logic(void)
5616 {
5617 int i;
5618
5619 /* Yield CPU */
5620 if (!in_interrupt()) {
5621 /*
5622 * Wait about 200ms before retrying again.
5623 * This controls the number of retries for single
5624 * lock operation.
5625 */
5626 msleep(100);
5627 schedule();
5628 } else {
5629 for (i = 0; i < 20; i++)
5630 cpu_relax(); /* This a nop instr on i386 */
5631 }
5632 }
5633
5634 static int
qla83xx_force_lock_recovery(scsi_qla_host_t * base_vha)5635 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5636 {
5637 int rval;
5638 uint32_t data;
5639 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5640 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5641 struct qla_hw_data *ha = base_vha->hw;
5642
5643 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5644 "Trying force recovery of the IDC lock.\n");
5645
5646 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5647 if (rval)
5648 return rval;
5649
5650 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5651 return QLA_SUCCESS;
5652 } else {
5653 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5654 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5655 data);
5656 if (rval)
5657 return rval;
5658
5659 msleep(200);
5660
5661 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5662 &data);
5663 if (rval)
5664 return rval;
5665
5666 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5667 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5668 ~(idc_lck_rcvry_stage_mask));
5669 rval = qla83xx_wr_reg(base_vha,
5670 QLA83XX_IDC_LOCK_RECOVERY, data);
5671 if (rval)
5672 return rval;
5673
5674 /* Forcefully perform IDC UnLock */
5675 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5676 &data);
5677 if (rval)
5678 return rval;
5679 /* Clear lock-id by setting 0xff */
5680 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5681 0xff);
5682 if (rval)
5683 return rval;
5684 /* Clear lock-recovery by setting 0x0 */
5685 rval = qla83xx_wr_reg(base_vha,
5686 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5687 if (rval)
5688 return rval;
5689 } else
5690 return QLA_SUCCESS;
5691 }
5692
5693 return rval;
5694 }
5695
5696 static int
qla83xx_idc_lock_recovery(scsi_qla_host_t * base_vha)5697 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5698 {
5699 int rval = QLA_SUCCESS;
5700 uint32_t o_drv_lockid, n_drv_lockid;
5701 unsigned long lock_recovery_timeout;
5702
5703 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5704 retry_lockid:
5705 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5706 if (rval)
5707 goto exit;
5708
5709 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5710 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5711 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5712 return QLA_SUCCESS;
5713 else
5714 return QLA_FUNCTION_FAILED;
5715 }
5716
5717 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5718 if (rval)
5719 goto exit;
5720
5721 if (o_drv_lockid == n_drv_lockid) {
5722 qla83xx_wait_logic();
5723 goto retry_lockid;
5724 } else
5725 return QLA_SUCCESS;
5726
5727 exit:
5728 return rval;
5729 }
5730
5731 void
qla83xx_idc_lock(scsi_qla_host_t * base_vha,uint16_t requester_id)5732 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5733 {
5734 uint32_t data;
5735 uint32_t lock_owner;
5736 struct qla_hw_data *ha = base_vha->hw;
5737
5738 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5739 retry_lock:
5740 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5741 == QLA_SUCCESS) {
5742 if (data) {
5743 /* Setting lock-id to our function-number */
5744 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5745 ha->portnum);
5746 } else {
5747 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5748 &lock_owner);
5749 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
5750 "Failed to acquire IDC lock, acquired by %d, "
5751 "retrying...\n", lock_owner);
5752
5753 /* Retry/Perform IDC-Lock recovery */
5754 if (qla83xx_idc_lock_recovery(base_vha)
5755 == QLA_SUCCESS) {
5756 qla83xx_wait_logic();
5757 goto retry_lock;
5758 } else
5759 ql_log(ql_log_warn, base_vha, 0xb075,
5760 "IDC Lock recovery FAILED.\n");
5761 }
5762
5763 }
5764
5765 return;
5766 }
5767
5768 static bool
qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host * vha,struct purex_entry_24xx * purex)5769 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha,
5770 struct purex_entry_24xx *purex)
5771 {
5772 char fwstr[16];
5773 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0];
5774 struct port_database_24xx *pdb;
5775
5776 /* Domain Controller is always logged-out. */
5777 /* if RDP request is not from Domain Controller: */
5778 if (sid != 0xfffc01)
5779 return false;
5780
5781 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid);
5782
5783 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL);
5784 if (!pdb) {
5785 ql_dbg(ql_dbg_init, vha, 0x0181,
5786 "%s: Failed allocate pdb\n", __func__);
5787 } else if (qla24xx_get_port_database(vha,
5788 le16_to_cpu(purex->nport_handle), pdb)) {
5789 ql_dbg(ql_dbg_init, vha, 0x0181,
5790 "%s: Failed get pdb sid=%x\n", __func__, sid);
5791 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE &&
5792 pdb->current_login_state != PDS_PRLI_COMPLETE) {
5793 ql_dbg(ql_dbg_init, vha, 0x0181,
5794 "%s: Port not logged in sid=%#x\n", __func__, sid);
5795 } else {
5796 /* RDP request is from logged in port */
5797 kfree(pdb);
5798 return false;
5799 }
5800 kfree(pdb);
5801
5802 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr));
5803 fwstr[strcspn(fwstr, " ")] = 0;
5804 /* if FW version allows RDP response length upto 2048 bytes: */
5805 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0)
5806 return false;
5807
5808 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr);
5809
5810 /* RDP response length is to be reduced to maximum 256 bytes */
5811 return true;
5812 }
5813
5814 /*
5815 * Function Name: qla24xx_process_purex_iocb
5816 *
5817 * Description:
5818 * Prepare a RDP response and send to Fabric switch
5819 *
5820 * PARAMETERS:
5821 * vha: SCSI qla host
5822 * purex: RDP request received by HBA
5823 */
qla24xx_process_purex_rdp(struct scsi_qla_host * vha,struct purex_item * item)5824 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha,
5825 struct purex_item *item)
5826 {
5827 struct qla_hw_data *ha = vha->hw;
5828 struct purex_entry_24xx *purex =
5829 (struct purex_entry_24xx *)&item->iocb;
5830 dma_addr_t rsp_els_dma;
5831 dma_addr_t rsp_payload_dma;
5832 dma_addr_t stat_dma;
5833 dma_addr_t sfp_dma;
5834 struct els_entry_24xx *rsp_els = NULL;
5835 struct rdp_rsp_payload *rsp_payload = NULL;
5836 struct link_statistics *stat = NULL;
5837 uint8_t *sfp = NULL;
5838 uint16_t sfp_flags = 0;
5839 uint rsp_payload_length = sizeof(*rsp_payload);
5840 int rval;
5841
5842 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180,
5843 "%s: Enter\n", __func__);
5844
5845 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181,
5846 "-------- ELS REQ -------\n");
5847 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182,
5848 purex, sizeof(*purex));
5849
5850 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) {
5851 rsp_payload_length =
5852 offsetof(typeof(*rsp_payload), optical_elmt_desc);
5853 ql_dbg(ql_dbg_init, vha, 0x0181,
5854 "Reducing RSP payload length to %u bytes...\n",
5855 rsp_payload_length);
5856 }
5857
5858 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els),
5859 &rsp_els_dma, GFP_KERNEL);
5860 if (!rsp_els) {
5861 ql_log(ql_log_warn, vha, 0x0183,
5862 "Failed allocate dma buffer ELS RSP.\n");
5863 goto dealloc;
5864 }
5865
5866 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
5867 &rsp_payload_dma, GFP_KERNEL);
5868 if (!rsp_payload) {
5869 ql_log(ql_log_warn, vha, 0x0184,
5870 "Failed allocate dma buffer ELS RSP payload.\n");
5871 goto dealloc;
5872 }
5873
5874 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
5875 &sfp_dma, GFP_KERNEL);
5876
5877 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat),
5878 &stat_dma, GFP_KERNEL);
5879
5880 /* Prepare Response IOCB */
5881 rsp_els->entry_type = ELS_IOCB_TYPE;
5882 rsp_els->entry_count = 1;
5883 rsp_els->sys_define = 0;
5884 rsp_els->entry_status = 0;
5885 rsp_els->handle = 0;
5886 rsp_els->nport_handle = purex->nport_handle;
5887 rsp_els->tx_dsd_count = cpu_to_le16(1);
5888 rsp_els->vp_index = purex->vp_idx;
5889 rsp_els->sof_type = EST_SOFI3;
5890 rsp_els->rx_xchg_address = purex->rx_xchg_addr;
5891 rsp_els->rx_dsd_count = 0;
5892 rsp_els->opcode = purex->els_frame_payload[0];
5893
5894 rsp_els->d_id[0] = purex->s_id[0];
5895 rsp_els->d_id[1] = purex->s_id[1];
5896 rsp_els->d_id[2] = purex->s_id[2];
5897
5898 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC);
5899 rsp_els->rx_byte_count = 0;
5900 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length);
5901
5902 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address);
5903 rsp_els->tx_len = rsp_els->tx_byte_count;
5904
5905 rsp_els->rx_address = 0;
5906 rsp_els->rx_len = 0;
5907
5908 /* Prepare Response Payload */
5909 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */
5910 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) -
5911 sizeof(rsp_payload->hdr));
5912
5913 /* Link service Request Info Descriptor */
5914 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1);
5915 rsp_payload->ls_req_info_desc.desc_len =
5916 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc));
5917 rsp_payload->ls_req_info_desc.req_payload_word_0 =
5918 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
5919
5920 /* Link service Request Info Descriptor 2 */
5921 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1);
5922 rsp_payload->ls_req_info_desc2.desc_len =
5923 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2));
5924 rsp_payload->ls_req_info_desc2.req_payload_word_0 =
5925 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
5926
5927
5928 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000);
5929 rsp_payload->sfp_diag_desc.desc_len =
5930 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc));
5931
5932 if (sfp) {
5933 /* SFP Flags */
5934 memset(sfp, 0, SFP_RTDI_LEN);
5935 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0);
5936 if (!rval) {
5937 /* SFP Flags bits 3-0: Port Tx Laser Type */
5938 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
5939 sfp_flags |= BIT_0; /* short wave */
5940 else if (sfp[0] & BIT_1)
5941 sfp_flags |= BIT_1; /* long wave 1310nm */
5942 else if (sfp[1] & BIT_4)
5943 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */
5944 }
5945
5946 /* SFP Type */
5947 memset(sfp, 0, SFP_RTDI_LEN);
5948 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0);
5949 if (!rval) {
5950 sfp_flags |= BIT_4; /* optical */
5951 if (sfp[0] == 0x3)
5952 sfp_flags |= BIT_6; /* sfp+ */
5953 }
5954
5955 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags);
5956
5957 /* SFP Diagnostics */
5958 memset(sfp, 0, SFP_RTDI_LEN);
5959 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0);
5960 if (!rval) {
5961 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
5962 rsp_payload->sfp_diag_desc.temperature = trx[0];
5963 rsp_payload->sfp_diag_desc.vcc = trx[1];
5964 rsp_payload->sfp_diag_desc.tx_bias = trx[2];
5965 rsp_payload->sfp_diag_desc.tx_power = trx[3];
5966 rsp_payload->sfp_diag_desc.rx_power = trx[4];
5967 }
5968 }
5969
5970 /* Port Speed Descriptor */
5971 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001);
5972 rsp_payload->port_speed_desc.desc_len =
5973 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc));
5974 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16(
5975 qla25xx_fdmi_port_speed_capability(ha));
5976 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16(
5977 qla25xx_fdmi_port_speed_currently(ha));
5978
5979 /* Link Error Status Descriptor */
5980 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002);
5981 rsp_payload->ls_err_desc.desc_len =
5982 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc));
5983
5984 if (stat) {
5985 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0);
5986 if (!rval) {
5987 rsp_payload->ls_err_desc.link_fail_cnt =
5988 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt));
5989 rsp_payload->ls_err_desc.loss_sync_cnt =
5990 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt));
5991 rsp_payload->ls_err_desc.loss_sig_cnt =
5992 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt));
5993 rsp_payload->ls_err_desc.prim_seq_err_cnt =
5994 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt));
5995 rsp_payload->ls_err_desc.inval_xmit_word_cnt =
5996 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt));
5997 rsp_payload->ls_err_desc.inval_crc_cnt =
5998 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt));
5999 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
6000 }
6001 }
6002
6003 /* Portname Descriptor */
6004 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003);
6005 rsp_payload->port_name_diag_desc.desc_len =
6006 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc));
6007 memcpy(rsp_payload->port_name_diag_desc.WWNN,
6008 vha->node_name,
6009 sizeof(rsp_payload->port_name_diag_desc.WWNN));
6010 memcpy(rsp_payload->port_name_diag_desc.WWPN,
6011 vha->port_name,
6012 sizeof(rsp_payload->port_name_diag_desc.WWPN));
6013
6014 /* F-Port Portname Descriptor */
6015 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003);
6016 rsp_payload->port_name_direct_desc.desc_len =
6017 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc));
6018 memcpy(rsp_payload->port_name_direct_desc.WWNN,
6019 vha->fabric_node_name,
6020 sizeof(rsp_payload->port_name_direct_desc.WWNN));
6021 memcpy(rsp_payload->port_name_direct_desc.WWPN,
6022 vha->fabric_port_name,
6023 sizeof(rsp_payload->port_name_direct_desc.WWPN));
6024
6025 /* Bufer Credit Descriptor */
6026 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006);
6027 rsp_payload->buffer_credit_desc.desc_len =
6028 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc));
6029 rsp_payload->buffer_credit_desc.fcport_b2b = 0;
6030 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0);
6031 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0);
6032
6033 if (ha->flags.plogi_template_valid) {
6034 uint32_t tmp =
6035 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred);
6036 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp);
6037 }
6038
6039 if (rsp_payload_length < sizeof(*rsp_payload))
6040 goto send;
6041
6042 /* Optical Element Descriptor, Temperature */
6043 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007);
6044 rsp_payload->optical_elmt_desc[0].desc_len =
6045 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6046 /* Optical Element Descriptor, Voltage */
6047 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007);
6048 rsp_payload->optical_elmt_desc[1].desc_len =
6049 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6050 /* Optical Element Descriptor, Tx Bias Current */
6051 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007);
6052 rsp_payload->optical_elmt_desc[2].desc_len =
6053 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6054 /* Optical Element Descriptor, Tx Power */
6055 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007);
6056 rsp_payload->optical_elmt_desc[3].desc_len =
6057 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6058 /* Optical Element Descriptor, Rx Power */
6059 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007);
6060 rsp_payload->optical_elmt_desc[4].desc_len =
6061 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6062
6063 if (sfp) {
6064 memset(sfp, 0, SFP_RTDI_LEN);
6065 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0);
6066 if (!rval) {
6067 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
6068
6069 /* Optical Element Descriptor, Temperature */
6070 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0];
6071 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1];
6072 rsp_payload->optical_elmt_desc[0].high_warn = trx[2];
6073 rsp_payload->optical_elmt_desc[0].low_warn = trx[3];
6074 rsp_payload->optical_elmt_desc[0].element_flags =
6075 cpu_to_be32(1 << 28);
6076
6077 /* Optical Element Descriptor, Voltage */
6078 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4];
6079 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5];
6080 rsp_payload->optical_elmt_desc[1].high_warn = trx[6];
6081 rsp_payload->optical_elmt_desc[1].low_warn = trx[7];
6082 rsp_payload->optical_elmt_desc[1].element_flags =
6083 cpu_to_be32(2 << 28);
6084
6085 /* Optical Element Descriptor, Tx Bias Current */
6086 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8];
6087 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9];
6088 rsp_payload->optical_elmt_desc[2].high_warn = trx[10];
6089 rsp_payload->optical_elmt_desc[2].low_warn = trx[11];
6090 rsp_payload->optical_elmt_desc[2].element_flags =
6091 cpu_to_be32(3 << 28);
6092
6093 /* Optical Element Descriptor, Tx Power */
6094 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12];
6095 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13];
6096 rsp_payload->optical_elmt_desc[3].high_warn = trx[14];
6097 rsp_payload->optical_elmt_desc[3].low_warn = trx[15];
6098 rsp_payload->optical_elmt_desc[3].element_flags =
6099 cpu_to_be32(4 << 28);
6100
6101 /* Optical Element Descriptor, Rx Power */
6102 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16];
6103 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17];
6104 rsp_payload->optical_elmt_desc[4].high_warn = trx[18];
6105 rsp_payload->optical_elmt_desc[4].low_warn = trx[19];
6106 rsp_payload->optical_elmt_desc[4].element_flags =
6107 cpu_to_be32(5 << 28);
6108 }
6109
6110 memset(sfp, 0, SFP_RTDI_LEN);
6111 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0);
6112 if (!rval) {
6113 /* Temperature high/low alarm/warning */
6114 rsp_payload->optical_elmt_desc[0].element_flags |=
6115 cpu_to_be32(
6116 (sfp[0] >> 7 & 1) << 3 |
6117 (sfp[0] >> 6 & 1) << 2 |
6118 (sfp[4] >> 7 & 1) << 1 |
6119 (sfp[4] >> 6 & 1) << 0);
6120
6121 /* Voltage high/low alarm/warning */
6122 rsp_payload->optical_elmt_desc[1].element_flags |=
6123 cpu_to_be32(
6124 (sfp[0] >> 5 & 1) << 3 |
6125 (sfp[0] >> 4 & 1) << 2 |
6126 (sfp[4] >> 5 & 1) << 1 |
6127 (sfp[4] >> 4 & 1) << 0);
6128
6129 /* Tx Bias Current high/low alarm/warning */
6130 rsp_payload->optical_elmt_desc[2].element_flags |=
6131 cpu_to_be32(
6132 (sfp[0] >> 3 & 1) << 3 |
6133 (sfp[0] >> 2 & 1) << 2 |
6134 (sfp[4] >> 3 & 1) << 1 |
6135 (sfp[4] >> 2 & 1) << 0);
6136
6137 /* Tx Power high/low alarm/warning */
6138 rsp_payload->optical_elmt_desc[3].element_flags |=
6139 cpu_to_be32(
6140 (sfp[0] >> 1 & 1) << 3 |
6141 (sfp[0] >> 0 & 1) << 2 |
6142 (sfp[4] >> 1 & 1) << 1 |
6143 (sfp[4] >> 0 & 1) << 0);
6144
6145 /* Rx Power high/low alarm/warning */
6146 rsp_payload->optical_elmt_desc[4].element_flags |=
6147 cpu_to_be32(
6148 (sfp[1] >> 7 & 1) << 3 |
6149 (sfp[1] >> 6 & 1) << 2 |
6150 (sfp[5] >> 7 & 1) << 1 |
6151 (sfp[5] >> 6 & 1) << 0);
6152 }
6153 }
6154
6155 /* Optical Product Data Descriptor */
6156 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008);
6157 rsp_payload->optical_prod_desc.desc_len =
6158 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc));
6159
6160 if (sfp) {
6161 memset(sfp, 0, SFP_RTDI_LEN);
6162 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0);
6163 if (!rval) {
6164 memcpy(rsp_payload->optical_prod_desc.vendor_name,
6165 sfp + 0,
6166 sizeof(rsp_payload->optical_prod_desc.vendor_name));
6167 memcpy(rsp_payload->optical_prod_desc.part_number,
6168 sfp + 20,
6169 sizeof(rsp_payload->optical_prod_desc.part_number));
6170 memcpy(rsp_payload->optical_prod_desc.revision,
6171 sfp + 36,
6172 sizeof(rsp_payload->optical_prod_desc.revision));
6173 memcpy(rsp_payload->optical_prod_desc.serial_number,
6174 sfp + 48,
6175 sizeof(rsp_payload->optical_prod_desc.serial_number));
6176 }
6177
6178 memset(sfp, 0, SFP_RTDI_LEN);
6179 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0);
6180 if (!rval) {
6181 memcpy(rsp_payload->optical_prod_desc.date,
6182 sfp + 0,
6183 sizeof(rsp_payload->optical_prod_desc.date));
6184 }
6185 }
6186
6187 send:
6188 ql_dbg(ql_dbg_init, vha, 0x0183,
6189 "Sending ELS Response to RDP Request...\n");
6190 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184,
6191 "-------- ELS RSP -------\n");
6192 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185,
6193 rsp_els, sizeof(*rsp_els));
6194 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186,
6195 "-------- ELS RSP PAYLOAD -------\n");
6196 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187,
6197 rsp_payload, rsp_payload_length);
6198
6199 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0);
6200
6201 if (rval) {
6202 ql_log(ql_log_warn, vha, 0x0188,
6203 "%s: iocb failed to execute -> %x\n", __func__, rval);
6204 } else if (rsp_els->comp_status) {
6205 ql_log(ql_log_warn, vha, 0x0189,
6206 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n",
6207 __func__, rsp_els->comp_status,
6208 rsp_els->error_subcode_1, rsp_els->error_subcode_2);
6209 } else {
6210 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__);
6211 }
6212
6213 dealloc:
6214 if (stat)
6215 dma_free_coherent(&ha->pdev->dev, sizeof(*stat),
6216 stat, stat_dma);
6217 if (sfp)
6218 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6219 sfp, sfp_dma);
6220 if (rsp_payload)
6221 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6222 rsp_payload, rsp_payload_dma);
6223 if (rsp_els)
6224 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6225 rsp_els, rsp_els_dma);
6226 }
6227
6228 void
qla24xx_free_purex_item(struct purex_item * item)6229 qla24xx_free_purex_item(struct purex_item *item)
6230 {
6231 if (item == &item->vha->default_item)
6232 memset(&item->vha->default_item, 0, sizeof(struct purex_item));
6233 else
6234 kfree(item);
6235 }
6236
qla24xx_process_purex_list(struct purex_list * list)6237 void qla24xx_process_purex_list(struct purex_list *list)
6238 {
6239 struct list_head head = LIST_HEAD_INIT(head);
6240 struct purex_item *item, *next;
6241 ulong flags;
6242
6243 spin_lock_irqsave(&list->lock, flags);
6244 list_splice_init(&list->head, &head);
6245 spin_unlock_irqrestore(&list->lock, flags);
6246
6247 list_for_each_entry_safe(item, next, &head, list) {
6248 list_del(&item->list);
6249 item->process_item(item->vha, item);
6250 qla24xx_free_purex_item(item);
6251 }
6252 }
6253
6254 void
qla83xx_idc_unlock(scsi_qla_host_t * base_vha,uint16_t requester_id)6255 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
6256 {
6257 #if 0
6258 uint16_t options = (requester_id << 15) | BIT_7;
6259 #endif
6260 uint16_t retry;
6261 uint32_t data;
6262 struct qla_hw_data *ha = base_vha->hw;
6263
6264 /* IDC-unlock implementation using driver-unlock/lock-id
6265 * remote registers
6266 */
6267 retry = 0;
6268 retry_unlock:
6269 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
6270 == QLA_SUCCESS) {
6271 if (data == ha->portnum) {
6272 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
6273 /* Clearing lock-id by setting 0xff */
6274 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
6275 } else if (retry < 10) {
6276 /* SV: XXX: IDC unlock retrying needed here? */
6277
6278 /* Retry for IDC-unlock */
6279 qla83xx_wait_logic();
6280 retry++;
6281 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
6282 "Failed to release IDC lock, retrying=%d\n", retry);
6283 goto retry_unlock;
6284 }
6285 } else if (retry < 10) {
6286 /* Retry for IDC-unlock */
6287 qla83xx_wait_logic();
6288 retry++;
6289 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
6290 "Failed to read drv-lockid, retrying=%d\n", retry);
6291 goto retry_unlock;
6292 }
6293
6294 return;
6295
6296 #if 0
6297 /* XXX: IDC-unlock implementation using access-control mbx */
6298 retry = 0;
6299 retry_unlock2:
6300 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
6301 if (retry < 10) {
6302 /* Retry for IDC-unlock */
6303 qla83xx_wait_logic();
6304 retry++;
6305 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
6306 "Failed to release IDC lock, retrying=%d\n", retry);
6307 goto retry_unlock2;
6308 }
6309 }
6310
6311 return;
6312 #endif
6313 }
6314
6315 int
__qla83xx_set_drv_presence(scsi_qla_host_t * vha)6316 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6317 {
6318 int rval = QLA_SUCCESS;
6319 struct qla_hw_data *ha = vha->hw;
6320 uint32_t drv_presence;
6321
6322 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6323 if (rval == QLA_SUCCESS) {
6324 drv_presence |= (1 << ha->portnum);
6325 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6326 drv_presence);
6327 }
6328
6329 return rval;
6330 }
6331
6332 int
qla83xx_set_drv_presence(scsi_qla_host_t * vha)6333 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6334 {
6335 int rval = QLA_SUCCESS;
6336
6337 qla83xx_idc_lock(vha, 0);
6338 rval = __qla83xx_set_drv_presence(vha);
6339 qla83xx_idc_unlock(vha, 0);
6340
6341 return rval;
6342 }
6343
6344 int
__qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6345 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6346 {
6347 int rval = QLA_SUCCESS;
6348 struct qla_hw_data *ha = vha->hw;
6349 uint32_t drv_presence;
6350
6351 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6352 if (rval == QLA_SUCCESS) {
6353 drv_presence &= ~(1 << ha->portnum);
6354 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6355 drv_presence);
6356 }
6357
6358 return rval;
6359 }
6360
6361 int
qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6362 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6363 {
6364 int rval = QLA_SUCCESS;
6365
6366 qla83xx_idc_lock(vha, 0);
6367 rval = __qla83xx_clear_drv_presence(vha);
6368 qla83xx_idc_unlock(vha, 0);
6369
6370 return rval;
6371 }
6372
6373 static void
qla83xx_need_reset_handler(scsi_qla_host_t * vha)6374 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
6375 {
6376 struct qla_hw_data *ha = vha->hw;
6377 uint32_t drv_ack, drv_presence;
6378 unsigned long ack_timeout;
6379
6380 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
6381 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
6382 while (1) {
6383 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6384 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6385 if ((drv_ack & drv_presence) == drv_presence)
6386 break;
6387
6388 if (time_after_eq(jiffies, ack_timeout)) {
6389 ql_log(ql_log_warn, vha, 0xb067,
6390 "RESET ACK TIMEOUT! drv_presence=0x%x "
6391 "drv_ack=0x%x\n", drv_presence, drv_ack);
6392 /*
6393 * The function(s) which did not ack in time are forced
6394 * to withdraw any further participation in the IDC
6395 * reset.
6396 */
6397 if (drv_ack != drv_presence)
6398 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6399 drv_ack);
6400 break;
6401 }
6402
6403 qla83xx_idc_unlock(vha, 0);
6404 msleep(1000);
6405 qla83xx_idc_lock(vha, 0);
6406 }
6407
6408 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
6409 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
6410 }
6411
6412 static int
qla83xx_device_bootstrap(scsi_qla_host_t * vha)6413 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
6414 {
6415 int rval = QLA_SUCCESS;
6416 uint32_t idc_control;
6417
6418 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
6419 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
6420
6421 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
6422 __qla83xx_get_idc_control(vha, &idc_control);
6423 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
6424 __qla83xx_set_idc_control(vha, 0);
6425
6426 qla83xx_idc_unlock(vha, 0);
6427 rval = qla83xx_restart_nic_firmware(vha);
6428 qla83xx_idc_lock(vha, 0);
6429
6430 if (rval != QLA_SUCCESS) {
6431 ql_log(ql_log_fatal, vha, 0xb06a,
6432 "Failed to restart NIC f/w.\n");
6433 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
6434 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
6435 } else {
6436 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
6437 "Success in restarting nic f/w.\n");
6438 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
6439 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
6440 }
6441
6442 return rval;
6443 }
6444
6445 /* Assumes idc_lock always held on entry */
6446 int
qla83xx_idc_state_handler(scsi_qla_host_t * base_vha)6447 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
6448 {
6449 struct qla_hw_data *ha = base_vha->hw;
6450 int rval = QLA_SUCCESS;
6451 unsigned long dev_init_timeout;
6452 uint32_t dev_state;
6453
6454 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
6455 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
6456
6457 while (1) {
6458
6459 if (time_after_eq(jiffies, dev_init_timeout)) {
6460 ql_log(ql_log_warn, base_vha, 0xb06e,
6461 "Initialization TIMEOUT!\n");
6462 /* Init timeout. Disable further NIC Core
6463 * communication.
6464 */
6465 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
6466 QLA8XXX_DEV_FAILED);
6467 ql_log(ql_log_info, base_vha, 0xb06f,
6468 "HW State: FAILED.\n");
6469 }
6470
6471 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6472 switch (dev_state) {
6473 case QLA8XXX_DEV_READY:
6474 if (ha->flags.nic_core_reset_owner)
6475 qla83xx_idc_audit(base_vha,
6476 IDC_AUDIT_COMPLETION);
6477 ha->flags.nic_core_reset_owner = 0;
6478 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6479 "Reset_owner reset by 0x%x.\n",
6480 ha->portnum);
6481 goto exit;
6482 case QLA8XXX_DEV_COLD:
6483 if (ha->flags.nic_core_reset_owner)
6484 rval = qla83xx_device_bootstrap(base_vha);
6485 else {
6486 /* Wait for AEN to change device-state */
6487 qla83xx_idc_unlock(base_vha, 0);
6488 msleep(1000);
6489 qla83xx_idc_lock(base_vha, 0);
6490 }
6491 break;
6492 case QLA8XXX_DEV_INITIALIZING:
6493 /* Wait for AEN to change device-state */
6494 qla83xx_idc_unlock(base_vha, 0);
6495 msleep(1000);
6496 qla83xx_idc_lock(base_vha, 0);
6497 break;
6498 case QLA8XXX_DEV_NEED_RESET:
6499 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6500 qla83xx_need_reset_handler(base_vha);
6501 else {
6502 /* Wait for AEN to change device-state */
6503 qla83xx_idc_unlock(base_vha, 0);
6504 msleep(1000);
6505 qla83xx_idc_lock(base_vha, 0);
6506 }
6507 /* reset timeout value after need reset handler */
6508 dev_init_timeout = jiffies +
6509 (ha->fcoe_dev_init_timeout * HZ);
6510 break;
6511 case QLA8XXX_DEV_NEED_QUIESCENT:
6512 /* XXX: DEBUG for now */
6513 qla83xx_idc_unlock(base_vha, 0);
6514 msleep(1000);
6515 qla83xx_idc_lock(base_vha, 0);
6516 break;
6517 case QLA8XXX_DEV_QUIESCENT:
6518 /* XXX: DEBUG for now */
6519 if (ha->flags.quiesce_owner)
6520 goto exit;
6521
6522 qla83xx_idc_unlock(base_vha, 0);
6523 msleep(1000);
6524 qla83xx_idc_lock(base_vha, 0);
6525 dev_init_timeout = jiffies +
6526 (ha->fcoe_dev_init_timeout * HZ);
6527 break;
6528 case QLA8XXX_DEV_FAILED:
6529 if (ha->flags.nic_core_reset_owner)
6530 qla83xx_idc_audit(base_vha,
6531 IDC_AUDIT_COMPLETION);
6532 ha->flags.nic_core_reset_owner = 0;
6533 __qla83xx_clear_drv_presence(base_vha);
6534 qla83xx_idc_unlock(base_vha, 0);
6535 qla8xxx_dev_failed_handler(base_vha);
6536 rval = QLA_FUNCTION_FAILED;
6537 qla83xx_idc_lock(base_vha, 0);
6538 goto exit;
6539 case QLA8XXX_BAD_VALUE:
6540 qla83xx_idc_unlock(base_vha, 0);
6541 msleep(1000);
6542 qla83xx_idc_lock(base_vha, 0);
6543 break;
6544 default:
6545 ql_log(ql_log_warn, base_vha, 0xb071,
6546 "Unknown Device State: %x.\n", dev_state);
6547 qla83xx_idc_unlock(base_vha, 0);
6548 qla8xxx_dev_failed_handler(base_vha);
6549 rval = QLA_FUNCTION_FAILED;
6550 qla83xx_idc_lock(base_vha, 0);
6551 goto exit;
6552 }
6553 }
6554
6555 exit:
6556 return rval;
6557 }
6558
6559 void
qla2x00_disable_board_on_pci_error(struct work_struct * work)6560 qla2x00_disable_board_on_pci_error(struct work_struct *work)
6561 {
6562 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6563 board_disable);
6564 struct pci_dev *pdev = ha->pdev;
6565 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6566
6567 ql_log(ql_log_warn, base_vha, 0x015b,
6568 "Disabling adapter.\n");
6569
6570 if (!atomic_read(&pdev->enable_cnt)) {
6571 ql_log(ql_log_info, base_vha, 0xfffc,
6572 "PCI device disabled, no action req for PCI error=%lx\n",
6573 base_vha->pci_flags);
6574 return;
6575 }
6576
6577 /*
6578 * if UNLOADING flag is already set, then continue unload,
6579 * where it was set first.
6580 */
6581 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
6582 return;
6583
6584 qla2x00_wait_for_sess_deletion(base_vha);
6585
6586 qla2x00_delete_all_vps(ha, base_vha);
6587
6588 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6589
6590 qla2x00_dfs_remove(base_vha);
6591
6592 qla84xx_put_chip(base_vha);
6593
6594 if (base_vha->timer_active)
6595 qla2x00_stop_timer(base_vha);
6596
6597 base_vha->flags.online = 0;
6598
6599 qla2x00_destroy_deferred_work(ha);
6600
6601 /*
6602 * Do not try to stop beacon blink as it will issue a mailbox
6603 * command.
6604 */
6605 qla2x00_free_sysfs_attr(base_vha, false);
6606
6607 fc_remove_host(base_vha->host);
6608
6609 scsi_remove_host(base_vha->host);
6610
6611 base_vha->flags.init_done = 0;
6612 qla25xx_delete_queues(base_vha);
6613 qla2x00_free_fcports(base_vha);
6614 qla2x00_free_irqs(base_vha);
6615 qla2x00_mem_free(ha);
6616 qla82xx_md_free(base_vha);
6617 qla2x00_free_queues(ha);
6618
6619 qla2x00_unmap_iobases(ha);
6620
6621 pci_release_selected_regions(ha->pdev, ha->bars);
6622 pci_disable_pcie_error_reporting(pdev);
6623 pci_disable_device(pdev);
6624
6625 /*
6626 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6627 */
6628 }
6629
6630 /**************************************************************************
6631 * qla2x00_do_dpc
6632 * This kernel thread is a task that is schedule by the interrupt handler
6633 * to perform the background processing for interrupts.
6634 *
6635 * Notes:
6636 * This task always run in the context of a kernel thread. It
6637 * is kick-off by the driver's detect code and starts up
6638 * up one per adapter. It immediately goes to sleep and waits for
6639 * some fibre event. When either the interrupt handler or
6640 * the timer routine detects a event it will one of the task
6641 * bits then wake us up.
6642 **************************************************************************/
6643 static int
qla2x00_do_dpc(void * data)6644 qla2x00_do_dpc(void *data)
6645 {
6646 scsi_qla_host_t *base_vha;
6647 struct qla_hw_data *ha;
6648 uint32_t online;
6649 struct qla_qpair *qpair;
6650
6651 ha = (struct qla_hw_data *)data;
6652 base_vha = pci_get_drvdata(ha->pdev);
6653
6654 set_user_nice(current, MIN_NICE);
6655
6656 set_current_state(TASK_INTERRUPTIBLE);
6657 while (!kthread_should_stop()) {
6658 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6659 "DPC handler sleeping.\n");
6660
6661 schedule();
6662
6663 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6664 goto end_loop;
6665
6666 if (ha->flags.eeh_busy) {
6667 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6668 "eeh_busy=%d.\n", ha->flags.eeh_busy);
6669 goto end_loop;
6670 }
6671
6672 ha->dpc_active = 1;
6673
6674 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6675 "DPC handler waking up, dpc_flags=0x%lx.\n",
6676 base_vha->dpc_flags);
6677
6678 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6679 break;
6680
6681 if (IS_P3P_TYPE(ha)) {
6682 if (IS_QLA8044(ha)) {
6683 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6684 &base_vha->dpc_flags)) {
6685 qla8044_idc_lock(ha);
6686 qla8044_wr_direct(base_vha,
6687 QLA8044_CRB_DEV_STATE_INDEX,
6688 QLA8XXX_DEV_FAILED);
6689 qla8044_idc_unlock(ha);
6690 ql_log(ql_log_info, base_vha, 0x4004,
6691 "HW State: FAILED.\n");
6692 qla8044_device_state_handler(base_vha);
6693 continue;
6694 }
6695
6696 } else {
6697 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6698 &base_vha->dpc_flags)) {
6699 qla82xx_idc_lock(ha);
6700 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6701 QLA8XXX_DEV_FAILED);
6702 qla82xx_idc_unlock(ha);
6703 ql_log(ql_log_info, base_vha, 0x0151,
6704 "HW State: FAILED.\n");
6705 qla82xx_device_state_handler(base_vha);
6706 continue;
6707 }
6708 }
6709
6710 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6711 &base_vha->dpc_flags)) {
6712
6713 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6714 "FCoE context reset scheduled.\n");
6715 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6716 &base_vha->dpc_flags))) {
6717 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6718 /* FCoE-ctx reset failed.
6719 * Escalate to chip-reset
6720 */
6721 set_bit(ISP_ABORT_NEEDED,
6722 &base_vha->dpc_flags);
6723 }
6724 clear_bit(ABORT_ISP_ACTIVE,
6725 &base_vha->dpc_flags);
6726 }
6727
6728 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6729 "FCoE context reset end.\n");
6730 }
6731 } else if (IS_QLAFX00(ha)) {
6732 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6733 &base_vha->dpc_flags)) {
6734 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6735 "Firmware Reset Recovery\n");
6736 if (qlafx00_reset_initialize(base_vha)) {
6737 /* Failed. Abort isp later. */
6738 if (!test_bit(UNLOADING,
6739 &base_vha->dpc_flags)) {
6740 set_bit(ISP_UNRECOVERABLE,
6741 &base_vha->dpc_flags);
6742 ql_dbg(ql_dbg_dpc, base_vha,
6743 0x4021,
6744 "Reset Recovery Failed\n");
6745 }
6746 }
6747 }
6748
6749 if (test_and_clear_bit(FX00_TARGET_SCAN,
6750 &base_vha->dpc_flags)) {
6751 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6752 "ISPFx00 Target Scan scheduled\n");
6753 if (qlafx00_rescan_isp(base_vha)) {
6754 if (!test_bit(UNLOADING,
6755 &base_vha->dpc_flags))
6756 set_bit(ISP_UNRECOVERABLE,
6757 &base_vha->dpc_flags);
6758 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6759 "ISPFx00 Target Scan Failed\n");
6760 }
6761 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6762 "ISPFx00 Target Scan End\n");
6763 }
6764 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6765 &base_vha->dpc_flags)) {
6766 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6767 "ISPFx00 Host Info resend scheduled\n");
6768 qlafx00_fx_disc(base_vha,
6769 &base_vha->hw->mr.fcport,
6770 FXDISC_REG_HOST_INFO);
6771 }
6772 }
6773
6774 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6775 &base_vha->dpc_flags)) {
6776 /* Semantic:
6777 * - NO-OP -- await next ISP-ABORT. Preferred method
6778 * to minimize disruptions that will occur
6779 * when a forced chip-reset occurs.
6780 * - Force -- ISP-ABORT scheduled.
6781 */
6782 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */
6783 }
6784
6785 if (test_and_clear_bit
6786 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6787 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
6788 bool do_reset = true;
6789
6790 switch (base_vha->qlini_mode) {
6791 case QLA2XXX_INI_MODE_ENABLED:
6792 break;
6793 case QLA2XXX_INI_MODE_DISABLED:
6794 if (!qla_tgt_mode_enabled(base_vha) &&
6795 !ha->flags.fw_started)
6796 do_reset = false;
6797 break;
6798 case QLA2XXX_INI_MODE_DUAL:
6799 if (!qla_dual_mode_enabled(base_vha) &&
6800 !ha->flags.fw_started)
6801 do_reset = false;
6802 break;
6803 default:
6804 break;
6805 }
6806
6807 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
6808 &base_vha->dpc_flags))) {
6809 base_vha->flags.online = 1;
6810 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6811 "ISP abort scheduled.\n");
6812 if (ha->isp_ops->abort_isp(base_vha)) {
6813 /* failed. retry later */
6814 set_bit(ISP_ABORT_NEEDED,
6815 &base_vha->dpc_flags);
6816 }
6817 clear_bit(ABORT_ISP_ACTIVE,
6818 &base_vha->dpc_flags);
6819 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6820 "ISP abort end.\n");
6821 }
6822 }
6823
6824 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) {
6825 if (atomic_read(&base_vha->loop_state) == LOOP_READY) {
6826 qla24xx_process_purex_list
6827 (&base_vha->purex_list);
6828 clear_bit(PROCESS_PUREX_IOCB,
6829 &base_vha->dpc_flags);
6830 }
6831 }
6832
6833 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6834 &base_vha->dpc_flags)) {
6835 qla2x00_update_fcports(base_vha);
6836 }
6837
6838 if (IS_QLAFX00(ha))
6839 goto loop_resync_check;
6840
6841 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
6842 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6843 "Quiescence mode scheduled.\n");
6844 if (IS_P3P_TYPE(ha)) {
6845 if (IS_QLA82XX(ha))
6846 qla82xx_device_state_handler(base_vha);
6847 if (IS_QLA8044(ha))
6848 qla8044_device_state_handler(base_vha);
6849 clear_bit(ISP_QUIESCE_NEEDED,
6850 &base_vha->dpc_flags);
6851 if (!ha->flags.quiesce_owner) {
6852 qla2x00_perform_loop_resync(base_vha);
6853 if (IS_QLA82XX(ha)) {
6854 qla82xx_idc_lock(ha);
6855 qla82xx_clear_qsnt_ready(
6856 base_vha);
6857 qla82xx_idc_unlock(ha);
6858 } else if (IS_QLA8044(ha)) {
6859 qla8044_idc_lock(ha);
6860 qla8044_clear_qsnt_ready(
6861 base_vha);
6862 qla8044_idc_unlock(ha);
6863 }
6864 }
6865 } else {
6866 clear_bit(ISP_QUIESCE_NEEDED,
6867 &base_vha->dpc_flags);
6868 qla2x00_quiesce_io(base_vha);
6869 }
6870 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6871 "Quiescence mode end.\n");
6872 }
6873
6874 if (test_and_clear_bit(RESET_MARKER_NEEDED,
6875 &base_vha->dpc_flags) &&
6876 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
6877
6878 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6879 "Reset marker scheduled.\n");
6880 qla2x00_rst_aen(base_vha);
6881 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
6882 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6883 "Reset marker end.\n");
6884 }
6885
6886 /* Retry each device up to login retry count */
6887 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
6888 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6889 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
6890
6891 if (!base_vha->relogin_jif ||
6892 time_after_eq(jiffies, base_vha->relogin_jif)) {
6893 base_vha->relogin_jif = jiffies + HZ;
6894 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6895
6896 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
6897 "Relogin scheduled.\n");
6898 qla24xx_post_relogin_work(base_vha);
6899 }
6900 }
6901 loop_resync_check:
6902 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
6903 &base_vha->dpc_flags)) {
6904
6905 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6906 "Loop resync scheduled.\n");
6907
6908 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
6909 &base_vha->dpc_flags))) {
6910
6911 qla2x00_loop_resync(base_vha);
6912
6913 clear_bit(LOOP_RESYNC_ACTIVE,
6914 &base_vha->dpc_flags);
6915 }
6916
6917 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6918 "Loop resync end.\n");
6919 }
6920
6921 if (IS_QLAFX00(ha))
6922 goto intr_on_check;
6923
6924 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6925 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6926 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6927 qla2xxx_flash_npiv_conf(base_vha);
6928 }
6929
6930 intr_on_check:
6931 if (!ha->interrupts_on)
6932 ha->isp_ops->enable_intrs(ha);
6933
6934 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
6935 &base_vha->dpc_flags)) {
6936 if (ha->beacon_blink_led == 1)
6937 ha->isp_ops->beacon_blink(base_vha);
6938 }
6939
6940 /* qpair online check */
6941 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6942 &base_vha->dpc_flags)) {
6943 if (ha->flags.eeh_busy ||
6944 ha->flags.pci_channel_io_perm_failure)
6945 online = 0;
6946 else
6947 online = 1;
6948
6949 mutex_lock(&ha->mq_lock);
6950 list_for_each_entry(qpair, &base_vha->qp_list,
6951 qp_list_elem)
6952 qpair->online = online;
6953 mutex_unlock(&ha->mq_lock);
6954 }
6955
6956 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED,
6957 &base_vha->dpc_flags)) {
6958 ql_log(ql_log_info, base_vha, 0xffffff,
6959 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6960 ha->nvme_last_rptd_aen);
6961 if (qla27xx_set_zio_threshold(base_vha,
6962 ha->nvme_last_rptd_aen)) {
6963 ql_log(ql_log_info, base_vha, 0xffffff,
6964 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6965 ha->nvme_last_rptd_aen);
6966 }
6967 }
6968
6969 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
6970 &base_vha->dpc_flags)) {
6971 ql_log(ql_log_info, base_vha, 0xffffff,
6972 "SET ZIO Activity exchange threshold to %d.\n",
6973 ha->last_zio_threshold);
6974 qla27xx_set_zio_threshold(base_vha,
6975 ha->last_zio_threshold);
6976 }
6977
6978 if (!IS_QLAFX00(ha))
6979 qla2x00_do_dpc_all_vps(base_vha);
6980
6981 if (test_and_clear_bit(N2N_LINK_RESET,
6982 &base_vha->dpc_flags)) {
6983 qla2x00_lip_reset(base_vha);
6984 }
6985
6986 ha->dpc_active = 0;
6987 end_loop:
6988 set_current_state(TASK_INTERRUPTIBLE);
6989 } /* End of while(1) */
6990 __set_current_state(TASK_RUNNING);
6991
6992 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6993 "DPC handler exiting.\n");
6994
6995 /*
6996 * Make sure that nobody tries to wake us up again.
6997 */
6998 ha->dpc_active = 0;
6999
7000 /* Cleanup any residual CTX SRBs. */
7001 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
7002
7003 return 0;
7004 }
7005
7006 void
qla2xxx_wake_dpc(struct scsi_qla_host * vha)7007 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
7008 {
7009 struct qla_hw_data *ha = vha->hw;
7010 struct task_struct *t = ha->dpc_thread;
7011
7012 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
7013 wake_up_process(t);
7014 }
7015
7016 /*
7017 * qla2x00_rst_aen
7018 * Processes asynchronous reset.
7019 *
7020 * Input:
7021 * ha = adapter block pointer.
7022 */
7023 static void
qla2x00_rst_aen(scsi_qla_host_t * vha)7024 qla2x00_rst_aen(scsi_qla_host_t *vha)
7025 {
7026 if (vha->flags.online && !vha->flags.reset_active &&
7027 !atomic_read(&vha->loop_down_timer) &&
7028 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
7029 do {
7030 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7031
7032 /*
7033 * Issue marker command only when we are going to start
7034 * the I/O.
7035 */
7036 vha->marker_needed = 1;
7037 } while (!atomic_read(&vha->loop_down_timer) &&
7038 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
7039 }
7040 }
7041
7042 /**************************************************************************
7043 * qla2x00_timer
7044 *
7045 * Description:
7046 * One second timer
7047 *
7048 * Context: Interrupt
7049 ***************************************************************************/
7050 void
qla2x00_timer(struct timer_list * t)7051 qla2x00_timer(struct timer_list *t)
7052 {
7053 scsi_qla_host_t *vha = from_timer(vha, t, timer);
7054 unsigned long cpu_flags = 0;
7055 int start_dpc = 0;
7056 int index;
7057 srb_t *sp;
7058 uint16_t w;
7059 struct qla_hw_data *ha = vha->hw;
7060 struct req_que *req;
7061
7062 if (ha->flags.eeh_busy) {
7063 ql_dbg(ql_dbg_timer, vha, 0x6000,
7064 "EEH = %d, restarting timer.\n",
7065 ha->flags.eeh_busy);
7066 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7067 return;
7068 }
7069
7070 /*
7071 * Hardware read to raise pending EEH errors during mailbox waits. If
7072 * the read returns -1 then disable the board.
7073 */
7074 if (!pci_channel_offline(ha->pdev)) {
7075 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
7076 qla2x00_check_reg16_for_disconnect(vha, w);
7077 }
7078
7079 /* Make sure qla82xx_watchdog is run only for physical port */
7080 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
7081 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
7082 start_dpc++;
7083 if (IS_QLA82XX(ha))
7084 qla82xx_watchdog(vha);
7085 else if (IS_QLA8044(ha))
7086 qla8044_watchdog(vha);
7087 }
7088
7089 if (!vha->vp_idx && IS_QLAFX00(ha))
7090 qlafx00_timer_routine(vha);
7091
7092 /* Loop down handler. */
7093 if (atomic_read(&vha->loop_down_timer) > 0 &&
7094 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
7095 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
7096 && vha->flags.online) {
7097
7098 if (atomic_read(&vha->loop_down_timer) ==
7099 vha->loop_down_abort_time) {
7100
7101 ql_log(ql_log_info, vha, 0x6008,
7102 "Loop down - aborting the queues before time expires.\n");
7103
7104 if (!IS_QLA2100(ha) && vha->link_down_timeout)
7105 atomic_set(&vha->loop_state, LOOP_DEAD);
7106
7107 /*
7108 * Schedule an ISP abort to return any FCP2-device
7109 * commands.
7110 */
7111 /* NPIV - scan physical port only */
7112 if (!vha->vp_idx) {
7113 spin_lock_irqsave(&ha->hardware_lock,
7114 cpu_flags);
7115 req = ha->req_q_map[0];
7116 for (index = 1;
7117 index < req->num_outstanding_cmds;
7118 index++) {
7119 fc_port_t *sfcp;
7120
7121 sp = req->outstanding_cmds[index];
7122 if (!sp)
7123 continue;
7124 if (sp->cmd_type != TYPE_SRB)
7125 continue;
7126 if (sp->type != SRB_SCSI_CMD)
7127 continue;
7128 sfcp = sp->fcport;
7129 if (!(sfcp->flags & FCF_FCP2_DEVICE))
7130 continue;
7131
7132 if (IS_QLA82XX(ha))
7133 set_bit(FCOE_CTX_RESET_NEEDED,
7134 &vha->dpc_flags);
7135 else
7136 set_bit(ISP_ABORT_NEEDED,
7137 &vha->dpc_flags);
7138 break;
7139 }
7140 spin_unlock_irqrestore(&ha->hardware_lock,
7141 cpu_flags);
7142 }
7143 start_dpc++;
7144 }
7145
7146 /* if the loop has been down for 4 minutes, reinit adapter */
7147 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
7148 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7149 ql_log(ql_log_warn, vha, 0x6009,
7150 "Loop down - aborting ISP.\n");
7151
7152 if (IS_QLA82XX(ha))
7153 set_bit(FCOE_CTX_RESET_NEEDED,
7154 &vha->dpc_flags);
7155 else
7156 set_bit(ISP_ABORT_NEEDED,
7157 &vha->dpc_flags);
7158 }
7159 }
7160 ql_dbg(ql_dbg_timer, vha, 0x600a,
7161 "Loop down - seconds remaining %d.\n",
7162 atomic_read(&vha->loop_down_timer));
7163 }
7164 /* Check if beacon LED needs to be blinked for physical host only */
7165 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
7166 /* There is no beacon_blink function for ISP82xx */
7167 if (!IS_P3P_TYPE(ha)) {
7168 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
7169 start_dpc++;
7170 }
7171 }
7172
7173 /* Process any deferred work. */
7174 if (!list_empty(&vha->work_list)) {
7175 unsigned long flags;
7176 bool q = false;
7177
7178 spin_lock_irqsave(&vha->work_lock, flags);
7179 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
7180 q = true;
7181 spin_unlock_irqrestore(&vha->work_lock, flags);
7182 if (q)
7183 queue_work(vha->hw->wq, &vha->iocb_work);
7184 }
7185
7186 /*
7187 * FC-NVME
7188 * see if the active AEN count has changed from what was last reported.
7189 */
7190 index = atomic_read(&ha->nvme_active_aen_cnt);
7191 if (!vha->vp_idx &&
7192 (index != ha->nvme_last_rptd_aen) &&
7193 (index >= DEFAULT_ZIO_THRESHOLD) &&
7194 ha->zio_mode == QLA_ZIO_MODE_6 &&
7195 !ha->flags.host_shutting_down) {
7196 ql_log(ql_log_info, vha, 0x3002,
7197 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
7198 ha->nvme_last_rptd_aen);
7199 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
7200 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7201 start_dpc++;
7202 }
7203
7204 if (!vha->vp_idx &&
7205 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold &&
7206 IS_ZIO_THRESHOLD_CAPABLE(ha)) {
7207 ql_log(ql_log_info, vha, 0x3002,
7208 "Sched: Set ZIO exchange threshold to %d.\n",
7209 ha->last_zio_threshold);
7210 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
7211 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7212 start_dpc++;
7213 }
7214
7215 /* Schedule the DPC routine if needed */
7216 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
7217 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
7218 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
7219 start_dpc ||
7220 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
7221 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
7222 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
7223 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
7224 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7225 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
7226 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) {
7227 ql_dbg(ql_dbg_timer, vha, 0x600b,
7228 "isp_abort_needed=%d loop_resync_needed=%d "
7229 "fcport_update_needed=%d start_dpc=%d "
7230 "reset_marker_needed=%d",
7231 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
7232 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
7233 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
7234 start_dpc,
7235 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
7236 ql_dbg(ql_dbg_timer, vha, 0x600c,
7237 "beacon_blink_needed=%d isp_unrecoverable=%d "
7238 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
7239 "relogin_needed=%d, Process_purex_iocb=%d.\n",
7240 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
7241 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
7242 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
7243 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
7244 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
7245 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags));
7246 qla2xxx_wake_dpc(vha);
7247 }
7248
7249 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7250 }
7251
7252 /* Firmware interface routines. */
7253
7254 #define FW_ISP21XX 0
7255 #define FW_ISP22XX 1
7256 #define FW_ISP2300 2
7257 #define FW_ISP2322 3
7258 #define FW_ISP24XX 4
7259 #define FW_ISP25XX 5
7260 #define FW_ISP81XX 6
7261 #define FW_ISP82XX 7
7262 #define FW_ISP2031 8
7263 #define FW_ISP8031 9
7264 #define FW_ISP27XX 10
7265 #define FW_ISP28XX 11
7266
7267 #define FW_FILE_ISP21XX "ql2100_fw.bin"
7268 #define FW_FILE_ISP22XX "ql2200_fw.bin"
7269 #define FW_FILE_ISP2300 "ql2300_fw.bin"
7270 #define FW_FILE_ISP2322 "ql2322_fw.bin"
7271 #define FW_FILE_ISP24XX "ql2400_fw.bin"
7272 #define FW_FILE_ISP25XX "ql2500_fw.bin"
7273 #define FW_FILE_ISP81XX "ql8100_fw.bin"
7274 #define FW_FILE_ISP82XX "ql8200_fw.bin"
7275 #define FW_FILE_ISP2031 "ql2600_fw.bin"
7276 #define FW_FILE_ISP8031 "ql8300_fw.bin"
7277 #define FW_FILE_ISP27XX "ql2700_fw.bin"
7278 #define FW_FILE_ISP28XX "ql2800_fw.bin"
7279
7280
7281 static DEFINE_MUTEX(qla_fw_lock);
7282
7283 static struct fw_blob qla_fw_blobs[] = {
7284 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
7285 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
7286 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
7287 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
7288 { .name = FW_FILE_ISP24XX, },
7289 { .name = FW_FILE_ISP25XX, },
7290 { .name = FW_FILE_ISP81XX, },
7291 { .name = FW_FILE_ISP82XX, },
7292 { .name = FW_FILE_ISP2031, },
7293 { .name = FW_FILE_ISP8031, },
7294 { .name = FW_FILE_ISP27XX, },
7295 { .name = FW_FILE_ISP28XX, },
7296 { .name = NULL, },
7297 };
7298
7299 struct fw_blob *
qla2x00_request_firmware(scsi_qla_host_t * vha)7300 qla2x00_request_firmware(scsi_qla_host_t *vha)
7301 {
7302 struct qla_hw_data *ha = vha->hw;
7303 struct fw_blob *blob;
7304
7305 if (IS_QLA2100(ha)) {
7306 blob = &qla_fw_blobs[FW_ISP21XX];
7307 } else if (IS_QLA2200(ha)) {
7308 blob = &qla_fw_blobs[FW_ISP22XX];
7309 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
7310 blob = &qla_fw_blobs[FW_ISP2300];
7311 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
7312 blob = &qla_fw_blobs[FW_ISP2322];
7313 } else if (IS_QLA24XX_TYPE(ha)) {
7314 blob = &qla_fw_blobs[FW_ISP24XX];
7315 } else if (IS_QLA25XX(ha)) {
7316 blob = &qla_fw_blobs[FW_ISP25XX];
7317 } else if (IS_QLA81XX(ha)) {
7318 blob = &qla_fw_blobs[FW_ISP81XX];
7319 } else if (IS_QLA82XX(ha)) {
7320 blob = &qla_fw_blobs[FW_ISP82XX];
7321 } else if (IS_QLA2031(ha)) {
7322 blob = &qla_fw_blobs[FW_ISP2031];
7323 } else if (IS_QLA8031(ha)) {
7324 blob = &qla_fw_blobs[FW_ISP8031];
7325 } else if (IS_QLA27XX(ha)) {
7326 blob = &qla_fw_blobs[FW_ISP27XX];
7327 } else if (IS_QLA28XX(ha)) {
7328 blob = &qla_fw_blobs[FW_ISP28XX];
7329 } else {
7330 return NULL;
7331 }
7332
7333 if (!blob->name)
7334 return NULL;
7335
7336 mutex_lock(&qla_fw_lock);
7337 if (blob->fw)
7338 goto out;
7339
7340 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7341 ql_log(ql_log_warn, vha, 0x0063,
7342 "Failed to load firmware image (%s).\n", blob->name);
7343 blob->fw = NULL;
7344 blob = NULL;
7345 }
7346
7347 out:
7348 mutex_unlock(&qla_fw_lock);
7349 return blob;
7350 }
7351
7352 static void
qla2x00_release_firmware(void)7353 qla2x00_release_firmware(void)
7354 {
7355 struct fw_blob *blob;
7356
7357 mutex_lock(&qla_fw_lock);
7358 for (blob = qla_fw_blobs; blob->name; blob++)
7359 release_firmware(blob->fw);
7360 mutex_unlock(&qla_fw_lock);
7361 }
7362
qla_pci_error_cleanup(scsi_qla_host_t * vha)7363 static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
7364 {
7365 struct qla_hw_data *ha = vha->hw;
7366 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
7367 struct qla_qpair *qpair = NULL;
7368 struct scsi_qla_host *vp;
7369 fc_port_t *fcport;
7370 int i;
7371 unsigned long flags;
7372
7373 ha->chip_reset++;
7374
7375 ha->base_qpair->chip_reset = ha->chip_reset;
7376 for (i = 0; i < ha->max_qpairs; i++) {
7377 if (ha->queue_pair_map[i])
7378 ha->queue_pair_map[i]->chip_reset =
7379 ha->base_qpair->chip_reset;
7380 }
7381
7382 /* purge MBox commands */
7383 if (atomic_read(&ha->num_pend_mbx_stage3)) {
7384 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
7385 complete(&ha->mbx_intr_comp);
7386 }
7387
7388 i = 0;
7389
7390 while (atomic_read(&ha->num_pend_mbx_stage3) ||
7391 atomic_read(&ha->num_pend_mbx_stage2) ||
7392 atomic_read(&ha->num_pend_mbx_stage1)) {
7393 msleep(20);
7394 i++;
7395 if (i > 50)
7396 break;
7397 }
7398
7399 ha->flags.purge_mbox = 0;
7400
7401 mutex_lock(&ha->mq_lock);
7402 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7403 qpair->online = 0;
7404 mutex_unlock(&ha->mq_lock);
7405
7406 qla2x00_mark_all_devices_lost(vha);
7407
7408 spin_lock_irqsave(&ha->vport_slock, flags);
7409 list_for_each_entry(vp, &ha->vp_list, list) {
7410 atomic_inc(&vp->vref_count);
7411 spin_unlock_irqrestore(&ha->vport_slock, flags);
7412 qla2x00_mark_all_devices_lost(vp);
7413 spin_lock_irqsave(&ha->vport_slock, flags);
7414 atomic_dec(&vp->vref_count);
7415 }
7416 spin_unlock_irqrestore(&ha->vport_slock, flags);
7417
7418 /* Clear all async request states across all VPs. */
7419 list_for_each_entry(fcport, &vha->vp_fcports, list)
7420 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7421
7422 spin_lock_irqsave(&ha->vport_slock, flags);
7423 list_for_each_entry(vp, &ha->vp_list, list) {
7424 atomic_inc(&vp->vref_count);
7425 spin_unlock_irqrestore(&ha->vport_slock, flags);
7426 list_for_each_entry(fcport, &vp->vp_fcports, list)
7427 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7428 spin_lock_irqsave(&ha->vport_slock, flags);
7429 atomic_dec(&vp->vref_count);
7430 }
7431 spin_unlock_irqrestore(&ha->vport_slock, flags);
7432 }
7433
7434
7435 static pci_ers_result_t
qla2xxx_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)7436 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
7437 {
7438 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
7439 struct qla_hw_data *ha = vha->hw;
7440
7441 ql_dbg(ql_dbg_aer, vha, 0x9000,
7442 "PCI error detected, state %x.\n", state);
7443
7444 if (!atomic_read(&pdev->enable_cnt)) {
7445 ql_log(ql_log_info, vha, 0xffff,
7446 "PCI device is disabled,state %x\n", state);
7447 return PCI_ERS_RESULT_NEED_RESET;
7448 }
7449
7450 switch (state) {
7451 case pci_channel_io_normal:
7452 ha->flags.eeh_busy = 0;
7453 if (ql2xmqsupport || ql2xnvmeenable) {
7454 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7455 qla2xxx_wake_dpc(vha);
7456 }
7457 return PCI_ERS_RESULT_CAN_RECOVER;
7458 case pci_channel_io_frozen:
7459 ha->flags.eeh_busy = 1;
7460 qla_pci_error_cleanup(vha);
7461 return PCI_ERS_RESULT_NEED_RESET;
7462 case pci_channel_io_perm_failure:
7463 ha->flags.pci_channel_io_perm_failure = 1;
7464 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
7465 if (ql2xmqsupport || ql2xnvmeenable) {
7466 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7467 qla2xxx_wake_dpc(vha);
7468 }
7469 return PCI_ERS_RESULT_DISCONNECT;
7470 }
7471 return PCI_ERS_RESULT_NEED_RESET;
7472 }
7473
7474 static pci_ers_result_t
qla2xxx_pci_mmio_enabled(struct pci_dev * pdev)7475 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
7476 {
7477 int risc_paused = 0;
7478 uint32_t stat;
7479 unsigned long flags;
7480 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7481 struct qla_hw_data *ha = base_vha->hw;
7482 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7483 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
7484
7485 if (IS_QLA82XX(ha))
7486 return PCI_ERS_RESULT_RECOVERED;
7487
7488 spin_lock_irqsave(&ha->hardware_lock, flags);
7489 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
7490 stat = rd_reg_word(®->hccr);
7491 if (stat & HCCR_RISC_PAUSE)
7492 risc_paused = 1;
7493 } else if (IS_QLA23XX(ha)) {
7494 stat = rd_reg_dword(®->u.isp2300.host_status);
7495 if (stat & HSR_RISC_PAUSED)
7496 risc_paused = 1;
7497 } else if (IS_FWI2_CAPABLE(ha)) {
7498 stat = rd_reg_dword(®24->host_status);
7499 if (stat & HSRX_RISC_PAUSED)
7500 risc_paused = 1;
7501 }
7502 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7503
7504 if (risc_paused) {
7505 ql_log(ql_log_info, base_vha, 0x9003,
7506 "RISC paused -- mmio_enabled, Dumping firmware.\n");
7507 qla2xxx_dump_fw(base_vha);
7508
7509 return PCI_ERS_RESULT_NEED_RESET;
7510 } else
7511 return PCI_ERS_RESULT_RECOVERED;
7512 }
7513
7514 static pci_ers_result_t
qla2xxx_pci_slot_reset(struct pci_dev * pdev)7515 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7516 {
7517 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
7518 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7519 struct qla_hw_data *ha = base_vha->hw;
7520 int rc;
7521 struct qla_qpair *qpair = NULL;
7522
7523 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
7524 "Slot Reset.\n");
7525
7526 /* Workaround: qla2xxx driver which access hardware earlier
7527 * needs error state to be pci_channel_io_online.
7528 * Otherwise mailbox command timesout.
7529 */
7530 pdev->error_state = pci_channel_io_normal;
7531
7532 pci_restore_state(pdev);
7533
7534 /* pci_restore_state() clears the saved_state flag of the device
7535 * save restored state which resets saved_state flag
7536 */
7537 pci_save_state(pdev);
7538
7539 if (ha->mem_only)
7540 rc = pci_enable_device_mem(pdev);
7541 else
7542 rc = pci_enable_device(pdev);
7543
7544 if (rc) {
7545 ql_log(ql_log_warn, base_vha, 0x9005,
7546 "Can't re-enable PCI device after reset.\n");
7547 goto exit_slot_reset;
7548 }
7549
7550
7551 if (ha->isp_ops->pci_config(base_vha))
7552 goto exit_slot_reset;
7553
7554 mutex_lock(&ha->mq_lock);
7555 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7556 qpair->online = 1;
7557 mutex_unlock(&ha->mq_lock);
7558
7559 base_vha->flags.online = 1;
7560 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7561 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
7562 ret = PCI_ERS_RESULT_RECOVERED;
7563 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7564
7565
7566 exit_slot_reset:
7567 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7568 "slot_reset return %x.\n", ret);
7569
7570 return ret;
7571 }
7572
7573 static void
qla2xxx_pci_resume(struct pci_dev * pdev)7574 qla2xxx_pci_resume(struct pci_dev *pdev)
7575 {
7576 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7577 struct qla_hw_data *ha = base_vha->hw;
7578 int ret;
7579
7580 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
7581 "pci_resume.\n");
7582
7583 ha->flags.eeh_busy = 0;
7584
7585 ret = qla2x00_wait_for_hba_online(base_vha);
7586 if (ret != QLA_SUCCESS) {
7587 ql_log(ql_log_fatal, base_vha, 0x9002,
7588 "The device failed to resume I/O from slot/link_reset.\n");
7589 }
7590 }
7591
7592 static void
qla_pci_reset_prepare(struct pci_dev * pdev)7593 qla_pci_reset_prepare(struct pci_dev *pdev)
7594 {
7595 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7596 struct qla_hw_data *ha = base_vha->hw;
7597 struct qla_qpair *qpair;
7598
7599 ql_log(ql_log_warn, base_vha, 0xffff,
7600 "%s.\n", __func__);
7601
7602 /*
7603 * PCI FLR/function reset is about to reset the
7604 * slot. Stop the chip to stop all DMA access.
7605 * It is assumed that pci_reset_done will be called
7606 * after FLR to resume Chip operation.
7607 */
7608 ha->flags.eeh_busy = 1;
7609 mutex_lock(&ha->mq_lock);
7610 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7611 qpair->online = 0;
7612 mutex_unlock(&ha->mq_lock);
7613
7614 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7615 qla2x00_abort_isp_cleanup(base_vha);
7616 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
7617 }
7618
7619 static void
qla_pci_reset_done(struct pci_dev * pdev)7620 qla_pci_reset_done(struct pci_dev *pdev)
7621 {
7622 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7623 struct qla_hw_data *ha = base_vha->hw;
7624 struct qla_qpair *qpair;
7625
7626 ql_log(ql_log_warn, base_vha, 0xffff,
7627 "%s.\n", __func__);
7628
7629 /*
7630 * FLR just completed by PCI layer. Resume adapter
7631 */
7632 ha->flags.eeh_busy = 0;
7633 mutex_lock(&ha->mq_lock);
7634 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7635 qpair->online = 1;
7636 mutex_unlock(&ha->mq_lock);
7637
7638 base_vha->flags.online = 1;
7639 ha->isp_ops->abort_isp(base_vha);
7640 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7641 }
7642
qla2xxx_map_queues(struct Scsi_Host * shost)7643 static int qla2xxx_map_queues(struct Scsi_Host *shost)
7644 {
7645 int rc;
7646 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
7647 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
7648
7649 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
7650 rc = blk_mq_map_queues(qmap);
7651 else
7652 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
7653 return rc;
7654 }
7655
7656 struct scsi_host_template qla2xxx_driver_template = {
7657 .module = THIS_MODULE,
7658 .name = QLA2XXX_DRIVER_NAME,
7659 .queuecommand = qla2xxx_queuecommand,
7660
7661 .eh_timed_out = fc_eh_timed_out,
7662 .eh_abort_handler = qla2xxx_eh_abort,
7663 .eh_device_reset_handler = qla2xxx_eh_device_reset,
7664 .eh_target_reset_handler = qla2xxx_eh_target_reset,
7665 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
7666 .eh_host_reset_handler = qla2xxx_eh_host_reset,
7667
7668 .slave_configure = qla2xxx_slave_configure,
7669
7670 .slave_alloc = qla2xxx_slave_alloc,
7671 .slave_destroy = qla2xxx_slave_destroy,
7672 .scan_finished = qla2xxx_scan_finished,
7673 .scan_start = qla2xxx_scan_start,
7674 .change_queue_depth = scsi_change_queue_depth,
7675 .map_queues = qla2xxx_map_queues,
7676 .this_id = -1,
7677 .cmd_per_lun = 3,
7678 .sg_tablesize = SG_ALL,
7679
7680 .max_sectors = 0xFFFF,
7681 .shost_attrs = qla2x00_host_attrs,
7682
7683 .supported_mode = MODE_INITIATOR,
7684 .track_queue_depth = 1,
7685 .cmd_size = sizeof(srb_t),
7686 };
7687
7688 static const struct pci_error_handlers qla2xxx_err_handler = {
7689 .error_detected = qla2xxx_pci_error_detected,
7690 .mmio_enabled = qla2xxx_pci_mmio_enabled,
7691 .slot_reset = qla2xxx_pci_slot_reset,
7692 .resume = qla2xxx_pci_resume,
7693 .reset_prepare = qla_pci_reset_prepare,
7694 .reset_done = qla_pci_reset_done,
7695 };
7696
7697 static struct pci_device_id qla2xxx_pci_tbl[] = {
7698 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
7699 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
7700 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
7701 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
7702 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
7703 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
7704 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
7705 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
7706 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
7707 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
7708 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
7709 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
7710 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
7711 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
7712 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
7713 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
7714 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
7715 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7716 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
7717 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
7718 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
7719 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
7720 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
7721 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
7722 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
7723 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
7724 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
7725 { 0 },
7726 };
7727 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
7728
7729 static struct pci_driver qla2xxx_pci_driver = {
7730 .name = QLA2XXX_DRIVER_NAME,
7731 .driver = {
7732 .owner = THIS_MODULE,
7733 },
7734 .id_table = qla2xxx_pci_tbl,
7735 .probe = qla2x00_probe_one,
7736 .remove = qla2x00_remove_one,
7737 .shutdown = qla2x00_shutdown,
7738 .err_handler = &qla2xxx_err_handler,
7739 };
7740
7741 static const struct file_operations apidev_fops = {
7742 .owner = THIS_MODULE,
7743 .llseek = noop_llseek,
7744 };
7745
7746 /**
7747 * qla2x00_module_init - Module initialization.
7748 **/
7749 static int __init
qla2x00_module_init(void)7750 qla2x00_module_init(void)
7751 {
7752 int ret = 0;
7753
7754 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64);
7755 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
7756 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
7757 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
7758 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
7759 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64);
7760 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
7761 BUILD_BUG_ON(sizeof(request_t) != 64);
7762 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64);
7763 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64);
7764 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64);
7765 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
7766 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64);
7767 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
7768 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
7769 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
7770 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
7771 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
7772 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
7773 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
7774 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2344);
7775 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424);
7776 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164);
7777 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260);
7778 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260);
7779 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16);
7780 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
7781 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256);
7782 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24);
7783 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256);
7784 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288);
7785 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216);
7786 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
7787 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64);
7788 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
7789 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64);
7790 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
7791 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
7792 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64);
7793 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64);
7794 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252);
7795 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64);
7796 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512);
7797 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512);
7798 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
7799 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64);
7800 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64);
7801 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634);
7802 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100);
7803 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976);
7804 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228);
7805 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52);
7806 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172);
7807 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524);
7808 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8);
7809 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12);
7810 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24);
7811 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420);
7812 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28);
7813 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32);
7814 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196);
7815 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE);
7816 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128);
7817 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8);
7818 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16);
7819 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24);
7820 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16);
7821 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336);
7822 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
7823 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64);
7824 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64);
7825 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64);
7826 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
7827 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52);
7828 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
7829 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64);
7830 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64);
7831 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64);
7832 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64);
7833 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64);
7834 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64);
7835 BUILD_BUG_ON(sizeof(sts_entry_t) != 64);
7836 BUILD_BUG_ON(sizeof(sw_info_t) != 32);
7837 BUILD_BUG_ON(sizeof(target_id_t) != 2);
7838
7839 /* Allocate cache for SRBs. */
7840 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
7841 SLAB_HWCACHE_ALIGN, NULL);
7842 if (srb_cachep == NULL) {
7843 ql_log(ql_log_fatal, NULL, 0x0001,
7844 "Unable to allocate SRB cache...Failing load!.\n");
7845 return -ENOMEM;
7846 }
7847
7848 /* Initialize target kmem_cache and mem_pools */
7849 ret = qlt_init();
7850 if (ret < 0) {
7851 goto destroy_cache;
7852 } else if (ret > 0) {
7853 /*
7854 * If initiator mode is explictly disabled by qlt_init(),
7855 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
7856 * performing scsi_scan_target() during LOOP UP event.
7857 */
7858 qla2xxx_transport_functions.disable_target_scan = 1;
7859 qla2xxx_transport_vport_functions.disable_target_scan = 1;
7860 }
7861
7862 /* Derive version string. */
7863 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
7864 if (ql2xextended_error_logging)
7865 strcat(qla2x00_version_str, "-debug");
7866 if (ql2xextended_error_logging == 1)
7867 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
7868
7869 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL)
7870 qla_insert_tgt_attrs();
7871
7872 qla2xxx_transport_template =
7873 fc_attach_transport(&qla2xxx_transport_functions);
7874 if (!qla2xxx_transport_template) {
7875 ql_log(ql_log_fatal, NULL, 0x0002,
7876 "fc_attach_transport failed...Failing load!.\n");
7877 ret = -ENODEV;
7878 goto qlt_exit;
7879 }
7880
7881 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
7882 if (apidev_major < 0) {
7883 ql_log(ql_log_fatal, NULL, 0x0003,
7884 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
7885 }
7886
7887 qla2xxx_transport_vport_template =
7888 fc_attach_transport(&qla2xxx_transport_vport_functions);
7889 if (!qla2xxx_transport_vport_template) {
7890 ql_log(ql_log_fatal, NULL, 0x0004,
7891 "fc_attach_transport vport failed...Failing load!.\n");
7892 ret = -ENODEV;
7893 goto unreg_chrdev;
7894 }
7895 ql_log(ql_log_info, NULL, 0x0005,
7896 "QLogic Fibre Channel HBA Driver: %s.\n",
7897 qla2x00_version_str);
7898 ret = pci_register_driver(&qla2xxx_pci_driver);
7899 if (ret) {
7900 ql_log(ql_log_fatal, NULL, 0x0006,
7901 "pci_register_driver failed...ret=%d Failing load!.\n",
7902 ret);
7903 goto release_vport_transport;
7904 }
7905 return ret;
7906
7907 release_vport_transport:
7908 fc_release_transport(qla2xxx_transport_vport_template);
7909
7910 unreg_chrdev:
7911 if (apidev_major >= 0)
7912 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7913 fc_release_transport(qla2xxx_transport_template);
7914
7915 qlt_exit:
7916 qlt_exit();
7917
7918 destroy_cache:
7919 kmem_cache_destroy(srb_cachep);
7920 return ret;
7921 }
7922
7923 /**
7924 * qla2x00_module_exit - Module cleanup.
7925 **/
7926 static void __exit
qla2x00_module_exit(void)7927 qla2x00_module_exit(void)
7928 {
7929 pci_unregister_driver(&qla2xxx_pci_driver);
7930 qla2x00_release_firmware();
7931 kmem_cache_destroy(ctx_cachep);
7932 fc_release_transport(qla2xxx_transport_vport_template);
7933 if (apidev_major >= 0)
7934 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7935 fc_release_transport(qla2xxx_transport_template);
7936 qlt_exit();
7937 kmem_cache_destroy(srb_cachep);
7938 }
7939
7940 module_init(qla2x00_module_init);
7941 module_exit(qla2x00_module_exit);
7942
7943 MODULE_AUTHOR("QLogic Corporation");
7944 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7945 MODULE_LICENSE("GPL");
7946 MODULE_FIRMWARE(FW_FILE_ISP21XX);
7947 MODULE_FIRMWARE(FW_FILE_ISP22XX);
7948 MODULE_FIRMWARE(FW_FILE_ISP2300);
7949 MODULE_FIRMWARE(FW_FILE_ISP2322);
7950 MODULE_FIRMWARE(FW_FILE_ISP24XX);
7951 MODULE_FIRMWARE(FW_FILE_ISP25XX);
7952