1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/format/u_format_s3tc.h"
32 #include "util/u_draw.h"
33 #include "util/u_index_modify.h"
34 #include "util/u_memory.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_math.h"
37 #include "tgsi/tgsi_parse.h"
38 #include "tgsi/tgsi_scan.h"
39 #include "tgsi/tgsi_ureg.h"
40
41 #include "nir.h"
42 #include "nir/nir_to_tgsi.h"
43 #include "nir/nir_to_tgsi_info.h"
44 #include "tgsi/tgsi_from_mesa.h"
45
r600_init_command_buffer(struct r600_command_buffer * cb,unsigned num_dw)46 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
47 {
48 assert(!cb->buf);
49 cb->buf = CALLOC(1, 4 * num_dw);
50 cb->max_num_dw = num_dw;
51 }
52
r600_release_command_buffer(struct r600_command_buffer * cb)53 void r600_release_command_buffer(struct r600_command_buffer *cb)
54 {
55 FREE(cb->buf);
56 }
57
r600_add_atom(struct r600_context * rctx,struct r600_atom * atom,unsigned id)58 void r600_add_atom(struct r600_context *rctx,
59 struct r600_atom *atom,
60 unsigned id)
61 {
62 assert(id < R600_NUM_ATOMS);
63 assert(rctx->atoms[id] == NULL);
64 rctx->atoms[id] = atom;
65 atom->id = id;
66 }
67
r600_init_atom(struct r600_context * rctx,struct r600_atom * atom,unsigned id,void (* emit)(struct r600_context * ctx,struct r600_atom * state),unsigned num_dw)68 void r600_init_atom(struct r600_context *rctx,
69 struct r600_atom *atom,
70 unsigned id,
71 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
72 unsigned num_dw)
73 {
74 atom->emit = (void*)emit;
75 atom->num_dw = num_dw;
76 r600_add_atom(rctx, atom, id);
77 }
78
r600_emit_cso_state(struct r600_context * rctx,struct r600_atom * atom)79 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
80 {
81 r600_emit_command_buffer(&rctx->b.gfx.cs, ((struct r600_cso_state*)atom)->cb);
82 }
83
r600_emit_alphatest_state(struct r600_context * rctx,struct r600_atom * atom)84 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
85 {
86 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
87 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
88 unsigned alpha_ref = a->sx_alpha_ref;
89
90 if (rctx->b.gfx_level >= EVERGREEN && a->cb0_export_16bpc) {
91 alpha_ref &= ~0x1FFF;
92 }
93
94 radeon_set_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
95 a->sx_alpha_test_control |
96 S_028410_ALPHA_TEST_BYPASS(a->bypass));
97 radeon_set_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
98 }
99
r600_memory_barrier(struct pipe_context * ctx,unsigned flags)100 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
101 {
102 struct r600_context *rctx = (struct r600_context *)ctx;
103
104 if (!(flags & ~PIPE_BARRIER_UPDATE))
105 return;
106
107 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
108 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
109
110 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
111 PIPE_BARRIER_SHADER_BUFFER |
112 PIPE_BARRIER_TEXTURE |
113 PIPE_BARRIER_IMAGE |
114 PIPE_BARRIER_STREAMOUT_BUFFER |
115 PIPE_BARRIER_GLOBAL_BUFFER)) {
116 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE|
117 R600_CONTEXT_INV_TEX_CACHE;
118 }
119
120 if (flags & (PIPE_BARRIER_FRAMEBUFFER|
121 PIPE_BARRIER_IMAGE))
122 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV;
123
124 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
125 }
126
r600_texture_barrier(struct pipe_context * ctx,unsigned flags)127 static void r600_texture_barrier(struct pipe_context *ctx, unsigned flags)
128 {
129 struct r600_context *rctx = (struct r600_context *)ctx;
130
131 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
132 R600_CONTEXT_FLUSH_AND_INV_CB |
133 R600_CONTEXT_FLUSH_AND_INV |
134 R600_CONTEXT_WAIT_3D_IDLE;
135 rctx->framebuffer.do_update_surf_dirtiness = true;
136 }
137
r600_conv_pipe_prim(unsigned prim)138 static unsigned r600_conv_pipe_prim(unsigned prim)
139 {
140 static const unsigned prim_conv[] = {
141 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
142 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
143 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
144 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
145 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
146 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
147 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
148 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
149 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
150 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
151 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
152 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
153 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
154 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
155 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
156 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
157 };
158 assert(prim < ARRAY_SIZE(prim_conv));
159 return prim_conv[prim];
160 }
161
r600_conv_prim_to_gs_out(unsigned mode)162 unsigned r600_conv_prim_to_gs_out(unsigned mode)
163 {
164 static const int prim_conv[] = {
165 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
166 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
167 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
168 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
169 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
170 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
171 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
172 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
173 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
174 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
175 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
176 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
177 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
178 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
179 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
180 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
181 };
182 assert(mode < ARRAY_SIZE(prim_conv));
183
184 return prim_conv[mode];
185 }
186
187 /* common state between evergreen and r600 */
188
r600_bind_blend_state_internal(struct r600_context * rctx,struct r600_blend_state * blend,bool blend_disable)189 static void r600_bind_blend_state_internal(struct r600_context *rctx,
190 struct r600_blend_state *blend, bool blend_disable)
191 {
192 unsigned color_control;
193 bool update_cb = false;
194
195 rctx->alpha_to_one = blend->alpha_to_one;
196 rctx->dual_src_blend = blend->dual_src_blend;
197
198 if (!blend_disable) {
199 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer);
200 color_control = blend->cb_color_control;
201 } else {
202 /* Blending is disabled. */
203 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer_no_blend);
204 color_control = blend->cb_color_control_no_blend;
205 }
206
207 /* Update derived states. */
208 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
209 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
210 update_cb = true;
211 }
212 if (rctx->b.gfx_level <= R700 &&
213 rctx->cb_misc_state.cb_color_control != color_control) {
214 rctx->cb_misc_state.cb_color_control = color_control;
215 update_cb = true;
216 }
217 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
218 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
219 update_cb = true;
220 }
221 if (update_cb) {
222 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
223 }
224 if (rctx->framebuffer.dual_src_blend != blend->dual_src_blend) {
225 rctx->framebuffer.dual_src_blend = blend->dual_src_blend;
226 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
227 }
228 }
229
r600_bind_blend_state(struct pipe_context * ctx,void * state)230 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
231 {
232 struct r600_context *rctx = (struct r600_context *)ctx;
233 struct r600_blend_state *blend = (struct r600_blend_state *)state;
234
235 if (!blend) {
236 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, NULL, NULL);
237 return;
238 }
239
240 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
241 }
242
r600_set_blend_color(struct pipe_context * ctx,const struct pipe_blend_color * state)243 static void r600_set_blend_color(struct pipe_context *ctx,
244 const struct pipe_blend_color *state)
245 {
246 struct r600_context *rctx = (struct r600_context *)ctx;
247
248 rctx->blend_color.state = *state;
249 r600_mark_atom_dirty(rctx, &rctx->blend_color.atom);
250 }
251
r600_emit_blend_color(struct r600_context * rctx,struct r600_atom * atom)252 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
253 {
254 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
255 struct pipe_blend_color *state = &rctx->blend_color.state;
256
257 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
258 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
259 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
260 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
261 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
262 }
263
r600_emit_vgt_state(struct r600_context * rctx,struct r600_atom * atom)264 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
265 {
266 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
267 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
268
269 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
270 radeon_set_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
271 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
272 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
273 if (a->last_draw_was_indirect) {
274 a->last_draw_was_indirect = false;
275 radeon_set_ctl_const(cs, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
276 }
277 }
278
r600_set_clip_state(struct pipe_context * ctx,const struct pipe_clip_state * state)279 static void r600_set_clip_state(struct pipe_context *ctx,
280 const struct pipe_clip_state *state)
281 {
282 struct r600_context *rctx = (struct r600_context *)ctx;
283
284 rctx->clip_state.state = *state;
285 r600_mark_atom_dirty(rctx, &rctx->clip_state.atom);
286 rctx->driver_consts[PIPE_SHADER_VERTEX].vs_ucp_dirty = true;
287 rctx->driver_consts[PIPE_SHADER_GEOMETRY].vs_ucp_dirty = true;
288 if (rctx->b.family >= CHIP_CEDAR)
289 rctx->driver_consts[PIPE_SHADER_TESS_EVAL].vs_ucp_dirty = true;
290 }
291
r600_set_stencil_ref(struct pipe_context * ctx,const struct r600_stencil_ref state)292 static void r600_set_stencil_ref(struct pipe_context *ctx,
293 const struct r600_stencil_ref state)
294 {
295 struct r600_context *rctx = (struct r600_context *)ctx;
296
297 rctx->stencil_ref.state = state;
298 r600_mark_atom_dirty(rctx, &rctx->stencil_ref.atom);
299 }
300
r600_emit_stencil_ref(struct r600_context * rctx,struct r600_atom * atom)301 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
302 {
303 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
304 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
305
306 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
307 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
308 S_028430_STENCILREF(a->state.ref_value[0]) |
309 S_028430_STENCILMASK(a->state.valuemask[0]) |
310 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
311 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
312 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
313 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
314 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
315 }
316
r600_set_pipe_stencil_ref(struct pipe_context * ctx,const struct pipe_stencil_ref state)317 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
318 const struct pipe_stencil_ref state)
319 {
320 struct r600_context *rctx = (struct r600_context *)ctx;
321 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
322 struct r600_stencil_ref ref;
323
324 rctx->stencil_ref.pipe_state = state;
325
326 if (!dsa)
327 return;
328
329 ref.ref_value[0] = state.ref_value[0];
330 ref.ref_value[1] = state.ref_value[1];
331 ref.valuemask[0] = dsa->valuemask[0];
332 ref.valuemask[1] = dsa->valuemask[1];
333 ref.writemask[0] = dsa->writemask[0];
334 ref.writemask[1] = dsa->writemask[1];
335
336 r600_set_stencil_ref(ctx, ref);
337 }
338
r600_bind_dsa_state(struct pipe_context * ctx,void * state)339 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
340 {
341 struct r600_context *rctx = (struct r600_context *)ctx;
342 struct r600_dsa_state *dsa = state;
343 struct r600_stencil_ref ref;
344
345 if (!state) {
346 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, NULL, NULL);
347 return;
348 }
349
350 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, dsa, &dsa->buffer);
351
352 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
353 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
354 ref.valuemask[0] = dsa->valuemask[0];
355 ref.valuemask[1] = dsa->valuemask[1];
356 ref.writemask[0] = dsa->writemask[0];
357 ref.writemask[1] = dsa->writemask[1];
358 if (rctx->zwritemask != dsa->zwritemask) {
359 rctx->zwritemask = dsa->zwritemask;
360 if (rctx->b.gfx_level >= EVERGREEN) {
361 /* work around some issue when not writing to zbuffer
362 * we are having lockup on evergreen so do not enable
363 * hyperz when not writing zbuffer
364 */
365 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
366 }
367 }
368
369 r600_set_stencil_ref(ctx, ref);
370
371 /* Update alphatest state. */
372 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
373 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
374 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
375 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
376 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
377 }
378 }
379
r600_bind_rs_state(struct pipe_context * ctx,void * state)380 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
381 {
382 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
383 struct r600_context *rctx = (struct r600_context *)ctx;
384
385 if (!state)
386 return;
387
388 rctx->rasterizer = rs;
389
390 r600_set_cso_state_with_cb(rctx, &rctx->rasterizer_state, rs, &rs->buffer);
391
392 if (rs->offset_enable &&
393 (rs->offset_units != rctx->poly_offset_state.offset_units ||
394 rs->offset_scale != rctx->poly_offset_state.offset_scale ||
395 rs->offset_units_unscaled != rctx->poly_offset_state.offset_units_unscaled)) {
396 rctx->poly_offset_state.offset_units = rs->offset_units;
397 rctx->poly_offset_state.offset_scale = rs->offset_scale;
398 rctx->poly_offset_state.offset_units_unscaled = rs->offset_units_unscaled;
399 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
400 }
401
402 /* Update clip_misc_state. */
403 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
404 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
405 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
406 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
407 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
408 }
409
410 r600_viewport_set_rast_deps(&rctx->b, rs->scissor_enable, rs->clip_halfz);
411
412 /* Re-emit PA_SC_LINE_STIPPLE. */
413 rctx->last_primitive_type = -1;
414 }
415
r600_delete_rs_state(struct pipe_context * ctx,void * state)416 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
417 {
418 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
419
420 r600_release_command_buffer(&rs->buffer);
421 FREE(rs);
422 }
423
r600_sampler_view_destroy(struct pipe_context * ctx,struct pipe_sampler_view * state)424 static void r600_sampler_view_destroy(struct pipe_context *ctx,
425 struct pipe_sampler_view *state)
426 {
427 struct r600_pipe_sampler_view *view = (struct r600_pipe_sampler_view *)state;
428
429 if (view->tex_resource->gpu_address &&
430 view->tex_resource->b.b.target == PIPE_BUFFER)
431 list_delinit(&view->list);
432
433 pipe_resource_reference(&state->texture, NULL);
434 FREE(view);
435 }
436
r600_sampler_states_dirty(struct r600_context * rctx,struct r600_sampler_states * state)437 void r600_sampler_states_dirty(struct r600_context *rctx,
438 struct r600_sampler_states *state)
439 {
440 if (state->dirty_mask) {
441 if (state->dirty_mask & state->has_bordercolor_mask) {
442 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
443 }
444 state->atom.num_dw =
445 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
446 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
447 r600_mark_atom_dirty(rctx, &state->atom);
448 }
449 }
450
r600_bind_sampler_states(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned count,void ** states)451 static void r600_bind_sampler_states(struct pipe_context *pipe,
452 enum pipe_shader_type shader,
453 unsigned start,
454 unsigned count, void **states)
455 {
456 struct r600_context *rctx = (struct r600_context *)pipe;
457 struct r600_textures_info *dst = &rctx->samplers[shader];
458 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
459 int seamless_cube_map = -1;
460 unsigned i;
461 /* This sets 1-bit for states with index >= count. */
462 uint32_t disable_mask = ~((1ull << count) - 1);
463 /* These are the new states set by this function. */
464 uint32_t new_mask = 0;
465
466 assert(start == 0); /* XXX fix below */
467
468 if (!states) {
469 disable_mask = ~0u;
470 count = 0;
471 }
472
473 for (i = 0; i < count; i++) {
474 struct r600_pipe_sampler_state *rstate = rstates[i];
475
476 if (rstate == dst->states.states[i]) {
477 continue;
478 }
479
480 if (rstate) {
481 if (rstate->border_color_use) {
482 dst->states.has_bordercolor_mask |= 1 << i;
483 } else {
484 dst->states.has_bordercolor_mask &= ~(1 << i);
485 }
486 seamless_cube_map = rstate->seamless_cube_map;
487
488 new_mask |= 1 << i;
489 } else {
490 disable_mask |= 1 << i;
491 }
492 }
493
494 memcpy(dst->states.states, rstates, sizeof(void*) * count);
495 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
496
497 dst->states.enabled_mask &= ~disable_mask;
498 dst->states.dirty_mask &= dst->states.enabled_mask;
499 dst->states.enabled_mask |= new_mask;
500 dst->states.dirty_mask |= new_mask;
501 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
502
503 r600_sampler_states_dirty(rctx, &dst->states);
504
505 /* Seamless cubemap state. */
506 if (rctx->b.gfx_level <= R700 &&
507 seamless_cube_map != -1 &&
508 seamless_cube_map != rctx->seamless_cube_map.enabled) {
509 /* change in TA_CNTL_AUX need a pipeline flush */
510 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
511 rctx->seamless_cube_map.enabled = seamless_cube_map;
512 r600_mark_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
513 }
514 }
515
r600_delete_sampler_state(struct pipe_context * ctx,void * state)516 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
517 {
518 free(state);
519 }
520
r600_delete_blend_state(struct pipe_context * ctx,void * state)521 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
522 {
523 struct r600_context *rctx = (struct r600_context *)ctx;
524 struct r600_blend_state *blend = (struct r600_blend_state*)state;
525
526 if (rctx->blend_state.cso == state) {
527 ctx->bind_blend_state(ctx, NULL);
528 }
529
530 r600_release_command_buffer(&blend->buffer);
531 r600_release_command_buffer(&blend->buffer_no_blend);
532 FREE(blend);
533 }
534
r600_delete_dsa_state(struct pipe_context * ctx,void * state)535 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
536 {
537 struct r600_context *rctx = (struct r600_context *)ctx;
538 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
539
540 if (rctx->dsa_state.cso == state) {
541 ctx->bind_depth_stencil_alpha_state(ctx, NULL);
542 }
543
544 r600_release_command_buffer(&dsa->buffer);
545 free(dsa);
546 }
547
r600_bind_vertex_elements(struct pipe_context * ctx,void * state)548 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
549 {
550 struct r600_context *rctx = (struct r600_context *)ctx;
551
552 r600_set_cso_state(rctx, &rctx->vertex_fetch_shader, state);
553 }
554
r600_delete_vertex_elements(struct pipe_context * ctx,void * state)555 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
556 {
557 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
558 if (shader)
559 r600_resource_reference(&shader->buffer, NULL);
560 FREE(shader);
561 }
562
r600_vertex_buffers_dirty(struct r600_context * rctx)563 void r600_vertex_buffers_dirty(struct r600_context *rctx)
564 {
565 if (rctx->vertex_buffer_state.dirty_mask) {
566 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.gfx_level >= EVERGREEN ? 12 : 11) *
567 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
568 r600_mark_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
569 }
570 }
571
r600_set_vertex_buffers(struct pipe_context * ctx,unsigned start_slot,unsigned count,unsigned unbind_num_trailing_slots,bool take_ownership,const struct pipe_vertex_buffer * input)572 static void r600_set_vertex_buffers(struct pipe_context *ctx,
573 unsigned start_slot, unsigned count,
574 unsigned unbind_num_trailing_slots,
575 bool take_ownership,
576 const struct pipe_vertex_buffer *input)
577 {
578 struct r600_context *rctx = (struct r600_context *)ctx;
579 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
580 struct pipe_vertex_buffer *vb = state->vb + start_slot;
581 unsigned i;
582 uint32_t disable_mask = 0;
583 /* These are the new buffers set by this function. */
584 uint32_t new_buffer_mask = 0;
585
586 /* Set vertex buffers. */
587 if (input) {
588 for (i = 0; i < count; i++) {
589 if ((input[i].buffer.resource != vb[i].buffer.resource) ||
590 (vb[i].stride != input[i].stride) ||
591 (vb[i].buffer_offset != input[i].buffer_offset) ||
592 (vb[i].is_user_buffer != input[i].is_user_buffer)) {
593 if (input[i].buffer.resource) {
594 vb[i].stride = input[i].stride;
595 vb[i].buffer_offset = input[i].buffer_offset;
596 if (take_ownership) {
597 pipe_resource_reference(&vb[i].buffer.resource, NULL);
598 vb[i].buffer.resource = input[i].buffer.resource;
599 } else {
600 pipe_resource_reference(&vb[i].buffer.resource,
601 input[i].buffer.resource);
602 }
603 new_buffer_mask |= 1 << i;
604 r600_context_add_resource_size(ctx, input[i].buffer.resource);
605 } else {
606 pipe_resource_reference(&vb[i].buffer.resource, NULL);
607 disable_mask |= 1 << i;
608 }
609 }
610 }
611 } else {
612 for (i = 0; i < count; i++) {
613 pipe_resource_reference(&vb[i].buffer.resource, NULL);
614 }
615 disable_mask = ((1ull << count) - 1);
616 }
617
618 for (i = 0; i < unbind_num_trailing_slots; i++) {
619 pipe_resource_reference(&vb[count + i].buffer.resource, NULL);
620 }
621 disable_mask |= ((1ull << unbind_num_trailing_slots) - 1) << count;
622
623 disable_mask <<= start_slot;
624 new_buffer_mask <<= start_slot;
625
626 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
627 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
628 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
629 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
630
631 r600_vertex_buffers_dirty(rctx);
632 }
633
r600_sampler_views_dirty(struct r600_context * rctx,struct r600_samplerview_state * state)634 void r600_sampler_views_dirty(struct r600_context *rctx,
635 struct r600_samplerview_state *state)
636 {
637 if (state->dirty_mask) {
638 state->atom.num_dw = (rctx->b.gfx_level >= EVERGREEN ? 14 : 13) *
639 util_bitcount(state->dirty_mask);
640 r600_mark_atom_dirty(rctx, &state->atom);
641 }
642 }
643
r600_set_sampler_views(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned count,unsigned unbind_num_trailing_slots,bool take_ownership,struct pipe_sampler_view ** views)644 static void r600_set_sampler_views(struct pipe_context *pipe,
645 enum pipe_shader_type shader,
646 unsigned start, unsigned count,
647 unsigned unbind_num_trailing_slots,
648 bool take_ownership,
649 struct pipe_sampler_view **views)
650 {
651 struct r600_context *rctx = (struct r600_context *) pipe;
652 struct r600_textures_info *dst = &rctx->samplers[shader];
653 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
654 uint32_t dirty_sampler_states_mask = 0;
655 unsigned i;
656 /* This sets 1-bit for textures with index >= count. */
657 uint32_t disable_mask = ~((1ull << count) - 1);
658 /* These are the new textures set by this function. */
659 uint32_t new_mask = 0;
660
661 /* Set textures with index >= count to NULL. */
662 uint32_t remaining_mask;
663
664 assert(start == 0); /* XXX fix below */
665
666 if (!views) {
667 disable_mask = ~0u;
668 count = 0;
669 }
670
671 remaining_mask = dst->views.enabled_mask & disable_mask;
672
673 while (remaining_mask) {
674 i = u_bit_scan(&remaining_mask);
675 assert(dst->views.views[i]);
676
677 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
678 }
679
680 for (i = 0; i < count; i++) {
681 if (rviews[i] == dst->views.views[i]) {
682 if (take_ownership) {
683 struct pipe_sampler_view *view = views[i];
684 pipe_sampler_view_reference(&view, NULL);
685 }
686 continue;
687 }
688
689 if (rviews[i]) {
690 struct r600_texture *rtex =
691 (struct r600_texture*)rviews[i]->base.texture;
692 bool is_buffer = rviews[i]->base.texture->target == PIPE_BUFFER;
693
694 if (!is_buffer && rtex->db_compatible) {
695 dst->views.compressed_depthtex_mask |= 1 << i;
696 } else {
697 dst->views.compressed_depthtex_mask &= ~(1 << i);
698 }
699
700 /* Track compressed colorbuffers. */
701 if (!is_buffer && rtex->cmask.size) {
702 dst->views.compressed_colortex_mask |= 1 << i;
703 } else {
704 dst->views.compressed_colortex_mask &= ~(1 << i);
705 }
706
707 /* Changing from array to non-arrays textures and vice versa requires
708 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
709 if (rctx->b.gfx_level <= R700 &&
710 (dst->states.enabled_mask & (1 << i)) &&
711 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
712 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
713 dirty_sampler_states_mask |= 1 << i;
714 }
715
716 if (take_ownership) {
717 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
718 dst->views.views[i] = (struct r600_pipe_sampler_view*)views[i];
719 } else {
720 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
721 }
722 new_mask |= 1 << i;
723 r600_context_add_resource_size(pipe, views[i]->texture);
724 } else {
725 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
726 disable_mask |= 1 << i;
727 }
728 }
729
730 dst->views.enabled_mask &= ~disable_mask;
731 dst->views.dirty_mask &= dst->views.enabled_mask;
732 dst->views.enabled_mask |= new_mask;
733 dst->views.dirty_mask |= new_mask;
734 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
735 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
736 dst->views.dirty_buffer_constants = TRUE;
737 r600_sampler_views_dirty(rctx, &dst->views);
738
739 if (dirty_sampler_states_mask) {
740 dst->states.dirty_mask |= dirty_sampler_states_mask;
741 r600_sampler_states_dirty(rctx, &dst->states);
742 }
743 }
744
r600_update_compressed_colortex_mask(struct r600_samplerview_state * views)745 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state *views)
746 {
747 uint32_t mask = views->enabled_mask;
748
749 while (mask) {
750 unsigned i = u_bit_scan(&mask);
751 struct pipe_resource *res = views->views[i]->base.texture;
752
753 if (res && res->target != PIPE_BUFFER) {
754 struct r600_texture *rtex = (struct r600_texture *)res;
755
756 if (rtex->cmask.size) {
757 views->compressed_colortex_mask |= 1 << i;
758 } else {
759 views->compressed_colortex_mask &= ~(1 << i);
760 }
761 }
762 }
763 }
764
r600_get_hw_atomic_count(const struct pipe_context * ctx,enum pipe_shader_type shader)765 static int r600_get_hw_atomic_count(const struct pipe_context *ctx,
766 enum pipe_shader_type shader)
767 {
768 const struct r600_context *rctx = (struct r600_context *)ctx;
769 int value = 0;
770 switch (shader) {
771 case PIPE_SHADER_FRAGMENT:
772 case PIPE_SHADER_COMPUTE:
773 default:
774 break;
775 case PIPE_SHADER_VERTEX:
776 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
777 break;
778 case PIPE_SHADER_GEOMETRY:
779 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
780 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
781 break;
782 case PIPE_SHADER_TESS_EVAL:
783 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
784 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
785 (rctx->gs_shader ? rctx->gs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] : 0);
786 break;
787 case PIPE_SHADER_TESS_CTRL:
788 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
789 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
790 (rctx->gs_shader ? rctx->gs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] : 0) +
791 rctx->tes_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
792 break;
793 }
794 return value;
795 }
796
r600_update_compressed_colortex_mask_images(struct r600_image_state * images)797 static void r600_update_compressed_colortex_mask_images(struct r600_image_state *images)
798 {
799 uint32_t mask = images->enabled_mask;
800
801 while (mask) {
802 unsigned i = u_bit_scan(&mask);
803 struct pipe_resource *res = images->views[i].base.resource;
804
805 if (res && res->target != PIPE_BUFFER) {
806 struct r600_texture *rtex = (struct r600_texture *)res;
807
808 if (rtex->cmask.size) {
809 images->compressed_colortex_mask |= 1 << i;
810 } else {
811 images->compressed_colortex_mask &= ~(1 << i);
812 }
813 }
814 }
815 }
816
817 /* Compute the key for the hw shader variant */
r600_shader_selector_key(const struct pipe_context * ctx,const struct r600_pipe_shader_selector * sel,union r600_shader_key * key)818 static inline void r600_shader_selector_key(const struct pipe_context *ctx,
819 const struct r600_pipe_shader_selector *sel,
820 union r600_shader_key *key)
821 {
822 const struct r600_context *rctx = (struct r600_context *)ctx;
823 memset(key, 0, sizeof(*key));
824
825 switch (sel->type) {
826 case PIPE_SHADER_VERTEX: {
827 key->vs.as_ls = (rctx->tes_shader != NULL);
828 if (!key->vs.as_ls)
829 key->vs.as_es = (rctx->gs_shader != NULL);
830
831 if (rctx->ps_shader->current->shader.gs_prim_id_input && !rctx->gs_shader) {
832 key->vs.as_gs_a = true;
833 key->vs.prim_id_out = rctx->ps_shader->current->shader.input[rctx->ps_shader->current->shader.ps_prim_id_input].spi_sid;
834 }
835 key->vs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_VERTEX);
836 break;
837 }
838 case PIPE_SHADER_GEOMETRY:
839 key->gs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_GEOMETRY);
840 key->gs.tri_strip_adj_fix = rctx->gs_tri_strip_adj_fix;
841 break;
842 case PIPE_SHADER_FRAGMENT: {
843 if (rctx->ps_shader->info.images_declared)
844 key->ps.image_size_const_offset = util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].views.enabled_mask);
845 key->ps.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_FRAGMENT);
846 key->ps.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
847 key->ps.alpha_to_one = rctx->alpha_to_one &&
848 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
849 !rctx->framebuffer.cb0_is_integer;
850 key->ps.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
851 key->ps.apply_sample_id_mask = (rctx->ps_iter_samples > 1) || !rctx->rasterizer->multisample_enable;
852 /* Dual-source blending only makes sense with nr_cbufs == 1. */
853 if (key->ps.nr_cbufs == 1 && rctx->dual_src_blend) {
854 key->ps.nr_cbufs = 2;
855 key->ps.dual_source_blend = 1;
856 }
857 break;
858 }
859 case PIPE_SHADER_TESS_EVAL:
860 key->tes.as_es = (rctx->gs_shader != NULL);
861 key->tes.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_TESS_EVAL);
862 break;
863 case PIPE_SHADER_TESS_CTRL:
864 key->tcs.prim_mode = rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
865 key->tcs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_TESS_CTRL);
866 break;
867 case PIPE_SHADER_COMPUTE:
868 break;
869 default:
870 assert(0);
871 }
872 }
873
874 static void
r600_shader_precompile_key(const struct pipe_context * ctx,const struct r600_pipe_shader_selector * sel,union r600_shader_key * key)875 r600_shader_precompile_key(const struct pipe_context *ctx,
876 const struct r600_pipe_shader_selector *sel,
877 union r600_shader_key *key)
878 {
879 memset(key, 0, sizeof(*key));
880
881 switch (sel->type) {
882 case PIPE_SHADER_VERTEX:
883 case PIPE_SHADER_TESS_EVAL:
884 /* Assume no tess or GS for setting .as_es. In order to
885 * precompile with es, we'd need the other shaders we're linked
886 * with (see the link_shader screen method)
887 */
888 break;
889
890 case PIPE_SHADER_GEOMETRY:
891 break;
892
893 case PIPE_SHADER_FRAGMENT:
894 key->ps.image_size_const_offset = sel->info.file_max[TGSI_FILE_IMAGE];
895
896 /* This is used for gl_FragColor output expansion to the number
897 * of color buffers bound, but also with sb it'll drop outputs
898 * to unused cbufs.
899 */
900 key->ps.nr_cbufs = sel->info.file_max[TGSI_FILE_OUTPUT] + 1;
901 break;
902
903 case PIPE_SHADER_TESS_CTRL:
904 /* Prim mode comes from the TES, but we need some valid value. */
905 key->tcs.prim_mode = PIPE_PRIM_TRIANGLES;
906 break;
907
908 case PIPE_SHADER_COMPUTE:
909 break;
910
911 default:
912 unreachable("bad shader stage");
913 break;
914 }
915 }
916
917 /* Select the hw shader variant depending on the current state.
918 * (*dirty) is set to 1 if current variant was changed */
r600_shader_select(struct pipe_context * ctx,struct r600_pipe_shader_selector * sel,bool * dirty,bool precompile)919 int r600_shader_select(struct pipe_context *ctx,
920 struct r600_pipe_shader_selector* sel,
921 bool *dirty, bool precompile)
922 {
923 union r600_shader_key key;
924 struct r600_pipe_shader * shader = NULL;
925 int r;
926
927 if (precompile)
928 r600_shader_precompile_key(ctx, sel, &key);
929 else
930 r600_shader_selector_key(ctx, sel, &key);
931
932 /* Check if we don't need to change anything.
933 * This path is also used for most shaders that don't need multiple
934 * variants, it will cost just a computation of the key and this
935 * test. */
936 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
937 return 0;
938 }
939
940 /* lookup if we have other variants in the list */
941 if (sel->num_shaders > 1) {
942 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
943
944 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
945 p = c;
946 c = c->next_variant;
947 }
948
949 if (c) {
950 p->next_variant = c->next_variant;
951 shader = c;
952 }
953 }
954
955 if (unlikely(!shader)) {
956 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
957 shader->selector = sel;
958
959 r = r600_pipe_shader_create(ctx, shader, key);
960 if (unlikely(r)) {
961 R600_ERR("Failed to build shader variant (type=%u) %d\n",
962 sel->type, r);
963 sel->current = NULL;
964 FREE(shader);
965 return r;
966 }
967
968 memcpy(&shader->key, &key, sizeof(key));
969 sel->num_shaders++;
970 }
971
972 if (dirty)
973 *dirty = true;
974
975 shader->next_variant = sel->current;
976 sel->current = shader;
977
978 return 0;
979 }
980
r600_create_shader_state_tokens(struct pipe_context * ctx,const void * prog,enum pipe_shader_ir ir,unsigned pipe_shader_type)981 struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx,
982 const void *prog, enum pipe_shader_ir ir,
983 unsigned pipe_shader_type)
984 {
985 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
986 struct r600_screen *rscreen = (struct r600_screen *)ctx->screen;
987
988 sel->type = pipe_shader_type;
989 if (ir == PIPE_SHADER_IR_TGSI) {
990 sel->tokens = tgsi_dup_tokens((const struct tgsi_token *)prog);
991 tgsi_scan_shader(sel->tokens, &sel->info);
992 } else if (ir == PIPE_SHADER_IR_NIR){
993 nir_shader *s = (nir_shader *)prog;
994
995 if (!(rscreen->b.debug_flags & DBG_NIR_PREFERRED)) {
996 sel->tokens = (void *)nir_to_tgsi(s, ctx->screen);
997 ir = PIPE_SHADER_IR_TGSI;
998 tgsi_scan_shader(sel->tokens, &sel->info);
999 } else {
1000 sel->nir = s;
1001 nir_tgsi_scan_shader(sel->nir, &sel->info, true);
1002 }
1003 }
1004 sel->ir_type = ir;
1005 return sel;
1006 }
1007
r600_create_shader_state(struct pipe_context * ctx,const struct pipe_shader_state * state,unsigned pipe_shader_type)1008 static void *r600_create_shader_state(struct pipe_context *ctx,
1009 const struct pipe_shader_state *state,
1010 unsigned pipe_shader_type)
1011 {
1012 int i;
1013 struct r600_pipe_shader_selector *sel;
1014
1015 if (state->type == PIPE_SHADER_IR_TGSI)
1016 sel = r600_create_shader_state_tokens(ctx, state->tokens, state->type, pipe_shader_type);
1017 else if (state->type == PIPE_SHADER_IR_NIR) {
1018 sel = r600_create_shader_state_tokens(ctx, state->ir.nir, state->type, pipe_shader_type);
1019 } else
1020 unreachable("Unknown shader type");
1021
1022 sel->so = state->stream_output;
1023
1024 switch (pipe_shader_type) {
1025 case PIPE_SHADER_GEOMETRY:
1026 sel->gs_output_prim =
1027 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1028 sel->gs_max_out_vertices =
1029 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1030 sel->gs_num_invocations =
1031 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1032 break;
1033 case PIPE_SHADER_VERTEX:
1034 case PIPE_SHADER_TESS_CTRL:
1035 sel->lds_patch_outputs_written_mask = 0;
1036 sel->lds_outputs_written_mask = 0;
1037
1038 for (i = 0; i < sel->info.num_outputs; i++) {
1039 unsigned name = sel->info.output_semantic_name[i];
1040 unsigned index = sel->info.output_semantic_index[i];
1041
1042 switch (name) {
1043 case TGSI_SEMANTIC_TESSINNER:
1044 case TGSI_SEMANTIC_TESSOUTER:
1045 case TGSI_SEMANTIC_PATCH:
1046 sel->lds_patch_outputs_written_mask |=
1047 1ull << r600_get_lds_unique_index(name, index);
1048 break;
1049 default:
1050 sel->lds_outputs_written_mask |=
1051 1ull << r600_get_lds_unique_index(name, index);
1052 }
1053 }
1054 break;
1055 default:
1056 break;
1057 }
1058
1059 /* Precompile the shader with the expected shader key, to reduce jank at
1060 * draw time. Also produces output for shader-db.
1061 */
1062 bool dirty;
1063 r600_shader_select(ctx, sel, &dirty, true);
1064
1065 return sel;
1066 }
1067
r600_create_ps_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1068 static void *r600_create_ps_state(struct pipe_context *ctx,
1069 const struct pipe_shader_state *state)
1070 {
1071 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
1072 }
1073
r600_create_vs_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1074 static void *r600_create_vs_state(struct pipe_context *ctx,
1075 const struct pipe_shader_state *state)
1076 {
1077 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
1078 }
1079
r600_create_gs_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1080 static void *r600_create_gs_state(struct pipe_context *ctx,
1081 const struct pipe_shader_state *state)
1082 {
1083 return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
1084 }
1085
r600_create_tcs_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1086 static void *r600_create_tcs_state(struct pipe_context *ctx,
1087 const struct pipe_shader_state *state)
1088 {
1089 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
1090 }
1091
r600_create_tes_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1092 static void *r600_create_tes_state(struct pipe_context *ctx,
1093 const struct pipe_shader_state *state)
1094 {
1095 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
1096 }
1097
r600_bind_ps_state(struct pipe_context * ctx,void * state)1098 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
1099 {
1100 struct r600_context *rctx = (struct r600_context *)ctx;
1101
1102 if (!state)
1103 state = rctx->dummy_pixel_shader;
1104
1105 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
1106 }
1107
r600_get_vs_info(struct r600_context * rctx)1108 static struct tgsi_shader_info *r600_get_vs_info(struct r600_context *rctx)
1109 {
1110 if (rctx->gs_shader)
1111 return &rctx->gs_shader->info;
1112 else if (rctx->tes_shader)
1113 return &rctx->tes_shader->info;
1114 else if (rctx->vs_shader)
1115 return &rctx->vs_shader->info;
1116 else
1117 return NULL;
1118 }
1119
r600_bind_vs_state(struct pipe_context * ctx,void * state)1120 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
1121 {
1122 struct r600_context *rctx = (struct r600_context *)ctx;
1123
1124 if (!state || rctx->vs_shader == state)
1125 return;
1126
1127 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
1128 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1129
1130 if (rctx->vs_shader->so.num_outputs)
1131 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
1132 }
1133
r600_bind_gs_state(struct pipe_context * ctx,void * state)1134 static void r600_bind_gs_state(struct pipe_context *ctx, void *state)
1135 {
1136 struct r600_context *rctx = (struct r600_context *)ctx;
1137
1138 if (state == rctx->gs_shader)
1139 return;
1140
1141 rctx->gs_shader = (struct r600_pipe_shader_selector *)state;
1142 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1143
1144 if (!state)
1145 return;
1146
1147 if (rctx->gs_shader->so.num_outputs)
1148 rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
1149 }
1150
r600_bind_tcs_state(struct pipe_context * ctx,void * state)1151 static void r600_bind_tcs_state(struct pipe_context *ctx, void *state)
1152 {
1153 struct r600_context *rctx = (struct r600_context *)ctx;
1154
1155 rctx->tcs_shader = (struct r600_pipe_shader_selector *)state;
1156 }
1157
r600_bind_tes_state(struct pipe_context * ctx,void * state)1158 static void r600_bind_tes_state(struct pipe_context *ctx, void *state)
1159 {
1160 struct r600_context *rctx = (struct r600_context *)ctx;
1161
1162 if (state == rctx->tes_shader)
1163 return;
1164
1165 rctx->tes_shader = (struct r600_pipe_shader_selector *)state;
1166 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1167
1168 if (!state)
1169 return;
1170
1171 if (rctx->tes_shader->so.num_outputs)
1172 rctx->b.streamout.stride_in_dw = rctx->tes_shader->so.stride;
1173 }
1174
r600_delete_shader_selector(struct pipe_context * ctx,struct r600_pipe_shader_selector * sel)1175 void r600_delete_shader_selector(struct pipe_context *ctx,
1176 struct r600_pipe_shader_selector *sel)
1177 {
1178 struct r600_pipe_shader *p = sel->current, *c;
1179 while (p) {
1180 c = p->next_variant;
1181 r600_pipe_shader_destroy(ctx, p);
1182 free(p);
1183 p = c;
1184 }
1185
1186 if (sel->ir_type == PIPE_SHADER_IR_TGSI) {
1187 free(sel->tokens);
1188 /* We might have converted the TGSI shader to a NIR shader */
1189 if (sel->nir)
1190 ralloc_free(sel->nir);
1191 }
1192 else if (sel->ir_type == PIPE_SHADER_IR_NIR)
1193 ralloc_free(sel->nir);
1194 free(sel);
1195 }
1196
1197
r600_delete_ps_state(struct pipe_context * ctx,void * state)1198 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
1199 {
1200 struct r600_context *rctx = (struct r600_context *)ctx;
1201 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1202
1203 if (rctx->ps_shader == sel) {
1204 rctx->ps_shader = NULL;
1205 }
1206
1207 r600_delete_shader_selector(ctx, sel);
1208 }
1209
r600_delete_vs_state(struct pipe_context * ctx,void * state)1210 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
1211 {
1212 struct r600_context *rctx = (struct r600_context *)ctx;
1213 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1214
1215 if (rctx->vs_shader == sel) {
1216 rctx->vs_shader = NULL;
1217 }
1218
1219 r600_delete_shader_selector(ctx, sel);
1220 }
1221
1222
r600_delete_gs_state(struct pipe_context * ctx,void * state)1223 static void r600_delete_gs_state(struct pipe_context *ctx, void *state)
1224 {
1225 struct r600_context *rctx = (struct r600_context *)ctx;
1226 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1227
1228 if (rctx->gs_shader == sel) {
1229 rctx->gs_shader = NULL;
1230 }
1231
1232 r600_delete_shader_selector(ctx, sel);
1233 }
1234
r600_delete_tcs_state(struct pipe_context * ctx,void * state)1235 static void r600_delete_tcs_state(struct pipe_context *ctx, void *state)
1236 {
1237 struct r600_context *rctx = (struct r600_context *)ctx;
1238 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1239
1240 if (rctx->tcs_shader == sel) {
1241 rctx->tcs_shader = NULL;
1242 }
1243
1244 r600_delete_shader_selector(ctx, sel);
1245 }
1246
r600_delete_tes_state(struct pipe_context * ctx,void * state)1247 static void r600_delete_tes_state(struct pipe_context *ctx, void *state)
1248 {
1249 struct r600_context *rctx = (struct r600_context *)ctx;
1250 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1251
1252 if (rctx->tes_shader == sel) {
1253 rctx->tes_shader = NULL;
1254 }
1255
1256 r600_delete_shader_selector(ctx, sel);
1257 }
1258
r600_constant_buffers_dirty(struct r600_context * rctx,struct r600_constbuf_state * state)1259 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
1260 {
1261 if (state->dirty_mask) {
1262 state->atom.num_dw = rctx->b.gfx_level >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
1263 : util_bitcount(state->dirty_mask)*19;
1264 r600_mark_atom_dirty(rctx, &state->atom);
1265 }
1266 }
1267
r600_set_constant_buffer(struct pipe_context * ctx,enum pipe_shader_type shader,uint index,bool take_ownership,const struct pipe_constant_buffer * input)1268 static void r600_set_constant_buffer(struct pipe_context *ctx,
1269 enum pipe_shader_type shader, uint index,
1270 bool take_ownership,
1271 const struct pipe_constant_buffer *input)
1272 {
1273 struct r600_context *rctx = (struct r600_context *)ctx;
1274 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
1275 struct pipe_constant_buffer *cb;
1276 const uint8_t *ptr;
1277
1278 /* Note that the gallium frontend can unbind constant buffers by
1279 * passing NULL here.
1280 */
1281 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
1282 state->enabled_mask &= ~(1 << index);
1283 state->dirty_mask &= ~(1 << index);
1284 pipe_resource_reference(&state->cb[index].buffer, NULL);
1285 return;
1286 }
1287
1288 cb = &state->cb[index];
1289 cb->buffer_size = input->buffer_size;
1290
1291 ptr = input->user_buffer;
1292
1293 if (ptr) {
1294 /* Upload the user buffer. */
1295 if (R600_BIG_ENDIAN) {
1296 uint32_t *tmpPtr;
1297 unsigned i, size = input->buffer_size;
1298
1299 if (!(tmpPtr = malloc(size))) {
1300 R600_ERR("Failed to allocate BE swap buffer.\n");
1301 return;
1302 }
1303
1304 for (i = 0; i < size / 4; ++i) {
1305 tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
1306 }
1307
1308 u_upload_data(ctx->stream_uploader, 0, size, 256,
1309 tmpPtr, &cb->buffer_offset, &cb->buffer);
1310 free(tmpPtr);
1311 } else {
1312 u_upload_data(ctx->stream_uploader, 0,
1313 input->buffer_size, 256, ptr,
1314 &cb->buffer_offset, &cb->buffer);
1315 }
1316 /* account it in gtt */
1317 rctx->b.gtt += input->buffer_size;
1318 } else {
1319 /* Setup the hw buffer. */
1320 cb->buffer_offset = input->buffer_offset;
1321 if (take_ownership) {
1322 pipe_resource_reference(&cb->buffer, NULL);
1323 cb->buffer = input->buffer;
1324 } else {
1325 pipe_resource_reference(&cb->buffer, input->buffer);
1326 }
1327 r600_context_add_resource_size(ctx, input->buffer);
1328 }
1329
1330 state->enabled_mask |= 1 << index;
1331 state->dirty_mask |= 1 << index;
1332 r600_constant_buffers_dirty(rctx, state);
1333 }
1334
r600_set_sample_mask(struct pipe_context * pipe,unsigned sample_mask)1335 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1336 {
1337 struct r600_context *rctx = (struct r600_context*)pipe;
1338
1339 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1340 return;
1341
1342 rctx->sample_mask.sample_mask = sample_mask;
1343 r600_mark_atom_dirty(rctx, &rctx->sample_mask.atom);
1344 }
1345
r600_update_driver_const_buffers(struct r600_context * rctx,bool compute_only)1346 void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_only)
1347 {
1348 int sh, size;
1349 void *ptr;
1350 struct pipe_constant_buffer cb;
1351 int start, end;
1352
1353 start = compute_only ? PIPE_SHADER_COMPUTE : 0;
1354 end = compute_only ? PIPE_SHADER_TYPES : PIPE_SHADER_COMPUTE;
1355
1356 int last_vertex_stage = PIPE_SHADER_VERTEX;
1357 if (rctx->tes_shader)
1358 last_vertex_stage = PIPE_SHADER_TESS_EVAL;
1359 if (rctx->gs_shader)
1360 last_vertex_stage = PIPE_SHADER_GEOMETRY;
1361
1362 for (sh = start; sh < end; sh++) {
1363 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[sh];
1364 if (!info->vs_ucp_dirty &&
1365 !info->texture_const_dirty &&
1366 !info->ps_sample_pos_dirty &&
1367 !info->tcs_default_levels_dirty &&
1368 !info->cs_block_grid_size_dirty)
1369 continue;
1370
1371 ptr = info->constants;
1372 size = info->alloc_size;
1373 if (info->vs_ucp_dirty) {
1374 assert(sh == PIPE_SHADER_VERTEX ||
1375 sh == PIPE_SHADER_GEOMETRY ||
1376 sh == PIPE_SHADER_TESS_EVAL);
1377 if (!size) {
1378 ptr = rctx->clip_state.state.ucp;
1379 size = R600_UCP_SIZE;
1380 } else {
1381 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1382 }
1383 info->vs_ucp_dirty = false;
1384 }
1385
1386 else if (info->ps_sample_pos_dirty) {
1387 assert(sh == PIPE_SHADER_FRAGMENT);
1388 if (!size) {
1389 ptr = rctx->sample_positions;
1390 size = R600_UCP_SIZE;
1391 } else {
1392 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1393 }
1394 info->ps_sample_pos_dirty = false;
1395 }
1396
1397 else if (info->cs_block_grid_size_dirty) {
1398 assert(sh == PIPE_SHADER_COMPUTE);
1399 if (!size) {
1400 ptr = rctx->cs_block_grid_sizes;
1401 size = R600_CS_BLOCK_GRID_SIZE;
1402 } else {
1403 memcpy(ptr, rctx->cs_block_grid_sizes, R600_CS_BLOCK_GRID_SIZE);
1404 }
1405 info->cs_block_grid_size_dirty = false;
1406 }
1407
1408 else if (info->tcs_default_levels_dirty) {
1409 /*
1410 * We'd only really need this for default tcs shader.
1411 */
1412 assert(sh == PIPE_SHADER_TESS_CTRL);
1413 if (!size) {
1414 ptr = rctx->tess_state;
1415 size = R600_TCS_DEFAULT_LEVELS_SIZE;
1416 } else {
1417 memcpy(ptr, rctx->tess_state, R600_TCS_DEFAULT_LEVELS_SIZE);
1418 }
1419 info->tcs_default_levels_dirty = false;
1420 }
1421
1422 if (info->texture_const_dirty) {
1423 assert (ptr);
1424 assert (size);
1425 if (sh == last_vertex_stage)
1426 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1427 if (sh == PIPE_SHADER_FRAGMENT)
1428 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1429 if (sh == PIPE_SHADER_COMPUTE)
1430 memcpy(ptr, rctx->cs_block_grid_sizes, R600_CS_BLOCK_GRID_SIZE);
1431 if (sh == PIPE_SHADER_TESS_CTRL)
1432 memcpy(ptr, rctx->tess_state, R600_TCS_DEFAULT_LEVELS_SIZE);
1433 }
1434 info->texture_const_dirty = false;
1435
1436 cb.buffer = NULL;
1437 cb.user_buffer = ptr;
1438 cb.buffer_offset = 0;
1439 cb.buffer_size = size;
1440 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, false, &cb);
1441 pipe_resource_reference(&cb.buffer, NULL);
1442 }
1443 }
1444
r600_alloc_buf_consts(struct r600_context * rctx,int shader_type,unsigned array_size,uint32_t * base_offset)1445 static void *r600_alloc_buf_consts(struct r600_context *rctx, int shader_type,
1446 unsigned array_size, uint32_t *base_offset)
1447 {
1448 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[shader_type];
1449 if (array_size + R600_UCP_SIZE > info->alloc_size) {
1450 info->constants = realloc(info->constants, array_size + R600_UCP_SIZE);
1451 info->alloc_size = array_size + R600_UCP_SIZE;
1452 }
1453 memset(info->constants + (R600_UCP_SIZE / 4), 0, array_size);
1454 info->texture_const_dirty = true;
1455 *base_offset = R600_UCP_SIZE;
1456 return info->constants;
1457 }
1458 /*
1459 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1460 * doesn't require full swizzles it does need masking and setting alpha
1461 * to one, so we setup a set of 5 constants with the masks + alpha value
1462 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1463 * then OR the alpha with the value given here.
1464 * We use a 6th constant to store the txq buffer size in
1465 * we use 7th slot for number of cube layers in a cube map array.
1466 */
r600_setup_buffer_constants(struct r600_context * rctx,int shader_type)1467 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1468 {
1469 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1470 int bits;
1471 uint32_t array_size;
1472 int i, j;
1473 uint32_t *constants;
1474 uint32_t base_offset;
1475 if (!samplers->views.dirty_buffer_constants)
1476 return;
1477
1478 samplers->views.dirty_buffer_constants = FALSE;
1479
1480 bits = util_last_bit(samplers->views.enabled_mask);
1481 array_size = bits * 8 * sizeof(uint32_t);
1482
1483 constants = r600_alloc_buf_consts(rctx, shader_type, array_size, &base_offset);
1484
1485 for (i = 0; i < bits; i++) {
1486 if (samplers->views.enabled_mask & (1 << i)) {
1487 int offset = (base_offset / 4) + i * 8;
1488 const struct util_format_description *desc;
1489 desc = util_format_description(samplers->views.views[i]->base.format);
1490
1491 for (j = 0; j < 4; j++)
1492 if (j < desc->nr_channels)
1493 constants[offset+j] = 0xffffffff;
1494 else
1495 constants[offset+j] = 0x0;
1496 if (desc->nr_channels < 4) {
1497 if (desc->channel[0].pure_integer)
1498 constants[offset+4] = 1;
1499 else
1500 constants[offset+4] = fui(1.0);
1501 } else
1502 constants[offset + 4] = 0;
1503
1504 constants[offset + 5] = samplers->views.views[i]->base.u.buf.size /
1505 util_format_get_blocksize(samplers->views.views[i]->base.format);
1506 constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
1507 }
1508 }
1509
1510 }
1511
1512 /* On evergreen we store one value
1513 * 1. number of cube layers in a cube map array.
1514 */
eg_setup_buffer_constants(struct r600_context * rctx,int shader_type)1515 void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1516 {
1517 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1518 struct r600_image_state *images = NULL;
1519 int bits, sview_bits, img_bits;
1520 uint32_t array_size;
1521 int i;
1522 uint32_t *constants;
1523 uint32_t base_offset;
1524
1525 if (shader_type == PIPE_SHADER_FRAGMENT) {
1526 images = &rctx->fragment_images;
1527 } else if (shader_type == PIPE_SHADER_COMPUTE) {
1528 images = &rctx->compute_images;
1529 }
1530
1531 if (!samplers->views.dirty_buffer_constants &&
1532 !(images && images->dirty_buffer_constants))
1533 return;
1534
1535 if (images)
1536 images->dirty_buffer_constants = FALSE;
1537 samplers->views.dirty_buffer_constants = FALSE;
1538
1539 bits = sview_bits = util_last_bit(samplers->views.enabled_mask);
1540 if (images)
1541 bits += util_last_bit(images->enabled_mask);
1542 img_bits = bits;
1543
1544 array_size = bits * sizeof(uint32_t);
1545
1546 constants = r600_alloc_buf_consts(rctx, shader_type, array_size,
1547 &base_offset);
1548
1549 for (i = 0; i < sview_bits; i++) {
1550 if (samplers->views.enabled_mask & (1 << i)) {
1551 uint32_t offset = (base_offset / 4) + i;
1552 constants[offset] = samplers->views.views[i]->base.texture->array_size / 6;
1553 }
1554 }
1555 if (images) {
1556 for (i = sview_bits; i < img_bits; i++) {
1557 int idx = i - sview_bits;
1558 if (images->enabled_mask & (1 << idx)) {
1559 uint32_t offset = (base_offset / 4) + i;
1560 constants[offset] = images->views[idx].base.resource->array_size / 6;
1561 }
1562 }
1563 }
1564 }
1565
1566 /* set sample xy locations as array of fragment shader constants */
r600_set_sample_locations_constant_buffer(struct r600_context * rctx)1567 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx)
1568 {
1569 struct pipe_context *ctx = &rctx->b.b;
1570
1571 assert(rctx->framebuffer.nr_samples < R600_UCP_SIZE);
1572 assert(rctx->framebuffer.nr_samples <= ARRAY_SIZE(rctx->sample_positions)/4);
1573
1574 memset(rctx->sample_positions, 0, 4 * 4 * 16);
1575 for (unsigned i = 0; i < rctx->framebuffer.nr_samples; i++) {
1576 ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &rctx->sample_positions[4*i]);
1577 /* Also fill in center-zeroed positions used for interpolateAtSample */
1578 rctx->sample_positions[4*i + 2] = rctx->sample_positions[4*i + 0] - 0.5f;
1579 rctx->sample_positions[4*i + 3] = rctx->sample_positions[4*i + 1] - 0.5f;
1580 }
1581
1582 rctx->driver_consts[PIPE_SHADER_FRAGMENT].ps_sample_pos_dirty = true;
1583 }
1584
update_shader_atom(struct pipe_context * ctx,struct r600_shader_state * state,struct r600_pipe_shader * shader)1585 static void update_shader_atom(struct pipe_context *ctx,
1586 struct r600_shader_state *state,
1587 struct r600_pipe_shader *shader)
1588 {
1589 struct r600_context *rctx = (struct r600_context *)ctx;
1590
1591 state->shader = shader;
1592 if (shader) {
1593 state->atom.num_dw = shader->command_buffer.num_dw;
1594 r600_context_add_resource_size(ctx, (struct pipe_resource *)shader->bo);
1595 } else {
1596 state->atom.num_dw = 0;
1597 }
1598 r600_mark_atom_dirty(rctx, &state->atom);
1599 }
1600
update_gs_block_state(struct r600_context * rctx,unsigned enable)1601 static void update_gs_block_state(struct r600_context *rctx, unsigned enable)
1602 {
1603 if (rctx->shader_stages.geom_enable != enable) {
1604 rctx->shader_stages.geom_enable = enable;
1605 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1606 }
1607
1608 if (rctx->gs_rings.enable != enable) {
1609 rctx->gs_rings.enable = enable;
1610 r600_mark_atom_dirty(rctx, &rctx->gs_rings.atom);
1611
1612 if (enable && !rctx->gs_rings.esgs_ring.buffer) {
1613 unsigned size = 0x1C000;
1614 rctx->gs_rings.esgs_ring.buffer =
1615 pipe_buffer_create(rctx->b.b.screen, 0,
1616 PIPE_USAGE_DEFAULT, size);
1617 rctx->gs_rings.esgs_ring.buffer_size = size;
1618
1619 size = 0x4000000;
1620
1621 rctx->gs_rings.gsvs_ring.buffer =
1622 pipe_buffer_create(rctx->b.b.screen, 0,
1623 PIPE_USAGE_DEFAULT, size);
1624 rctx->gs_rings.gsvs_ring.buffer_size = size;
1625 }
1626
1627 if (enable) {
1628 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1629 R600_GS_RING_CONST_BUFFER, false, &rctx->gs_rings.esgs_ring);
1630 if (rctx->tes_shader) {
1631 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1632 R600_GS_RING_CONST_BUFFER, false, &rctx->gs_rings.gsvs_ring);
1633 } else {
1634 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1635 R600_GS_RING_CONST_BUFFER, false, &rctx->gs_rings.gsvs_ring);
1636 }
1637 } else {
1638 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1639 R600_GS_RING_CONST_BUFFER, false, NULL);
1640 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1641 R600_GS_RING_CONST_BUFFER, false, NULL);
1642 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1643 R600_GS_RING_CONST_BUFFER, false, NULL);
1644 }
1645 }
1646 }
1647
r600_update_clip_state(struct r600_context * rctx,struct r600_pipe_shader * current)1648 static void r600_update_clip_state(struct r600_context *rctx,
1649 struct r600_pipe_shader *current)
1650 {
1651 if (current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1652 current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1653 current->shader.cull_dist_write != rctx->clip_misc_state.cull_dist_write ||
1654 current->shader.vs_position_window_space != rctx->clip_misc_state.clip_disable ||
1655 current->shader.vs_out_viewport != rctx->clip_misc_state.vs_out_viewport) {
1656 rctx->clip_misc_state.pa_cl_vs_out_cntl = current->pa_cl_vs_out_cntl;
1657 rctx->clip_misc_state.clip_dist_write = current->shader.clip_dist_write;
1658 rctx->clip_misc_state.cull_dist_write = current->shader.cull_dist_write;
1659 rctx->clip_misc_state.clip_disable = current->shader.vs_position_window_space;
1660 rctx->clip_misc_state.vs_out_viewport = current->shader.vs_out_viewport;
1661 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
1662 }
1663 }
1664
r600_generate_fixed_func_tcs(struct r600_context * rctx)1665 static void r600_generate_fixed_func_tcs(struct r600_context *rctx)
1666 {
1667 struct ureg_src const0, const1;
1668 struct ureg_dst tessouter, tessinner;
1669 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
1670
1671 if (!ureg)
1672 return; /* if we get here, we're screwed */
1673
1674 assert(!rctx->fixed_func_tcs_shader);
1675
1676 ureg_DECL_constant2D(ureg, 0, 1, R600_BUFFER_INFO_CONST_BUFFER);
1677 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1678 R600_BUFFER_INFO_CONST_BUFFER);
1679 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1680 R600_BUFFER_INFO_CONST_BUFFER);
1681
1682 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1683 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1684
1685 ureg_MOV(ureg, tessouter, const0);
1686 ureg_MOV(ureg, tessinner, const1);
1687 ureg_END(ureg);
1688
1689 rctx->fixed_func_tcs_shader =
1690 ureg_create_shader_and_destroy(ureg, &rctx->b.b);
1691 }
1692
r600_update_compressed_resource_state(struct r600_context * rctx,bool compute_only)1693 void r600_update_compressed_resource_state(struct r600_context *rctx, bool compute_only)
1694 {
1695 unsigned i;
1696 unsigned counter;
1697
1698 counter = p_atomic_read(&rctx->screen->b.compressed_colortex_counter);
1699 if (counter != rctx->b.last_compressed_colortex_counter) {
1700 rctx->b.last_compressed_colortex_counter = counter;
1701
1702 if (compute_only) {
1703 r600_update_compressed_colortex_mask(&rctx->samplers[PIPE_SHADER_COMPUTE].views);
1704 } else {
1705 for (i = 0; i < PIPE_SHADER_TYPES; ++i) {
1706 r600_update_compressed_colortex_mask(&rctx->samplers[i].views);
1707 }
1708 }
1709 if (!compute_only)
1710 r600_update_compressed_colortex_mask_images(&rctx->fragment_images);
1711 r600_update_compressed_colortex_mask_images(&rctx->compute_images);
1712 }
1713
1714 /* Decompress textures if needed. */
1715 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1716 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1717
1718 if (compute_only)
1719 if (i != PIPE_SHADER_COMPUTE)
1720 continue;
1721 if (views->compressed_depthtex_mask) {
1722 r600_decompress_depth_textures(rctx, views);
1723 }
1724 if (views->compressed_colortex_mask) {
1725 r600_decompress_color_textures(rctx, views);
1726 }
1727 }
1728
1729 {
1730 struct r600_image_state *istate;
1731
1732 if (!compute_only) {
1733 istate = &rctx->fragment_images;
1734 if (istate->compressed_depthtex_mask)
1735 r600_decompress_depth_images(rctx, istate);
1736 if (istate->compressed_colortex_mask)
1737 r600_decompress_color_images(rctx, istate);
1738 }
1739
1740 istate = &rctx->compute_images;
1741 if (istate->compressed_depthtex_mask)
1742 r600_decompress_depth_images(rctx, istate);
1743 if (istate->compressed_colortex_mask)
1744 r600_decompress_color_images(rctx, istate);
1745 }
1746 }
1747
1748 /* update MEM_SCRATCH buffers if needed */
r600_setup_scratch_area_for_shader(struct r600_context * rctx,struct r600_pipe_shader * shader,struct r600_scratch_buffer * scratch,unsigned ring_base_reg,unsigned item_size_reg,unsigned ring_size_reg)1749 void r600_setup_scratch_area_for_shader(struct r600_context *rctx,
1750 struct r600_pipe_shader *shader, struct r600_scratch_buffer *scratch,
1751 unsigned ring_base_reg, unsigned item_size_reg, unsigned ring_size_reg)
1752 {
1753 unsigned num_ses = rctx->screen->b.info.max_se;
1754 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
1755 unsigned nthreads = 128;
1756
1757 unsigned itemsize = shader->scratch_space_needed * 4;
1758 unsigned size = align(itemsize * nthreads * num_pipes * num_ses * 4, 256);
1759
1760 if (scratch->dirty ||
1761 unlikely(shader->scratch_space_needed != scratch->item_size ||
1762 size > scratch->size)) {
1763 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1764
1765 scratch->dirty = false;
1766
1767 if (size > scratch->size) {
1768 // Release prior one if any
1769 if (scratch->buffer) {
1770 pipe_resource_reference((struct pipe_resource**)&scratch->buffer, NULL);
1771 }
1772
1773 scratch->buffer = (struct r600_resource *)pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1774 PIPE_USAGE_DEFAULT, size);
1775 if (scratch->buffer) {
1776 scratch->size = size;
1777 }
1778 }
1779
1780 scratch->item_size = shader->scratch_space_needed;
1781
1782 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1783 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1784 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1785
1786 // multi-SE chips need programming per SE
1787 for (unsigned se = 0; se < num_ses; se++) {
1788 struct r600_resource *rbuffer = scratch->buffer;
1789 unsigned size_per_se = size / num_ses;
1790
1791 // Direct to particular SE
1792 if (num_ses > 1) {
1793 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX,
1794 S_0802C_INSTANCE_INDEX(0) |
1795 S_0802C_SE_INDEX(se) |
1796 S_0802C_INSTANCE_BROADCAST_WRITES(1) |
1797 S_0802C_SE_BROADCAST_WRITES(0));
1798 }
1799
1800 radeon_set_config_reg(cs, ring_base_reg, (rbuffer->gpu_address + size_per_se * se) >> 8);
1801 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1802 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1803 RADEON_USAGE_READWRITE |
1804 RADEON_PRIO_SCRATCH_BUFFER));
1805 radeon_set_context_reg(cs, item_size_reg, itemsize);
1806 radeon_set_config_reg(cs, ring_size_reg, size_per_se >> 8);
1807 }
1808
1809 // Restore broadcast mode
1810 if (num_ses > 1) {
1811 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX,
1812 S_0802C_INSTANCE_INDEX(0) |
1813 S_0802C_SE_INDEX(0) |
1814 S_0802C_INSTANCE_BROADCAST_WRITES(1) |
1815 S_0802C_SE_BROADCAST_WRITES(1));
1816 }
1817
1818 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1819 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1820 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1821 }
1822 }
1823
r600_setup_scratch_buffers(struct r600_context * rctx)1824 void r600_setup_scratch_buffers(struct r600_context *rctx) {
1825 static const struct {
1826 unsigned ring_base;
1827 unsigned item_size;
1828 unsigned ring_size;
1829 } regs[R600_NUM_HW_STAGES] = {
1830 [R600_HW_STAGE_PS] = { R_008C68_SQ_PSTMP_RING_BASE, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, R_008C6C_SQ_PSTMP_RING_SIZE },
1831 [R600_HW_STAGE_VS] = { R_008C60_SQ_VSTMP_RING_BASE, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, R_008C64_SQ_VSTMP_RING_SIZE },
1832 [R600_HW_STAGE_GS] = { R_008C58_SQ_GSTMP_RING_BASE, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, R_008C5C_SQ_GSTMP_RING_SIZE },
1833 [R600_HW_STAGE_ES] = { R_008C50_SQ_ESTMP_RING_BASE, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, R_008C54_SQ_ESTMP_RING_SIZE }
1834 };
1835
1836 for (unsigned i = 0; i < R600_NUM_HW_STAGES; i++) {
1837 struct r600_pipe_shader *stage = rctx->hw_shader_stages[i].shader;
1838
1839 if (stage && unlikely(stage->scratch_space_needed)) {
1840 r600_setup_scratch_area_for_shader(rctx, stage,
1841 &rctx->scratch_buffers[i], regs[i].ring_base, regs[i].item_size, regs[i].ring_size);
1842 }
1843 }
1844 }
1845
1846 #define SELECT_SHADER_OR_FAIL(x) do { \
1847 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty, false); \
1848 if (unlikely(!rctx->x##_shader->current)) \
1849 return false; \
1850 } while(0)
1851
1852 #define UPDATE_SHADER(hw, sw) do { \
1853 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1854 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1855 } while(0)
1856
1857 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1858 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1859 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1860 clip_so_current = rctx->sw##_shader->current; \
1861 } \
1862 } while(0)
1863
1864 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1865 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1866 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1867 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1868 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1869 } \
1870 } while(0)
1871
1872 #define SET_NULL_SHADER(hw) do { \
1873 if (rctx->hw_shader_stages[(hw)].shader) \
1874 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1875 } while (0)
1876
r600_update_derived_state(struct r600_context * rctx)1877 static bool r600_update_derived_state(struct r600_context *rctx)
1878 {
1879 struct pipe_context * ctx = (struct pipe_context*)rctx;
1880 bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
1881 bool tcs_dirty = false, tes_dirty = false, fixed_func_tcs_dirty = false;
1882 bool blend_disable;
1883 bool need_buf_const;
1884 struct r600_pipe_shader *clip_so_current = NULL;
1885
1886 if (!rctx->blitter->running)
1887 r600_update_compressed_resource_state(rctx, false);
1888
1889 SELECT_SHADER_OR_FAIL(ps);
1890
1891 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1892
1893 update_gs_block_state(rctx, rctx->gs_shader != NULL);
1894
1895 if (rctx->gs_shader)
1896 SELECT_SHADER_OR_FAIL(gs);
1897
1898 /* Hull Shader */
1899 if (rctx->tcs_shader) {
1900 SELECT_SHADER_OR_FAIL(tcs);
1901
1902 UPDATE_SHADER(EG_HW_STAGE_HS, tcs);
1903 } else if (rctx->tes_shader) {
1904 if (!rctx->fixed_func_tcs_shader) {
1905 r600_generate_fixed_func_tcs(rctx);
1906 if (!rctx->fixed_func_tcs_shader)
1907 return false;
1908
1909 }
1910 SELECT_SHADER_OR_FAIL(fixed_func_tcs);
1911
1912 UPDATE_SHADER(EG_HW_STAGE_HS, fixed_func_tcs);
1913 } else
1914 SET_NULL_SHADER(EG_HW_STAGE_HS);
1915
1916 if (rctx->tes_shader) {
1917 SELECT_SHADER_OR_FAIL(tes);
1918 }
1919
1920 SELECT_SHADER_OR_FAIL(vs);
1921
1922 if (rctx->gs_shader) {
1923 if (!rctx->shader_stages.geom_enable) {
1924 rctx->shader_stages.geom_enable = true;
1925 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1926 }
1927
1928 /* gs_shader provides GS and VS (copy shader) */
1929 UPDATE_SHADER_GS(R600_HW_STAGE_GS, R600_HW_STAGE_VS, gs);
1930
1931 /* vs_shader is used as ES */
1932
1933 if (rctx->tes_shader) {
1934 /* VS goes to LS, TES goes to ES */
1935 UPDATE_SHADER(R600_HW_STAGE_ES, tes);
1936 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1937 } else {
1938 /* vs_shader is used as ES */
1939 UPDATE_SHADER(R600_HW_STAGE_ES, vs);
1940 SET_NULL_SHADER(EG_HW_STAGE_LS);
1941 }
1942 } else {
1943 if (unlikely(rctx->hw_shader_stages[R600_HW_STAGE_GS].shader)) {
1944 SET_NULL_SHADER(R600_HW_STAGE_GS);
1945 SET_NULL_SHADER(R600_HW_STAGE_ES);
1946 rctx->shader_stages.geom_enable = false;
1947 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1948 }
1949
1950 if (rctx->tes_shader) {
1951 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1952 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, tes);
1953 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1954 } else {
1955 SET_NULL_SHADER(EG_HW_STAGE_LS);
1956 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, vs);
1957 }
1958 }
1959
1960 /*
1961 * XXX: I believe there's some fatal flaw in the dirty state logic when
1962 * enabling/disabling tes.
1963 * VS/ES share all buffer/resource/sampler slots. If TES is enabled,
1964 * it will therefore overwrite the VS slots. If it now gets disabled,
1965 * the VS needs to rebind all buffer/resource/sampler slots - not only
1966 * has TES overwritten the corresponding slots, but when the VS was
1967 * operating as LS the things with correpsonding dirty bits got bound
1968 * to LS slots and won't reflect what is dirty as VS stage even if the
1969 * TES didn't overwrite it. The story for re-enabled TES is similar.
1970 * In any case, we're not allowed to submit any TES state when
1971 * TES is disabled (the gallium frontend may not do this but this looks
1972 * like an optimization to me, not something which can be relied on).
1973 */
1974
1975 /* Update clip misc state. */
1976 if (clip_so_current) {
1977 r600_update_clip_state(rctx, clip_so_current);
1978 rctx->b.streamout.enabled_stream_buffers_mask = clip_so_current->enabled_stream_buffers_mask;
1979 }
1980
1981 if (unlikely(ps_dirty || rctx->hw_shader_stages[R600_HW_STAGE_PS].shader != rctx->ps_shader->current ||
1982 rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
1983 rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
1984
1985 bool msaa = rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0;
1986 if (unlikely(rctx->ps_shader &&
1987 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1988 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade) ||
1989 (msaa != rctx->ps_shader->current->msaa)))) {
1990
1991 if (rctx->b.gfx_level >= EVERGREEN)
1992 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1993 else
1994 r600_update_ps_state(ctx, rctx->ps_shader->current);
1995 }
1996
1997 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs ||
1998 rctx->cb_misc_state.ps_color_export_mask != rctx->ps_shader->current->ps_color_export_mask) {
1999 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
2000 rctx->cb_misc_state.ps_color_export_mask = rctx->ps_shader->current->ps_color_export_mask;
2001 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2002 }
2003
2004 if (rctx->b.gfx_level <= R700) {
2005 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
2006
2007 if (rctx->cb_misc_state.multiwrite != multiwrite) {
2008 rctx->cb_misc_state.multiwrite = multiwrite;
2009 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2010 }
2011 }
2012
2013 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
2014 }
2015 UPDATE_SHADER(R600_HW_STAGE_PS, ps);
2016
2017 if (rctx->b.gfx_level >= EVERGREEN) {
2018 evergreen_update_db_shader_control(rctx);
2019 } else {
2020 r600_update_db_shader_control(rctx);
2021 }
2022
2023 /* For each shader stage that needs to spill, set up buffer for MEM_SCRATCH */
2024 if (rctx->b.gfx_level >= EVERGREEN) {
2025 evergreen_setup_scratch_buffers(rctx);
2026 } else {
2027 r600_setup_scratch_buffers(rctx);
2028 }
2029
2030 /* on R600 we stuff masks + txq info into one constant buffer */
2031 /* on evergreen we only need a txq info one */
2032 if (rctx->ps_shader) {
2033 need_buf_const = rctx->ps_shader->current->shader.uses_tex_buffers || rctx->ps_shader->current->shader.has_txq_cube_array_z_comp;
2034 if (need_buf_const) {
2035 if (rctx->b.gfx_level < EVERGREEN)
2036 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
2037 else
2038 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
2039 }
2040 }
2041
2042 if (rctx->vs_shader) {
2043 need_buf_const = rctx->vs_shader->current->shader.uses_tex_buffers || rctx->vs_shader->current->shader.has_txq_cube_array_z_comp;
2044 if (need_buf_const) {
2045 if (rctx->b.gfx_level < EVERGREEN)
2046 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
2047 else
2048 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
2049 }
2050 }
2051
2052 if (rctx->gs_shader) {
2053 need_buf_const = rctx->gs_shader->current->shader.uses_tex_buffers || rctx->gs_shader->current->shader.has_txq_cube_array_z_comp;
2054 if (need_buf_const) {
2055 if (rctx->b.gfx_level < EVERGREEN)
2056 r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
2057 else
2058 eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
2059 }
2060 }
2061
2062 if (rctx->tes_shader) {
2063 assert(rctx->b.gfx_level >= EVERGREEN);
2064 need_buf_const = rctx->tes_shader->current->shader.uses_tex_buffers ||
2065 rctx->tes_shader->current->shader.has_txq_cube_array_z_comp;
2066 if (need_buf_const) {
2067 eg_setup_buffer_constants(rctx, PIPE_SHADER_TESS_EVAL);
2068 }
2069 if (rctx->tcs_shader) {
2070 need_buf_const = rctx->tcs_shader->current->shader.uses_tex_buffers ||
2071 rctx->tcs_shader->current->shader.has_txq_cube_array_z_comp;
2072 if (need_buf_const) {
2073 eg_setup_buffer_constants(rctx, PIPE_SHADER_TESS_CTRL);
2074 }
2075 }
2076 }
2077
2078 r600_update_driver_const_buffers(rctx, false);
2079
2080 if (rctx->b.gfx_level < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
2081 if (!r600_adjust_gprs(rctx)) {
2082 /* discard rendering */
2083 return false;
2084 }
2085 }
2086
2087 if (rctx->b.gfx_level == EVERGREEN) {
2088 if (!evergreen_adjust_gprs(rctx)) {
2089 /* discard rendering */
2090 return false;
2091 }
2092 }
2093
2094 blend_disable = (rctx->dual_src_blend &&
2095 rctx->ps_shader->current->nr_ps_color_outputs < 2);
2096
2097 if (blend_disable != rctx->force_blend_disable) {
2098 rctx->force_blend_disable = blend_disable;
2099 r600_bind_blend_state_internal(rctx,
2100 rctx->blend_state.cso,
2101 blend_disable);
2102 }
2103
2104 return true;
2105 }
2106
r600_emit_clip_misc_state(struct r600_context * rctx,struct r600_atom * atom)2107 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2108 {
2109 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2110 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
2111
2112 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2113 state->pa_cl_clip_cntl |
2114 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
2115 S_028810_CLIP_DISABLE(state->clip_disable));
2116 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2117 state->pa_cl_vs_out_cntl |
2118 (state->clip_plane_enable & state->clip_dist_write) |
2119 (state->cull_dist_write << 8));
2120 /* reuse needs to be set off if we write oViewport */
2121 if (rctx->b.gfx_level >= EVERGREEN)
2122 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2123 S_028AB4_REUSE_OFF(state->vs_out_viewport));
2124 }
2125
2126 /* rast_prim is the primitive type after GS. */
r600_emit_rasterizer_prim_state(struct r600_context * rctx)2127 static inline void r600_emit_rasterizer_prim_state(struct r600_context *rctx)
2128 {
2129 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2130 enum pipe_prim_type rast_prim = rctx->current_rast_prim;
2131
2132 /* Skip this if not rendering lines. */
2133 if (rast_prim != PIPE_PRIM_LINES &&
2134 rast_prim != PIPE_PRIM_LINE_LOOP &&
2135 rast_prim != PIPE_PRIM_LINE_STRIP &&
2136 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
2137 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
2138 return;
2139
2140 if (rast_prim == rctx->last_rast_prim)
2141 return;
2142
2143 /* For lines, reset the stipple pattern at each primitive. Otherwise,
2144 * reset the stipple pattern at each packet (line strips, line loops).
2145 */
2146 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
2147 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2) |
2148 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
2149 rctx->last_rast_prim = rast_prim;
2150 }
2151
r600_draw_vbo(struct pipe_context * ctx,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)2152 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info,
2153 unsigned drawid_offset,
2154 const struct pipe_draw_indirect_info *indirect,
2155 const struct pipe_draw_start_count_bias *draws,
2156 unsigned num_draws)
2157 {
2158 if (num_draws > 1) {
2159 util_draw_multi(ctx, info, drawid_offset, indirect, draws, num_draws);
2160 return;
2161 }
2162
2163 struct r600_context *rctx = (struct r600_context *)ctx;
2164 struct pipe_resource *indexbuf = !info->index_size || info->has_user_indices ? NULL : info->index.resource;
2165 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2166 bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off;
2167 bool has_user_indices = info->index_size && info->has_user_indices;
2168 uint64_t mask;
2169 unsigned num_patches, dirty_tex_counter, index_offset = 0;
2170 unsigned index_size = info->index_size;
2171 int index_bias;
2172 struct r600_shader_atomic combined_atomics[8];
2173 uint8_t atomic_used_mask = 0;
2174 struct pipe_stream_output_target *count_from_so = NULL;
2175
2176 if (indirect && indirect->count_from_stream_output) {
2177 count_from_so = indirect->count_from_stream_output;
2178 indirect = NULL;
2179 }
2180
2181 if (!indirect && !draws[0].count && (index_size || !count_from_so)) {
2182 return;
2183 }
2184
2185 if (unlikely(!rctx->vs_shader)) {
2186 assert(0);
2187 return;
2188 }
2189 if (unlikely(!rctx->ps_shader &&
2190 (!rctx->rasterizer || !rctx->rasterizer->rasterizer_discard))) {
2191 assert(0);
2192 return;
2193 }
2194
2195 /* make sure that the gfx ring is only one active */
2196 if (radeon_emitted(&rctx->b.dma.cs, 0)) {
2197 rctx->b.dma.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
2198 }
2199
2200 if (rctx->cmd_buf_is_compute) {
2201 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
2202 rctx->cmd_buf_is_compute = false;
2203 }
2204
2205 /* Re-emit the framebuffer state if needed. */
2206 dirty_tex_counter = p_atomic_read(&rctx->b.screen->dirty_tex_counter);
2207 if (unlikely(dirty_tex_counter != rctx->b.last_dirty_tex_counter)) {
2208 rctx->b.last_dirty_tex_counter = dirty_tex_counter;
2209 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
2210 rctx->framebuffer.do_update_surf_dirtiness = true;
2211 }
2212
2213 if (rctx->gs_shader) {
2214 /* Determine whether the GS triangle strip adjacency fix should
2215 * be applied. Rotate every other triangle if
2216 * - triangle strips with adjacency are fed to the GS and
2217 * - primitive restart is disabled (the rotation doesn't help
2218 * when the restart occurs after an odd number of triangles).
2219 */
2220 bool gs_tri_strip_adj_fix =
2221 !rctx->tes_shader &&
2222 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
2223 !info->primitive_restart;
2224 if (gs_tri_strip_adj_fix != rctx->gs_tri_strip_adj_fix)
2225 rctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
2226 }
2227 if (!r600_update_derived_state(rctx)) {
2228 /* useless to render because current rendering command
2229 * can't be achieved
2230 */
2231 return;
2232 }
2233
2234 rctx->current_rast_prim = (rctx->gs_shader)? rctx->gs_shader->gs_output_prim
2235 : (rctx->tes_shader)? rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE]
2236 : info->mode;
2237
2238 if (rctx->b.gfx_level >= EVERGREEN) {
2239 evergreen_emit_atomic_buffer_setup_count(rctx, NULL, combined_atomics, &atomic_used_mask);
2240 }
2241
2242 if (index_size) {
2243 index_offset += draws[0].start * index_size;
2244
2245 /* Translate 8-bit indices to 16-bit. */
2246 if (unlikely(index_size == 1)) {
2247 struct pipe_resource *out_buffer = NULL;
2248 unsigned out_offset;
2249 void *ptr;
2250 unsigned start, count;
2251
2252 if (likely(!indirect)) {
2253 start = 0;
2254 count = draws[0].count;
2255 }
2256 else {
2257 /* Have to get start/count from indirect buffer, slow path ahead... */
2258 struct r600_resource *indirect_resource = (struct r600_resource *)indirect->buffer;
2259 unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource,
2260 PIPE_MAP_READ);
2261 if (data) {
2262 data += indirect->offset / sizeof(unsigned);
2263 start = data[2] * index_size;
2264 count = data[0];
2265 }
2266 else {
2267 start = 0;
2268 count = 0;
2269 }
2270 }
2271
2272 u_upload_alloc(ctx->stream_uploader, start, count * 2,
2273 256, &out_offset, &out_buffer, &ptr);
2274 if (unlikely(!ptr))
2275 return;
2276
2277 util_shorten_ubyte_elts_to_userptr(
2278 &rctx->b.b, info, 0, 0, index_offset, count, ptr);
2279
2280 indexbuf = out_buffer;
2281 index_offset = out_offset;
2282 index_size = 2;
2283 has_user_indices = false;
2284 }
2285
2286 /* Upload the index buffer.
2287 * The upload is skipped for small index counts on little-endian machines
2288 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
2289 * Indirect draws never use immediate indices.
2290 * Note: Instanced rendering in combination with immediate indices hangs. */
2291 if (has_user_indices && (R600_BIG_ENDIAN || indirect ||
2292 info->instance_count > 1 ||
2293 draws[0].count*index_size > 20)) {
2294 unsigned start_offset = draws[0].start * index_size;
2295 indexbuf = NULL;
2296 u_upload_data(ctx->stream_uploader, start_offset,
2297 draws[0].count * index_size, 256,
2298 (char*)info->index.user + start_offset,
2299 &index_offset, &indexbuf);
2300 index_offset -= start_offset;
2301 has_user_indices = false;
2302 }
2303 index_bias = draws->index_bias;
2304 } else {
2305 index_bias = indirect ? 0 : draws[0].start;
2306 }
2307
2308 /* Set the index offset and primitive restart. */
2309 bool restart_index_changed = info->primitive_restart &&
2310 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info->restart_index;
2311
2312 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info->primitive_restart ||
2313 restart_index_changed ||
2314 rctx->vgt_state.vgt_indx_offset != index_bias ||
2315 (rctx->vgt_state.last_draw_was_indirect && !indirect)) {
2316 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info->primitive_restart;
2317 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info->restart_index;
2318 rctx->vgt_state.vgt_indx_offset = index_bias;
2319 r600_mark_atom_dirty(rctx, &rctx->vgt_state.atom);
2320 }
2321
2322 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
2323 if (rctx->b.gfx_level == R600) {
2324 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
2325 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2326 }
2327
2328 if (rctx->b.gfx_level >= EVERGREEN)
2329 evergreen_setup_tess_constants(rctx, info, &num_patches);
2330
2331 /* Emit states. */
2332 r600_need_cs_space(rctx, has_user_indices ? 5 : 0, TRUE, util_bitcount(atomic_used_mask));
2333 r600_flush_emit(rctx);
2334
2335 mask = rctx->dirty_atoms;
2336 while (mask != 0) {
2337 r600_emit_atom(rctx, rctx->atoms[u_bit_scan64(&mask)]);
2338 }
2339
2340 if (rctx->b.gfx_level >= EVERGREEN) {
2341 evergreen_emit_atomic_buffer_setup(rctx, false, combined_atomics, atomic_used_mask);
2342 }
2343
2344 if (rctx->b.gfx_level == CAYMAN) {
2345 /* Copied from radeonsi. */
2346 unsigned primgroup_size = 128; /* recommended without a GS */
2347 bool ia_switch_on_eop = false;
2348 bool partial_vs_wave = false;
2349
2350 if (rctx->gs_shader)
2351 primgroup_size = 64; /* recommended with a GS */
2352
2353 if ((rctx->rasterizer && rctx->rasterizer->pa_sc_line_stipple) ||
2354 (rctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
2355 ia_switch_on_eop = true;
2356 }
2357
2358 if (r600_get_strmout_en(&rctx->b))
2359 partial_vs_wave = true;
2360
2361 radeon_set_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
2362 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
2363 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
2364 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
2365 }
2366
2367 if (rctx->b.gfx_level >= EVERGREEN) {
2368 uint32_t ls_hs_config = evergreen_get_ls_hs_config(rctx, info,
2369 num_patches);
2370
2371 evergreen_set_ls_hs_config(rctx, cs, ls_hs_config);
2372 evergreen_set_lds_alloc(rctx, cs, rctx->lds_alloc);
2373 }
2374
2375 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
2376 * even though it should have no effect on those. */
2377 if (rctx->b.gfx_level == R600 && rctx->rasterizer) {
2378 unsigned su_sc_mode_cntl = rctx->rasterizer->pa_su_sc_mode_cntl;
2379 unsigned prim = info->mode;
2380
2381 if (rctx->gs_shader) {
2382 prim = rctx->gs_shader->gs_output_prim;
2383 }
2384 prim = r600_conv_prim_to_gs_out(prim); /* decrease the number of types to 3 */
2385
2386 if (prim == V_028A6C_OUTPRIM_TYPE_POINTLIST ||
2387 prim == V_028A6C_OUTPRIM_TYPE_LINESTRIP ||
2388 info->mode == R600_PRIM_RECTANGLE_LIST) {
2389 su_sc_mode_cntl &= C_028814_CULL_FRONT;
2390 }
2391 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
2392 }
2393
2394 /* Update start instance. */
2395 if (!indirect && rctx->last_start_instance != info->start_instance) {
2396 radeon_set_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
2397 rctx->last_start_instance = info->start_instance;
2398 }
2399
2400 /* Update the primitive type. */
2401 if (rctx->last_primitive_type != info->mode) {
2402 r600_emit_rasterizer_prim_state(rctx);
2403 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
2404 r600_conv_pipe_prim(info->mode));
2405
2406 rctx->last_primitive_type = info->mode;
2407 }
2408
2409 /* Draw packets. */
2410 if (likely(!indirect)) {
2411 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2412 radeon_emit(cs, info->instance_count);
2413 } else {
2414 uint64_t va = r600_resource(indirect->buffer)->gpu_address;
2415 assert(rctx->b.gfx_level >= EVERGREEN);
2416
2417 // Invalidate so non-indirect draw calls reset this state
2418 rctx->vgt_state.last_draw_was_indirect = true;
2419 rctx->last_start_instance = -1;
2420
2421 radeon_emit(cs, PKT3(EG_PKT3_SET_BASE, 2, 0));
2422 radeon_emit(cs, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE);
2423 radeon_emit(cs, va);
2424 radeon_emit(cs, (va >> 32UL) & 0xFF);
2425
2426 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2427 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2428 (struct r600_resource*)indirect->buffer,
2429 RADEON_USAGE_READ |
2430 RADEON_PRIO_DRAW_INDIRECT));
2431 }
2432
2433 if (index_size) {
2434 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2435 radeon_emit(cs, index_size == 4 ?
2436 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
2437 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0)));
2438
2439 if (has_user_indices) {
2440 unsigned size_bytes = draws[0].count*index_size;
2441 unsigned size_dw = align(size_bytes, 4) / 4;
2442 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit));
2443 radeon_emit(cs, draws[0].count);
2444 radeon_emit(cs, V_0287F0_DI_SRC_SEL_IMMEDIATE);
2445 radeon_emit_array(cs, info->index.user + draws[0].start * index_size, size_dw);
2446 } else {
2447 uint64_t va = r600_resource(indexbuf)->gpu_address + index_offset;
2448
2449 if (likely(!indirect)) {
2450 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX, 3, render_cond_bit));
2451 radeon_emit(cs, va);
2452 radeon_emit(cs, (va >> 32UL) & 0xFF);
2453 radeon_emit(cs, draws[0].count);
2454 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
2455 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2456 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2457 (struct r600_resource*)indexbuf,
2458 RADEON_USAGE_READ |
2459 RADEON_PRIO_INDEX_BUFFER));
2460 }
2461 else {
2462 uint32_t max_size = (indexbuf->width0 - index_offset) / index_size;
2463
2464 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BASE, 1, 0));
2465 radeon_emit(cs, va);
2466 radeon_emit(cs, (va >> 32UL) & 0xFF);
2467
2468 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2469 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2470 (struct r600_resource*)indexbuf,
2471 RADEON_USAGE_READ |
2472 RADEON_PRIO_INDEX_BUFFER));
2473
2474 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, 0));
2475 radeon_emit(cs, max_size);
2476
2477 radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, render_cond_bit));
2478 radeon_emit(cs, indirect->offset);
2479 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
2480 }
2481 }
2482 } else {
2483 if (unlikely(count_from_so)) {
2484 struct r600_so_target *t = (struct r600_so_target*)count_from_so;
2485 uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
2486
2487 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
2488
2489 radeon_emit(cs, PKT3(PKT3_COPY_DW, 4, 0));
2490 radeon_emit(cs, COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG);
2491 radeon_emit(cs, va & 0xFFFFFFFFUL); /* src address lo */
2492 radeon_emit(cs, (va >> 32UL) & 0xFFUL); /* src address hi */
2493 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2); /* dst register */
2494 radeon_emit(cs, 0); /* unused */
2495
2496 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2497 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2498 t->buf_filled_size, RADEON_USAGE_READ |
2499 RADEON_PRIO_SO_FILLED_SIZE));
2500 }
2501
2502 if (likely(!indirect)) {
2503 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
2504 radeon_emit(cs, draws[0].count);
2505 }
2506 else {
2507 radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDIRECT, 1, render_cond_bit));
2508 radeon_emit(cs, indirect->offset);
2509 }
2510 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2511 (count_from_so ? S_0287F0_USE_OPAQUE(1) : 0));
2512 }
2513
2514 /* SMX returns CONTEXT_DONE too early workaround */
2515 if (rctx->b.family == CHIP_R600 ||
2516 rctx->b.family == CHIP_RV610 ||
2517 rctx->b.family == CHIP_RV630 ||
2518 rctx->b.family == CHIP_RV635) {
2519 /* if we have gs shader or streamout
2520 we need to do a wait idle after every draw */
2521 if (rctx->gs_shader || r600_get_strmout_en(&rctx->b)) {
2522 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2523 }
2524 }
2525
2526 /* ES ring rolling over at EOP - workaround */
2527 if (rctx->b.gfx_level == R600) {
2528 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2529 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT));
2530 }
2531
2532
2533 if (rctx->b.gfx_level >= EVERGREEN)
2534 evergreen_emit_atomic_buffer_save(rctx, false, combined_atomics, &atomic_used_mask);
2535
2536 if (rctx->trace_buf)
2537 eg_trace_emit(rctx);
2538
2539 if (rctx->framebuffer.do_update_surf_dirtiness) {
2540 /* Set the depth buffer as dirty. */
2541 if (rctx->framebuffer.state.zsbuf) {
2542 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
2543 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2544
2545 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2546
2547 if (rtex->surface.has_stencil)
2548 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2549 }
2550 if (rctx->framebuffer.compressed_cb_mask) {
2551 struct pipe_surface *surf;
2552 struct r600_texture *rtex;
2553 unsigned mask = rctx->framebuffer.compressed_cb_mask;
2554
2555 do {
2556 unsigned i = u_bit_scan(&mask);
2557 surf = rctx->framebuffer.state.cbufs[i];
2558 rtex = (struct r600_texture*)surf->texture;
2559
2560 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2561
2562 } while (mask);
2563 }
2564 rctx->framebuffer.do_update_surf_dirtiness = false;
2565 }
2566
2567 if (index_size && indexbuf != info->index.resource)
2568 pipe_resource_reference(&indexbuf, NULL);
2569 rctx->b.num_draw_calls++;
2570 }
2571
r600_translate_stencil_op(int s_op)2572 uint32_t r600_translate_stencil_op(int s_op)
2573 {
2574 switch (s_op) {
2575 case PIPE_STENCIL_OP_KEEP:
2576 return V_028800_STENCIL_KEEP;
2577 case PIPE_STENCIL_OP_ZERO:
2578 return V_028800_STENCIL_ZERO;
2579 case PIPE_STENCIL_OP_REPLACE:
2580 return V_028800_STENCIL_REPLACE;
2581 case PIPE_STENCIL_OP_INCR:
2582 return V_028800_STENCIL_INCR;
2583 case PIPE_STENCIL_OP_DECR:
2584 return V_028800_STENCIL_DECR;
2585 case PIPE_STENCIL_OP_INCR_WRAP:
2586 return V_028800_STENCIL_INCR_WRAP;
2587 case PIPE_STENCIL_OP_DECR_WRAP:
2588 return V_028800_STENCIL_DECR_WRAP;
2589 case PIPE_STENCIL_OP_INVERT:
2590 return V_028800_STENCIL_INVERT;
2591 default:
2592 R600_ERR("Unknown stencil op %d", s_op);
2593 assert(0);
2594 break;
2595 }
2596 return 0;
2597 }
2598
r600_translate_fill(uint32_t func)2599 uint32_t r600_translate_fill(uint32_t func)
2600 {
2601 switch(func) {
2602 case PIPE_POLYGON_MODE_FILL:
2603 return 2;
2604 case PIPE_POLYGON_MODE_LINE:
2605 return 1;
2606 case PIPE_POLYGON_MODE_POINT:
2607 return 0;
2608 default:
2609 assert(0);
2610 return 0;
2611 }
2612 }
2613
r600_tex_wrap(unsigned wrap)2614 unsigned r600_tex_wrap(unsigned wrap)
2615 {
2616 switch (wrap) {
2617 default:
2618 case PIPE_TEX_WRAP_REPEAT:
2619 return V_03C000_SQ_TEX_WRAP;
2620 case PIPE_TEX_WRAP_CLAMP:
2621 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
2622 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2623 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
2624 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2625 return V_03C000_SQ_TEX_CLAMP_BORDER;
2626 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2627 return V_03C000_SQ_TEX_MIRROR;
2628 case PIPE_TEX_WRAP_MIRROR_CLAMP:
2629 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
2630 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
2631 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2632 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
2633 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
2634 }
2635 }
2636
r600_tex_mipfilter(unsigned filter)2637 unsigned r600_tex_mipfilter(unsigned filter)
2638 {
2639 switch (filter) {
2640 case PIPE_TEX_MIPFILTER_NEAREST:
2641 return V_03C000_SQ_TEX_Z_FILTER_POINT;
2642 case PIPE_TEX_MIPFILTER_LINEAR:
2643 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
2644 default:
2645 case PIPE_TEX_MIPFILTER_NONE:
2646 return V_03C000_SQ_TEX_Z_FILTER_NONE;
2647 }
2648 }
2649
r600_tex_compare(unsigned compare)2650 unsigned r600_tex_compare(unsigned compare)
2651 {
2652 switch (compare) {
2653 default:
2654 case PIPE_FUNC_NEVER:
2655 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
2656 case PIPE_FUNC_LESS:
2657 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
2658 case PIPE_FUNC_EQUAL:
2659 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
2660 case PIPE_FUNC_LEQUAL:
2661 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2662 case PIPE_FUNC_GREATER:
2663 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
2664 case PIPE_FUNC_NOTEQUAL:
2665 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2666 case PIPE_FUNC_GEQUAL:
2667 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2668 case PIPE_FUNC_ALWAYS:
2669 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2670 }
2671 }
2672
wrap_mode_uses_border_color(unsigned wrap,bool linear_filter)2673 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2674 {
2675 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2676 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2677 (linear_filter &&
2678 (wrap == PIPE_TEX_WRAP_CLAMP ||
2679 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2680 }
2681
sampler_state_needs_border_color(const struct pipe_sampler_state * state)2682 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2683 {
2684 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2685 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2686
2687 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2688 state->border_color.ui[2] || state->border_color.ui[3]) &&
2689 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2690 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2691 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2692 }
2693
r600_emit_shader(struct r600_context * rctx,struct r600_atom * a)2694 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
2695 {
2696
2697 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2698 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader;
2699
2700 if (!shader)
2701 return;
2702
2703 r600_emit_command_buffer(cs, &shader->command_buffer);
2704 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2705 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->bo,
2706 RADEON_USAGE_READ | RADEON_PRIO_SHADER_BINARY));
2707 }
2708
r600_get_swizzle_combined(const unsigned char * swizzle_format,const unsigned char * swizzle_view,boolean vtx)2709 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
2710 const unsigned char *swizzle_view,
2711 boolean vtx)
2712 {
2713 unsigned i;
2714 unsigned char swizzle[4];
2715 unsigned result = 0;
2716 const uint32_t tex_swizzle_shift[4] = {
2717 16, 19, 22, 25,
2718 };
2719 const uint32_t vtx_swizzle_shift[4] = {
2720 3, 6, 9, 12,
2721 };
2722 const uint32_t swizzle_bit[4] = {
2723 0, 1, 2, 3,
2724 };
2725 const uint32_t *swizzle_shift = tex_swizzle_shift;
2726
2727 if (vtx)
2728 swizzle_shift = vtx_swizzle_shift;
2729
2730 if (swizzle_view) {
2731 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
2732 } else {
2733 memcpy(swizzle, swizzle_format, 4);
2734 }
2735
2736 /* Get swizzle. */
2737 for (i = 0; i < 4; i++) {
2738 switch (swizzle[i]) {
2739 case PIPE_SWIZZLE_Y:
2740 result |= swizzle_bit[1] << swizzle_shift[i];
2741 break;
2742 case PIPE_SWIZZLE_Z:
2743 result |= swizzle_bit[2] << swizzle_shift[i];
2744 break;
2745 case PIPE_SWIZZLE_W:
2746 result |= swizzle_bit[3] << swizzle_shift[i];
2747 break;
2748 case PIPE_SWIZZLE_0:
2749 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
2750 break;
2751 case PIPE_SWIZZLE_1:
2752 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
2753 break;
2754 default: /* PIPE_SWIZZLE_X */
2755 result |= swizzle_bit[0] << swizzle_shift[i];
2756 }
2757 }
2758 return result;
2759 }
2760
2761 /* texture format translate */
r600_translate_texformat(struct pipe_screen * screen,enum pipe_format format,const unsigned char * swizzle_view,uint32_t * word4_p,uint32_t * yuv_format_p,bool do_endian_swap)2762 uint32_t r600_translate_texformat(struct pipe_screen *screen,
2763 enum pipe_format format,
2764 const unsigned char *swizzle_view,
2765 uint32_t *word4_p, uint32_t *yuv_format_p,
2766 bool do_endian_swap)
2767 {
2768 struct r600_screen *rscreen = (struct r600_screen *)screen;
2769 uint32_t result = 0, word4 = 0, yuv_format = 0;
2770 const struct util_format_description *desc;
2771 boolean uniform = TRUE;
2772 bool is_srgb_valid = FALSE;
2773 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2774 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2775 const unsigned char swizzle_xxxy[4] = {0, 0, 0, 1};
2776 const unsigned char swizzle_zyx1[4] = {2, 1, 0, 5};
2777 const unsigned char swizzle_zyxw[4] = {2, 1, 0, 3};
2778
2779 int i;
2780 const uint32_t sign_bit[4] = {
2781 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
2782 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
2783 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
2784 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
2785 };
2786
2787 /* Need to replace the specified texture formats in case of big-endian.
2788 * These formats are formats that have channels with number of bits
2789 * not divisible by 8.
2790 * Mesa conversion functions don't swap bits for those formats, and because
2791 * we transmit this over a serial bus to the GPU (PCIe), the
2792 * bit-endianess is important!!!
2793 * In case we have an "opposite" format, just use that for the swizzling
2794 * information. If we don't have such an "opposite" format, we need
2795 * to use a fixed swizzle info instead (see below)
2796 */
2797 if (format == PIPE_FORMAT_R4A4_UNORM && do_endian_swap)
2798 format = PIPE_FORMAT_A4R4_UNORM;
2799
2800 desc = util_format_description(format);
2801
2802 /* Depth and stencil swizzling is handled separately. */
2803 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
2804 /* Need to check for specific texture formats that don't have
2805 * an "opposite" format we can use. For those formats, we directly
2806 * specify the swizzling, which is the LE swizzling as defined in
2807 * u_format.csv
2808 */
2809 if (do_endian_swap) {
2810 if (format == PIPE_FORMAT_L4A4_UNORM)
2811 word4 |= r600_get_swizzle_combined(swizzle_xxxy, swizzle_view, FALSE);
2812 else if (format == PIPE_FORMAT_B4G4R4A4_UNORM)
2813 word4 |= r600_get_swizzle_combined(swizzle_zyxw, swizzle_view, FALSE);
2814 else if (format == PIPE_FORMAT_B4G4R4X4_UNORM || format == PIPE_FORMAT_B5G6R5_UNORM)
2815 word4 |= r600_get_swizzle_combined(swizzle_zyx1, swizzle_view, FALSE);
2816 else
2817 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
2818 } else {
2819 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
2820 }
2821 }
2822
2823 /* Colorspace (return non-RGB formats directly). */
2824 switch (desc->colorspace) {
2825 /* Depth stencil formats */
2826 case UTIL_FORMAT_COLORSPACE_ZS:
2827 switch (format) {
2828 /* Depth sampler formats. */
2829 case PIPE_FORMAT_Z16_UNORM:
2830 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2831 result = FMT_16;
2832 goto out_word4;
2833 case PIPE_FORMAT_Z24X8_UNORM:
2834 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2835 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2836 result = FMT_8_24;
2837 goto out_word4;
2838 case PIPE_FORMAT_X8Z24_UNORM:
2839 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2840 if (rscreen->b.gfx_level < EVERGREEN)
2841 goto out_unknown;
2842 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2843 result = FMT_24_8;
2844 goto out_word4;
2845 case PIPE_FORMAT_Z32_FLOAT:
2846 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2847 result = FMT_32_FLOAT;
2848 goto out_word4;
2849 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2850 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2851 result = FMT_X24_8_32_FLOAT;
2852 goto out_word4;
2853 /* Stencil sampler formats. */
2854 case PIPE_FORMAT_S8_UINT:
2855 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2856 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2857 result = FMT_8;
2858 goto out_word4;
2859 case PIPE_FORMAT_X24S8_UINT:
2860 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2861 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2862 result = FMT_8_24;
2863 goto out_word4;
2864 case PIPE_FORMAT_S8X24_UINT:
2865 if (rscreen->b.gfx_level < EVERGREEN)
2866 goto out_unknown;
2867 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2868 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2869 result = FMT_24_8;
2870 goto out_word4;
2871 case PIPE_FORMAT_X32_S8X24_UINT:
2872 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2873 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2874 result = FMT_X24_8_32_FLOAT;
2875 goto out_word4;
2876 default:
2877 goto out_unknown;
2878 }
2879
2880 case UTIL_FORMAT_COLORSPACE_YUV:
2881 yuv_format |= (1 << 30);
2882 switch (format) {
2883 case PIPE_FORMAT_UYVY:
2884 case PIPE_FORMAT_YUYV:
2885 default:
2886 break;
2887 }
2888 goto out_unknown; /* XXX */
2889
2890 case UTIL_FORMAT_COLORSPACE_SRGB:
2891 word4 |= S_038010_FORCE_DEGAMMA(1);
2892 break;
2893
2894 default:
2895 break;
2896 }
2897
2898 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
2899 switch (format) {
2900 case PIPE_FORMAT_RGTC1_SNORM:
2901 case PIPE_FORMAT_LATC1_SNORM:
2902 word4 |= sign_bit[0];
2903 FALLTHROUGH;
2904 case PIPE_FORMAT_RGTC1_UNORM:
2905 case PIPE_FORMAT_LATC1_UNORM:
2906 result = FMT_BC4;
2907 goto out_word4;
2908 case PIPE_FORMAT_RGTC2_SNORM:
2909 case PIPE_FORMAT_LATC2_SNORM:
2910 word4 |= sign_bit[0] | sign_bit[1];
2911 FALLTHROUGH;
2912 case PIPE_FORMAT_RGTC2_UNORM:
2913 case PIPE_FORMAT_LATC2_UNORM:
2914 result = FMT_BC5;
2915 goto out_word4;
2916 default:
2917 goto out_unknown;
2918 }
2919 }
2920
2921 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
2922 switch (format) {
2923 case PIPE_FORMAT_DXT1_RGB:
2924 case PIPE_FORMAT_DXT1_RGBA:
2925 case PIPE_FORMAT_DXT1_SRGB:
2926 case PIPE_FORMAT_DXT1_SRGBA:
2927 result = FMT_BC1;
2928 is_srgb_valid = TRUE;
2929 goto out_word4;
2930 case PIPE_FORMAT_DXT3_RGBA:
2931 case PIPE_FORMAT_DXT3_SRGBA:
2932 result = FMT_BC2;
2933 is_srgb_valid = TRUE;
2934 goto out_word4;
2935 case PIPE_FORMAT_DXT5_RGBA:
2936 case PIPE_FORMAT_DXT5_SRGBA:
2937 result = FMT_BC3;
2938 is_srgb_valid = TRUE;
2939 goto out_word4;
2940 default:
2941 goto out_unknown;
2942 }
2943 }
2944
2945 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
2946 if (rscreen->b.gfx_level < EVERGREEN)
2947 goto out_unknown;
2948
2949 switch (format) {
2950 case PIPE_FORMAT_BPTC_RGBA_UNORM:
2951 case PIPE_FORMAT_BPTC_SRGBA:
2952 result = FMT_BC7;
2953 is_srgb_valid = TRUE;
2954 goto out_word4;
2955 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2956 word4 |= sign_bit[0] | sign_bit[1] | sign_bit[2];
2957 FALLTHROUGH;
2958 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
2959 result = FMT_BC6;
2960 goto out_word4;
2961 default:
2962 goto out_unknown;
2963 }
2964 }
2965
2966 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2967 switch (format) {
2968 case PIPE_FORMAT_R8G8_B8G8_UNORM:
2969 case PIPE_FORMAT_G8R8_B8R8_UNORM:
2970 result = FMT_GB_GR;
2971 goto out_word4;
2972 case PIPE_FORMAT_G8R8_G8B8_UNORM:
2973 case PIPE_FORMAT_R8G8_R8B8_UNORM:
2974 result = FMT_BG_RG;
2975 goto out_word4;
2976 default:
2977 goto out_unknown;
2978 }
2979 }
2980
2981 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
2982 result = FMT_5_9_9_9_SHAREDEXP;
2983 goto out_word4;
2984 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
2985 result = FMT_10_11_11_FLOAT;
2986 goto out_word4;
2987 }
2988
2989
2990 for (i = 0; i < desc->nr_channels; i++) {
2991 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2992 word4 |= sign_bit[i];
2993 }
2994 }
2995
2996 /* R8G8Bx_SNORM - XXX CxV8U8 */
2997
2998 /* See whether the components are of the same size. */
2999 for (i = 1; i < desc->nr_channels; i++) {
3000 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
3001 }
3002
3003 /* Non-uniform formats. */
3004 if (!uniform) {
3005 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
3006 desc->channel[0].pure_integer)
3007 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
3008 switch(desc->nr_channels) {
3009 case 3:
3010 if (desc->channel[0].size == 5 &&
3011 desc->channel[1].size == 6 &&
3012 desc->channel[2].size == 5) {
3013 result = FMT_5_6_5;
3014 goto out_word4;
3015 }
3016 goto out_unknown;
3017 case 4:
3018 if (desc->channel[0].size == 5 &&
3019 desc->channel[1].size == 5 &&
3020 desc->channel[2].size == 5 &&
3021 desc->channel[3].size == 1) {
3022 result = FMT_1_5_5_5;
3023 goto out_word4;
3024 }
3025 if (desc->channel[0].size == 10 &&
3026 desc->channel[1].size == 10 &&
3027 desc->channel[2].size == 10 &&
3028 desc->channel[3].size == 2) {
3029 result = FMT_2_10_10_10;
3030 goto out_word4;
3031 }
3032 goto out_unknown;
3033 }
3034 goto out_unknown;
3035 }
3036
3037 /* Find the first non-VOID channel. */
3038 for (i = 0; i < 4; i++) {
3039 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
3040 break;
3041 }
3042 }
3043
3044 if (i == 4)
3045 goto out_unknown;
3046
3047 /* uniform formats */
3048 switch (desc->channel[i].type) {
3049 case UTIL_FORMAT_TYPE_UNSIGNED:
3050 case UTIL_FORMAT_TYPE_SIGNED:
3051 #if 0
3052 if (!desc->channel[i].normalized &&
3053 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
3054 goto out_unknown;
3055 }
3056 #endif
3057 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
3058 desc->channel[i].pure_integer)
3059 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
3060
3061 switch (desc->channel[i].size) {
3062 case 4:
3063 switch (desc->nr_channels) {
3064 case 2:
3065 result = FMT_4_4;
3066 goto out_word4;
3067 case 4:
3068 result = FMT_4_4_4_4;
3069 goto out_word4;
3070 }
3071 goto out_unknown;
3072 case 8:
3073 switch (desc->nr_channels) {
3074 case 1:
3075 result = FMT_8;
3076 is_srgb_valid = TRUE;
3077 goto out_word4;
3078 case 2:
3079 result = FMT_8_8;
3080 goto out_word4;
3081 case 4:
3082 result = FMT_8_8_8_8;
3083 is_srgb_valid = TRUE;
3084 goto out_word4;
3085 }
3086 goto out_unknown;
3087 case 16:
3088 switch (desc->nr_channels) {
3089 case 1:
3090 result = FMT_16;
3091 goto out_word4;
3092 case 2:
3093 result = FMT_16_16;
3094 goto out_word4;
3095 case 4:
3096 result = FMT_16_16_16_16;
3097 goto out_word4;
3098 }
3099 goto out_unknown;
3100 case 32:
3101 switch (desc->nr_channels) {
3102 case 1:
3103 result = FMT_32;
3104 goto out_word4;
3105 case 2:
3106 result = FMT_32_32;
3107 goto out_word4;
3108 case 4:
3109 result = FMT_32_32_32_32;
3110 goto out_word4;
3111 }
3112 }
3113 goto out_unknown;
3114
3115 case UTIL_FORMAT_TYPE_FLOAT:
3116 switch (desc->channel[i].size) {
3117 case 16:
3118 switch (desc->nr_channels) {
3119 case 1:
3120 result = FMT_16_FLOAT;
3121 goto out_word4;
3122 case 2:
3123 result = FMT_16_16_FLOAT;
3124 goto out_word4;
3125 case 4:
3126 result = FMT_16_16_16_16_FLOAT;
3127 goto out_word4;
3128 }
3129 goto out_unknown;
3130 case 32:
3131 switch (desc->nr_channels) {
3132 case 1:
3133 result = FMT_32_FLOAT;
3134 goto out_word4;
3135 case 2:
3136 result = FMT_32_32_FLOAT;
3137 goto out_word4;
3138 case 4:
3139 result = FMT_32_32_32_32_FLOAT;
3140 goto out_word4;
3141 }
3142 }
3143 goto out_unknown;
3144 }
3145
3146 out_word4:
3147
3148 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
3149 return ~0;
3150 if (word4_p)
3151 *word4_p = word4;
3152 if (yuv_format_p)
3153 *yuv_format_p = yuv_format;
3154 return result;
3155 out_unknown:
3156 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
3157 return ~0;
3158 }
3159
r600_translate_colorformat(enum amd_gfx_level chip,enum pipe_format format,bool do_endian_swap)3160 uint32_t r600_translate_colorformat(enum amd_gfx_level chip, enum pipe_format format,
3161 bool do_endian_swap)
3162 {
3163 const struct util_format_description *desc = util_format_description(format);
3164 int channel = util_format_get_first_non_void_channel(format);
3165 bool is_float;
3166
3167 #define HAS_SIZE(x,y,z,w) \
3168 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
3169 desc->channel[2].size == (z) && desc->channel[3].size == (w))
3170
3171 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
3172 return V_0280A0_COLOR_10_11_11_FLOAT;
3173
3174 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
3175 channel == -1)
3176 return ~0U;
3177
3178 is_float = desc->channel[channel].type == UTIL_FORMAT_TYPE_FLOAT;
3179
3180 switch (desc->nr_channels) {
3181 case 1:
3182 switch (desc->channel[0].size) {
3183 case 8:
3184 return V_0280A0_COLOR_8;
3185 case 16:
3186 if (is_float)
3187 return V_0280A0_COLOR_16_FLOAT;
3188 else
3189 return V_0280A0_COLOR_16;
3190 case 32:
3191 if (is_float)
3192 return V_0280A0_COLOR_32_FLOAT;
3193 else
3194 return V_0280A0_COLOR_32;
3195 }
3196 break;
3197 case 2:
3198 if (desc->channel[0].size == desc->channel[1].size) {
3199 switch (desc->channel[0].size) {
3200 case 4:
3201 if (chip <= R700)
3202 return V_0280A0_COLOR_4_4;
3203 else
3204 return ~0U; /* removed on Evergreen */
3205 case 8:
3206 return V_0280A0_COLOR_8_8;
3207 case 16:
3208 if (is_float)
3209 return V_0280A0_COLOR_16_16_FLOAT;
3210 else
3211 return V_0280A0_COLOR_16_16;
3212 case 32:
3213 if (is_float)
3214 return V_0280A0_COLOR_32_32_FLOAT;
3215 else
3216 return V_0280A0_COLOR_32_32;
3217 }
3218 } else if (HAS_SIZE(8,24,0,0)) {
3219 return (do_endian_swap ? V_0280A0_COLOR_8_24 : V_0280A0_COLOR_24_8);
3220 } else if (HAS_SIZE(24,8,0,0)) {
3221 return V_0280A0_COLOR_8_24;
3222 }
3223 break;
3224 case 3:
3225 if (HAS_SIZE(5,6,5,0)) {
3226 return V_0280A0_COLOR_5_6_5;
3227 } else if (HAS_SIZE(32,8,24,0)) {
3228 return V_0280A0_COLOR_X24_8_32_FLOAT;
3229 }
3230 break;
3231 case 4:
3232 if (desc->channel[0].size == desc->channel[1].size &&
3233 desc->channel[0].size == desc->channel[2].size &&
3234 desc->channel[0].size == desc->channel[3].size) {
3235 switch (desc->channel[0].size) {
3236 case 4:
3237 return V_0280A0_COLOR_4_4_4_4;
3238 case 8:
3239 return V_0280A0_COLOR_8_8_8_8;
3240 case 16:
3241 if (is_float)
3242 return V_0280A0_COLOR_16_16_16_16_FLOAT;
3243 else
3244 return V_0280A0_COLOR_16_16_16_16;
3245 case 32:
3246 if (is_float)
3247 return V_0280A0_COLOR_32_32_32_32_FLOAT;
3248 else
3249 return V_0280A0_COLOR_32_32_32_32;
3250 }
3251 } else if (HAS_SIZE(5,5,5,1)) {
3252 return V_0280A0_COLOR_1_5_5_5;
3253 } else if (HAS_SIZE(10,10,10,2)) {
3254 return V_0280A0_COLOR_2_10_10_10;
3255 }
3256 break;
3257 }
3258 return ~0U;
3259 }
3260
r600_colorformat_endian_swap(uint32_t colorformat,bool do_endian_swap)3261 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap)
3262 {
3263 if (R600_BIG_ENDIAN) {
3264 switch(colorformat) {
3265 /* 8-bit buffers. */
3266 case V_0280A0_COLOR_4_4:
3267 case V_0280A0_COLOR_8:
3268 return ENDIAN_NONE;
3269
3270 /* 16-bit buffers. */
3271 case V_0280A0_COLOR_8_8:
3272 /*
3273 * No need to do endian swaps on array formats,
3274 * as mesa<-->pipe formats conversion take into account
3275 * the endianess
3276 */
3277 return ENDIAN_NONE;
3278
3279 case V_0280A0_COLOR_5_6_5:
3280 case V_0280A0_COLOR_1_5_5_5:
3281 case V_0280A0_COLOR_4_4_4_4:
3282 case V_0280A0_COLOR_16:
3283 return (do_endian_swap ? ENDIAN_8IN16 : ENDIAN_NONE);
3284
3285 /* 32-bit buffers. */
3286 case V_0280A0_COLOR_8_8_8_8:
3287 /*
3288 * No need to do endian swaps on array formats,
3289 * as mesa<-->pipe formats conversion take into account
3290 * the endianess
3291 */
3292 return ENDIAN_NONE;
3293
3294 case V_0280A0_COLOR_2_10_10_10:
3295 case V_0280A0_COLOR_8_24:
3296 case V_0280A0_COLOR_24_8:
3297 case V_0280A0_COLOR_32_FLOAT:
3298 return (do_endian_swap ? ENDIAN_8IN32 : ENDIAN_NONE);
3299
3300 case V_0280A0_COLOR_16_16_FLOAT:
3301 case V_0280A0_COLOR_16_16:
3302 return ENDIAN_8IN16;
3303
3304 /* 64-bit buffers. */
3305 case V_0280A0_COLOR_16_16_16_16:
3306 case V_0280A0_COLOR_16_16_16_16_FLOAT:
3307 return ENDIAN_8IN16;
3308
3309 case V_0280A0_COLOR_32_32_FLOAT:
3310 case V_0280A0_COLOR_32_32:
3311 case V_0280A0_COLOR_X24_8_32_FLOAT:
3312 return ENDIAN_8IN32;
3313
3314 /* 128-bit buffers. */
3315 case V_0280A0_COLOR_32_32_32_32_FLOAT:
3316 case V_0280A0_COLOR_32_32_32_32:
3317 return ENDIAN_8IN32;
3318 default:
3319 return ENDIAN_NONE; /* Unsupported. */
3320 }
3321 } else {
3322 return ENDIAN_NONE;
3323 }
3324 }
3325
r600_invalidate_buffer(struct pipe_context * ctx,struct pipe_resource * buf)3326 static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
3327 {
3328 struct r600_context *rctx = (struct r600_context*)ctx;
3329 struct r600_resource *rbuffer = r600_resource(buf);
3330 unsigned i, shader, mask;
3331 struct r600_pipe_sampler_view *view;
3332
3333 /* Reallocate the buffer in the same pipe_resource. */
3334 r600_alloc_resource(&rctx->screen->b, rbuffer);
3335
3336 /* We changed the buffer, now we need to bind it where the old one was bound. */
3337 /* Vertex buffers. */
3338 mask = rctx->vertex_buffer_state.enabled_mask;
3339 while (mask) {
3340 i = u_bit_scan(&mask);
3341 if (rctx->vertex_buffer_state.vb[i].buffer.resource == &rbuffer->b.b) {
3342 rctx->vertex_buffer_state.dirty_mask |= 1 << i;
3343 r600_vertex_buffers_dirty(rctx);
3344 }
3345 }
3346 /* Streamout buffers. */
3347 for (i = 0; i < rctx->b.streamout.num_targets; i++) {
3348 if (rctx->b.streamout.targets[i] &&
3349 rctx->b.streamout.targets[i]->b.buffer == &rbuffer->b.b) {
3350 if (rctx->b.streamout.begin_emitted) {
3351 r600_emit_streamout_end(&rctx->b);
3352 }
3353 rctx->b.streamout.append_bitmask = rctx->b.streamout.enabled_mask;
3354 r600_streamout_buffers_dirty(&rctx->b);
3355 }
3356 }
3357
3358 /* Constant buffers. */
3359 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
3360 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
3361 bool found = false;
3362 uint32_t mask = state->enabled_mask;
3363
3364 while (mask) {
3365 unsigned i = u_bit_scan(&mask);
3366 if (state->cb[i].buffer == &rbuffer->b.b) {
3367 found = true;
3368 state->dirty_mask |= 1 << i;
3369 }
3370 }
3371 if (found) {
3372 r600_constant_buffers_dirty(rctx, state);
3373 }
3374 }
3375
3376 /* Texture buffer objects - update the virtual addresses in descriptors. */
3377 LIST_FOR_EACH_ENTRY(view, &rctx->texture_buffers, list) {
3378 if (view->base.texture == &rbuffer->b.b) {
3379 uint64_t offset = view->base.u.buf.offset;
3380 uint64_t va = rbuffer->gpu_address + offset;
3381
3382 view->tex_resource_words[0] = va;
3383 view->tex_resource_words[2] &= C_038008_BASE_ADDRESS_HI;
3384 view->tex_resource_words[2] |= S_038008_BASE_ADDRESS_HI(va >> 32);
3385 }
3386 }
3387 /* Texture buffer objects - make bindings dirty if needed. */
3388 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
3389 struct r600_samplerview_state *state = &rctx->samplers[shader].views;
3390 bool found = false;
3391 uint32_t mask = state->enabled_mask;
3392
3393 while (mask) {
3394 unsigned i = u_bit_scan(&mask);
3395 if (state->views[i]->base.texture == &rbuffer->b.b) {
3396 found = true;
3397 state->dirty_mask |= 1 << i;
3398 }
3399 }
3400 if (found) {
3401 r600_sampler_views_dirty(rctx, state);
3402 }
3403 }
3404
3405 /* SSBOs */
3406 struct r600_image_state *istate = &rctx->fragment_buffers;
3407 {
3408 uint32_t mask = istate->enabled_mask;
3409 bool found = false;
3410 while (mask) {
3411 unsigned i = u_bit_scan(&mask);
3412 if (istate->views[i].base.resource == &rbuffer->b.b) {
3413 found = true;
3414 istate->dirty_mask |= 1 << i;
3415 }
3416 }
3417 if (found) {
3418 r600_mark_atom_dirty(rctx, &istate->atom);
3419 }
3420 }
3421
3422 }
3423
r600_set_active_query_state(struct pipe_context * ctx,bool enable)3424 static void r600_set_active_query_state(struct pipe_context *ctx, bool enable)
3425 {
3426 struct r600_context *rctx = (struct r600_context*)ctx;
3427
3428 /* Pipeline stat & streamout queries. */
3429 if (enable) {
3430 rctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
3431 rctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
3432 } else {
3433 rctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
3434 rctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
3435 }
3436
3437 /* Occlusion queries. */
3438 if (rctx->db_misc_state.occlusion_queries_disabled != !enable) {
3439 rctx->db_misc_state.occlusion_queries_disabled = !enable;
3440 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3441 }
3442 }
3443
r600_need_gfx_cs_space(struct pipe_context * ctx,unsigned num_dw,bool include_draw_vbo)3444 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3445 bool include_draw_vbo)
3446 {
3447 r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo, 0);
3448 }
3449
3450 /* keep this at the end of this file, please */
r600_init_common_state_functions(struct r600_context * rctx)3451 void r600_init_common_state_functions(struct r600_context *rctx)
3452 {
3453 rctx->b.b.create_fs_state = r600_create_ps_state;
3454 rctx->b.b.create_vs_state = r600_create_vs_state;
3455 rctx->b.b.create_gs_state = r600_create_gs_state;
3456 rctx->b.b.create_tcs_state = r600_create_tcs_state;
3457 rctx->b.b.create_tes_state = r600_create_tes_state;
3458 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
3459 rctx->b.b.bind_blend_state = r600_bind_blend_state;
3460 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
3461 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
3462 rctx->b.b.bind_fs_state = r600_bind_ps_state;
3463 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
3464 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
3465 rctx->b.b.bind_vs_state = r600_bind_vs_state;
3466 rctx->b.b.bind_gs_state = r600_bind_gs_state;
3467 rctx->b.b.bind_tcs_state = r600_bind_tcs_state;
3468 rctx->b.b.bind_tes_state = r600_bind_tes_state;
3469 rctx->b.b.delete_blend_state = r600_delete_blend_state;
3470 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
3471 rctx->b.b.delete_fs_state = r600_delete_ps_state;
3472 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
3473 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
3474 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
3475 rctx->b.b.delete_vs_state = r600_delete_vs_state;
3476 rctx->b.b.delete_gs_state = r600_delete_gs_state;
3477 rctx->b.b.delete_tcs_state = r600_delete_tcs_state;
3478 rctx->b.b.delete_tes_state = r600_delete_tes_state;
3479 rctx->b.b.set_blend_color = r600_set_blend_color;
3480 rctx->b.b.set_clip_state = r600_set_clip_state;
3481 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
3482 rctx->b.b.set_sample_mask = r600_set_sample_mask;
3483 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
3484 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
3485 rctx->b.b.set_sampler_views = r600_set_sampler_views;
3486 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
3487 rctx->b.b.memory_barrier = r600_memory_barrier;
3488 rctx->b.b.texture_barrier = r600_texture_barrier;
3489 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
3490 rctx->b.b.set_active_query_state = r600_set_active_query_state;
3491
3492 rctx->b.b.draw_vbo = r600_draw_vbo;
3493 rctx->b.invalidate_buffer = r600_invalidate_buffer;
3494 rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
3495 }
3496