1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "r600_query.h"
30 #include "util/format/u_format.h"
31 #include "util/u_log.h"
32 #include "util/u_memory.h"
33 #include "util/u_pack_color.h"
34 #include "util/u_surface.h"
35 #include "util/os_time.h"
36 #include "frontend/winsys_handle.h"
37 #include <errno.h>
38 #include <inttypes.h>
39
40 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
41 struct r600_texture *rtex);
42 static enum radeon_surf_mode
43 r600_choose_tiling(struct r600_common_screen *rscreen,
44 const struct pipe_resource *templ);
45
46
r600_prepare_for_dma_blit(struct r600_common_context * rctx,struct r600_texture * rdst,unsigned dst_level,unsigned dstx,unsigned dsty,unsigned dstz,struct r600_texture * rsrc,unsigned src_level,const struct pipe_box * src_box)47 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
48 struct r600_texture *rdst,
49 unsigned dst_level, unsigned dstx,
50 unsigned dsty, unsigned dstz,
51 struct r600_texture *rsrc,
52 unsigned src_level,
53 const struct pipe_box *src_box)
54 {
55 if (!rctx->dma.cs.priv)
56 return false;
57
58 if (rdst->surface.bpe != rsrc->surface.bpe)
59 return false;
60
61 /* MSAA: Blits don't exist in the real world. */
62 if (rsrc->resource.b.b.nr_samples > 1 ||
63 rdst->resource.b.b.nr_samples > 1)
64 return false;
65
66 /* Depth-stencil surfaces:
67 * When dst is linear, the DB->CB copy preserves HTILE.
68 * When dst is tiled, the 3D path must be used to update HTILE.
69 */
70 if (rsrc->is_depth || rdst->is_depth)
71 return false;
72
73 /* CMASK as:
74 * src: Both texture and SDMA paths need decompression. Use SDMA.
75 * dst: If overwriting the whole texture, discard CMASK and use
76 * SDMA. Otherwise, use the 3D path.
77 */
78 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) {
79 /* The CMASK clear is only enabled for the first level. */
80 assert(dst_level == 0);
81 if (!util_texrange_covers_whole_level(&rdst->resource.b.b, dst_level,
82 dstx, dsty, dstz, src_box->width,
83 src_box->height, src_box->depth))
84 return false;
85
86 r600_texture_discard_cmask(rctx->screen, rdst);
87 }
88
89 /* All requirements are met. Prepare textures for SDMA. */
90 if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level))
91 rctx->b.flush_resource(&rctx->b, &rsrc->resource.b.b);
92
93 assert(!(rsrc->dirty_level_mask & (1 << src_level)));
94 assert(!(rdst->dirty_level_mask & (1 << dst_level)));
95
96 return true;
97 }
98
99 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
r600_copy_region_with_blit(struct pipe_context * pipe,struct pipe_resource * dst,unsigned dst_level,unsigned dstx,unsigned dsty,unsigned dstz,struct pipe_resource * src,unsigned src_level,const struct pipe_box * src_box)100 static void r600_copy_region_with_blit(struct pipe_context *pipe,
101 struct pipe_resource *dst,
102 unsigned dst_level,
103 unsigned dstx, unsigned dsty, unsigned dstz,
104 struct pipe_resource *src,
105 unsigned src_level,
106 const struct pipe_box *src_box)
107 {
108 struct pipe_blit_info blit;
109
110 memset(&blit, 0, sizeof(blit));
111 blit.src.resource = src;
112 blit.src.format = src->format;
113 blit.src.level = src_level;
114 blit.src.box = *src_box;
115 blit.dst.resource = dst;
116 blit.dst.format = dst->format;
117 blit.dst.level = dst_level;
118 blit.dst.box.x = dstx;
119 blit.dst.box.y = dsty;
120 blit.dst.box.z = dstz;
121 blit.dst.box.width = src_box->width;
122 blit.dst.box.height = src_box->height;
123 blit.dst.box.depth = src_box->depth;
124 blit.mask = util_format_get_mask(src->format) &
125 util_format_get_mask(dst->format);
126 blit.filter = PIPE_TEX_FILTER_NEAREST;
127
128 if (blit.mask) {
129 pipe->blit(pipe, &blit);
130 }
131 }
132
133 /* Copy from a full GPU texture to a transfer's staging one. */
r600_copy_to_staging_texture(struct pipe_context * ctx,struct r600_transfer * rtransfer)134 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
135 {
136 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
137 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
138 struct pipe_resource *dst = &rtransfer->staging->b.b;
139 struct pipe_resource *src = transfer->resource;
140
141 if (src->nr_samples > 1) {
142 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
143 src, transfer->level, &transfer->box);
144 return;
145 }
146
147 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
148 &transfer->box);
149 }
150
151 /* Copy from a transfer's staging texture to a full GPU one. */
r600_copy_from_staging_texture(struct pipe_context * ctx,struct r600_transfer * rtransfer)152 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
153 {
154 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
155 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
156 struct pipe_resource *dst = transfer->resource;
157 struct pipe_resource *src = &rtransfer->staging->b.b;
158 struct pipe_box sbox;
159
160 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
161
162 if (dst->nr_samples > 1) {
163 r600_copy_region_with_blit(ctx, dst, transfer->level,
164 transfer->box.x, transfer->box.y, transfer->box.z,
165 src, 0, &sbox);
166 return;
167 }
168
169 rctx->dma_copy(ctx, dst, transfer->level,
170 transfer->box.x, transfer->box.y, transfer->box.z,
171 src, 0, &sbox);
172 }
173
r600_texture_get_offset(struct r600_common_screen * rscreen,struct r600_texture * rtex,unsigned level,const struct pipe_box * box,unsigned * stride,unsigned * layer_stride)174 static unsigned r600_texture_get_offset(struct r600_common_screen *rscreen,
175 struct r600_texture *rtex, unsigned level,
176 const struct pipe_box *box,
177 unsigned *stride,
178 unsigned *layer_stride)
179 {
180 *stride = rtex->surface.u.legacy.level[level].nblk_x *
181 rtex->surface.bpe;
182 assert((uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX);
183 *layer_stride = (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4;
184
185 if (!box)
186 return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
187
188 /* Each texture is an array of mipmap levels. Each level is
189 * an array of slices. */
190 return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256 +
191 box->z * (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 +
192 (box->y / rtex->surface.blk_h *
193 rtex->surface.u.legacy.level[level].nblk_x +
194 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
195 }
196
r600_init_surface(struct r600_common_screen * rscreen,struct radeon_surf * surface,const struct pipe_resource * ptex,enum radeon_surf_mode array_mode,unsigned pitch_in_bytes_override,unsigned offset,bool is_imported,bool is_scanout,bool is_flushed_depth)197 static int r600_init_surface(struct r600_common_screen *rscreen,
198 struct radeon_surf *surface,
199 const struct pipe_resource *ptex,
200 enum radeon_surf_mode array_mode,
201 unsigned pitch_in_bytes_override,
202 unsigned offset,
203 bool is_imported,
204 bool is_scanout,
205 bool is_flushed_depth)
206 {
207 const struct util_format_description *desc =
208 util_format_description(ptex->format);
209 bool is_depth, is_stencil;
210 int r;
211 unsigned i, bpe, flags = 0;
212
213 is_depth = util_format_has_depth(desc);
214 is_stencil = util_format_has_stencil(desc);
215
216 if (rscreen->gfx_level >= EVERGREEN && !is_flushed_depth &&
217 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
218 bpe = 4; /* stencil is allocated separately on evergreen */
219 } else {
220 bpe = util_format_get_blocksize(ptex->format);
221 assert(util_is_power_of_two_or_zero(bpe));
222 }
223
224 if (!is_flushed_depth && is_depth) {
225 flags |= RADEON_SURF_ZBUFFER;
226
227 if (is_stencil)
228 flags |= RADEON_SURF_SBUFFER;
229 }
230
231 if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
232 /* This should catch bugs in gallium users setting incorrect flags. */
233 assert(ptex->nr_samples <= 1 &&
234 ptex->array_size == 1 &&
235 ptex->depth0 == 1 &&
236 ptex->last_level == 0 &&
237 !(flags & RADEON_SURF_Z_OR_SBUFFER));
238
239 flags |= RADEON_SURF_SCANOUT;
240 }
241
242 if (ptex->bind & PIPE_BIND_SHARED)
243 flags |= RADEON_SURF_SHAREABLE;
244 if (is_imported)
245 flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
246
247 r = rscreen->ws->surface_init(rscreen->ws, ptex,
248 flags, bpe, array_mode, surface);
249 if (r) {
250 return r;
251 }
252
253 if (pitch_in_bytes_override &&
254 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) {
255 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
256 * for those
257 */
258 surface->u.legacy.level[0].nblk_x = pitch_in_bytes_override / bpe;
259 surface->u.legacy.level[0].slice_size_dw =
260 ((uint64_t)pitch_in_bytes_override * surface->u.legacy.level[0].nblk_y) / 4;
261 }
262
263 if (offset) {
264 for (i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
265 surface->u.legacy.level[i].offset_256B += offset / 256;
266 }
267
268 return 0;
269 }
270
r600_texture_init_metadata(struct r600_common_screen * rscreen,struct r600_texture * rtex,struct radeon_bo_metadata * metadata)271 static void r600_texture_init_metadata(struct r600_common_screen *rscreen,
272 struct r600_texture *rtex,
273 struct radeon_bo_metadata *metadata)
274 {
275 struct radeon_surf *surface = &rtex->surface;
276
277 memset(metadata, 0, sizeof(*metadata));
278
279 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
280 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
281 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
282 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
283 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
284 metadata->u.legacy.bankw = surface->u.legacy.bankw;
285 metadata->u.legacy.bankh = surface->u.legacy.bankh;
286 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
287 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
288 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
289 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
290 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
291 }
292
r600_surface_import_metadata(struct r600_common_screen * rscreen,struct radeon_surf * surf,struct radeon_bo_metadata * metadata,enum radeon_surf_mode * array_mode,bool * is_scanout)293 static void r600_surface_import_metadata(struct r600_common_screen *rscreen,
294 struct radeon_surf *surf,
295 struct radeon_bo_metadata *metadata,
296 enum radeon_surf_mode *array_mode,
297 bool *is_scanout)
298 {
299 surf->u.legacy.pipe_config = metadata->u.legacy.pipe_config;
300 surf->u.legacy.bankw = metadata->u.legacy.bankw;
301 surf->u.legacy.bankh = metadata->u.legacy.bankh;
302 surf->u.legacy.tile_split = metadata->u.legacy.tile_split;
303 surf->u.legacy.mtilea = metadata->u.legacy.mtilea;
304 surf->u.legacy.num_banks = metadata->u.legacy.num_banks;
305
306 if (metadata->u.legacy.macrotile == RADEON_LAYOUT_TILED)
307 *array_mode = RADEON_SURF_MODE_2D;
308 else if (metadata->u.legacy.microtile == RADEON_LAYOUT_TILED)
309 *array_mode = RADEON_SURF_MODE_1D;
310 else
311 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
312
313 *is_scanout = metadata->u.legacy.scanout;
314 }
315
r600_eliminate_fast_color_clear(struct r600_common_context * rctx,struct r600_texture * rtex)316 static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
317 struct r600_texture *rtex)
318 {
319 struct r600_common_screen *rscreen = rctx->screen;
320 struct pipe_context *ctx = &rctx->b;
321
322 if (ctx == rscreen->aux_context)
323 mtx_lock(&rscreen->aux_context_lock);
324
325 ctx->flush_resource(ctx, &rtex->resource.b.b);
326 ctx->flush(ctx, NULL, 0);
327
328 if (ctx == rscreen->aux_context)
329 mtx_unlock(&rscreen->aux_context_lock);
330 }
331
r600_texture_discard_cmask(struct r600_common_screen * rscreen,struct r600_texture * rtex)332 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
333 struct r600_texture *rtex)
334 {
335 if (!rtex->cmask.size)
336 return;
337
338 assert(rtex->resource.b.b.nr_samples <= 1);
339
340 /* Disable CMASK. */
341 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
342 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
343 rtex->dirty_level_mask = 0;
344
345 rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
346
347 if (rtex->cmask_buffer != &rtex->resource)
348 r600_resource_reference(&rtex->cmask_buffer, NULL);
349
350 /* Notify all contexts about the change. */
351 p_atomic_inc(&rscreen->dirty_tex_counter);
352 p_atomic_inc(&rscreen->compressed_colortex_counter);
353 }
354
r600_reallocate_texture_inplace(struct r600_common_context * rctx,struct r600_texture * rtex,unsigned new_bind_flag,bool invalidate_storage)355 static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
356 struct r600_texture *rtex,
357 unsigned new_bind_flag,
358 bool invalidate_storage)
359 {
360 struct pipe_screen *screen = rctx->b.screen;
361 struct r600_texture *new_tex;
362 struct pipe_resource templ = rtex->resource.b.b;
363 unsigned i;
364
365 templ.bind |= new_bind_flag;
366
367 /* r600g doesn't react to dirty_tex_descriptor_counter */
368 if (rctx->gfx_level < GFX6)
369 return;
370
371 if (rtex->resource.b.is_shared)
372 return;
373
374 if (new_bind_flag == PIPE_BIND_LINEAR) {
375 if (rtex->surface.is_linear)
376 return;
377
378 /* This fails with MSAA, depth, and compressed textures. */
379 if (r600_choose_tiling(rctx->screen, &templ) !=
380 RADEON_SURF_MODE_LINEAR_ALIGNED)
381 return;
382 }
383
384 new_tex = (struct r600_texture*)screen->resource_create(screen, &templ);
385 if (!new_tex)
386 return;
387
388 /* Copy the pixels to the new texture. */
389 if (!invalidate_storage) {
390 for (i = 0; i <= templ.last_level; i++) {
391 struct pipe_box box;
392
393 u_box_3d(0, 0, 0,
394 u_minify(templ.width0, i), u_minify(templ.height0, i),
395 util_num_layers(&templ, i), &box);
396
397 rctx->dma_copy(&rctx->b, &new_tex->resource.b.b, i, 0, 0, 0,
398 &rtex->resource.b.b, i, &box);
399 }
400 }
401
402 if (new_bind_flag == PIPE_BIND_LINEAR) {
403 r600_texture_discard_cmask(rctx->screen, rtex);
404 }
405
406 /* Replace the structure fields of rtex. */
407 rtex->resource.b.b.bind = templ.bind;
408 pb_reference(&rtex->resource.buf, new_tex->resource.buf);
409 rtex->resource.gpu_address = new_tex->resource.gpu_address;
410 rtex->resource.vram_usage = new_tex->resource.vram_usage;
411 rtex->resource.gart_usage = new_tex->resource.gart_usage;
412 rtex->resource.bo_size = new_tex->resource.bo_size;
413 rtex->resource.bo_alignment = new_tex->resource.bo_alignment;
414 rtex->resource.domains = new_tex->resource.domains;
415 rtex->resource.flags = new_tex->resource.flags;
416 rtex->size = new_tex->size;
417 rtex->db_render_format = new_tex->db_render_format;
418 rtex->db_compatible = new_tex->db_compatible;
419 rtex->can_sample_z = new_tex->can_sample_z;
420 rtex->can_sample_s = new_tex->can_sample_s;
421 rtex->surface = new_tex->surface;
422 rtex->fmask = new_tex->fmask;
423 rtex->cmask = new_tex->cmask;
424 rtex->cb_color_info = new_tex->cb_color_info;
425 rtex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode;
426 rtex->htile_offset = new_tex->htile_offset;
427 rtex->depth_cleared = new_tex->depth_cleared;
428 rtex->stencil_cleared = new_tex->stencil_cleared;
429 rtex->non_disp_tiling = new_tex->non_disp_tiling;
430 rtex->framebuffers_bound = new_tex->framebuffers_bound;
431
432 if (new_bind_flag == PIPE_BIND_LINEAR) {
433 assert(!rtex->htile_offset);
434 assert(!rtex->cmask.size);
435 assert(!rtex->fmask.size);
436 assert(!rtex->is_depth);
437 }
438
439 r600_texture_reference(&new_tex, NULL);
440
441 p_atomic_inc(&rctx->screen->dirty_tex_counter);
442 }
443
r600_texture_get_info(struct pipe_screen * screen,struct pipe_resource * resource,unsigned * pstride,unsigned * poffset)444 static void r600_texture_get_info(struct pipe_screen* screen,
445 struct pipe_resource *resource,
446 unsigned *pstride,
447 unsigned *poffset)
448 {
449 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
450 struct r600_texture *rtex = (struct r600_texture*)resource;
451 unsigned stride = 0;
452 unsigned offset = 0;
453
454 if (!rscreen || !rtex)
455 return;
456
457 if (resource->target != PIPE_BUFFER) {
458 offset = (uint64_t)rtex->surface.u.legacy.level[0].offset_256B * 256;
459 stride = rtex->surface.u.legacy.level[0].nblk_x *
460 rtex->surface.bpe;
461 }
462
463 if (pstride)
464 *pstride = stride;
465
466 if (poffset)
467 *poffset = offset;
468 }
469
r600_texture_get_handle(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_resource * resource,struct winsys_handle * whandle,unsigned usage)470 static bool r600_texture_get_handle(struct pipe_screen* screen,
471 struct pipe_context *ctx,
472 struct pipe_resource *resource,
473 struct winsys_handle *whandle,
474 unsigned usage)
475 {
476 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
477 struct r600_common_context *rctx;
478 struct r600_resource *res = (struct r600_resource*)resource;
479 struct r600_texture *rtex = (struct r600_texture*)resource;
480 struct radeon_bo_metadata metadata;
481 bool update_metadata = false;
482 unsigned stride, offset, slice_size;
483
484 ctx = threaded_context_unwrap_sync(ctx);
485 rctx = (struct r600_common_context*)(ctx ? ctx : rscreen->aux_context);
486
487 if (resource->target != PIPE_BUFFER) {
488 /* This is not supported now, but it might be required for OpenCL
489 * interop in the future.
490 */
491 if (resource->nr_samples > 1 || rtex->is_depth)
492 return false;
493
494 /* Move a suballocated texture into a non-suballocated allocation. */
495 if (rscreen->ws->buffer_is_suballocated(res->buf) ||
496 rtex->surface.tile_swizzle) {
497 assert(!res->b.is_shared);
498 r600_reallocate_texture_inplace(rctx, rtex,
499 PIPE_BIND_SHARED, false);
500 rctx->b.flush(&rctx->b, NULL, 0);
501 assert(res->b.b.bind & PIPE_BIND_SHARED);
502 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
503 assert(rtex->surface.tile_swizzle == 0);
504 }
505
506 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
507 rtex->cmask.size) {
508 /* Eliminate fast clear (CMASK) */
509 r600_eliminate_fast_color_clear(rctx, rtex);
510
511 /* Disable CMASK if flush_resource isn't going
512 * to be called.
513 */
514 if (rtex->cmask.size)
515 r600_texture_discard_cmask(rscreen, rtex);
516 }
517
518 /* Set metadata. */
519 if (!res->b.is_shared || update_metadata) {
520 r600_texture_init_metadata(rscreen, rtex, &metadata);
521
522 rscreen->ws->buffer_set_metadata(rscreen->ws, res->buf, &metadata, NULL);
523 }
524
525 slice_size = (uint64_t)rtex->surface.u.legacy.level[0].slice_size_dw * 4;
526 } else {
527 /* Move a suballocated buffer into a non-suballocated allocation. */
528 if (rscreen->ws->buffer_is_suballocated(res->buf)) {
529 assert(!res->b.is_shared);
530
531 /* Allocate a new buffer with PIPE_BIND_SHARED. */
532 struct pipe_resource templ = res->b.b;
533 templ.bind |= PIPE_BIND_SHARED;
534
535 struct pipe_resource *newb =
536 screen->resource_create(screen, &templ);
537 if (!newb)
538 return false;
539
540 /* Copy the old buffer contents to the new one. */
541 struct pipe_box box;
542 u_box_1d(0, newb->width0, &box);
543 rctx->b.resource_copy_region(&rctx->b, newb, 0, 0, 0, 0,
544 &res->b.b, 0, &box);
545 /* Move the new buffer storage to the old pipe_resource. */
546 r600_replace_buffer_storage(&rctx->b, &res->b.b, newb);
547 pipe_resource_reference(&newb, NULL);
548
549 assert(res->b.b.bind & PIPE_BIND_SHARED);
550 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
551 }
552
553 /* Buffers */
554 slice_size = 0;
555 }
556
557 r600_texture_get_info(screen, resource, &stride, &offset);
558
559 if (res->b.is_shared) {
560 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
561 * doesn't set it.
562 */
563 res->external_usage |= usage & ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
564 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
565 res->external_usage &= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
566 } else {
567 res->b.is_shared = true;
568 res->external_usage = usage;
569 }
570
571 whandle->stride = stride;
572 whandle->offset = offset + slice_size * whandle->layer;
573
574 return rscreen->ws->buffer_get_handle(rscreen->ws, res->buf, whandle);
575 }
576
r600_texture_destroy(struct pipe_screen * screen,struct pipe_resource * ptex)577 void r600_texture_destroy(struct pipe_screen *screen, struct pipe_resource *ptex)
578 {
579 struct r600_texture *rtex = (struct r600_texture*)ptex;
580 struct r600_resource *resource = &rtex->resource;
581
582 r600_texture_reference(&rtex->flushed_depth_texture, NULL);
583 pipe_resource_reference((struct pipe_resource**)&resource->immed_buffer, NULL);
584
585 if (rtex->cmask_buffer != &rtex->resource) {
586 r600_resource_reference(&rtex->cmask_buffer, NULL);
587 }
588 pb_reference(&resource->buf, NULL);
589 FREE(rtex);
590 }
591
592 /* The number of samples can be specified independently of the texture. */
r600_texture_get_fmask_info(struct r600_common_screen * rscreen,struct r600_texture * rtex,unsigned nr_samples,struct r600_fmask_info * out)593 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
594 struct r600_texture *rtex,
595 unsigned nr_samples,
596 struct r600_fmask_info *out)
597 {
598 /* FMASK is allocated like an ordinary texture. */
599 struct pipe_resource templ = rtex->resource.b.b;
600 struct radeon_surf fmask = {};
601 unsigned flags, bpe;
602
603 memset(out, 0, sizeof(*out));
604
605 templ.nr_samples = 1;
606 flags = rtex->surface.flags | RADEON_SURF_FMASK;
607
608 /* Use the same parameters and tile mode. */
609 fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw;
610 fmask.u.legacy.bankh = rtex->surface.u.legacy.bankh;
611 fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea;
612 fmask.u.legacy.tile_split = rtex->surface.u.legacy.tile_split;
613
614 if (nr_samples <= 4)
615 fmask.u.legacy.bankh = 4;
616
617 switch (nr_samples) {
618 case 2:
619 case 4:
620 bpe = 1;
621 break;
622 case 8:
623 bpe = 4;
624 break;
625 default:
626 R600_ERR("Invalid sample count for FMASK allocation.\n");
627 return;
628 }
629
630 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
631 * This can be fixed by writing a separate FMASK allocator specifically
632 * for R600-R700 asics. */
633 if (rscreen->gfx_level <= R700) {
634 bpe *= 2;
635 }
636
637 if (rscreen->ws->surface_init(rscreen->ws, &templ,
638 flags, bpe, RADEON_SURF_MODE_2D, &fmask)) {
639 R600_ERR("Got error in surface_init while allocating FMASK.\n");
640 return;
641 }
642
643 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
644
645 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
646 if (out->slice_tile_max)
647 out->slice_tile_max -= 1;
648
649 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
650 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
651 out->bank_height = fmask.u.legacy.bankh;
652 out->tile_swizzle = fmask.tile_swizzle;
653 out->alignment = MAX2(256, 1 << fmask.surf_alignment_log2);
654 out->size = fmask.surf_size;
655 }
656
r600_texture_allocate_fmask(struct r600_common_screen * rscreen,struct r600_texture * rtex)657 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
658 struct r600_texture *rtex)
659 {
660 r600_texture_get_fmask_info(rscreen, rtex,
661 rtex->resource.b.b.nr_samples, &rtex->fmask);
662
663 rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
664 rtex->size = rtex->fmask.offset + rtex->fmask.size;
665 }
666
r600_texture_get_cmask_info(struct r600_common_screen * rscreen,struct r600_texture * rtex,struct r600_cmask_info * out)667 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
668 struct r600_texture *rtex,
669 struct r600_cmask_info *out)
670 {
671 unsigned cmask_tile_width = 8;
672 unsigned cmask_tile_height = 8;
673 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
674 unsigned element_bits = 4;
675 unsigned cmask_cache_bits = 1024;
676 unsigned num_pipes = rscreen->info.num_tile_pipes;
677 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
678
679 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
680 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
681 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
682 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
683 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
684
685 unsigned pitch_elements = align(rtex->resource.b.b.width0, macro_tile_width);
686 unsigned height = align(rtex->resource.b.b.height0, macro_tile_height);
687
688 unsigned base_align = num_pipes * pipe_interleave_bytes;
689 unsigned slice_bytes =
690 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
691
692 assert(macro_tile_width % 128 == 0);
693 assert(macro_tile_height % 128 == 0);
694
695 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
696 out->alignment = MAX2(256, base_align);
697 out->size = util_num_layers(&rtex->resource.b.b, 0) *
698 align(slice_bytes, base_align);
699 }
700
r600_texture_allocate_cmask(struct r600_common_screen * rscreen,struct r600_texture * rtex)701 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
702 struct r600_texture *rtex)
703 {
704 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
705
706 rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
707 rtex->size = rtex->cmask.offset + rtex->cmask.size;
708
709 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
710 }
711
r600_texture_alloc_cmask_separate(struct r600_common_screen * rscreen,struct r600_texture * rtex)712 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
713 struct r600_texture *rtex)
714 {
715 if (rtex->cmask_buffer)
716 return;
717
718 assert(rtex->cmask.size == 0);
719
720 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
721
722 rtex->cmask_buffer = (struct r600_resource *)
723 r600_aligned_buffer_create(&rscreen->b,
724 R600_RESOURCE_FLAG_UNMAPPABLE,
725 PIPE_USAGE_DEFAULT,
726 rtex->cmask.size,
727 rtex->cmask.alignment);
728 if (rtex->cmask_buffer == NULL) {
729 rtex->cmask.size = 0;
730 return;
731 }
732
733 /* update colorbuffer state bits */
734 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
735
736 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
737
738 p_atomic_inc(&rscreen->compressed_colortex_counter);
739 }
740
eg_resource_alloc_immed(struct r600_common_screen * rscreen,struct r600_resource * res,unsigned immed_size)741 void eg_resource_alloc_immed(struct r600_common_screen *rscreen,
742 struct r600_resource *res,
743 unsigned immed_size)
744 {
745 res->immed_buffer = (struct r600_resource *)
746 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
747 PIPE_USAGE_DEFAULT, immed_size);
748 }
749
r600_texture_get_htile_size(struct r600_common_screen * rscreen,struct r600_texture * rtex)750 static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
751 struct r600_texture *rtex)
752 {
753 unsigned cl_width, cl_height, width, height;
754 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
755 unsigned num_pipes = rscreen->info.num_tile_pipes;
756
757 rtex->surface.meta_size = 0;
758
759 /* HW bug on R6xx. */
760 if (rscreen->gfx_level == R600 &&
761 (rtex->resource.b.b.width0 > 7680 ||
762 rtex->resource.b.b.height0 > 7680))
763 return;
764
765 switch (num_pipes) {
766 case 1:
767 cl_width = 32;
768 cl_height = 16;
769 break;
770 case 2:
771 cl_width = 32;
772 cl_height = 32;
773 break;
774 case 4:
775 cl_width = 64;
776 cl_height = 32;
777 break;
778 case 8:
779 cl_width = 64;
780 cl_height = 64;
781 break;
782 case 16:
783 cl_width = 128;
784 cl_height = 64;
785 break;
786 default:
787 assert(0);
788 return;
789 }
790
791 width = align(rtex->surface.u.legacy.level[0].nblk_x, cl_width * 8);
792 height = align(rtex->surface.u.legacy.level[0].nblk_y, cl_height * 8);
793
794 slice_elements = (width * height) / (8 * 8);
795 slice_bytes = slice_elements * 4;
796
797 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
798 base_align = num_pipes * pipe_interleave_bytes;
799
800 rtex->surface.meta_alignment_log2 = util_logbase2(base_align);
801 rtex->surface.meta_size =
802 util_num_layers(&rtex->resource.b.b, 0) *
803 align(slice_bytes, base_align);
804 }
805
r600_texture_allocate_htile(struct r600_common_screen * rscreen,struct r600_texture * rtex)806 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
807 struct r600_texture *rtex)
808 {
809 r600_texture_get_htile_size(rscreen, rtex);
810
811 if (!rtex->surface.meta_size)
812 return;
813
814 rtex->htile_offset = align(rtex->size, 1 << rtex->surface.meta_alignment_log2);
815 rtex->size = rtex->htile_offset + rtex->surface.meta_size;
816 }
817
r600_print_texture_info(struct r600_common_screen * rscreen,struct r600_texture * rtex,struct u_log_context * log)818 void r600_print_texture_info(struct r600_common_screen *rscreen,
819 struct r600_texture *rtex, struct u_log_context *log)
820 {
821 int i;
822
823 /* Common parameters. */
824 u_log_printf(log, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
825 "blk_h=%u, array_size=%u, last_level=%u, "
826 "bpe=%u, nsamples=%u, flags=0x%"PRIx64", %s\n",
827 rtex->resource.b.b.width0, rtex->resource.b.b.height0,
828 rtex->resource.b.b.depth0, rtex->surface.blk_w,
829 rtex->surface.blk_h,
830 rtex->resource.b.b.array_size, rtex->resource.b.b.last_level,
831 rtex->surface.bpe, rtex->resource.b.b.nr_samples,
832 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
833
834 u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
835 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
836 rtex->surface.surf_size, 1 << rtex->surface.surf_alignment_log2, rtex->surface.u.legacy.bankw,
837 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
838 rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config,
839 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
840
841 if (rtex->fmask.size)
842 u_log_printf(log, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, "
843 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
844 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
845 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
846 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
847
848 if (rtex->cmask.size)
849 u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, "
850 "slice_tile_max=%u\n",
851 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
852 rtex->cmask.slice_tile_max);
853
854 if (rtex->htile_offset)
855 u_log_printf(log, " HTile: offset=%"PRIu64", size=%u "
856 "alignment=%u\n",
857 rtex->htile_offset, rtex->surface.meta_size,
858 1 << rtex->surface.meta_alignment_log2);
859
860 for (i = 0; i <= rtex->resource.b.b.last_level; i++)
861 u_log_printf(log, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
862 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
863 "mode=%u, tiling_index = %u\n",
864 i, (uint64_t)rtex->surface.u.legacy.level[i].offset_256B * 256,
865 (uint64_t)rtex->surface.u.legacy.level[i].slice_size_dw * 4,
866 u_minify(rtex->resource.b.b.width0, i),
867 u_minify(rtex->resource.b.b.height0, i),
868 u_minify(rtex->resource.b.b.depth0, i),
869 rtex->surface.u.legacy.level[i].nblk_x,
870 rtex->surface.u.legacy.level[i].nblk_y,
871 rtex->surface.u.legacy.level[i].mode,
872 rtex->surface.u.legacy.tiling_index[i]);
873
874 if (rtex->surface.has_stencil) {
875 u_log_printf(log, " StencilLayout: tilesplit=%u\n",
876 rtex->surface.u.legacy.stencil_tile_split);
877 for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
878 u_log_printf(log, " StencilLevel[%i]: offset=%"PRIu64", "
879 "slice_size=%"PRIu64", npix_x=%u, "
880 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
881 "mode=%u, tiling_index = %u\n",
882 i, (uint64_t)rtex->surface.u.legacy.zs.stencil_level[i].offset_256B * 256,
883 (uint64_t)rtex->surface.u.legacy.zs.stencil_level[i].slice_size_dw * 4,
884 u_minify(rtex->resource.b.b.width0, i),
885 u_minify(rtex->resource.b.b.height0, i),
886 u_minify(rtex->resource.b.b.depth0, i),
887 rtex->surface.u.legacy.zs.stencil_level[i].nblk_x,
888 rtex->surface.u.legacy.zs.stencil_level[i].nblk_y,
889 rtex->surface.u.legacy.zs.stencil_level[i].mode,
890 rtex->surface.u.legacy.zs.stencil_tiling_index[i]);
891 }
892 }
893 }
894
895 /* Common processing for r600_texture_create and r600_texture_from_handle */
896 static struct r600_texture *
r600_texture_create_object(struct pipe_screen * screen,const struct pipe_resource * base,struct pb_buffer * buf,struct radeon_surf * surface)897 r600_texture_create_object(struct pipe_screen *screen,
898 const struct pipe_resource *base,
899 struct pb_buffer *buf,
900 struct radeon_surf *surface)
901 {
902 struct r600_texture *rtex;
903 struct r600_resource *resource;
904 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
905
906 rtex = CALLOC_STRUCT(r600_texture);
907 if (!rtex)
908 return NULL;
909
910 resource = &rtex->resource;
911 resource->b.b = *base;
912 pipe_reference_init(&resource->b.b.reference, 1);
913 resource->b.b.screen = screen;
914
915 /* don't include stencil-only formats which we don't support for rendering */
916 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
917
918 rtex->surface = *surface;
919 rtex->size = rtex->surface.surf_size;
920 rtex->db_render_format = base->format;
921
922 /* Tiled depth textures utilize the non-displayable tile order.
923 * This must be done after r600_setup_surface.
924 * Applies to R600-Cayman. */
925 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.u.legacy.level[0].mode >= RADEON_SURF_MODE_1D;
926 /* Applies to GCN. */
927 rtex->last_msaa_resolve_target_micro_mode = rtex->surface.micro_tile_mode;
928
929 if (rtex->is_depth) {
930 if (base->flags & (R600_RESOURCE_FLAG_TRANSFER |
931 R600_RESOURCE_FLAG_FLUSHED_DEPTH) ||
932 rscreen->gfx_level >= EVERGREEN) {
933 rtex->can_sample_z = !rtex->surface.u.legacy.depth_adjusted;
934 rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted;
935 } else {
936 if (rtex->resource.b.b.nr_samples <= 1 &&
937 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
938 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT))
939 rtex->can_sample_z = true;
940 }
941
942 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
943 R600_RESOURCE_FLAG_FLUSHED_DEPTH))) {
944 rtex->db_compatible = true;
945
946 if (!(rscreen->debug_flags & DBG_NO_HYPERZ))
947 r600_texture_allocate_htile(rscreen, rtex);
948 }
949 } else {
950 if (base->nr_samples > 1) {
951 if (!buf) {
952 r600_texture_allocate_fmask(rscreen, rtex);
953 r600_texture_allocate_cmask(rscreen, rtex);
954 rtex->cmask_buffer = &rtex->resource;
955 }
956 if (!rtex->fmask.size || !rtex->cmask.size) {
957 FREE(rtex);
958 return NULL;
959 }
960 }
961 }
962
963 /* Now create the backing buffer. */
964 if (!buf) {
965 r600_init_resource_fields(rscreen, resource, rtex->size,
966 1 << rtex->surface.surf_alignment_log2);
967
968 if (!r600_alloc_resource(rscreen, resource)) {
969 FREE(rtex);
970 return NULL;
971 }
972 } else {
973 resource->buf = buf;
974 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
975 resource->bo_size = buf->size;
976 resource->bo_alignment = 1 << buf->alignment_log2;
977 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
978 if (resource->domains & RADEON_DOMAIN_VRAM)
979 resource->vram_usage = buf->size;
980 else if (resource->domains & RADEON_DOMAIN_GTT)
981 resource->gart_usage = buf->size;
982 }
983
984 if (rtex->cmask.size) {
985 /* Initialize the cmask to 0xCC (= compressed state). */
986 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
987 rtex->cmask.offset, rtex->cmask.size,
988 0xCCCCCCCC);
989 }
990 if (rtex->htile_offset) {
991 uint32_t clear_value = 0;
992
993 r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
994 rtex->htile_offset,
995 rtex->surface.meta_size,
996 clear_value);
997 }
998
999 /* Initialize the CMASK base register value. */
1000 rtex->cmask.base_address_reg =
1001 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1002
1003 if (rscreen->debug_flags & DBG_VM) {
1004 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1005 rtex->resource.gpu_address,
1006 rtex->resource.gpu_address + rtex->resource.buf->size,
1007 base->width0, base->height0, util_num_layers(base, 0), base->last_level+1,
1008 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
1009 }
1010
1011 if (rscreen->debug_flags & DBG_TEX) {
1012 puts("Texture:");
1013 struct u_log_context log;
1014 u_log_context_init(&log);
1015 r600_print_texture_info(rscreen, rtex, &log);
1016 u_log_new_page_print(&log, stdout);
1017 fflush(stdout);
1018 u_log_context_destroy(&log);
1019 }
1020
1021 return rtex;
1022 }
1023
1024 static enum radeon_surf_mode
r600_choose_tiling(struct r600_common_screen * rscreen,const struct pipe_resource * templ)1025 r600_choose_tiling(struct r600_common_screen *rscreen,
1026 const struct pipe_resource *templ)
1027 {
1028 const struct util_format_description *desc = util_format_description(templ->format);
1029 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
1030 bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
1031 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
1032
1033 /* MSAA resources must be 2D tiled. */
1034 if (templ->nr_samples > 1)
1035 return RADEON_SURF_MODE_2D;
1036
1037 /* Transfer resources should be linear. */
1038 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
1039 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1040
1041 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1042 if (rscreen->gfx_level >= R600 && rscreen->gfx_level <= CAYMAN &&
1043 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
1044 (templ->target == PIPE_TEXTURE_2D ||
1045 templ->target == PIPE_TEXTURE_3D))
1046 force_tiling = true;
1047
1048 /* Handle common candidates for the linear mode.
1049 * Compressed textures and DB surfaces must always be tiled.
1050 */
1051 if (!force_tiling &&
1052 !is_depth_stencil &&
1053 !util_format_is_compressed(templ->format)) {
1054 if (rscreen->debug_flags & DBG_NO_TILING)
1055 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1056
1057 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1058 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
1059 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1060
1061 if (templ->bind & PIPE_BIND_LINEAR)
1062 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1063
1064 /* 1D textures should be linear - fixes image operations on 1d */
1065 if (templ->target == PIPE_TEXTURE_1D ||
1066 templ->target == PIPE_TEXTURE_1D_ARRAY)
1067 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1068
1069 /* Textures likely to be mapped often. */
1070 if (templ->usage == PIPE_USAGE_STAGING ||
1071 templ->usage == PIPE_USAGE_STREAM)
1072 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1073 }
1074
1075 /* Make small textures 1D tiled. */
1076 if (templ->width0 <= 16 || templ->height0 <= 16 ||
1077 (rscreen->debug_flags & DBG_NO_2D_TILING))
1078 return RADEON_SURF_MODE_1D;
1079
1080 /* The allocator will switch to 1D if needed. */
1081 return RADEON_SURF_MODE_2D;
1082 }
1083
r600_texture_create(struct pipe_screen * screen,const struct pipe_resource * templ)1084 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
1085 const struct pipe_resource *templ)
1086 {
1087 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1088 struct radeon_surf surface = {0};
1089 bool is_flushed_depth = templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1090 int r;
1091
1092 r = r600_init_surface(rscreen, &surface, templ,
1093 r600_choose_tiling(rscreen, templ), 0, 0,
1094 false, false, is_flushed_depth);
1095 if (r) {
1096 return NULL;
1097 }
1098
1099 return (struct pipe_resource *)
1100 r600_texture_create_object(screen, templ, NULL, &surface);
1101 }
1102
r600_texture_from_handle(struct pipe_screen * screen,const struct pipe_resource * templ,struct winsys_handle * whandle,unsigned usage)1103 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
1104 const struct pipe_resource *templ,
1105 struct winsys_handle *whandle,
1106 unsigned usage)
1107 {
1108 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1109 struct pb_buffer *buf = NULL;
1110 enum radeon_surf_mode array_mode;
1111 struct radeon_surf surface = {};
1112 int r;
1113 struct radeon_bo_metadata metadata = {};
1114 struct r600_texture *rtex;
1115 bool is_scanout;
1116
1117 /* Support only 2D textures without mipmaps */
1118 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
1119 templ->depth0 != 1 || templ->last_level != 0)
1120 return NULL;
1121
1122 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
1123 rscreen->info.max_alignment, false);
1124 if (!buf)
1125 return NULL;
1126
1127 rscreen->ws->buffer_get_metadata(rscreen->ws, buf, &metadata, NULL);
1128 r600_surface_import_metadata(rscreen, &surface, &metadata,
1129 &array_mode, &is_scanout);
1130
1131 r = r600_init_surface(rscreen, &surface, templ, array_mode,
1132 whandle->stride, whandle->offset,
1133 true, is_scanout, false);
1134 if (r) {
1135 return NULL;
1136 }
1137
1138 rtex = r600_texture_create_object(screen, templ, buf, &surface);
1139 if (!rtex)
1140 return NULL;
1141
1142 rtex->resource.b.is_shared = true;
1143 rtex->resource.external_usage = usage;
1144
1145 assert(rtex->surface.tile_swizzle == 0);
1146 return &rtex->resource.b.b;
1147 }
1148
r600_init_flushed_depth_texture(struct pipe_context * ctx,struct pipe_resource * texture,struct r600_texture ** staging)1149 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
1150 struct pipe_resource *texture,
1151 struct r600_texture **staging)
1152 {
1153 struct r600_texture *rtex = (struct r600_texture*)texture;
1154 struct pipe_resource resource;
1155 struct r600_texture **flushed_depth_texture = staging ?
1156 staging : &rtex->flushed_depth_texture;
1157 enum pipe_format pipe_format = texture->format;
1158
1159 if (!staging) {
1160 if (rtex->flushed_depth_texture)
1161 return true; /* it's ready */
1162
1163 if (!rtex->can_sample_z && rtex->can_sample_s) {
1164 switch (pipe_format) {
1165 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1166 /* Save memory by not allocating the S plane. */
1167 pipe_format = PIPE_FORMAT_Z32_FLOAT;
1168 break;
1169 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1170 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1171 /* Save memory bandwidth by not copying the
1172 * stencil part during flush.
1173 *
1174 * This potentially increases memory bandwidth
1175 * if an application uses both Z and S texturing
1176 * simultaneously (a flushed Z24S8 texture
1177 * would be stored compactly), but how often
1178 * does that really happen?
1179 */
1180 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
1181 break;
1182 default:;
1183 }
1184 } else if (!rtex->can_sample_s && rtex->can_sample_z) {
1185 assert(util_format_has_stencil(util_format_description(pipe_format)));
1186
1187 /* DB->CB copies to an 8bpp surface don't work. */
1188 pipe_format = PIPE_FORMAT_X24S8_UINT;
1189 }
1190 }
1191
1192 memset(&resource, 0, sizeof(resource));
1193 resource.target = texture->target;
1194 resource.format = pipe_format;
1195 resource.width0 = texture->width0;
1196 resource.height0 = texture->height0;
1197 resource.depth0 = texture->depth0;
1198 resource.array_size = texture->array_size;
1199 resource.last_level = texture->last_level;
1200 resource.nr_samples = texture->nr_samples;
1201 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1202 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
1203 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1204
1205 if (staging)
1206 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
1207
1208 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
1209 if (*flushed_depth_texture == NULL) {
1210 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1211 return false;
1212 }
1213
1214 (*flushed_depth_texture)->non_disp_tiling = false;
1215 return true;
1216 }
1217
1218 /**
1219 * Initialize the pipe_resource descriptor to be of the same size as the box,
1220 * which is supposed to hold a subregion of the texture "orig" at the given
1221 * mipmap level.
1222 */
r600_init_temp_resource_from_box(struct pipe_resource * res,struct pipe_resource * orig,const struct pipe_box * box,unsigned level,unsigned flags)1223 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1224 struct pipe_resource *orig,
1225 const struct pipe_box *box,
1226 unsigned level, unsigned flags)
1227 {
1228 memset(res, 0, sizeof(*res));
1229 res->format = orig->format;
1230 res->width0 = box->width;
1231 res->height0 = box->height;
1232 res->depth0 = 1;
1233 res->array_size = 1;
1234 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1235 res->flags = flags;
1236
1237 /* We must set the correct texture target and dimensions for a 3D box. */
1238 if (box->depth > 1 && util_max_layer(orig, level) > 0) {
1239 res->target = PIPE_TEXTURE_2D_ARRAY;
1240 res->array_size = box->depth;
1241 } else {
1242 res->target = PIPE_TEXTURE_2D;
1243 }
1244 }
1245
r600_can_invalidate_texture(struct r600_common_screen * rscreen,struct r600_texture * rtex,unsigned transfer_usage,const struct pipe_box * box)1246 static bool r600_can_invalidate_texture(struct r600_common_screen *rscreen,
1247 struct r600_texture *rtex,
1248 unsigned transfer_usage,
1249 const struct pipe_box *box)
1250 {
1251 /* r600g doesn't react to dirty_tex_descriptor_counter */
1252 return rscreen->gfx_level >= GFX6 &&
1253 !rtex->resource.b.is_shared &&
1254 !(transfer_usage & PIPE_MAP_READ) &&
1255 rtex->resource.b.b.last_level == 0 &&
1256 util_texrange_covers_whole_level(&rtex->resource.b.b, 0,
1257 box->x, box->y, box->z,
1258 box->width, box->height,
1259 box->depth);
1260 }
1261
r600_texture_invalidate_storage(struct r600_common_context * rctx,struct r600_texture * rtex)1262 static void r600_texture_invalidate_storage(struct r600_common_context *rctx,
1263 struct r600_texture *rtex)
1264 {
1265 struct r600_common_screen *rscreen = rctx->screen;
1266
1267 /* There is no point in discarding depth and tiled buffers. */
1268 assert(!rtex->is_depth);
1269 assert(rtex->surface.is_linear);
1270
1271 /* Reallocate the buffer in the same pipe_resource. */
1272 r600_alloc_resource(rscreen, &rtex->resource);
1273
1274 /* Initialize the CMASK base address (needed even without CMASK). */
1275 rtex->cmask.base_address_reg =
1276 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1277
1278 p_atomic_inc(&rscreen->dirty_tex_counter);
1279
1280 rctx->num_alloc_tex_transfer_bytes += rtex->size;
1281 }
1282
r600_texture_transfer_map(struct pipe_context * ctx,struct pipe_resource * texture,unsigned level,unsigned usage,const struct pipe_box * box,struct pipe_transfer ** ptransfer)1283 void *r600_texture_transfer_map(struct pipe_context *ctx,
1284 struct pipe_resource *texture,
1285 unsigned level,
1286 unsigned usage,
1287 const struct pipe_box *box,
1288 struct pipe_transfer **ptransfer)
1289 {
1290 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1291 struct r600_texture *rtex = (struct r600_texture*)texture;
1292 struct r600_transfer *trans;
1293 struct r600_resource *buf;
1294 unsigned offset = 0;
1295 char *map;
1296 bool use_staging_texture = false;
1297
1298 assert(!(texture->flags & R600_RESOURCE_FLAG_TRANSFER));
1299 assert(box->width && box->height && box->depth);
1300
1301 /* Depth textures use staging unconditionally. */
1302 if (!rtex->is_depth) {
1303 /* Degrade the tile mode if we get too many transfers on APUs.
1304 * On dGPUs, the staging texture is always faster.
1305 * Only count uploads that are at least 4x4 pixels large.
1306 */
1307 if (!rctx->screen->info.has_dedicated_vram &&
1308 level == 0 &&
1309 box->width >= 4 && box->height >= 4 &&
1310 p_atomic_inc_return(&rtex->num_level0_transfers) == 10) {
1311 bool can_invalidate =
1312 r600_can_invalidate_texture(rctx->screen, rtex,
1313 usage, box);
1314
1315 r600_reallocate_texture_inplace(rctx, rtex,
1316 PIPE_BIND_LINEAR,
1317 can_invalidate);
1318 }
1319
1320 /* Tiled textures need to be converted into a linear texture for CPU
1321 * access. The staging texture is always linear and is placed in GART.
1322 *
1323 * Reading from VRAM or GTT WC is slow, always use the staging
1324 * texture in this case.
1325 *
1326 * Use the staging texture for uploads if the underlying BO
1327 * is busy.
1328 */
1329 if (!rtex->surface.is_linear)
1330 use_staging_texture = true;
1331 else if (usage & PIPE_MAP_READ)
1332 use_staging_texture =
1333 rtex->resource.domains & RADEON_DOMAIN_VRAM ||
1334 rtex->resource.flags & RADEON_FLAG_GTT_WC;
1335 /* Write & linear only: */
1336 else if (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf,
1337 RADEON_USAGE_READWRITE) ||
1338 !rctx->ws->buffer_wait(rctx->ws, rtex->resource.buf, 0,
1339 RADEON_USAGE_READWRITE)) {
1340 /* It's busy. */
1341 if (r600_can_invalidate_texture(rctx->screen, rtex,
1342 usage, box))
1343 r600_texture_invalidate_storage(rctx, rtex);
1344 else
1345 use_staging_texture = true;
1346 }
1347 }
1348
1349 trans = CALLOC_STRUCT(r600_transfer);
1350 if (!trans)
1351 return NULL;
1352 pipe_resource_reference(&trans->b.b.resource, texture);
1353 trans->b.b.level = level;
1354 trans->b.b.usage = usage;
1355 trans->b.b.box = *box;
1356
1357 if (rtex->is_depth) {
1358 struct r600_texture *staging_depth;
1359
1360 if (rtex->resource.b.b.nr_samples > 1) {
1361 /* MSAA depth buffers need to be converted to single sample buffers.
1362 *
1363 * Mapping MSAA depth buffers can occur if ReadPixels is called
1364 * with a multisample GLX visual.
1365 *
1366 * First downsample the depth buffer to a temporary texture,
1367 * then decompress the temporary one to staging.
1368 *
1369 * Only the region being mapped is transfered.
1370 */
1371 struct pipe_resource resource;
1372
1373 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1374
1375 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1376 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1377 FREE(trans);
1378 return NULL;
1379 }
1380
1381 if (usage & PIPE_MAP_READ) {
1382 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1383 if (!temp) {
1384 R600_ERR("failed to create a temporary depth texture\n");
1385 FREE(trans);
1386 return NULL;
1387 }
1388
1389 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1390 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1391 0, 0, 0, box->depth, 0, 0);
1392 pipe_resource_reference(&temp, NULL);
1393 }
1394
1395 /* Just get the strides. */
1396 r600_texture_get_offset(rctx->screen, staging_depth, level, NULL,
1397 &trans->b.b.stride,
1398 &trans->b.b.layer_stride);
1399 } else {
1400 /* XXX: only readback the rectangle which is being mapped? */
1401 /* XXX: when discard is true, no need to read back from depth texture */
1402 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1403 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1404 FREE(trans);
1405 return NULL;
1406 }
1407
1408 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1409 level, level,
1410 box->z, box->z + box->depth - 1,
1411 0, 0);
1412
1413 offset = r600_texture_get_offset(rctx->screen, staging_depth,
1414 level, box,
1415 &trans->b.b.stride,
1416 &trans->b.b.layer_stride);
1417 }
1418
1419 trans->staging = (struct r600_resource*)staging_depth;
1420 buf = trans->staging;
1421 } else if (use_staging_texture) {
1422 struct pipe_resource resource;
1423 struct r600_texture *staging;
1424
1425 r600_init_temp_resource_from_box(&resource, texture, box, level,
1426 R600_RESOURCE_FLAG_TRANSFER);
1427 resource.usage = (usage & PIPE_MAP_READ) ?
1428 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1429
1430 /* Create the temporary texture. */
1431 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1432 if (!staging) {
1433 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1434 FREE(trans);
1435 return NULL;
1436 }
1437 trans->staging = &staging->resource;
1438
1439 /* Just get the strides. */
1440 r600_texture_get_offset(rctx->screen, staging, 0, NULL,
1441 &trans->b.b.stride,
1442 &trans->b.b.layer_stride);
1443
1444 if (usage & PIPE_MAP_READ)
1445 r600_copy_to_staging_texture(ctx, trans);
1446 else
1447 usage |= PIPE_MAP_UNSYNCHRONIZED;
1448
1449 buf = trans->staging;
1450 } else {
1451 /* the resource is mapped directly */
1452 offset = r600_texture_get_offset(rctx->screen, rtex, level, box,
1453 &trans->b.b.stride,
1454 &trans->b.b.layer_stride);
1455 buf = &rtex->resource;
1456 }
1457
1458 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1459 r600_resource_reference(&trans->staging, NULL);
1460 FREE(trans);
1461 return NULL;
1462 }
1463
1464 *ptransfer = &trans->b.b;
1465 return map + offset;
1466 }
1467
r600_texture_transfer_unmap(struct pipe_context * ctx,struct pipe_transfer * transfer)1468 void r600_texture_transfer_unmap(struct pipe_context *ctx,
1469 struct pipe_transfer* transfer)
1470 {
1471 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1472 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1473 struct pipe_resource *texture = transfer->resource;
1474 struct r600_texture *rtex = (struct r600_texture*)texture;
1475
1476 if ((transfer->usage & PIPE_MAP_WRITE) && rtransfer->staging) {
1477 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1478 ctx->resource_copy_region(ctx, texture, transfer->level,
1479 transfer->box.x, transfer->box.y, transfer->box.z,
1480 &rtransfer->staging->b.b, transfer->level,
1481 &transfer->box);
1482 } else {
1483 r600_copy_from_staging_texture(ctx, rtransfer);
1484 }
1485 }
1486
1487 if (rtransfer->staging) {
1488 rctx->num_alloc_tex_transfer_bytes += rtransfer->staging->buf->size;
1489 r600_resource_reference(&rtransfer->staging, NULL);
1490 }
1491
1492 /* Heuristic for {upload, draw, upload, draw, ..}:
1493 *
1494 * Flush the gfx IB if we've allocated too much texture storage.
1495 *
1496 * The idea is that we don't want to build IBs that use too much
1497 * memory and put pressure on the kernel memory manager and we also
1498 * want to make temporary and invalidated buffers go idle ASAP to
1499 * decrease the total memory usage or make them reusable. The memory
1500 * usage will be slightly higher than given here because of the buffer
1501 * cache in the winsys.
1502 *
1503 * The result is that the kernel memory manager is never a bottleneck.
1504 */
1505 if (rctx->num_alloc_tex_transfer_bytes > (uint64_t)rctx->screen->info.gart_size_kb * 1024 / 4) {
1506 rctx->gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
1507 rctx->num_alloc_tex_transfer_bytes = 0;
1508 }
1509
1510 pipe_resource_reference(&transfer->resource, NULL);
1511 FREE(transfer);
1512 }
1513
r600_create_surface_custom(struct pipe_context * pipe,struct pipe_resource * texture,const struct pipe_surface * templ,unsigned width0,unsigned height0,unsigned width,unsigned height)1514 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1515 struct pipe_resource *texture,
1516 const struct pipe_surface *templ,
1517 unsigned width0, unsigned height0,
1518 unsigned width, unsigned height)
1519 {
1520 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1521
1522 if (!surface)
1523 return NULL;
1524
1525 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1526 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1527
1528 pipe_reference_init(&surface->base.reference, 1);
1529 pipe_resource_reference(&surface->base.texture, texture);
1530 surface->base.context = pipe;
1531 surface->base.format = templ->format;
1532 surface->base.width = width;
1533 surface->base.height = height;
1534 surface->base.u = templ->u;
1535
1536 surface->width0 = width0;
1537 surface->height0 = height0;
1538
1539 return &surface->base;
1540 }
1541
r600_create_surface(struct pipe_context * pipe,struct pipe_resource * tex,const struct pipe_surface * templ)1542 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1543 struct pipe_resource *tex,
1544 const struct pipe_surface *templ)
1545 {
1546 unsigned level = templ->u.tex.level;
1547 unsigned width = u_minify(tex->width0, level);
1548 unsigned height = u_minify(tex->height0, level);
1549 unsigned width0 = tex->width0;
1550 unsigned height0 = tex->height0;
1551
1552 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1553 const struct util_format_description *tex_desc
1554 = util_format_description(tex->format);
1555 const struct util_format_description *templ_desc
1556 = util_format_description(templ->format);
1557
1558 assert(tex_desc->block.bits == templ_desc->block.bits);
1559
1560 /* Adjust size of surface if and only if the block width or
1561 * height is changed. */
1562 if (tex_desc->block.width != templ_desc->block.width ||
1563 tex_desc->block.height != templ_desc->block.height) {
1564 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1565 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1566
1567 width = nblks_x * templ_desc->block.width;
1568 height = nblks_y * templ_desc->block.height;
1569
1570 width0 = util_format_get_nblocksx(tex->format, width0);
1571 height0 = util_format_get_nblocksy(tex->format, height0);
1572 }
1573 }
1574
1575 return r600_create_surface_custom(pipe, tex, templ,
1576 width0, height0,
1577 width, height);
1578 }
1579
r600_surface_destroy(struct pipe_context * pipe,struct pipe_surface * surface)1580 static void r600_surface_destroy(struct pipe_context *pipe,
1581 struct pipe_surface *surface)
1582 {
1583 struct r600_surface *surf = (struct r600_surface*)surface;
1584 r600_resource_reference(&surf->cb_buffer_fmask, NULL);
1585 r600_resource_reference(&surf->cb_buffer_cmask, NULL);
1586 pipe_resource_reference(&surface->texture, NULL);
1587 FREE(surface);
1588 }
1589
r600_clear_texture(struct pipe_context * pipe,struct pipe_resource * tex,unsigned level,const struct pipe_box * box,const void * data)1590 static void r600_clear_texture(struct pipe_context *pipe,
1591 struct pipe_resource *tex,
1592 unsigned level,
1593 const struct pipe_box *box,
1594 const void *data)
1595 {
1596 struct pipe_screen *screen = pipe->screen;
1597 struct r600_texture *rtex = (struct r600_texture*)tex;
1598 struct pipe_surface tmpl = {{0}};
1599 struct pipe_surface *sf;
1600
1601 tmpl.format = tex->format;
1602 tmpl.u.tex.first_layer = box->z;
1603 tmpl.u.tex.last_layer = box->z + box->depth - 1;
1604 tmpl.u.tex.level = level;
1605 sf = pipe->create_surface(pipe, tex, &tmpl);
1606 if (!sf)
1607 return;
1608
1609 if (rtex->is_depth) {
1610 unsigned clear;
1611 float depth;
1612 uint8_t stencil = 0;
1613
1614 /* Depth is always present. */
1615 clear = PIPE_CLEAR_DEPTH;
1616 util_format_unpack_z_float(tex->format, &depth, data, 1);
1617
1618 if (rtex->surface.has_stencil) {
1619 clear |= PIPE_CLEAR_STENCIL;
1620 util_format_unpack_s_8uint(tex->format, &stencil, data, 1);
1621 }
1622
1623 pipe->clear_depth_stencil(pipe, sf, clear, depth, stencil,
1624 box->x, box->y,
1625 box->width, box->height, false);
1626 } else {
1627 union pipe_color_union color;
1628
1629 util_format_unpack_rgba(tex->format, color.ui, data, 1);
1630
1631 if (screen->is_format_supported(screen, tex->format,
1632 tex->target, 0, 0,
1633 PIPE_BIND_RENDER_TARGET)) {
1634 pipe->clear_render_target(pipe, sf, &color,
1635 box->x, box->y,
1636 box->width, box->height, false);
1637 } else {
1638 /* Software fallback - just for R9G9B9E5_FLOAT */
1639 util_clear_render_target(pipe, sf, &color,
1640 box->x, box->y,
1641 box->width, box->height);
1642 }
1643 }
1644 pipe_surface_reference(&sf, NULL);
1645 }
1646
r600_translate_colorswap(enum pipe_format format,bool do_endian_swap)1647 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap)
1648 {
1649 const struct util_format_description *desc = util_format_description(format);
1650
1651 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1652
1653 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1654 return V_0280A0_SWAP_STD;
1655
1656 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1657 return ~0U;
1658
1659 switch (desc->nr_channels) {
1660 case 1:
1661 if (HAS_SWIZZLE(0,X))
1662 return V_0280A0_SWAP_STD; /* X___ */
1663 else if (HAS_SWIZZLE(3,X))
1664 return V_0280A0_SWAP_ALT_REV; /* ___X */
1665 break;
1666 case 2:
1667 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1668 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1669 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1670 return V_0280A0_SWAP_STD; /* XY__ */
1671 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1672 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1673 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1674 /* YX__ */
1675 return (do_endian_swap ? V_0280A0_SWAP_STD : V_0280A0_SWAP_STD_REV);
1676 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1677 return V_0280A0_SWAP_ALT; /* X__Y */
1678 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1679 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1680 break;
1681 case 3:
1682 if (HAS_SWIZZLE(0,X))
1683 return (do_endian_swap ? V_0280A0_SWAP_STD_REV : V_0280A0_SWAP_STD);
1684 else if (HAS_SWIZZLE(0,Z))
1685 return V_0280A0_SWAP_STD_REV; /* ZYX */
1686 break;
1687 case 4:
1688 /* check the middle channels, the 1st and 4th channel can be NONE */
1689 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) {
1690 return V_0280A0_SWAP_STD; /* XYZW */
1691 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) {
1692 return V_0280A0_SWAP_STD_REV; /* WZYX */
1693 } else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) {
1694 return V_0280A0_SWAP_ALT; /* ZYXW */
1695 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) {
1696 /* YZWX */
1697 if (desc->is_array)
1698 return V_0280A0_SWAP_ALT_REV;
1699 else
1700 return (do_endian_swap ? V_0280A0_SWAP_ALT : V_0280A0_SWAP_ALT_REV);
1701 }
1702 break;
1703 }
1704 return ~0U;
1705 }
1706
1707 /* FAST COLOR CLEAR */
1708
evergreen_set_clear_color(struct r600_texture * rtex,enum pipe_format surface_format,const union pipe_color_union * color)1709 static void evergreen_set_clear_color(struct r600_texture *rtex,
1710 enum pipe_format surface_format,
1711 const union pipe_color_union *color)
1712 {
1713 union util_color uc;
1714
1715 memset(&uc, 0, sizeof(uc));
1716
1717 if (rtex->surface.bpe == 16) {
1718 /* DCC fast clear only:
1719 * CLEAR_WORD0 = R = G = B
1720 * CLEAR_WORD1 = A
1721 */
1722 assert(color->ui[0] == color->ui[1] &&
1723 color->ui[0] == color->ui[2]);
1724 uc.ui[0] = color->ui[0];
1725 uc.ui[1] = color->ui[3];
1726 } else {
1727 util_pack_color_union(surface_format, &uc, color);
1728 }
1729
1730 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1731 }
1732
evergreen_do_fast_color_clear(struct r600_common_context * rctx,struct pipe_framebuffer_state * fb,struct r600_atom * fb_state,unsigned * buffers,ubyte * dirty_cbufs,const union pipe_color_union * color)1733 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1734 struct pipe_framebuffer_state *fb,
1735 struct r600_atom *fb_state,
1736 unsigned *buffers, ubyte *dirty_cbufs,
1737 const union pipe_color_union *color)
1738 {
1739 int i;
1740
1741 /* This function is broken in BE, so just disable this path for now */
1742 #if UTIL_ARCH_BIG_ENDIAN
1743 return;
1744 #endif
1745
1746 if (rctx->render_cond)
1747 return;
1748
1749 for (i = 0; i < fb->nr_cbufs; i++) {
1750 struct r600_texture *tex;
1751 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1752
1753 if (!fb->cbufs[i])
1754 continue;
1755
1756 /* if this colorbuffer is not being cleared */
1757 if (!(*buffers & clear_bit))
1758 continue;
1759
1760 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1761
1762 /* the clear is allowed if all layers are bound */
1763 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1764 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1765 continue;
1766 }
1767
1768 /* cannot clear mipmapped textures */
1769 if (fb->cbufs[i]->texture->last_level != 0) {
1770 continue;
1771 }
1772
1773 /* only supported on tiled surfaces */
1774 if (tex->surface.is_linear) {
1775 continue;
1776 }
1777
1778 /* shared textures can't use fast clear without an explicit flush,
1779 * because there is no way to communicate the clear color among
1780 * all clients
1781 */
1782 if (tex->resource.b.is_shared &&
1783 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
1784 continue;
1785
1786 /* Use a slow clear for small surfaces where the cost of
1787 * the eliminate pass can be higher than the benefit of fast
1788 * clear. AMDGPU-pro does this, but the numbers may differ.
1789 *
1790 * This helps on both dGPUs and APUs, even small ones.
1791 */
1792 if (tex->resource.b.b.nr_samples <= 1 &&
1793 tex->resource.b.b.width0 * tex->resource.b.b.height0 <= 300 * 300)
1794 continue;
1795
1796 {
1797 /* 128-bit formats are unusupported */
1798 if (tex->surface.bpe > 8) {
1799 continue;
1800 }
1801
1802 /* ensure CMASK is enabled */
1803 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1804 if (tex->cmask.size == 0) {
1805 continue;
1806 }
1807
1808 /* Do the fast clear. */
1809 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1810 tex->cmask.offset, tex->cmask.size, 0,
1811 R600_COHERENCY_CB_META);
1812
1813 bool need_compressed_update = !tex->dirty_level_mask;
1814
1815 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1816
1817 if (need_compressed_update)
1818 p_atomic_inc(&rctx->screen->compressed_colortex_counter);
1819 }
1820
1821 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1822
1823 if (dirty_cbufs)
1824 *dirty_cbufs |= 1 << i;
1825 rctx->set_atom_dirty(rctx, fb_state, true);
1826 *buffers &= ~clear_bit;
1827 }
1828 }
1829
1830 static struct pipe_memory_object *
r600_memobj_from_handle(struct pipe_screen * screen,struct winsys_handle * whandle,bool dedicated)1831 r600_memobj_from_handle(struct pipe_screen *screen,
1832 struct winsys_handle *whandle,
1833 bool dedicated)
1834 {
1835 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1836 struct r600_memory_object *memobj = CALLOC_STRUCT(r600_memory_object);
1837 struct pb_buffer *buf = NULL;
1838
1839 if (!memobj)
1840 return NULL;
1841
1842 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
1843 rscreen->info.max_alignment, false);
1844 if (!buf) {
1845 free(memobj);
1846 return NULL;
1847 }
1848
1849 memobj->b.dedicated = dedicated;
1850 memobj->buf = buf;
1851 memobj->stride = whandle->stride;
1852 memobj->offset = whandle->offset;
1853
1854 return (struct pipe_memory_object *)memobj;
1855
1856 }
1857
1858 static void
r600_memobj_destroy(struct pipe_screen * screen,struct pipe_memory_object * _memobj)1859 r600_memobj_destroy(struct pipe_screen *screen,
1860 struct pipe_memory_object *_memobj)
1861 {
1862 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
1863
1864 pb_reference(&memobj->buf, NULL);
1865 free(memobj);
1866 }
1867
1868 static struct pipe_resource *
r600_texture_from_memobj(struct pipe_screen * screen,const struct pipe_resource * templ,struct pipe_memory_object * _memobj,uint64_t offset)1869 r600_texture_from_memobj(struct pipe_screen *screen,
1870 const struct pipe_resource *templ,
1871 struct pipe_memory_object *_memobj,
1872 uint64_t offset)
1873 {
1874 int r;
1875 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1876 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
1877 struct r600_texture *rtex;
1878 struct radeon_surf surface = {};
1879 struct radeon_bo_metadata metadata = {};
1880 enum radeon_surf_mode array_mode;
1881 bool is_scanout;
1882 struct pb_buffer *buf = NULL;
1883
1884 if (memobj->b.dedicated) {
1885 rscreen->ws->buffer_get_metadata(rscreen->ws, memobj->buf, &metadata, NULL);
1886 r600_surface_import_metadata(rscreen, &surface, &metadata,
1887 &array_mode, &is_scanout);
1888 } else {
1889 /**
1890 * The bo metadata is unset for un-dedicated images. So we fall
1891 * back to linear. See answer to question 5 of the
1892 * VK_KHX_external_memory spec for some details.
1893 *
1894 * It is possible that this case isn't going to work if the
1895 * surface pitch isn't correctly aligned by default.
1896 *
1897 * In order to support it correctly we require multi-image
1898 * metadata to be syncrhonized between radv and radeonsi. The
1899 * semantics of associating multiple image metadata to a memory
1900 * object on the vulkan export side are not concretely defined
1901 * either.
1902 *
1903 * All the use cases we are aware of at the moment for memory
1904 * objects use dedicated allocations. So lets keep the initial
1905 * implementation simple.
1906 *
1907 * A possible alternative is to attempt to reconstruct the
1908 * tiling information when the TexParameter TEXTURE_TILING_EXT
1909 * is set.
1910 */
1911 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1912 is_scanout = false;
1913
1914 }
1915
1916 r = r600_init_surface(rscreen, &surface, templ,
1917 array_mode, memobj->stride,
1918 offset, true, is_scanout,
1919 false);
1920 if (r)
1921 return NULL;
1922
1923 rtex = r600_texture_create_object(screen, templ, memobj->buf, &surface);
1924 if (!rtex)
1925 return NULL;
1926
1927 /* r600_texture_create_object doesn't increment refcount of
1928 * memobj->buf, so increment it here.
1929 */
1930 pb_reference(&buf, memobj->buf);
1931
1932 rtex->resource.b.is_shared = true;
1933 rtex->resource.external_usage = PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE;
1934
1935 return &rtex->resource.b.b;
1936 }
1937
r600_init_screen_texture_functions(struct r600_common_screen * rscreen)1938 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1939 {
1940 rscreen->b.resource_from_handle = r600_texture_from_handle;
1941 rscreen->b.resource_get_handle = r600_texture_get_handle;
1942 rscreen->b.resource_get_info = r600_texture_get_info;
1943 rscreen->b.resource_from_memobj = r600_texture_from_memobj;
1944 rscreen->b.memobj_create_from_handle = r600_memobj_from_handle;
1945 rscreen->b.memobj_destroy = r600_memobj_destroy;
1946 }
1947
r600_init_context_texture_functions(struct r600_common_context * rctx)1948 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1949 {
1950 rctx->b.create_surface = r600_create_surface;
1951 rctx->b.surface_destroy = r600_surface_destroy;
1952 rctx->b.clear_texture = r600_clear_texture;
1953 }
1954