1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #pragma once 19 20 #include "../sys.h" 21 22 #define LM_BASE 0x80000000 23 24 #define ILM_BASE (LM_BASE + 0x40000000) 25 #define DLM_BASE (LM_BASE + 0x40200000) 26 #define CPU_ILM_BASE (0x00000000) 27 #define CPU_DLM_BASE (0x00080000) 28 29 #define SC_BASE_ADDR 0x1401c0 30 /******************************* reset registers: 1401e0 ******************************/ 31 #define reg_rst REG_ADDR32(0x1401e0) 32 33 #define reg_rst0 REG_ADDR8(0x1401e0) 34 enum { 35 FLD_RST0_HSPI = BIT(0), 36 FLD_RST0_I2C = BIT(1), 37 FLD_RST0_UART0 = BIT(2), 38 FLD_RST0_USB = BIT(3), 39 FLD_RST0_PWM = BIT(4), 40 // RSVD 41 FLD_RST0_UART1 = BIT(6), 42 FLD_RST0_SWIRE = BIT(7), 43 }; 44 45 #define reg_rst1 REG_ADDR8(0x1401e1) 46 enum { 47 // RSVD 48 FLD_RST1_SYS_STIMER = BIT(1), 49 FLD_RST1_DMA = BIT(2), 50 FLD_RST1_ALGM = BIT(3), 51 FLD_RST1_PKE = BIT(4), 52 // RSVD 53 FLD_RST1_PSPI = BIT(6), 54 FLD_RST1_SPISLV = BIT(7), 55 }; 56 57 #define reg_rst2 REG_ADDR8(0x1401e2) 58 enum { 59 FLD_RST2_TIMER = BIT(0), 60 FLD_RST2_AUD = BIT(1), 61 FLD_RST2_TRNG = BIT(2), 62 // RSVD 63 FLD_RST2_MCU = BIT(4), 64 FLD_RST2_LM = BIT(5), 65 FLD_RST2_NPE = BIT(6), 66 // RSVD 67 }; 68 69 #define reg_rst3 REG_ADDR8(0x1401e3) 70 enum { 71 FLD_RST3_ZB = BIT(0), 72 FLD_RST3_MSTCLK = BIT(1), 73 FLD_RST3_LPCLK = BIT(2), 74 FLD_RST3_ZB_CRYPT = BIT(3), 75 FLD_RST3_MSPI = BIT(4), 76 FLD_RST3_CODEC = BIT(5), 77 FLD_RST3_SARADC = BIT(6), 78 FLD_RST3_ALG = BIT(7), 79 }; 80 81 #define reg_clk_en REG_ADDR32(0x1401e4) 82 83 #define reg_clk_en0 REG_ADDR8(0x1401e4) 84 enum { 85 FLD_CLK0_HSPI_EN = BIT(0), 86 FLD_CLK0_I2C_EN = BIT(1), 87 FLD_CLK0_UART0_EN = BIT(2), 88 FLD_CLK0_USB_EN = BIT(3), 89 FLD_CLK0_PWM_EN = BIT(4), 90 FLD_CLK0_UART1_EN = BIT(6), 91 FLD_CLK0_SWIRE_EN = BIT(7), 92 }; 93 94 #define reg_clk_en1 REG_ADDR8(0x1401e5) 95 enum { 96 FLD_CLK1_SYS_TIMER_EN = BIT(1), 97 FLD_CLK1_ALGM_EN = BIT(3), 98 FLD_CLK1_PKE_EN = BIT(4), 99 FLD_CLK1_MACHINETIME_EN = BIT(5), 100 FLD_CLK1_PSPI_EN = BIT(6), 101 FLD_CLK1_SPISLV_EN = BIT(7), 102 }; 103 104 #define reg_clk_en2 REG_ADDR8(0x1401e6) 105 enum { 106 FLD_CLK2_TIMER_EN = BIT(0), 107 FLD_CLK2_AUD_EN = BIT(1), 108 FLD_CLK2_TRNG_EN = BIT(2), 109 FLD_CLK2_MCU_EN = BIT(4), 110 111 FLD_CLK2_NPE_EN = BIT(6), 112 FLD_CLK2_EOC_EN = BIT(7), 113 }; 114 115 #define reg_clk_en3 REG_ADDR8(0x1401e7) 116 enum { 117 FLD_CLK3_ZB_PCLK_EN = BIT(0), 118 FLD_CLK3_ZB_MSTCLK_EN = BIT(1), 119 FLD_CLK3_ZB_LPCLK_EN = BIT(2), 120 }; 121 122 #define reg_clk_sel0 REG_ADDR8(0x1401e8) 123 enum { 124 FLD_CLK_SCLK_DIV = BIT_RNG(0, 3), 125 FLD_CLK_SCLK_SEL = BIT_RNG(4, 6), 126 FLD_CLK_MSPI_CLK_SEL = BIT(7), 127 }; 128 129 #define reg_clk_sel1 REG_ADDR8(0x1401e9) 130 enum { 131 FLD_CLK_MSPI_DIV = BIT_RNG(4, 7), 132 }; 133 134 #define reg_i2s_step REG_ADDR8(SC_BASE_ADDR + 0x2a) 135 enum { 136 FLD_I2S_STEP = BIT_RNG(0, 6), 137 FLD_I2S_CLK_EN = BIT(7), 138 }; 139 140 #define reg_i2s_mod REG_ADDR8(SC_BASE_ADDR + 0x2b) 141 142 #define reg_dmic_step REG_ADDR8(SC_BASE_ADDR + 0x2c) 143 enum { 144 FLD_DMIC_STEP = BIT_RNG(0, 6), 145 FLD_DMIC_SEL = BIT(7), 146 }; 147 148 #define reg_dmic_mod REG_ADDR8(SC_BASE_ADDR + 0x2d) 149 150 #define reg_wakeup_en REG_ADDR8(SC_BASE_ADDR + 0x2e) 151 enum { 152 FLD_USB_PWDN_I = BIT(0), 153 FLD_GPIO_WAKEUP_I = BIT(1), 154 FLD_USB_RESUME = BIT(2), 155 FLD_STANDBY_EX = BIT(3), 156 }; 157 158 #define reg_dmic_clk_set REG_ADDR8(SC_BASE_ADDR + 0x33) 159 160 #define reg_wakeup_status 0x64 161 typedef enum { 162 FLD_WKUP_CMP = BIT(0), 163 FLD_WKUP_TIMER = BIT(1), 164 FLD_WKUP_DIG = BIT(2), 165 FLD_WKUP_PAD = BIT(3), 166 FLD_WKUP_MDEC = BIT(4), 167 FLD_MDEC_RSVD = BIT_RNG(5, 7), 168 } wakeup_status_e; 169