1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #ifndef SPI_REG_H 19 #define SPI_REG_H 20 21 #include "../sys.h" 22 23 /******************************* hspi registers: 0x1FFFFC0 ******************************/ 24 25 #define HSPI_BASE_ADDR 0x1FFFFC0 26 #define PSPI_BASE_ADDR 0x140040 27 #define BASE_ADDR_DIFF 0x1EBFF80 28 29 #define reg_hspi_data_buf_adr 0x1FFFFC8 30 #define reg_hspi_xip_base_adr 0x1000000 31 #define reg_spi_data_buf_adr(i) 0x140048 + (i)*BASE_ADDR_DIFF 32 /** 33 * BIT[0:1] the minimum time between the edge of SPI_CS and the edges of SPI_CLK. 34 * The actual duration is (SPI_CLK_OUT/2)*(cs2sclk+1).master only 35 * BIT[2] set 3line mode ,MOSI is bi-directional signal in regular mode.master only 36 * BIT[3] transfer data with least significant bit first.1: LSB 0: MSB default. master/slave 37 * BIT[4] set dual io mode.master only 38 * BIT[5:6] set spi 4 mode. master/slave 39 * * * bit5: CPHA-SPI_CLK Phase,bit6: CPOL-SPI_CLK Polarity 40 * MODE0: CPHA = 0 , CPOL =0; 41 * MODE1: CPHA = 0 , CPOL =1; 42 * MODE2: CPHA = 1 , CPOL =0; 43 * MODE3: CPHA = 1, CPOL =1; 44 * BIT[7] set master/slave mode. 0 slave 1 master default.master/slave 45 */ 46 #define reg_spi_mode0(i) REG_ADDR8(PSPI_BASE_ADDR + (i)*BASE_ADDR_DIFF) 47 enum { 48 FLD_SPI_CS2SCLK = BIT_RNG(0, 1), 49 FLD_SPI_3LINE = BIT(2), 50 FLD_SPI_LSB = BIT(3), 51 FLD_SPI_DUAL = BIT(4), 52 FLD_SPI_MODE_WORK_MODE = BIT_RNG(5, 6), 53 FLD_SPI_MASTER_MODE = BIT(7), 54 }; 55 56 /* the clock freq ratio between the source_clock and spi_clock.master only 57 * spi_clock=source_clock/((spi_clk_div+1)*2) 58 * spi_clk_div=reg_hspi_mode1[7:0]. max_value=0xff,spi_clock==source_clock 59 */ 60 #define reg_spi_mode1(i) REG_ADDR8(PSPI_BASE_ADDR + 0x01 + (i)*BASE_ADDR_DIFF) 61 62 /** 63 * BIT[0] set cmd format 0: single mode 1: the format of the cmd phase is the same as the data phase(Dual/Quad). 64 * Master only 65 * BIT[1] set spi quad I/O mode. master only 66 * BIT[2] set the spi commnd phase enable.master only 67 * BIT[4:7] the minimum time that SPI CS should stay HIGH. 68 * The actual duration is (SPI_CLK period_out / 2)*(csht+1).default=2,master only 69 */ 70 #define reg_spi_mode2(i) REG_ADDR8(PSPI_BASE_ADDR + 0x02 + (i)*BASE_ADDR_DIFF) 71 72 enum { 73 FLD_HSPI_CMD_FMT = BIT(0), 74 FLD_HSPI_QUAD = BIT(1), 75 FLD_SPI_CMD_EN = BIT(2), 76 FLD_SPI_HSPI_MODE2_RESERVED = BIT(3), 77 FLD_SPI_CSHT = BIT_RNG(4, 7), 78 }; 79 80 /** 81 * BIT[0:7] transfer count0 for write data.master only 82 */ 83 #define reg_spi_tx_cnt0(i) REG_ADDR8(PSPI_BASE_ADDR + 0x03 + (i)*BASE_ADDR_DIFF) 84 85 /** 86 * BIT[0:7] transfer count1 for write data.master only 87 */ 88 #define reg_spi_tx_cnt1(i) REG_ADDR8(PSPI_BASE_ADDR + 0x12 + (i) * (BASE_ADDR_DIFF - 0x12 + 0x20)) 89 90 /** 91 * BIT[0:7] transfer count2 for write data.master only 92 */ 93 #define reg_spi_tx_cnt2(i) REG_ADDR8(PSPI_BASE_ADDR + 0x13 + (i) * (BASE_ADDR_DIFF - 0x13 + 0x21)) 94 95 /** 96 * BIT[0:7] transfer count0 for read data.master only 97 */ 98 #define reg_spi_rx_cnt0(i) REG_ADDR8(PSPI_BASE_ADDR + 0x04 + (i)*BASE_ADDR_DIFF) 99 100 /** 101 * BIT[0:7] transfer count1 for read data.master only 102 */ 103 #define reg_spi_rx_cnt1(i) REG_ADDR8(PSPI_BASE_ADDR + 0x10 + (i) * (BASE_ADDR_DIFF - 0x10 + 0x1e)) 104 105 /** 106 * BIT[0:7] transfer count2 for read data.master only 107 */ 108 #define reg_spi_rx_cnt2(i) REG_ADDR8(PSPI_BASE_ADDR + 0x11 + (i) * (BASE_ADDR_DIFF - 0x11 + 0x1f)) 109 110 /** 111 * BIT[0:3] dummy data cnt, dummy is always single wire mode, dummy number = dummy_cnt + 1.master only 112 * BIT[4:7] the transfer mode.master only 113 * the transfer sequence could be: 114 * 0x0:write and read at the same time(must enbale CmdEn) 115 * 0x1:write only 116 * 0x2:read only(must enbale CmdEn) 117 * 0x3:write,read 118 * 0x4:read,write 119 * 0x5:write,dummy,read 120 * 0x6:read,dummy,write(must enbale CmdEn) 121 * 0x7:None Data(must enbale CmdEn) 122 * 0x8:Dummy,write 123 * 0x9:Dummy,read 124 * 0xa~0xf:reserved 125 */ 126 #define reg_spi_trans0(i) REG_ADDR8(PSPI_BASE_ADDR + 0x05 + (i)*BASE_ADDR_DIFF) 127 128 enum { 129 FLD_SPI_DUMMY_CNT = BIT_RNG(0, 3), 130 FLD_SPI_TRANSMODE = BIT_RNG(4, 7), 131 }; 132 133 /** 134 * BIT[0:7] SPI Command.master only 135 */ 136 137 #define reg_spi_trans1(i) REG_ADDR8(PSPI_BASE_ADDR + 0x06 + (i)*BASE_ADDR_DIFF) 138 enum { 139 FLD_SPI_CMD_RESERVED = BIT(0), 140 FLD_SPI_CMD_TRANS_HWORD = BIT(1), // 1 apb hword transfer 141 FLD_SPI_CMD_TRANS_WORD = BIT(2), // 1 apb word transfer 142 FLD_SPI_CMD_RD_DUMMY_4CYCLE = BIT(3), // 0 8cycle 1 4cycle 143 FLD_SPI_CMD_ADDR_AUTO_INCREASE = BIT(4), // 0 AUTO incease 144 FLD_SPI_CMD_DATA_DUAL = BIT(5), // 0 Single 1 DuaL 145 FLD_SPI_CMD_ADDR_DUAL = BIT(6), // 0 Single 1 DuaL 146 FLD_SPI_CMD_RD_EN = BIT(7), // 0 write 1 read 147 }; 148 149 /** 150 * BIT[0] enable the SPI Receive FIFO Overrun interrupt . slave only 151 * BIT[1] enable the SPI Transmit FIFO Underrun interrupt. slave only 152 * BIT[2] enable the SPI Receive FIFO Threshold interrupt.master/slave 153 * BIT[3] enable the SPI Transmit FIFO Threshold interrupt.master/slave 154 * BIT[4] enable the SPI Transmit end interrupt.master/slave 155 * BIT[5] enable slvCmdint.The slave command interrupt is triggered each byte command received (starting 8 bit). 156 * Slave only 157 * BIT[6] enable RX DMA 158 * BIT[7] enable TX DMA 159 */ 160 161 #define reg_spi_trans2(i) REG_ADDR8(PSPI_BASE_ADDR + 0x07 + (i)*BASE_ADDR_DIFF) 162 enum { 163 FLD_SPI_RXFIFO_OR_INT_EN = BIT(0), 164 FLD_SPI_TXFIFO_UR_INT_EN = BIT(1), 165 FLD_SPI_RXFIFO_INT_EN = BIT(2), 166 FLD_SPI_TXFIFO_INT_EN = BIT(3), 167 FLD_SPI_END_INT_EN = BIT(4), 168 FLD_SPI_SLV_CMD_EN = BIT(5), 169 FLD_SPI_RX_DMA_EN = BIT(6), 170 FLD_SPI_TX_DMA_EN = BIT(7), 171 }; 172 173 /** 174 * BIT[0:7] data0[7:0] to transmit or received. 175 */ 176 177 #define reg_spi_wr_rd_data0(i) REG_ADDR8(PSPI_BASE_ADDR + 0x08 + (i)*BASE_ADDR_DIFF) 178 /** 179 * BIT[0:7] data1[7:0] to transmit or received. 180 */ 181 182 #define reg_spi_wr_rd_data1(i) REG_ADDR8(PSPI_BASE_ADDR + 0x09 + (i)*BASE_ADDR_DIFF) 183 /** 184 * BIT[0:7] data2[7:0] to transmit or received. 185 */ 186 #define reg_spi_wr_rd_data2(i) REG_ADDR8(PSPI_BASE_ADDR + 0x0a + (i)*BASE_ADDR_DIFF) 187 188 /** 189 * BIT[0:7] data3[7:0] to transmit or received. 190 */ 191 192 #define reg_spi_wr_rd_data3(i) REG_ADDR8(PSPI_BASE_ADDR + 0x0b + (i)*BASE_ADDR_DIFF) 193 194 #define reg_spi_wr_rd_data(i, j) REG_ADDR8(PSPI_BASE_ADDR + 0x08 + (j) + (i)*BASE_ADDR_DIFF) 195 196 /** 197 * BIT[0:3] number of valid entries in the rxfifo. 198 * BIT[4:7] number of valid entries in the txfifo. 199 */ 200 #define reg_spi_fifo_num(i) REG_ADDR8(PSPI_BASE_ADDR + 0x0c + (i)*BASE_ADDR_DIFF) 201 202 enum { 203 FLD_SPI_RXF_NUM = BIT_RNG(0, 3), 204 FLD_SPI_TXF_NUM = BIT_RNG(4, 7), 205 }; 206 207 /** 208 * BIT[2] rxfifo reset,write 1 to reset. Spi clock must turn on. 209 * BIT[3] txfifo reset,write 1 to reset. Spi clock must turn on 210 * BIT[4] rxfifo full flag. 211 * BIT[5] rxfifo empty flag 212 * BIT[6] txfifo full flag. 213 * BIT[7] txfifo empty flag 214 */ 215 #define reg_spi_fifo_state(i) REG_ADDR8(PSPI_BASE_ADDR + 0x0d + (i)*BASE_ADDR_DIFF) 216 217 enum { 218 FLD_SPI_FIFO_STA_RESERVED = BIT_RNG(0, 1), 219 FLD_SPI_RXF_CLR = BIT(2), 220 FLD_SPI_TXF_CLR = BIT(3), 221 FLD_SPI_RXF_FULL = BIT(4), 222 FLD_SPI_RXF_EMPTY = BIT(5), 223 FLD_SPI_TXF_FULL = BIT(6), 224 FLD_SPI_TXF_EMPTY = BIT(7), 225 }; 226 227 /** 228 * BIT[2] RX FIFO Overrun interrupt status. slave only 229 * BIT[3] TX FIFO Underrun interrupt status. slave only 230 * BIT[4] RX FIFO Threshold interrupt status.set 1 to clear. master/slave 231 * BIT[5] TX FIFO Threshold interrupt status.set 1 to clear. master/slave 232 * BIT[6] End of SPI Transfer interrupt status.set 1 to clear.master/slave 233 * BIT[7] Slave Command Interrupt status.set 1 to clear.slave only 234 */ 235 #define reg_spi_irq_state(i) REG_ADDR8(PSPI_BASE_ADDR + 0x0e + (i)*BASE_ADDR_DIFF) 236 237 enum { 238 FLD_SPI_STATE_RESERVED = BIT_RNG(0, 1), 239 FLD_SPI_RXF_OR_INT = BIT(2), 240 FLD_SPI_TXF_UR_INT = BIT(3), 241 FLD_SPI_RXF_INT = BIT(4), 242 FLD_SPI_TXF_INT = BIT(5), 243 FLD_SPI_END_INT = BIT(6), 244 FLD_SPI_SLV_CMD_INT = BIT(7), 245 }; 246 247 /** 248 * BIT[0] set this bit to indicate that spi as slave is ready for data transaction 249 * BIT[1] spi soft reset.high valid. 250 * BIT[4:6] fifo threshold. 0x4 default. 251 * BIT[7] SPI transfer status .1 is busy, 0 not busy. 252 */ 253 #define reg_spi_status(i) REG_ADDR8(PSPI_BASE_ADDR + 0x0f + (i)*BASE_ADDR_DIFF) 254 enum { 255 FLD_HSPI_SLAVE_READY = BIT(0), 256 FLD_HSPI_SOFT_RESET = BIT(1), 257 FLD_HSPI_HSPI_STATUS_RESERVED = BIT_RNG(2, 3), 258 FLD_HSPI_FIFO_THRES = BIT_RNG(4, 6), 259 FLD_HSPI_BUSY = BIT(7), 260 }; 261 262 /** 263 * BIT[0:7] hspi_addr0. 264 */ 265 #define reg_hspi_addr0 REG_ADDR8(HSPI_BASE_ADDR + 0x10) 266 267 /** 268 * BIT[0:7] hspi_addr1. 269 */ 270 #define reg_hspi_addr1 REG_ADDR8(HSPI_BASE_ADDR + 0x11) 271 272 /** 273 * BIT[0:7] hspi_addr2. 274 */ 275 #define reg_hspi_addr2 REG_ADDR8(HSPI_BASE_ADDR + 0x12) 276 277 /** 278 * BIT[0:7] hspi_addr3. 279 */ 280 #define reg_hspi_addr3 REG_ADDR8(HSPI_BASE_ADDR + 0x13) 281 282 #define reg_hspi_addr(i) REG_ADDR8(HSPI_BASE_ADDR + 0x10 + (i)) 283 284 // hspi_addr0~ hspi_addr3. 285 286 #define reg_hspi_addr_32 REG_ADDR32(HSPI_BASE_ADDR + 0x10) 287 288 /** 289 * BIT[0] 1:enable addr phase, master only 290 * BIT[1] 0:single mode 1:the format of addr phase is the same as the data phase(Dual/Quad).master only 291 * BIT[2:3] address length.2'b00:1bye 2'b01:2bytes 2'b10:3bytes 2'b11:4bytes.master only 292 * BIT[4] enable xip. 293 * BIT[5] stop xip. 294 * BIT[6] xip mode 0:xip normal mode 1:xip sequential mode 295 * BIT[7] 0:xip timeout ,disable 1:xip timeout enable .default 1 296 */ 297 #define reg_hspi_xip_ctrl REG_ADDR8(HSPI_BASE_ADDR + 0x14) 298 enum { 299 FLD_HSPI_ADDR_EN = BIT(0), 300 FLD_HSPI_ADDR_FMT = BIT(1), 301 FLD_HSPI_ADDR_LEN = BIT_RNG(2, 3), 302 FLD_HSPI_XIP_ENABLE = BIT(4), 303 FLD_HSPI_XIP_STOP = BIT(5), 304 FLD_HSPI_XIP_MODE = BIT(6), 305 FLD_HSPI_XIP_TIMEOUT_MODE = BIT(7), 306 }; 307 308 /** 309 * BIT[0:7] write command used for xip 310 */ 311 #define reg_hspi_xip_wr_cmd REG_ADDR8(HSPI_BASE_ADDR + 0x15) 312 313 /** 314 * BIT[0:7] read command used for xip 315 */ 316 #define reg_hspi_xip_rd_cmd REG_ADDR8(HSPI_BASE_ADDR + 0x16) 317 318 /** 319 * BIT[0:7] Use this combined with xip_mode being xip sequential mode. 320 * Default page boundary size is 32byte, 2^page_size. 321 */ 322 #define reg_hspi_page_size REG_ADDR8(HSPI_BASE_ADDR + 0x17) 323 324 /** 325 * BIT[0:3] xip write mode .default 1, write trans mode is write only. 326 * BIT[4:7] xip read mode. default 2 ,read trans mode is read only. 327 */ 328 #define reg_hspi_xip_trans_mode REG_ADDR8(HSPI_BASE_ADDR + 0x18) 329 enum { 330 FLD_HSPI_XIP_WR_TRANS_MODE = BIT_RNG(0, 3), 331 FLD_HSPI_XIP_RD_TRANS_MODE = BIT_RNG(4, 7), 332 }; 333 334 /** 335 * BIT[0:7] xip_addr_offset0. 336 */ 337 #define reg_hspi_xip_addr_offset0 REG_ADDR8(HSPI_BASE_ADDR + 0x19) 338 339 /** 340 * BIT[0:7] xip_addr_offset1. 341 */ 342 #define reg_hspi_xip_addr_offset1 REG_ADDR8(HSPI_BASE_ADDR + 0x1a) 343 344 /** 345 * BIT[0:7] xip_addr_offset2. 346 */ 347 #define reg_hspi_xip_addr_offset2 REG_ADDR8(HSPI_BASE_ADDR + 0x1b) 348 349 /** 350 * BIT[0:7] xip_addr_offset3. 351 */ 352 #define reg_hspi_xip_addr_offset3 REG_ADDR8(HSPI_BASE_ADDR + 0x1c) 353 354 /** 355 * BIT[0:7] when XIP_TIMEOUT_MODE enable,timeout period=spi_clock_out_period*timeout_cnt 356 */ 357 #define reg_hspi_xip_timeout_cnt REG_ADDR8(HSPI_BASE_ADDR + 0x1d) 358 /** 359 * BIT[0] 1:enable hspi 3line dcx (data/command selection), master only,for spi panel(LCD OLED ...) 360 * BIT[1] hspi 3line dcx (data/command selection). 0:command 1:data 361 * BIT[4:2] 2data_lane mode.3'b000:2data_lane close 3'b001:RGB565 3'b011:RGB666 3'b011:RGB888. 362 */ 363 #define reg_hspi_panel_ctrl REG_ADDR8(HSPI_BASE_ADDR + 0x22) 364 enum { 365 FLD_HSPI_PANEL_3LINE_DCX_EN = BIT(0), 366 FLD_HSPI_PANEL_3LINE_DCX = BIT(1), 367 FLD_HSPI_PANEL_2DATA_LANE = BIT_RNG(2, 4), 368 }; 369 370 #endif 371