1 /*
2 *
3 * Copyright 2013 Rockchip Electronics Co., LTD.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17
18 #undef ROCKCHIP_LOG_TAG
19 #define ROCKCHIP_LOG_TAG "omx_osal_rga"
20
21 #include <securec.h>
22 #include <stdio.h>
23 #include <sys/ioctl.h>
24 #include <fcntl.h>
25 #include <poll.h>
26 #include <dlfcn.h>
27 #include <unistd.h>
28 #include <string.h>
29 #include <errno.h>
30 #include "vpu_type.h"
31 #include "Rockchip_OMX_Def.h"
32 #include "vpu_global.h"
33 #include "Rockchip_OSAL_Log.h"
34 #include "Rockchip_OSAL_Memory.h"
35 #include "rga.h"
36 #include "Rockchip_OSAL_RGA_Process.h"
37
38 #ifdef USE_DRM
39 #include "drmrga.h"
40 #include "RgaApi.h"
41 #else
42 typedef struct _rga_ctx {
43 int32_t rga_fd;
44 } rga_ctx_t;
45 typedef struct _rga_info {
46 int xoffset;
47 int yoffset;
48 int width;
49 int height;
50 int vir_w;
51 int vir_h;
52 int format;
53 int fd;
54 void *vir_addr;
55 int type;
56 } rga_info_t;
57 #endif
58
rga_dev_open(void ** rga_ctx)59 OMX_S32 rga_dev_open(void **rga_ctx)
60 {
61 #ifndef USE_DRM
62 rga_ctx_t *ctx = NULL;
63 ctx = Rockchip_OSAL_Malloc(sizeof(rga_ctx_t));
64 Rockchip_OSAL_Memset(ctx, 0, sizeof(rga_ctx_t));
65 ctx->rga_fd = -1;
66 ctx->rga_fd = open("/dev/rga", O_RDWR, 0);
67 if (ctx->rga_fd < 0) {
68 omx_err("rga open fail");
69 return -1;
70 }
71 *rga_ctx = ctx;
72 return 0;
73 #else
74 RgaInit(rga_ctx);
75 if (*rga_ctx == NULL) {
76 return -1;
77 }
78 return 0;
79 #endif
80 }
81
rga_dev_close(void * rga_ctx)82 OMX_S32 rga_dev_close(void *rga_ctx)
83 {
84 #ifndef USE_DRM
85 rga_ctx_t *ctx = (rga_ctx_t *)rga_ctx;
86 if (ctx == NULL) {
87 return 0;
88 }
89 if (ctx->rga_fd >= 0) {
90 close(ctx->rga_fd);
91 ctx->rga_fd = -1;
92 }
93 Rockchip_OSAL_Free(rga_ctx);
94 rga_ctx = NULL;
95 return 0;
96 #else
97 RgaDeInit(rga_ctx);
98 return 0;
99 #endif
100 }
101 #ifndef USE_DRM
102 #define RGA_BUF_GEM_TYPE_DMA 0x80
rga_copy(RockchipVideoPlane * plane,VPUMemLinear_t * vpumem,uint32_t Width,uint32_t Height,int format,int rga_fd)103 OMX_S32 rga_copy(RockchipVideoPlane *plane, VPUMemLinear_t *vpumem, uint32_t Width,
104 uint32_t Height, int format, int rga_fd)
105 {
106 struct rga_req Rga_Request;
107 Rockchip_OSAL_Memset(&Rga_Request, 0x0, sizeof(Rga_Request));
108 #ifdef SOFIA_3GR
109 Rga_Request.line_draw_info.color = plane->fd & 0xffff;
110 #else
111 Rga_Request.src.yrgb_addr = plane->fd;
112 #endif
113 Rga_Request.src.uv_addr = 0;
114 Rga_Request.src.v_addr = 0;
115 Rga_Request.src.vir_w = plane->stride;
116 Rga_Request.src.vir_h = Height;
117
118 Rga_Request.src.format = format;
119
120 Rga_Request.src.act_w = Width;
121 Rga_Request.src.act_h = Height;
122 Rga_Request.src.x_offset = 0;
123 Rga_Request.src.y_offset = 0;
124 Rga_Request.dst.yrgb_addr = 0;
125 #ifdef SOFIA_3GR
126 if (!VPUMemJudgeIommu()) {
127 Rga_Request.dst.yrgb_addr = vpumem->phy_addr;
128 } else {
129 Rga_Request.line_draw_info.color |= (vpumem->phy_addr & 0xffff) << 16; // 16:byte alignment
130 Rga_Request.dst.uv_addr = vpumem->vir_addr;
131 }
132
133 #else
134 if (!VPUMemJudgeIommu()) {
135 Rga_Request.dst.uv_addr = vpumem->phy_addr;
136 } else {
137 Rga_Request.dst.yrgb_addr = vpumem->phy_addr;
138 Rga_Request.dst.uv_addr = (unsigned long)vpumem->vir_addr;
139 }
140 #endif
141 Rga_Request.dst.v_addr = 0;
142 Rga_Request.dst.vir_w = Width;
143 Rga_Request.dst.vir_h = Height;
144 Rga_Request.dst.format = Rga_Request.src.format;
145
146 Rga_Request.clip.xmin = 0;
147 Rga_Request.clip.xmax = Width - 1;
148 Rga_Request.clip.ymin = 0;
149 Rga_Request.clip.ymax = Height - 1;
150
151 Rga_Request.dst.act_w = Width;
152 Rga_Request.dst.act_h = Height;
153 Rga_Request.dst.x_offset = 0;
154 Rga_Request.dst.y_offset = 0;
155 Rga_Request.rotate_mode = 0;
156 Rga_Request.render_mode = 5; // 5:value of render_mode
157 Rga_Request.render_mode |= RGA_BUF_GEM_TYPE_DMA;
158 if (plane->type == ANB_PRIVATE_BUF_VIRTUAL) {
159 Rga_Request.src.uv_addr = (unsigned long)plane->addr;
160 Rga_Request.mmu_info.mmu_en = 1;
161 Rga_Request.mmu_info.mmu_flag = ((2 & 0x3) << 4) | 1; // 2:byte alignment, 4:byte alignment
162 if (VPUMemJudgeIommu()) {
163 // 31:byte alignment, 10:byte alignment, 8:byte alignment
164 Rga_Request.mmu_info.mmu_flag |= ((1 << 31) | (1 << 10) | (1 << 8));
165 } else {
166 // 31:byte alignment, 8:byte alignment
167 Rga_Request.mmu_info.mmu_flag |= ((1 << 31) | (1 << 8));
168 }
169 } else {
170 if (VPUMemJudgeIommu()) {
171 Rga_Request.mmu_info.mmu_en = 1;
172 Rga_Request.mmu_info.mmu_flag = ((2 & 0x3) << 4) | 1; // 2:byte alignment, 4:byte alignment
173 // 31:byte alignment, 10:byte alignment, 8:byte alignment
174 Rga_Request.mmu_info.mmu_flag |= ((1 << 31) | (1 << 10) | (1 << 8));
175 }
176 }
177 omx_trace("rga start in");
178 if (ioctl(rga_fd, RGA_BLIT_SYNC, &Rga_Request) != 0) {
179 omx_err("rga rga_copy fail");
180 return -1;
181 }
182 omx_trace("rga start out");
183 return 0;
184 }
185
rga_crop_scale(RockchipVideoPlane * plane,VPUMemLinear_t * vpumem,OMX_VIDEO_PARAMS_EXTENDED * param_video,RK_U32 orgin_w,RK_U32 orgin_h,int rga_fd)186 OMX_S32 rga_crop_scale(RockchipVideoPlane *plane,
187 VPUMemLinear_t *vpumem, OMX_VIDEO_PARAMS_EXTENDED *param_video,
188 RK_U32 orgin_w, RK_U32 orgin_h, int rga_fd)
189 {
190 struct rga_req Rga_Request;
191 RK_U32 new_width = 0, new_height = 0;
192 Rockchip_OSAL_Memset(&Rga_Request, 0x0, sizeof(Rga_Request));
193 if (param_video->bEnableScaling || param_video->bEnableCropping) {
194 if (param_video->bEnableScaling) {
195 new_width = param_video->ui16ScaledWidth;
196 new_height = param_video->ui16ScaledHeight;
197 } else if (param_video->bEnableCropping) {
198 new_width = orgin_w - param_video->ui16CropLeft - param_video->ui16CropRight;
199 new_height = orgin_h - param_video->ui16CropTop - param_video->ui16CropBottom;
200 }
201 }
202 #ifdef SOFIA_3GR
203 Rga_Request.line_draw_info.color = plane->fd & 0xffff;
204 #else
205 Rga_Request.src.yrgb_addr = plane->fd;
206 #endif
207
208 Rga_Request.src.uv_addr = 0;
209 Rga_Request.src.v_addr = 0;
210 Rga_Request.src.vir_w = plane->stride;
211 Rga_Request.src.vir_h = orgin_h;
212
213 Rga_Request.src.format = RK_FORMAT_YCbCr_420_SP;
214 if (param_video->bEnableCropping) {
215 Rga_Request.src.act_w = orgin_w - param_video->ui16CropLeft - param_video->ui16CropRight;
216 Rga_Request.src.act_h = orgin_h - param_video->ui16CropTop - param_video->ui16CropBottom;
217 Rga_Request.src.x_offset = param_video->ui16CropLeft;
218 Rga_Request.src.y_offset = param_video->ui16CropTop;
219 } else {
220 Rga_Request.src.act_w = orgin_w;
221 Rga_Request.src.act_h = orgin_h;
222 Rga_Request.src.x_offset = 0;
223 Rga_Request.src.y_offset = 0;
224 }
225
226 Rga_Request.dst.yrgb_addr = 0;
227
228 #ifdef SOFIA_3GR
229 if (!VPUMemJudgeIommu()) {
230 Rga_Request.dst.yrgb_addr = vpumem->phy_addr;
231 Rga_Request.dst.uv_addr = vpumem->phy_addr + plane->stride * orgin_h;
232 } else {
233 Rga_Request.line_draw_info.color |= (vpumem->phy_addr & 0xffff) << 16; // 16:byte alignment
234 Rga_Request.dst.uv_addr = (unsigned long)vpumem->vir_addr;
235 }
236 #else
237 if (!VPUMemJudgeIommu()) {
238 Rga_Request.dst.uv_addr = vpumem->phy_addr;
239 } else {
240 Rga_Request.dst.yrgb_addr = vpumem->phy_addr;
241 Rga_Request.dst.uv_addr = (unsigned long)vpumem->vir_addr;
242 }
243 #endif
244 Rga_Request.dst.v_addr = 0;
245 Rga_Request.dst.vir_w = new_width;
246 Rga_Request.dst.vir_h = new_height;
247 Rga_Request.dst.format = RK_FORMAT_YCbCr_420_SP;
248
249 Rga_Request.clip.xmin = 0;
250 Rga_Request.clip.xmax = new_width - 1;
251 Rga_Request.clip.ymin = 0;
252 Rga_Request.clip.ymax = new_height - 1;
253
254 Rga_Request.dst.act_w = new_width;
255 Rga_Request.dst.act_h = new_height;
256 Rga_Request.dst.x_offset = 0;
257 Rga_Request.dst.y_offset = 0;
258 Rga_Request.rotate_mode = 1;
259 Rga_Request.sina = 0;
260 Rga_Request.cosa = 65536; // 65536:2^16
261
262 if (plane->type == ANB_PRIVATE_BUF_VIRTUAL) {
263 Rga_Request.src.uv_addr = (unsigned long)plane->addr;
264 Rga_Request.mmu_info.mmu_en = 1;
265 Rga_Request.mmu_info.mmu_flag = ((2 & 0x3) << 4) | 1; // 2:byte alignment, 4:byte alignment
266 if (VPUMemJudgeIommu()) {
267 // 31:byte alignment, 10:byte alignment, 8:byte alignment
268 Rga_Request.mmu_info.mmu_flag |= ((1 << 31) | (1 << 10) | (1 << 8));
269 } else {
270 Rga_Request.mmu_info.mmu_flag |= ((1 << 31) | (1 << 8)); // 31:byte alignment, 8:byte alignment
271 }
272 } else {
273 if (VPUMemJudgeIommu()) {
274 Rga_Request.mmu_info.mmu_en = 1;
275 Rga_Request.mmu_info.mmu_flag = ((2 & 0x3) << 4) | 1; // 2:byte alignment, 4:byte alignment
276 // 31:byte alignment, 10:byte alignment, 8:byte alignment
277 Rga_Request.mmu_info.mmu_flag |= ((1 << 31) | (1 << 10) | (1 << 8));
278 }
279 }
280
281 omx_trace("rga start in");
282
283 if (ioctl(rga_fd, RGA_BLIT_SYNC, &Rga_Request) != 0) {
284 omx_err("rga_rgb2nv12 rga RGA_BLIT_SYNC fail");
285 return -1;
286 }
287 omx_trace("rga start out");
288 return 0;
289 }
290
rga_set_info(rga_info_t * info,int w,int h,int v_w,int v_h,int fd,int format,void * vir_addr,int type)291 void rga_set_info(rga_info_t *info, int w, int h, int v_w, int v_h, int fd, int format, void *vir_addr, int type)
292 {
293 info->width = w;
294 info->height = h;
295 info->vir_w = v_w;
296 info->vir_h = v_h;
297 info->fd = fd;
298 info->format = format;
299 info->vir_addr = vir_addr;
300 info->type = type;
301 }
302
rga_convert(rga_info_t * src,rga_info_t * dst,int rga_fd)303 OMX_S32 rga_convert(rga_info_t *src, rga_info_t *dst, int rga_fd)
304 {
305 if (rga_fd < 0) {
306 return -1;
307 }
308 struct rga_req Rga_Request;
309 Rockchip_OSAL_Memset(&Rga_Request, 0x0, sizeof(Rga_Request));
310 Rga_Request.src.yrgb_addr = 0;
311 #ifdef SOFIA_3GR
312 if (!VPUMemJudgeIommu()) {
313 Rga_Request.src.yrgb_addr = src->fd;
314 Rga_Request.src.uv_addr = src->fd + src->vir_w * src->vir_h;
315 } else {
316 Rga_Request.line_draw_info.color = src->fd & 0xffff;
317 Rga_Request.src.yrgb_addr = src->fd;
318 Rga_Request.src.uv_addr = src->vir_addr;
319 }
320 #else
321 if (!VPUMemJudgeIommu()) {
322 Rga_Request.src.uv_addr = src->fd;
323 } else {
324 Rga_Request.src.yrgb_addr = src->fd;
325 Rga_Request.src.uv_addr = (unsigned long)src->vir_addr;
326 }
327 #endif
328 Rga_Request.src.v_addr = 0;
329 Rga_Request.src.vir_w = src->vir_w;
330 Rga_Request.src.vir_h = src->vir_h;
331 Rga_Request.src.format = src->format;
332
333 Rga_Request.src.act_w = src->width;
334 Rga_Request.src.act_h = src->height;
335 Rga_Request.src.x_offset = 0;
336 Rga_Request.src.y_offset = 0;
337 #ifdef SOFIA_3GR
338 Rga_Request.line_draw_info.color |= (dst->fd & 0xffff) << 16; // 16:byte alignment
339 #else
340 Rga_Request.dst.yrgb_addr = dst->fd ;
341 #endif
342 Rga_Request.dst.uv_addr = 0;
343 Rga_Request.dst.v_addr = 0;
344 Rga_Request.dst.vir_w = dst->vir_w;
345 Rga_Request.dst.vir_h = dst->vir_h;
346 Rga_Request.dst.format = dst->format;
347 Rga_Request.clip.xmin = 0;
348 Rga_Request.clip.xmax = dst->vir_w - 1;
349 Rga_Request.clip.ymin = 0;
350 Rga_Request.clip.ymax = dst->vir_h - 1;
351 Rga_Request.dst.act_w = dst->width;
352 Rga_Request.dst.act_h = dst->height;
353 Rga_Request.dst.x_offset = 0;
354 Rga_Request.dst.y_offset = 0;
355 Rga_Request.rotate_mode = 0;
356 Rga_Request.yuv2rgb_mode = (2 << 4); // 2:byte alignment, 4:byte alignment
357 if (src->type == ANB_PRIVATE_BUF_VIRTUAL || dst->type == ANB_PRIVATE_BUF_VIRTUAL) {
358 Rga_Request.mmu_info.mmu_flag = ((2 & 0x3) << 4) | 1; // 2:byte alignment, 4:byte alignment
359 Rga_Request.mmu_info.mmu_en = 1;
360 if (src->type == ANB_PRIVATE_BUF_VIRTUAL) {
361 Rga_Request.src.uv_addr = (unsigned long)(src->vir_addr);
362 Rga_Request.mmu_info.mmu_flag |= ((1 << 31) | (1 << 8)); // 31:byte alignment, 8:byte alignment
363 } else {
364 Rga_Request.dst.uv_addr = (unsigned long)(dst->vir_addr);
365 Rga_Request.mmu_info.mmu_flag |= ((1 << 31) | (1 << 10)); // 31:byte alignment, 10:byte alignment
366 }
367 if (VPUMemJudgeIommu()) {
368 // 31:byte alignment, 10:byte alignment, 8:byte alignment
369 Rga_Request.mmu_info.mmu_flag |= ((1 << 31) | (1 << 10) | (1 << 8));
370 }
371 } else {
372 if (VPUMemJudgeIommu()) {
373 Rga_Request.mmu_info.mmu_en = 1;
374 Rga_Request.mmu_info.mmu_flag = ((2 & 0x3) << 4) | 1; // 2:byte alignment, 4:byte alignment
375 // 31:byte alignment, 10:byte alignment, 8:byte alignment
376 Rga_Request.mmu_info.mmu_flag |= (1 << 31) | (1 << 10) | (1 << 8);
377 }
378 }
379 if (ioctl(rga_fd, RGA_BLIT_SYNC, &Rga_Request) != 0) {
380 omx_err("rga_convert fail");
381 return -1;
382 }
383 return 0;
384 }
385 #endif
386
rga_nv12_crop_scale(RockchipVideoPlane * plane,VPUMemLinear_t * vpumem,OMX_VIDEO_PARAMS_EXTENDED * param_video,RK_U32 orgin_w,RK_U32 orgin_h,void * rga_ctx)387 void rga_nv12_crop_scale(RockchipVideoPlane *plane,
388 VPUMemLinear_t *vpumem, OMX_VIDEO_PARAMS_EXTENDED *param_video,
389 RK_U32 orgin_w, RK_U32 orgin_h, void* rga_ctx)
390 {
391 #ifndef USE_DRM
392 rga_ctx_t *ctx = (rga_ctx_t *)rga_ctx;
393 if (ctx == NULL) {
394 return;
395 }
396 if (rga_crop_scale(plane, vpumem, param_video, orgin_w, orgin_h, ctx->rga_fd) < 0) {
397 omx_err("rga_crop_scale fail");
398 }
399 #else
400 RK_U32 new_width = 0, new_height = 0;
401 rga_info_t src;
402 rga_info_t dst;
403 (void) rga_ctx;
404 memset_s((void*)&src, sizeof(rga_info_t), 0, sizeof(rga_info_t));
405 memset_s((void*)&dst, sizeof(rga_info_t), 0, sizeof(rga_info_t));
406 if (param_video->bEnableScaling || param_video->bEnableCropping) {
407 if (param_video->bEnableScaling) {
408 new_width = param_video->ui16ScaledWidth;
409 new_height = param_video->ui16ScaledHeight;
410 } else if (param_video->bEnableCropping) {
411 new_width = orgin_w - param_video->ui16CropLeft - param_video->ui16CropRight;
412 new_height = orgin_h - param_video->ui16CropTop - param_video->ui16CropBottom;
413 }
414 }
415
416 if (param_video->bEnableCropping) {
417 RK_U32 x, y, w, h;
418 w = orgin_w - param_video->ui16CropLeft - param_video->ui16CropRight;
419 h = orgin_h - param_video->ui16CropTop - param_video->ui16CropBottom;
420 x = param_video->ui16CropLeft;
421 y = param_video->ui16CropTop;
422 rga_set_rect(&src.rect, x, y, w, h, plane->stride, h, HAL_PIXEL_FORMAT_YCrCb_NV12);
423 } else {
424 rga_set_rect(&src.rect, 0, 0, orgin_w, orgin_h, plane->stride, orgin_h, HAL_PIXEL_FORMAT_YCrCb_NV12);
425 }
426 rga_set_rect(&dst.rect, 0, 0, orgin_w, orgin_h, orgin_w, orgin_h, HAL_PIXEL_FORMAT_YCrCb_NV12);
427 src.fd = plane->fd;
428 dst.fd = vpumem->phy_addr;
429 if (RgaBlit(&src, &dst, NULL)) {
430 omx_err("RgaBlit fail");
431 }
432 #endif
433 }
434
rga_rgb2nv12(RockchipVideoPlane * plane,VPUMemLinear_t * vpumem,uint32_t Width,uint32_t Height,uint32_t dstWidth,uint32_t dstHeight,void * rga_ctx)435 void rga_rgb2nv12(RockchipVideoPlane *plane, VPUMemLinear_t *vpumem,
436 uint32_t Width, uint32_t Height, uint32_t dstWidth, uint32_t dstHeight, void* rga_ctx)
437 {
438 (void)dstWidth;
439 (void)dstHeight;
440 #ifndef USE_DRM
441 rga_info_t src;
442 rga_info_t dst;
443
444 rga_ctx_t *ctx = (rga_ctx_t *)rga_ctx;
445 memset_s((void*)&src, sizeof(rga_info_t), 0, sizeof(rga_info_t));
446 memset_s((void*)&dst, sizeof(rga_info_t), 0, sizeof(rga_info_t));
447 if (ctx == NULL) {
448 return;
449 }
450 rga_set_info(&src, Width, Height, plane->stride, Height, plane->fd,
451 RK_FORMAT_RGBA_8888, (void *)plane->addr, plane->type);
452 rga_set_info(&dst, dstWidth, dstHeight, dstWidth, dstHeight, vpumem->phy_addr,
453 RK_FORMAT_YCbCr_420_SP, (void *)vpumem->vir_addr, 0);
454 if (rga_convert(&src, &dst, ctx->rga_fd) < 0) {
455 omx_err("rga_rgb2nv12 fail");
456 }
457 #else
458 rga_info_t src;
459 rga_info_t dst;
460 (void) rga_ctx;
461 memset_s((void*)&src, sizeof(rga_info_t), 0, sizeof(rga_info_t));
462 memset_s((void*)&dst, sizeof(rga_info_t), 0, sizeof(rga_info_t));
463 omx_trace(" plane->stride %lu", plane->stride);
464 rga_set_rect(&src.rect, 0, 0, Width, Height, plane->stride, Height, HAL_PIXEL_FORMAT_RGBA_8888);
465 rga_set_rect(&dst.rect, 0, 0, Width, Height, dstWidth, dstHeight, HAL_PIXEL_FORMAT_YCrCb_NV12);
466 src.fd = plane->fd;
467 dst.fd = vpumem->phy_addr;
468 omx_trace("RgaBlit in src.fd = 0x%x, dst.fd = 0x%x", src.fd, dst.fd);
469 if (RgaBlit(&src, &dst, NULL)) {
470 omx_err("RgaBlit fail");
471 }
472 omx_trace("RgaBlit out");
473 #endif
474 }
475
rga_nv122rgb(RockchipVideoPlane * planes,VPUMemLinear_t * vpumem,uint32_t Width,uint32_t Height,int dst_format,void * rga_ctx)476 void rga_nv122rgb(RockchipVideoPlane *planes, VPUMemLinear_t *vpumem, uint32_t Width,
477 uint32_t Height, int dst_format, void* rga_ctx)
478 {
479 #ifndef USE_DRM
480 rga_info_t src;
481 rga_info_t dst;
482 rga_ctx_t *ctx = (rga_ctx_t *)rga_ctx;
483 Rockchip_OSAL_Memset((void*)&src, 0, sizeof(rga_info_t));
484 Rockchip_OSAL_Memset((void*)&dst, 0, sizeof(rga_info_t));
485 Width = (Width + 15) & (~15); // 15:byte alignment
486 Height = (Height + 15) & (~15); // 15:byte alignment
487 rga_set_info(&src, Width, Height, Width, Height,
488 vpumem->phy_addr, RK_FORMAT_YCbCr_420_SP, (void *)vpumem->vir_addr, 0);
489 rga_set_info(&dst, Width, Height, planes->stride,
490 Height, planes->fd, dst_format, (void *)planes->addr, planes->type);
491 if (ctx == NULL) {
492 return;
493 }
494 if (rga_convert(&src, &dst, ctx->rga_fd) < 0) {
495 omx_err("rga_nv122rgb fail");
496 }
497 #else
498 rga_info_t src;
499 rga_info_t dst;
500 (void) rga_ctx;
501 Rockchip_OSAL_Memset((void*)&src, 0, sizeof(rga_info_t));
502 Rockchip_OSAL_Memset((void*)&dst, 0, sizeof(rga_info_t));
503 rga_set_rect(&src.rect, 0, 0, Width, Height,
504 (Width + 15) & (~15), Height, HAL_PIXEL_FORMAT_YCrCb_NV12); // 15:byte alignment
505 if (dst_format == RK_FORMAT_BGRA_8888) {
506 dst_format = HAL_PIXEL_FORMAT_BGRA_8888;
507 } else if (dst_format == RK_FORMAT_RGBA_8888) {
508 dst_format = HAL_PIXEL_FORMAT_RGBA_8888;
509 }
510 rga_set_rect(&dst.rect, 0, 0, Width, Height, planes->stride, Height, dst_format);
511 src.fd = vpumem->phy_addr;
512 dst.fd = planes->fd;
513 if (RgaBlit(&src, &dst, NULL)) {
514 omx_err("RgaBlit fail");
515 }
516 #endif
517 }
518
rga_nv12_copy(RockchipVideoPlane * plane,VPUMemLinear_t * vpumem,uint32_t Width,uint32_t Height,void * rga_ctx)519 void rga_nv12_copy(RockchipVideoPlane *plane, VPUMemLinear_t *vpumem, uint32_t Width, uint32_t Height, void* rga_ctx)
520 {
521 #ifndef USE_DRM
522 int format = RK_FORMAT_YCbCr_420_SP;
523 rga_ctx_t *ctx = (rga_ctx_t *)rga_ctx;
524 if (ctx == NULL) {
525 return;
526 }
527
528 if (rga_copy(plane, vpumem, Width, Height, format, ctx->rga_fd) < 0) {
529 omx_err("rga_nv12_copy fail");
530 }
531 #else
532 rga_info_t src;
533 rga_info_t dst;
534 (void) rga_ctx;
535 memset_s((void*)&src, sizeof(rga_info_t), 0, sizeof(rga_info_t));
536 memset_s((void*)&dst, sizeof(rga_info_t), 0, sizeof(rga_info_t));
537 rga_set_rect(&src.rect, 0, 0, Width, Height, plane->stride, Height, HAL_PIXEL_FORMAT_YCrCb_NV12);
538 rga_set_rect(&dst.rect, 0, 0, Width, Height, Width, Height, HAL_PIXEL_FORMAT_YCrCb_NV12);
539 src.fd = plane->fd;
540 dst.fd = vpumem->phy_addr;
541 if (RgaBlit(&src, &dst, NULL)) {
542 omx_err("RgaBlit fail");
543 }
544
545 #endif
546 }
547
rga_rgb_copy(RockchipVideoPlane * plane,VPUMemLinear_t * vpumem,uint32_t Width,uint32_t Height,void * rga_ctx)548 void rga_rgb_copy(RockchipVideoPlane *plane, VPUMemLinear_t *vpumem, uint32_t Width, uint32_t Height, void* rga_ctx)
549 {
550 #ifndef USE_DRM
551 int format = RK_FORMAT_RGBA_8888;
552 rga_ctx_t *ctx = (rga_ctx_t *)rga_ctx;
553 if (ctx == NULL) {
554 return;
555 }
556 if (rga_copy(plane, vpumem, Width, Height, format, ctx->rga_fd) < 0) {
557 omx_err("rga_nv12_copy fail");
558 }
559 #else
560 rga_info_t src;
561 rga_info_t dst;
562 (void) rga_ctx;
563 memset_s((void*)&src, sizeof(rga_info_t), 0, sizeof(rga_info_t));
564 memset_s((void*)&dst, sizeof(rga_info_t), 0, sizeof(rga_info_t));
565 rga_set_rect(&src.rect, 0, 0, Width, Height, plane->stride, Height, HAL_PIXEL_FORMAT_RGBA_8888);
566 rga_set_rect(&dst.rect, 0, 0, Width, Height, Width, Height, HAL_PIXEL_FORMAT_RGBA_8888);
567 src.fd = plane->fd;
568 dst.fd = vpumem->phy_addr;
569 if (RgaBlit(&src, &dst, NULL)) {
570 omx_err("RgaBlit fail");
571 }
572 #endif
573 }