1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Zheng Yang <zhengyang@rock-chips.com>
5 */
6
7 #include <drm/drm_of.h>
8 #include <drm/drm_probe_helper.h>
9 #include <drm/drm_simple_kms_helper.h>
10
11 #include <linux/clk.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15
16 #include "rk3066_hdmi.h"
17
18 #include "rockchip_drm_drv.h"
19 #include "rockchip_drm_vop.h"
20
21 #define DEFAULT_PLLA_RATE 30000000
22
23 struct hdmi_data_info {
24 int vic; /* The CEA Video ID (VIC) of the current drm display mode. */
25 bool sink_is_hdmi;
26 unsigned int enc_out_format;
27 unsigned int colorimetry;
28 };
29
30 struct rk3066_hdmi_i2c {
31 struct i2c_adapter adap;
32
33 u8 ddc_addr;
34 u8 segment_addr;
35 u8 stat;
36
37 struct mutex i2c_lock; /* For i2c operation. */
38 struct completion cmpltn;
39 };
40
41 struct rk3066_hdmi {
42 struct device *dev;
43 struct drm_device *drm_dev;
44 struct regmap *grf_regmap;
45 int irq;
46 struct clk *hclk;
47 void __iomem *regs;
48
49 struct drm_connector connector;
50 struct drm_encoder encoder;
51
52 struct rk3066_hdmi_i2c *i2c;
53 struct i2c_adapter *ddc;
54
55 unsigned int tmdsclk;
56
57 struct hdmi_data_info hdmi_data;
58 struct drm_display_mode previous_mode;
59 };
60
61 #define to_rk3066_hdmi(x) container_of(x, struct rk3066_hdmi, x)
62
hdmi_readb(struct rk3066_hdmi * hdmi,u16 offset)63 static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset)
64 {
65 return readl_relaxed(hdmi->regs + offset);
66 }
67
hdmi_writeb(struct rk3066_hdmi * hdmi,u16 offset,u32 val)68 static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val)
69 {
70 writel_relaxed(val, hdmi->regs + offset);
71 }
72
hdmi_modb(struct rk3066_hdmi * hdmi,u16 offset,u32 msk,u32 val)73 static inline void hdmi_modb(struct rk3066_hdmi *hdmi, u16 offset, u32 msk, u32 val)
74 {
75 u8 temp = hdmi_readb(hdmi, offset) & ~msk;
76
77 temp |= val & msk;
78 hdmi_writeb(hdmi, offset, temp);
79 }
80
rk3066_hdmi_i2c_init(struct rk3066_hdmi * hdmi)81 static void rk3066_hdmi_i2c_init(struct rk3066_hdmi *hdmi)
82 {
83 int ddc_bus_freq;
84
85 ddc_bus_freq = (hdmi->tmdsclk >> 0x2) / HDMI_SCL_RATE;
86
87 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
88 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_H, (ddc_bus_freq >> 0x8) & 0xFF);
89
90 /* Clear the EDID interrupt flag and mute the interrupt. */
91 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0);
92 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, HDMI_INTR_EDID_MASK);
93 }
94
rk3066_hdmi_get_power_mode(struct rk3066_hdmi * hdmi)95 static inline u8 rk3066_hdmi_get_power_mode(struct rk3066_hdmi *hdmi)
96 {
97 return hdmi_readb(hdmi, HDMI_SYS_CTRL) & HDMI_SYS_POWER_MODE_MASK;
98 }
99
rk3066_hdmi_set_power_mode(struct rk3066_hdmi * hdmi,int mode)100 static void rk3066_hdmi_set_power_mode(struct rk3066_hdmi *hdmi, int mode)
101 {
102 u8 current_mode, next_mode;
103 u8 i = 0;
104
105 current_mode = rk3066_hdmi_get_power_mode(hdmi);
106
107 DRM_DEV_DEBUG(hdmi->dev, "mode :%d\n", mode);
108 DRM_DEV_DEBUG(hdmi->dev, "current_mode :%d\n", current_mode);
109
110 if (current_mode == mode) {
111 return;
112 }
113
114 do {
115 if (current_mode > mode) {
116 next_mode = current_mode / 0x2;
117 } else {
118 if (current_mode < HDMI_SYS_POWER_MODE_A) {
119 next_mode = HDMI_SYS_POWER_MODE_A;
120 } else {
121 next_mode = current_mode * 0x2;
122 }
123 }
124
125 DRM_DEV_DEBUG(hdmi->dev, "%d: next_mode :%d\n", i, next_mode);
126
127 if (next_mode != HDMI_SYS_POWER_MODE_D) {
128 hdmi_modb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_MASK, next_mode);
129 } else {
130 hdmi_writeb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_D | HDMI_SYS_PLL_RESET_MASK);
131 usleep_range(0x5a, 0x64);
132 hdmi_writeb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_D | HDMI_SYS_PLLB_RESET);
133 usleep_range(0x5a, 0x64);
134 hdmi_writeb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_D);
135 }
136 current_mode = next_mode;
137 i = i + 1;
138 } while ((next_mode != mode) && (i < 0x5));
139
140 /*
141 * When the IP controller isn't configured with accurate video timing,
142 * DDC_CLK should be equal to the PLLA frequency, which is 30MHz,
143 * so we need to init the TMDS rate to the PCLK rate and reconfigure
144 * the DDC clock.
145 */
146 if (mode < HDMI_SYS_POWER_MODE_D) {
147 hdmi->tmdsclk = DEFAULT_PLLA_RATE;
148 }
149 }
150
rk3066_hdmi_upload_frame(struct rk3066_hdmi * hdmi,int setup_rc,union hdmi_infoframe * frame,u32 frame_index,u32 mask,u32 disable,u32 enable)151 static int rk3066_hdmi_upload_frame(struct rk3066_hdmi *hdmi, int setup_rc, union hdmi_infoframe *frame,
152 u32 frame_index, u32 mask, u32 disable, u32 enable)
153 {
154 if (mask) {
155 hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, disable);
156 }
157
158 hdmi_writeb(hdmi, HDMI_CP_BUF_INDEX, frame_index);
159
160 if (setup_rc >= 0) {
161 u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE];
162 ssize_t rc, i;
163
164 rc = hdmi_infoframe_pack(frame, packed_frame, sizeof(packed_frame));
165 if (rc < 0) {
166 return rc;
167 }
168
169 for (i = 0; i < rc; i++) {
170 hdmi_writeb(hdmi, HDMI_CP_BUF_ACC_HB0 + i * 0x4, packed_frame[i]);
171 }
172
173 if (mask) {
174 hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, enable);
175 }
176 }
177
178 return setup_rc;
179 }
180
rk3066_hdmi_config_avi(struct rk3066_hdmi * hdmi,struct drm_display_mode * mode)181 static int rk3066_hdmi_config_avi(struct rk3066_hdmi *hdmi, struct drm_display_mode *mode)
182 {
183 union hdmi_infoframe frame;
184 int rc;
185
186 rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, &hdmi->connector, mode);
187
188 if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV444) {
189 frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
190 } else if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV422) {
191 frame.avi.colorspace = HDMI_COLORSPACE_YUV422;
192 } else {
193 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
194 }
195
196 frame.avi.colorimetry = hdmi->hdmi_data.colorimetry;
197 frame.avi.scan_mode = HDMI_SCAN_MODE_NONE;
198
199 return rk3066_hdmi_upload_frame(hdmi, rc, &frame, HDMI_INFOFRAME_AVI, 0, 0, 0);
200 }
201
rk3066_hdmi_config_video_timing(struct rk3066_hdmi * hdmi,struct drm_display_mode * mode)202 static int rk3066_hdmi_config_video_timing(struct rk3066_hdmi *hdmi, struct drm_display_mode *mode)
203 {
204 int value, vsync_offset;
205
206 /* Set the details for the external polarity and interlace mode. */
207 value = HDMI_EXT_VIDEO_SET_EN;
208 value |= mode->flags & DRM_MODE_FLAG_PHSYNC ? HDMI_VIDEO_HSYNC_ACTIVE_HIGH : HDMI_VIDEO_HSYNC_ACTIVE_LOW;
209 value |= mode->flags & DRM_MODE_FLAG_PVSYNC ? HDMI_VIDEO_VSYNC_ACTIVE_HIGH : HDMI_VIDEO_VSYNC_ACTIVE_LOW;
210 value |= mode->flags & DRM_MODE_FLAG_INTERLACE ? HDMI_VIDEO_MODE_INTERLACE : HDMI_VIDEO_MODE_PROGRESSIVE;
211
212 if (hdmi->hdmi_data.vic == 0x2 || hdmi->hdmi_data.vic == 0x3) {
213 vsync_offset = 0x6;
214 } else {
215 vsync_offset = 0;
216 }
217
218 value |= vsync_offset << HDMI_VIDEO_VSYNC_OFFSET_SHIFT;
219 hdmi_writeb(hdmi, HDMI_EXT_VIDEO_PARA, value);
220
221 /* Set the details for the external video timing. */
222 value = mode->htotal;
223 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_L, value & 0xFF);
224 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_H, (value >> 0x8) & 0xFF);
225
226 value = mode->htotal - mode->hdisplay;
227 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_L, value & 0xFF);
228 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_H, (value >> 0x8) & 0xFF);
229
230 value = mode->htotal - mode->hsync_start;
231 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_L, value & 0xFF);
232 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_H, (value >> 0x8) & 0xFF);
233
234 value = mode->hsync_end - mode->hsync_start;
235 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_L, value & 0xFF);
236 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_H, (value >> 0x8) & 0xFF);
237
238 value = mode->vtotal;
239 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_L, value & 0xFF);
240 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_H, (value >> 0x8) & 0xFF);
241
242 value = mode->vtotal - mode->vdisplay;
243 hdmi_writeb(hdmi, HDMI_EXT_VBLANK_L, value & 0xFF);
244
245 value = mode->vtotal - mode->vsync_start + vsync_offset;
246 hdmi_writeb(hdmi, HDMI_EXT_VDELAY, value & 0xFF);
247
248 value = mode->vsync_end - mode->vsync_start;
249 hdmi_writeb(hdmi, HDMI_EXT_VDURATION, value & 0xFF);
250
251 return 0;
252 }
253
rk3066_hdmi_phy_write(struct rk3066_hdmi * hdmi,u16 offset,u8 value)254 static void rk3066_hdmi_phy_write(struct rk3066_hdmi *hdmi, u16 offset, u8 value)
255 {
256 hdmi_writeb(hdmi, offset, value);
257 hdmi_modb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_PLL_RESET_MASK, HDMI_SYS_PLL_RESET);
258 usleep_range(0x5a, 0x64);
259 hdmi_modb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_PLL_RESET_MASK, 0);
260 usleep_range(0x384, 0x3e8);
261 }
262
rk3066_hdmi_config_phy(struct rk3066_hdmi * hdmi)263 static void rk3066_hdmi_config_phy(struct rk3066_hdmi *hdmi)
264 {
265 /* TMDS uses the same frequency as dclk. */
266 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x22);
267
268 /*
269 * The semi-public documentation does not describe the hdmi registers
270 * used by the function rk3066_hdmi_phy_write(), so we keep using
271 * these magic values for now.
272 */
273 if (hdmi->tmdsclk > 0x5f5e100) {
274 rk3066_hdmi_phy_write(hdmi, 0x158, 0x0E);
275 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
276 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
277 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
278 rk3066_hdmi_phy_write(hdmi, 0x168, 0xDA);
279 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA1);
280 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
281 rk3066_hdmi_phy_write(hdmi, 0x174, 0x22);
282 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
283 } else if (hdmi->tmdsclk > 0x2faf080) {
284 rk3066_hdmi_phy_write(hdmi, 0x158, 0x06);
285 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
286 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
287 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
288 rk3066_hdmi_phy_write(hdmi, 0x168, 0xCA);
289 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA3);
290 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
291 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20);
292 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
293 } else {
294 rk3066_hdmi_phy_write(hdmi, 0x158, 0x02);
295 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
296 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
297 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
298 rk3066_hdmi_phy_write(hdmi, 0x168, 0xC2);
299 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA2);
300 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
301 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20);
302 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
303 }
304 }
305
rk3066_hdmi_setup(struct rk3066_hdmi * hdmi,struct drm_display_mode * mode)306 static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi, struct drm_display_mode *mode)
307 {
308 hdmi->hdmi_data.vic = drm_match_cea_mode(mode);
309 hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB;
310
311 if (hdmi->hdmi_data.vic == 0x6 || hdmi->hdmi_data.vic == 0x7 || hdmi->hdmi_data.vic == 0x15 ||
312 hdmi->hdmi_data.vic == 0x16 || hdmi->hdmi_data.vic == 0x2 || hdmi->hdmi_data.vic == 0x3 ||
313 hdmi->hdmi_data.vic == 0x11 || hdmi->hdmi_data.vic == 0x12) {
314 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
315 } else {
316 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
317 }
318
319 hdmi->tmdsclk = mode->clock * 0x3e8;
320
321 /* Mute video and audio output. */
322 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_VIDEO_AUDIO_DISABLE_MASK, HDMI_AUDIO_DISABLE | HDMI_VIDEO_DISABLE);
323
324 /* Set power state to mode B. */
325 if (rk3066_hdmi_get_power_mode(hdmi) != HDMI_SYS_POWER_MODE_B) {
326 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B);
327 }
328
329 /* Input video mode is RGB 24 bit. Use external data enable signal. */
330 hdmi_modb(hdmi, HDMI_AV_CTRL1, HDMI_VIDEO_DE_MASK, HDMI_VIDEO_EXTERNAL_DE);
331 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL1,
332 HDMI_VIDEO_OUTPUT_RGB444 | HDMI_VIDEO_INPUT_DATA_DEPTH_8BIT | HDMI_VIDEO_INPUT_COLOR_RGB);
333 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x20);
334
335 rk3066_hdmi_config_video_timing(hdmi, mode);
336
337 if (hdmi->hdmi_data.sink_is_hdmi) {
338 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, HDMI_VIDEO_MODE_HDMI);
339 rk3066_hdmi_config_avi(hdmi, mode);
340 } else {
341 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 0);
342 }
343
344 rk3066_hdmi_config_phy(hdmi);
345
346 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_E);
347
348 /*
349 * When the IP controller is configured with accurate video
350 * timing, the TMDS clock source should be switched to
351 * DCLK_LCDC, so we need to init the TMDS rate to the pixel mode
352 * clock rate and reconfigure the DDC clock.
353 */
354 rk3066_hdmi_i2c_init(hdmi);
355
356 /* Unmute video output. */
357 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_VIDEO_AUDIO_DISABLE_MASK, HDMI_AUDIO_DISABLE);
358 return 0;
359 }
360
rk3066_hdmi_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adj_mode)361 static void rk3066_hdmi_encoder_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
362 struct drm_display_mode *adj_mode)
363 {
364 struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
365
366 /* Store the display mode for plugin/DPMS poweron events. */
367 memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode));
368 }
369
rk3066_hdmi_encoder_enable(struct drm_encoder * encoder)370 static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder)
371 {
372 struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
373 int mux, val;
374
375 mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
376 if (mux) {
377 val = (HDMI_VIDEO_SEL << 0x10) | HDMI_VIDEO_SEL;
378 } else {
379 val = HDMI_VIDEO_SEL << 0x10;
380 }
381
382 regmap_write(hdmi->grf_regmap, GRF_SOC_CON0, val);
383
384 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder enable select: vop%s\n", (mux) ? "1" : "0");
385
386 rk3066_hdmi_setup(hdmi, &hdmi->previous_mode);
387 }
388
rk3066_hdmi_encoder_disable(struct drm_encoder * encoder)389 static void rk3066_hdmi_encoder_disable(struct drm_encoder *encoder)
390 {
391 struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
392
393 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n");
394
395 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_E) {
396 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL2, HDMI_VIDEO_AUDIO_DISABLE_MASK);
397 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_AUDIO_CP_LOGIC_RESET_MASK, HDMI_AUDIO_CP_LOGIC_RESET);
398 usleep_range(0x1f4, 0x1fe);
399 }
400 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A);
401 }
402
rk3066_hdmi_encoder_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adj_mode)403 static bool rk3066_hdmi_encoder_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode,
404 struct drm_display_mode *adj_mode)
405 {
406 return true;
407 }
408
rk3066_hdmi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)409 static int rk3066_hdmi_encoder_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state,
410 struct drm_connector_state *conn_state)
411 {
412 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
413
414 s->output_mode = ROCKCHIP_OUT_MODE_P888;
415 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
416
417 return 0;
418 }
419
420 static const struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = {
421 .enable = rk3066_hdmi_encoder_enable,
422 .disable = rk3066_hdmi_encoder_disable,
423 .mode_fixup = rk3066_hdmi_encoder_mode_fixup,
424 .mode_set = rk3066_hdmi_encoder_mode_set,
425 .atomic_check = rk3066_hdmi_encoder_atomic_check,
426 };
427
rk3066_hdmi_connector_detect(struct drm_connector * connector,bool force)428 static enum drm_connector_status rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force)
429 {
430 struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
431
432 return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ? connector_status_connected
433 : connector_status_disconnected;
434 }
435
rk3066_hdmi_connector_get_modes(struct drm_connector * connector)436 static int rk3066_hdmi_connector_get_modes(struct drm_connector *connector)
437 {
438 struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
439 struct edid *edid;
440 int ret = 0;
441
442 if (!hdmi->ddc) {
443 return 0;
444 }
445
446 edid = drm_get_edid(connector, hdmi->ddc);
447 if (edid) {
448 hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid);
449 drm_connector_update_edid_property(connector, edid);
450 ret = drm_add_edid_modes(connector, edid);
451 kfree(edid);
452 }
453
454 return ret;
455 }
456
rk3066_hdmi_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)457 static enum drm_mode_status rk3066_hdmi_connector_mode_valid(struct drm_connector *connector,
458 struct drm_display_mode *mode)
459 {
460 u32 vic = drm_match_cea_mode(mode);
461 if (vic > 1) {
462 return MODE_OK;
463 } else {
464 return MODE_BAD;
465 }
466 }
467
rk3066_hdmi_connector_best_encoder(struct drm_connector * connector)468 static struct drm_encoder *rk3066_hdmi_connector_best_encoder(struct drm_connector *connector)
469 {
470 struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
471
472 return &hdmi->encoder;
473 }
474
rk3066_hdmi_probe_single_connector_modes(struct drm_connector * connector,uint32_t maxX,uint32_t maxY)475 static int rk3066_hdmi_probe_single_connector_modes(struct drm_connector *connector, uint32_t maxX, uint32_t maxY)
476 {
477 if (maxX > 0x780) {
478 maxX = 0x780;
479 }
480 if (maxY > 0x438) {
481 maxY = 0x438;
482 }
483
484 return drm_helper_probe_single_connector_modes(connector, maxX, maxY);
485 }
486
rk3066_hdmi_connector_destroy(struct drm_connector * connector)487 static void rk3066_hdmi_connector_destroy(struct drm_connector *connector)
488 {
489 drm_connector_unregister(connector);
490 drm_connector_cleanup(connector);
491 }
492
493 static const struct drm_connector_funcs rk3066_hdmi_connector_funcs = {
494 .fill_modes = rk3066_hdmi_probe_single_connector_modes,
495 .detect = rk3066_hdmi_connector_detect,
496 .destroy = rk3066_hdmi_connector_destroy,
497 .reset = drm_atomic_helper_connector_reset,
498 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
499 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
500 };
501
502 static const struct drm_connector_helper_funcs rk3066_hdmi_connector_helper_funcs = {
503 .get_modes = rk3066_hdmi_connector_get_modes,
504 .mode_valid = rk3066_hdmi_connector_mode_valid,
505 .best_encoder = rk3066_hdmi_connector_best_encoder,
506 };
507
rk3066_hdmi_register(struct drm_device * drm,struct rk3066_hdmi * hdmi)508 static int rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi)
509 {
510 struct drm_encoder *encoder = &hdmi->encoder;
511 struct device *dev = hdmi->dev;
512
513 encoder->possible_crtcs = rockchip_drm_of_find_possible_crtcs(drm, dev->of_node);
514
515 /*
516 * If we failed to find the CRTC(s) which this encoder is
517 * supposed to be connected to, it's because the CRTC has
518 * not been registered yet. Defer probing, and hope that
519 * the required CRTC is added later.
520 */
521 if (encoder->possible_crtcs == 0) {
522 return -EPROBE_DEFER;
523 }
524
525 drm_encoder_helper_add(encoder, &rk3066_hdmi_encoder_helper_funcs);
526 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
527
528 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
529
530 drm_connector_helper_add(&hdmi->connector, &rk3066_hdmi_connector_helper_funcs);
531 drm_connector_init_with_ddc(drm, &hdmi->connector, &rk3066_hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA,
532 hdmi->ddc);
533
534 drm_connector_attach_encoder(&hdmi->connector, encoder);
535
536 return 0;
537 }
538
rk3066_hdmi_hardirq(int irq,void * dev_id)539 static irqreturn_t rk3066_hdmi_hardirq(int irq, void *dev_id)
540 {
541 struct rk3066_hdmi *hdmi = dev_id;
542 irqreturn_t ret = IRQ_NONE;
543 u8 interrupt;
544
545 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_A) {
546 hdmi_writeb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_B);
547 }
548
549 interrupt = hdmi_readb(hdmi, HDMI_INTR_STATUS1);
550 if (interrupt) {
551 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, interrupt);
552 }
553
554 if (interrupt & HDMI_INTR_EDID_MASK) {
555 hdmi->i2c->stat = interrupt;
556 complete(&hdmi->i2c->cmpltn);
557 }
558
559 if (interrupt & (HDMI_INTR_HOTPLUG | HDMI_INTR_MSENS)) {
560 ret = IRQ_WAKE_THREAD;
561 }
562
563 return ret;
564 }
565
rk3066_hdmi_irq(int irq,void * dev_id)566 static irqreturn_t rk3066_hdmi_irq(int irq, void *dev_id)
567 {
568 struct rk3066_hdmi *hdmi = dev_id;
569
570 drm_helper_hpd_irq_event(hdmi->connector.dev);
571
572 return IRQ_HANDLED;
573 }
574
rk3066_hdmi_i2c_read(struct rk3066_hdmi * hdmi,struct i2c_msg * msgs)575 static int rk3066_hdmi_i2c_read(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs)
576 {
577 int length = msgs->len;
578 u8 *buf = msgs->buf;
579 int ret;
580
581 ret = wait_for_completion_timeout(&hdmi->i2c->cmpltn, HZ / 0xa);
582 if (!ret || (hdmi->i2c->stat & HDMI_INTR_EDID_ERR)) {
583 return -EAGAIN;
584 }
585
586 while (length--) {
587 *buf++ = hdmi_readb(hdmi, HDMI_DDC_READ_FIFO_ADDR);
588 }
589
590 return 0;
591 }
592
rk3066_hdmi_i2c_write(struct rk3066_hdmi * hdmi,struct i2c_msg * msgs)593 static int rk3066_hdmi_i2c_write(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs)
594 {
595 /*
596 * The DDC module only supports read EDID message, so
597 * we assume that each word write to this i2c adapter
598 * should be the offset of the EDID word address.
599 */
600 if (msgs->len != 1 || (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR)) {
601 return -EINVAL;
602 }
603
604 reinit_completion(&hdmi->i2c->cmpltn);
605
606 if (msgs->addr == DDC_SEGMENT_ADDR) {
607 hdmi->i2c->segment_addr = msgs->buf[0];
608 }
609 if (msgs->addr == DDC_ADDR) {
610 hdmi->i2c->ddc_addr = msgs->buf[0];
611 }
612
613 /* Set edid fifo first address. */
614 hdmi_writeb(hdmi, HDMI_EDID_FIFO_ADDR, 0x00);
615
616 /* Set edid word address 0x00/0x80. */
617 hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
618
619 /* Set edid segment pointer. */
620 hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
621
622 return 0;
623 }
624
rk3066_hdmi_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)625 static int rk3066_hdmi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
626 {
627 struct rk3066_hdmi *hdmi = i2c_get_adapdata(adap);
628 struct rk3066_hdmi_i2c *i2c = hdmi->i2c;
629 int i, ret = 0;
630
631 mutex_lock(&i2c->i2c_lock);
632
633 rk3066_hdmi_i2c_init(hdmi);
634
635 /* Unmute HDMI EDID interrupt. */
636 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, HDMI_INTR_EDID_MASK);
637 i2c->stat = 0;
638
639 for (i = 0; i < num; i++) {
640 DRM_DEV_DEBUG(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", i + 1, num, msgs[i].len, msgs[i].flags);
641
642 if (msgs[i].flags & I2C_M_RD) {
643 ret = rk3066_hdmi_i2c_read(hdmi, &msgs[i]);
644 } else {
645 ret = rk3066_hdmi_i2c_write(hdmi, &msgs[i]);
646 }
647
648 if (ret < 0) {
649 break;
650 }
651 }
652
653 if (!ret) {
654 ret = num;
655 }
656
657 /* Mute HDMI EDID interrupt. */
658 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0);
659
660 mutex_unlock(&i2c->i2c_lock);
661
662 return ret;
663 }
664
rk3066_hdmi_i2c_func(struct i2c_adapter * adapter)665 static u32 rk3066_hdmi_i2c_func(struct i2c_adapter *adapter)
666 {
667 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
668 }
669
670 static const struct i2c_algorithm rk3066_hdmi_algorithm = {
671 .master_xfer = rk3066_hdmi_i2c_xfer,
672 .functionality = rk3066_hdmi_i2c_func,
673 };
674
rk3066_hdmi_i2c_adapter(struct rk3066_hdmi * hdmi)675 static struct i2c_adapter *rk3066_hdmi_i2c_adapter(struct rk3066_hdmi *hdmi)
676 {
677 struct i2c_adapter *adap;
678 struct rk3066_hdmi_i2c *i2c;
679 int ret;
680
681 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
682 if (!i2c) {
683 return ERR_PTR(-ENOMEM);
684 }
685
686 mutex_init(&i2c->i2c_lock);
687 init_completion(&i2c->cmpltn);
688
689 adap = &i2c->adap;
690 adap->class = I2C_CLASS_DDC;
691 adap->owner = THIS_MODULE;
692 adap->dev.parent = hdmi->dev;
693 adap->dev.of_node = hdmi->dev->of_node;
694 adap->algo = &rk3066_hdmi_algorithm;
695 strlcpy(adap->name, "RK3066 HDMI", sizeof(adap->name));
696 i2c_set_adapdata(adap, hdmi);
697
698 ret = i2c_add_adapter(adap);
699 if (ret) {
700 DRM_DEV_ERROR(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
701 devm_kfree(hdmi->dev, i2c);
702 return ERR_PTR(ret);
703 }
704
705 hdmi->i2c = i2c;
706
707 DRM_DEV_DEBUG(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
708
709 return adap;
710 }
711
rk3066_hdmi_bind(struct device * dev,struct device * master,void * data)712 static int rk3066_hdmi_bind(struct device *dev, struct device *master, void *data)
713 {
714 struct platform_device *pdev = to_platform_device(dev);
715 struct drm_device *drm = data;
716 struct rk3066_hdmi *hdmi;
717 int irq;
718 int ret;
719
720 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
721 if (!hdmi) {
722 return -ENOMEM;
723 }
724
725 hdmi->dev = dev;
726 hdmi->drm_dev = drm;
727 hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
728 if (IS_ERR(hdmi->regs)) {
729 return PTR_ERR(hdmi->regs);
730 }
731
732 irq = platform_get_irq(pdev, 0);
733 if (irq < 0) {
734 return irq;
735 }
736
737 hdmi->hclk = devm_clk_get(dev, "hclk");
738 if (IS_ERR(hdmi->hclk)) {
739 DRM_DEV_ERROR(dev, "unable to get HDMI hclk clock\n");
740 return PTR_ERR(hdmi->hclk);
741 }
742
743 ret = clk_prepare_enable(hdmi->hclk);
744 if (ret) {
745 DRM_DEV_ERROR(dev, "cannot enable HDMI hclk clock: %d\n", ret);
746 return ret;
747 }
748
749 hdmi->grf_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
750 if (IS_ERR(hdmi->grf_regmap)) {
751 DRM_DEV_ERROR(dev, "unable to get rockchip,grf\n");
752 ret = PTR_ERR(hdmi->grf_regmap);
753 goto err_disable_hclk;
754 }
755
756 /* internal hclk = hdmi_hclk / 25 */
757 hdmi_writeb(hdmi, HDMI_INTERNAL_CLK_DIVIDER, 0x19);
758
759 hdmi->ddc = rk3066_hdmi_i2c_adapter(hdmi);
760 if (IS_ERR(hdmi->ddc)) {
761 ret = PTR_ERR(hdmi->ddc);
762 hdmi->ddc = NULL;
763 goto err_disable_hclk;
764 }
765
766 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B);
767 usleep_range(0x3e7, 0x3e8);
768 hdmi_writeb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_HOTPLUG);
769 hdmi_writeb(hdmi, HDMI_INTR_MASK2, 0);
770 hdmi_writeb(hdmi, HDMI_INTR_MASK3, 0);
771 hdmi_writeb(hdmi, HDMI_INTR_MASK4, 0);
772 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A);
773
774 ret = rk3066_hdmi_register(drm, hdmi);
775 if (ret) {
776 goto err_disable_i2c;
777 }
778
779 dev_set_drvdata(dev, hdmi);
780
781 ret = devm_request_threaded_irq(dev, irq, rk3066_hdmi_hardirq, rk3066_hdmi_irq, IRQF_SHARED, dev_name(dev), hdmi);
782 if (ret) {
783 DRM_DEV_ERROR(dev, "failed to request hdmi irq: %d\n", ret);
784 goto err_cleanup_hdmi;
785 }
786
787 return 0;
788
789 err_cleanup_hdmi:
790 hdmi->connector.funcs->destroy(&hdmi->connector);
791 hdmi->encoder.funcs->destroy(&hdmi->encoder);
792 err_disable_i2c:
793 i2c_put_adapter(hdmi->ddc);
794 err_disable_hclk:
795 clk_disable_unprepare(hdmi->hclk);
796
797 return ret;
798 }
799
rk3066_hdmi_unbind(struct device * dev,struct device * master,void * data)800 static void rk3066_hdmi_unbind(struct device *dev, struct device *master, void *data)
801 {
802 struct rk3066_hdmi *hdmi = dev_get_drvdata(dev);
803
804 hdmi->connector.funcs->destroy(&hdmi->connector);
805 hdmi->encoder.funcs->destroy(&hdmi->encoder);
806
807 i2c_put_adapter(hdmi->ddc);
808 clk_disable_unprepare(hdmi->hclk);
809 }
810
811 static const struct component_ops rk3066_hdmi_ops = {
812 .bind = rk3066_hdmi_bind,
813 .unbind = rk3066_hdmi_unbind,
814 };
815
rk3066_hdmi_probe(struct platform_device * pdev)816 static int rk3066_hdmi_probe(struct platform_device *pdev)
817 {
818 return component_add(&pdev->dev, &rk3066_hdmi_ops);
819 }
820
rk3066_hdmi_remove(struct platform_device * pdev)821 static int rk3066_hdmi_remove(struct platform_device *pdev)
822 {
823 component_del(&pdev->dev, &rk3066_hdmi_ops);
824
825 return 0;
826 }
827
828 static const struct of_device_id rk3066_hdmi_dt_ids[] = {
829 {.compatible = "rockchip,rk3066-hdmi"},
830 {},
831 };
832 MODULE_DEVICE_TABLE(of, rk3066_hdmi_dt_ids);
833
834 struct platform_driver rk3066_hdmi_driver = {
835 .probe = rk3066_hdmi_probe,
836 .remove = rk3066_hdmi_remove,
837 .driver =
838 {
839 .name = "rockchip-rk3066-hdmi",
840 .of_match_table = rk3066_hdmi_dt_ids,
841 },
842 };
843